config.json

{
    "meta": {
        "version": 2,
        "flow": [
            "Yosys.Synthesis",
            "OpenROAD.CheckSDCFiles",
            "OpenROAD.Floorplan",
            "OpenROAD.TapEndcapInsertion",
            "OpenROAD.GeneratePDN",
            "OpenROAD.IOPlacement",
            "OpenROAD.GlobalPlacement",
            "OpenROAD.RepairDesign",
            "OpenROAD.DetailedPlacement",
            "OpenROAD.GlobalRouting",
            "OpenROAD.DetailedRouting",
            "OpenROAD.FillInsertion",
            "Magic.StreamOut",
            "Magic.DRC",
            "Checker.MagicDRC",
            "Magic.SpiceExtraction",
            "Netgen.LVS",
            "Checker.LVS"
        ]
    },
    "DESIGN_NAME": "inverter",
    "VERILOG_FILES": "dir::src/*.v",
    "CLOCK_PORT": null,
    "FP_SIZING": "absolute",
    "DIE_AREA": [
        0,
        0,
        50,
        50
    ],
    "PL_TARGET_DENSITY": 0.75,
    "FP_PDN_AUTO_ADJUST": false,
    "FP_PDN_VPITCH": 25,
    "FP_PDN_HPITCH": 25,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "//": "With those two defined, the repair design step should do nothing:",
    "RSZ_DONT_TOUCH_RX": "^in$",
    "RSZ_DONT_TOUCH_LIST": [
        "out"
    ]
}