diff --git a/docs/doxygen/html/_e_f___driver___common_8h.html b/docs/doxygen/html/_e_f___driver___common_8h.html new file mode 100644 index 0000000..519bb31 --- /dev/null +++ b/docs/doxygen/html/_e_f___driver___common_8h.html @@ -0,0 +1,255 @@ + + +
+ + + + +
+ EF_SPI APIs
+
+ |
+
C header file for common driver definitions and types. +More...
+#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
Go to the source code of this file.
++Macros | |
#define | EF_DRIVER_OK ((uint32_t)0) |
Operation succeeded. | |
#define | EF_DRIVER_ERROR ((uint32_t)1) |
Unspecified error. | |
#define | EF_DRIVER_ERROR_BUSY ((uint32_t)2) |
Driver is busy. | |
#define | EF_DRIVER_ERROR_TIMEOUT ((uint32_t)3) |
Timeout occurred. | |
#define | EF_DRIVER_ERROR_UNSUPPORTED ((uint32_t)4) |
Operation not supported. | |
#define | EF_DRIVER_ERROR_PARAMETER ((uint32_t)5) |
Parameter error. | |
#define | EF_DRIVER_ERROR_SPECIFIC ((uint32_t)6) |
Start of driver specific errors. | |
+Typedefs | |
typedef uint32_t | EF_DRIVER_STATUS |
A type that is used to return the status of the driver functions. | |
C header file for common driver definitions and types.
+#define EF_DRIVER_ERROR ((uint32_t)1) | +
Unspecified error.
+ +#define EF_DRIVER_ERROR_BUSY ((uint32_t)2) | +
Driver is busy.
+ +#define EF_DRIVER_ERROR_PARAMETER ((uint32_t)5) | +
Parameter error.
+ +#define EF_DRIVER_ERROR_SPECIFIC ((uint32_t)6) | +
Start of driver specific errors.
+ +#define EF_DRIVER_ERROR_TIMEOUT ((uint32_t)3) | +
Timeout occurred.
+ +#define EF_DRIVER_ERROR_UNSUPPORTED ((uint32_t)4) | +
Operation not supported.
+ +#define EF_DRIVER_OK ((uint32_t)0) | +
Operation succeeded.
+ +typedef uint32_t EF_DRIVER_STATUS | +
A type that is used to return the status of the driver functions.
+ +
+ EF_SPI APIs
+
+ |
+
+ EF_SPI APIs
+
+ |
+
C file for SPI APIs which contains the function Implementations. +More...
+#include "EF_SPI.h"
+Macros | |
#define | EF_SPI_C |
#define | EF_SPI_TXDATA_MAX_VALUE 0x000000FF |
+Functions | |
EF_DRIVER_STATUS | EF_SPI_setGclkEnable (EF_SPI_TYPE_PTR spi, uint32_t value) |
sets the GCLK enable bit in the SPI register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_writeData (EF_SPI_TYPE_PTR spi, uint32_t data) |
writes a byte of data to the TXDATA register | |
EF_DRIVER_STATUS | EF_SPI_readData (EF_SPI_TYPE_PTR spi, uint32_t *data) |
reads a byte of data from the RXDATA register | |
EF_DRIVER_STATUS | EF_SPI_writepolarity (EF_SPI_TYPE_PTR spi, bool polarity) |
sets the clock polarity of the SPI in the CFG register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_writePhase (EF_SPI_TYPE_PTR spi, bool phase) |
sets the clock phase of the SPI in the CFG register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_readTxFifoEmpty (EF_SPI_TYPE_PTR spi, uint32_t *TXfifo_state) |
reads the TX FIFO empty flag from the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_readRxFifoEmpty (EF_SPI_TYPE_PTR spi, uint32_t *RXfifo_state) |
reads the RX FIFO empty flag from the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_waitTxFifoEmpty (EF_SPI_TYPE_PTR spi) |
waits for the TX FIFO to be empty by polling the TX FIFO empty flag in the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_waitRxFifoNotEmpty (EF_SPI_TYPE_PTR spi) |
waits for the RX FIFO to be not empty by polling the RX FIFO empty flag in the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_FifoRxFlush (EF_SPI_TYPE_PTR spi) |
flushes the RX FIFO by writing to the RX FIFO FLUSH register | |
EF_DRIVER_STATUS | EF_SPI_enable (EF_SPI_TYPE_PTR spi) |
enables the SPI by setting the enable bit in the CTRL register to 1, enables spi master pulse generation | |
EF_DRIVER_STATUS | EF_SPI_disable (EF_SPI_TYPE_PTR spi) |
disables the SPI by setting the enable bit in the CTRL register to 0, disables spi master pulse generation | |
EF_DRIVER_STATUS | EF_SPI_enableRx (EF_SPI_TYPE_PTR spi) |
enables the RX by setting the RX enable bit in the CTRL register to 1, enables storing bytes recieved from slave in RX FIFO | |
EF_DRIVER_STATUS | EF_SPI_disableRx (EF_SPI_TYPE_PTR spi) |
disables the RX by setting the RX enable bit in the CTRL register to 0, disables storing bytes recieved from slave in RX FIFO | |
EF_DRIVER_STATUS | EF_SPI_assertCs (EF_SPI_TYPE_PTR spi) |
asserts the CS line by setting the SS bit in the CTRL register to 1, asserts the CS line to start a transaction with the slave | |
EF_DRIVER_STATUS | EF_SPI_deassertCs (EF_SPI_TYPE_PTR spi) |
deasserts the CS line by setting the SS bit in the CTRL register to 0, deasserts the CS line to end a transaction with the slave | |
EF_DRIVER_STATUS | EF_SPI_setIM (EF_SPI_TYPE_PTR spi, uint32_t mask) |
EF_DRIVER_STATUS | EF_SPI_getIM (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
EF_DRIVER_STATUS | EF_SPI_getRIS (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
EF_DRIVER_STATUS | EF_SPI_getMIS (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
C file for SPI APIs which contains the function Implementations.
+#define EF_SPI_C | +
#define EF_SPI_TXDATA_MAX_VALUE 0x000000FF | +
EF_DRIVER_STATUS EF_SPI_assertCs | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
asserts the CS line by setting the SS bit in the CTRL register to 1, asserts the CS line to start a transaction with the slave
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_deassertCs | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
deasserts the CS line by setting the SS bit in the CTRL register to 0, deasserts the CS line to end a transaction with the slave
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_disable | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
disables the SPI by setting the enable bit in the CTRL register to 0, disables spi master pulse generation
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_disableRx | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
disables the RX by setting the RX enable bit in the CTRL register to 0, disables storing bytes recieved from slave in RX FIFO
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_enable | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
enables the SPI by setting the enable bit in the CTRL register to 1, enables spi master pulse generation
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_enableRx | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
enables the RX by setting the RX enable bit in the CTRL register to 1, enables storing bytes recieved from slave in RX FIFO
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_FifoRxFlush | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
flushes the RX FIFO by writing to the RX FIFO FLUSH register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_getIM | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Interrupts Masking Register; which enable and disables interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_getMIS | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Masked Interrupt Status Register; which shows the status of the interrupts after masking (ANDing) RIS by IM. The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_getRIS | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Raw Interrupt Status Register; which shows the status of the interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_readData | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +data | +
+ | ) | ++ |
reads a byte of data from the RXDATA register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | data | The data read from the RXDATA register |
EF_DRIVER_STATUS EF_SPI_readRxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +RXfifo_state | +
+ | ) | ++ |
reads the RX FIFO empty flag from the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | RXfifo_state | The RX FIFO empty flag value |
EF_DRIVER_STATUS EF_SPI_readTxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +TXfifo_state | +
+ | ) | ++ |
reads the TX FIFO empty flag from the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | TXfifo_state | The TX FIFO empty flag value |
EF_DRIVER_STATUS EF_SPI_setGclkEnable | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +value | +
+ | ) | ++ |
sets the GCLK enable bit in the SPI register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | value | The value of the GCLK enable bit |
EF_DRIVER_STATUS EF_SPI_setIM | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +mask | +
+ | ) | ++ |
sets the value of the Interrupts Masking Register; which enable and disables interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_waitRxFifoNotEmpty | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
waits for the RX FIFO to be not empty by polling the RX FIFO empty flag in the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_waitTxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
waits for the TX FIFO to be empty by polling the TX FIFO empty flag in the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_writeData | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +data | +
+ | ) | ++ |
writes a byte of data to the TXDATA register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | data | The data to be written to the TXDATA register |
EF_DRIVER_STATUS EF_SPI_writePhase | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | bool | +phase | +
+ | ) | ++ |
sets the clock phase of the SPI in the CFG register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | phase | The clock phase value |
EF_DRIVER_STATUS EF_SPI_writepolarity | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | bool | +polarity | +
+ | ) | ++ |
sets the clock polarity of the SPI in the CFG register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | polarity | The clock polarity value |
+ EF_SPI APIs
+
+ |
+
C header file for SPI APIs which contains the function prototypes. +More...
+ +Go to the source code of this file.
++Functions | |
EF_DRIVER_STATUS | EF_SPI_setGclkEnable (EF_SPI_TYPE_PTR spi, uint32_t value) |
sets the GCLK enable bit in the SPI register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_writeData (EF_SPI_TYPE_PTR spi, uint32_t data) |
writes a byte of data to the TXDATA register | |
EF_DRIVER_STATUS | EF_SPI_readData (EF_SPI_TYPE_PTR spi, uint32_t *data) |
reads a byte of data from the RXDATA register | |
EF_DRIVER_STATUS | EF_SPI_writepolarity (EF_SPI_TYPE_PTR spi, bool polarity) |
sets the clock polarity of the SPI in the CFG register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_writePhase (EF_SPI_TYPE_PTR spi, bool phase) |
sets the clock phase of the SPI in the CFG register to a certain value | |
EF_DRIVER_STATUS | EF_SPI_readTxFifoEmpty (EF_SPI_TYPE_PTR spi, uint32_t *TXfifo_state) |
reads the TX FIFO empty flag from the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_readRxFifoEmpty (EF_SPI_TYPE_PTR spi, uint32_t *RXfifo_state) |
reads the RX FIFO empty flag from the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_waitTxFifoEmpty (EF_SPI_TYPE_PTR spi) |
waits for the TX FIFO to be empty by polling the TX FIFO empty flag in the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_waitRxFifoNotEmpty (EF_SPI_TYPE_PTR spi) |
waits for the RX FIFO to be not empty by polling the RX FIFO empty flag in the STATUS register | |
EF_DRIVER_STATUS | EF_SPI_FifoRxFlush (EF_SPI_TYPE_PTR spi) |
flushes the RX FIFO by writing to the RX FIFO FLUSH register | |
EF_DRIVER_STATUS | EF_SPI_enable (EF_SPI_TYPE_PTR spi) |
enables the SPI by setting the enable bit in the CTRL register to 1, enables spi master pulse generation | |
EF_DRIVER_STATUS | EF_SPI_disable (EF_SPI_TYPE_PTR spi) |
disables the SPI by setting the enable bit in the CTRL register to 0, disables spi master pulse generation | |
EF_DRIVER_STATUS | EF_SPI_enableRx (EF_SPI_TYPE_PTR spi) |
enables the RX by setting the RX enable bit in the CTRL register to 1, enables storing bytes recieved from slave in RX FIFO | |
EF_DRIVER_STATUS | EF_SPI_disableRx (EF_SPI_TYPE_PTR spi) |
disables the RX by setting the RX enable bit in the CTRL register to 0, disables storing bytes recieved from slave in RX FIFO | |
EF_DRIVER_STATUS | EF_SPI_assertCs (EF_SPI_TYPE_PTR spi) |
asserts the CS line by setting the SS bit in the CTRL register to 1, asserts the CS line to start a transaction with the slave | |
EF_DRIVER_STATUS | EF_SPI_deassertCs (EF_SPI_TYPE_PTR spi) |
deasserts the CS line by setting the SS bit in the CTRL register to 0, deasserts the CS line to end a transaction with the slave | |
EF_DRIVER_STATUS | EF_SPI_setIM (EF_SPI_TYPE_PTR spi, uint32_t mask) |
EF_DRIVER_STATUS | EF_SPI_getIM (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
EF_DRIVER_STATUS | EF_SPI_getRIS (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
EF_DRIVER_STATUS | EF_SPI_getMIS (EF_SPI_TYPE_PTR spi, uint32_t *mask) |
EF_DRIVER_STATUS | EF_SPI_setICR (EF_SPI_TYPE_PTR spi, uint32_t mask) |
C header file for SPI APIs which contains the function prototypes.
+EF_DRIVER_STATUS EF_SPI_assertCs | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
asserts the CS line by setting the SS bit in the CTRL register to 1, asserts the CS line to start a transaction with the slave
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_deassertCs | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
deasserts the CS line by setting the SS bit in the CTRL register to 0, deasserts the CS line to end a transaction with the slave
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_disable | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
disables the SPI by setting the enable bit in the CTRL register to 0, disables spi master pulse generation
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_disableRx | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
disables the RX by setting the RX enable bit in the CTRL register to 0, disables storing bytes recieved from slave in RX FIFO
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_enable | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
enables the SPI by setting the enable bit in the CTRL register to 1, enables spi master pulse generation
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_enableRx | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
enables the RX by setting the RX enable bit in the CTRL register to 1, enables storing bytes recieved from slave in RX FIFO
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_FifoRxFlush | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
flushes the RX FIFO by writing to the RX FIFO FLUSH register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_getIM | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Interrupts Masking Register; which enable and disables interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_getMIS | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Masked Interrupt Status Register; which shows the status of the interrupts after masking (ANDing) RIS by IM. The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_getRIS | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +mask | +
+ | ) | ++ |
gets the value of the Raw Interrupt Status Register; which shows the status of the interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_readData | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +data | +
+ | ) | ++ |
reads a byte of data from the RXDATA register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | data | The data read from the RXDATA register |
EF_DRIVER_STATUS EF_SPI_readRxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +RXfifo_state | +
+ | ) | ++ |
reads the RX FIFO empty flag from the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | RXfifo_state | The RX FIFO empty flag value |
EF_DRIVER_STATUS EF_SPI_readTxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t * | +TXfifo_state | +
+ | ) | ++ |
reads the TX FIFO empty flag from the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[out] | TXfifo_state | The TX FIFO empty flag value |
EF_DRIVER_STATUS EF_SPI_setGclkEnable | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +value | +
+ | ) | ++ |
sets the GCLK enable bit in the SPI register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | value | The value of the GCLK enable bit |
EF_DRIVER_STATUS EF_SPI_setICR | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +mask | +
+ | ) | ++ |
sets the value of the Interrupt Clear Register; which clears the interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_setIM | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +mask | +
+ | ) | ++ |
sets the value of the Interrupts Masking Register; which enable and disables interrupts The mask value is a 6-bit value, where each bit corresponds to a specific interrupt
[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | mask | The required mask value |
EF_DRIVER_STATUS EF_SPI_waitRxFifoNotEmpty | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
waits for the RX FIFO to be not empty by polling the RX FIFO empty flag in the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_waitTxFifoEmpty | +( | +EF_SPI_TYPE_PTR | +spi | ) | ++ |
waits for the TX FIFO to be empty by polling the TX FIFO empty flag in the STATUS register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
EF_DRIVER_STATUS EF_SPI_writeData | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | uint32_t | +data | +
+ | ) | ++ |
writes a byte of data to the TXDATA register
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | data | The data to be written to the TXDATA register |
EF_DRIVER_STATUS EF_SPI_writePhase | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | bool | +phase | +
+ | ) | ++ |
sets the clock phase of the SPI in the CFG register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | phase | The clock phase value |
EF_DRIVER_STATUS EF_SPI_writepolarity | +( | +EF_SPI_TYPE_PTR | +spi, | +
+ | + | bool | +polarity | +
+ | ) | ++ |
sets the clock polarity of the SPI in the CFG register to a certain value
+[in] | spi | An EF_SPI_TYPE pointer, which points to the base memory address of SPI registers. EF_SPI_TYPE is a structure that contains the SPI registers. |
[in] | polarity | The clock polarity value |
+ EF_SPI APIs
+
+ |
+
+ EF_SPI APIs
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#include "EF_Driver_Common.h"
Go to the source code of this file.
++Classes | |
struct | _EF_SPI_TYPE_ |
+Macros | |
#define | IO_TYPES |
#define | __R volatile const uint32_t |
#define | __W volatile uint32_t |
#define | __RW volatile uint32_t |
#define | EF_SPI_CFG_REG_CPOL_BIT ((uint32_t)0) |
#define | EF_SPI_CFG_REG_CPOL_MASK ((uint32_t)0x1) |
#define | EF_SPI_CFG_REG_CPHA_BIT ((uint32_t)1) |
#define | EF_SPI_CFG_REG_CPHA_MASK ((uint32_t)0x2) |
#define | EF_SPI_CTRL_REG_SS_BIT ((uint32_t)0) |
#define | EF_SPI_CTRL_REG_SS_MASK ((uint32_t)0x1) |
#define | EF_SPI_CTRL_REG_ENABLE_BIT ((uint32_t)1) |
#define | EF_SPI_CTRL_REG_ENABLE_MASK ((uint32_t)0x2) |
#define | EF_SPI_CTRL_REG_RX_EN_BIT ((uint32_t)2) |
#define | EF_SPI_CTRL_REG_RX_EN_MASK ((uint32_t)0x4) |
#define | EF_SPI_STATUS_REG_TX_E_BIT ((uint32_t)0) |
#define | EF_SPI_STATUS_REG_TX_E_MASK ((uint32_t)0x1) |
#define | EF_SPI_STATUS_REG_TX_F_BIT ((uint32_t)1) |
#define | EF_SPI_STATUS_REG_TX_F_MASK ((uint32_t)0x2) |
#define | EF_SPI_STATUS_REG_RX_E_BIT ((uint32_t)2) |
#define | EF_SPI_STATUS_REG_RX_E_MASK ((uint32_t)0x4) |
#define | EF_SPI_STATUS_REG_RX_F_BIT ((uint32_t)3) |
#define | EF_SPI_STATUS_REG_RX_F_MASK ((uint32_t)0x8) |
#define | EF_SPI_STATUS_REG_TX_B_BIT ((uint32_t)4) |
#define | EF_SPI_STATUS_REG_TX_B_MASK ((uint32_t)0x10) |
#define | EF_SPI_STATUS_REG_RX_A_BIT ((uint32_t)5) |
#define | EF_SPI_STATUS_REG_RX_A_MASK ((uint32_t)0x20) |
#define | EF_SPI_RX_FIFO_LEVEL_REG_LEVEL_BIT ((uint32_t)0) |
#define | EF_SPI_RX_FIFO_LEVEL_REG_LEVEL_MASK ((uint32_t)0xf) |
#define | EF_SPI_RX_FIFO_THRESHOLD_REG_THRESHOLD_BIT ((uint32_t)0) |
#define | EF_SPI_RX_FIFO_THRESHOLD_REG_THRESHOLD_MASK ((uint32_t)0xf) |
#define | EF_SPI_RX_FIFO_FLUSH_REG_FLUSH_BIT ((uint32_t)0) |
#define | EF_SPI_RX_FIFO_FLUSH_REG_FLUSH_MASK ((uint32_t)0x1) |
#define | EF_SPI_TX_FIFO_LEVEL_REG_LEVEL_BIT ((uint32_t)0) |
#define | EF_SPI_TX_FIFO_LEVEL_REG_LEVEL_MASK ((uint32_t)0xf) |
#define | EF_SPI_TX_FIFO_THRESHOLD_REG_THRESHOLD_BIT ((uint32_t)0) |
#define | EF_SPI_TX_FIFO_THRESHOLD_REG_THRESHOLD_MASK ((uint32_t)0xf) |
#define | EF_SPI_TX_FIFO_FLUSH_REG_FLUSH_BIT ((uint32_t)0) |
#define | EF_SPI_TX_FIFO_FLUSH_REG_FLUSH_MASK ((uint32_t)0x1) |
#define | EF_SPI_TXE_FLAG ((uint32_t)0x1) |
#define | EF_SPI_TXF_FLAG ((uint32_t)0x2) |
#define | EF_SPI_RXE_FLAG ((uint32_t)0x4) |
#define | EF_SPI_RXF_FLAG ((uint32_t)0x8) |
#define | EF_SPI_TXB_FLAG ((uint32_t)0x10) |
#define | EF_SPI_RXA_FLAG ((uint32_t)0x20) |
+Typedefs | |
typedef struct _EF_SPI_TYPE_ | EF_SPI_TYPE |
typedef EF_SPI_TYPE * | EF_SPI_TYPE_PTR |
#define __R volatile const uint32_t | +
#define __RW volatile uint32_t | +
#define __W volatile uint32_t | +
#define EF_SPI_CFG_REG_CPHA_BIT ((uint32_t)1) | +
#define EF_SPI_CFG_REG_CPHA_MASK ((uint32_t)0x2) | +
#define EF_SPI_CFG_REG_CPOL_BIT ((uint32_t)0) | +
#define EF_SPI_CFG_REG_CPOL_MASK ((uint32_t)0x1) | +
#define EF_SPI_CTRL_REG_ENABLE_BIT ((uint32_t)1) | +
#define EF_SPI_CTRL_REG_ENABLE_MASK ((uint32_t)0x2) | +
#define EF_SPI_CTRL_REG_RX_EN_BIT ((uint32_t)2) | +
#define EF_SPI_CTRL_REG_RX_EN_MASK ((uint32_t)0x4) | +
#define EF_SPI_CTRL_REG_SS_BIT ((uint32_t)0) | +
#define EF_SPI_CTRL_REG_SS_MASK ((uint32_t)0x1) | +
#define EF_SPI_RX_FIFO_FLUSH_REG_FLUSH_BIT ((uint32_t)0) | +
#define EF_SPI_RX_FIFO_FLUSH_REG_FLUSH_MASK ((uint32_t)0x1) | +
#define EF_SPI_RX_FIFO_LEVEL_REG_LEVEL_BIT ((uint32_t)0) | +
#define EF_SPI_RX_FIFO_LEVEL_REG_LEVEL_MASK ((uint32_t)0xf) | +
#define EF_SPI_RX_FIFO_THRESHOLD_REG_THRESHOLD_BIT ((uint32_t)0) | +
#define EF_SPI_RX_FIFO_THRESHOLD_REG_THRESHOLD_MASK ((uint32_t)0xf) | +
#define EF_SPI_RXA_FLAG ((uint32_t)0x20) | +
#define EF_SPI_RXE_FLAG ((uint32_t)0x4) | +
#define EF_SPI_RXF_FLAG ((uint32_t)0x8) | +
#define EF_SPI_STATUS_REG_RX_A_BIT ((uint32_t)5) | +
#define EF_SPI_STATUS_REG_RX_A_MASK ((uint32_t)0x20) | +
#define EF_SPI_STATUS_REG_RX_E_BIT ((uint32_t)2) | +
#define EF_SPI_STATUS_REG_RX_E_MASK ((uint32_t)0x4) | +
#define EF_SPI_STATUS_REG_RX_F_BIT ((uint32_t)3) | +
#define EF_SPI_STATUS_REG_RX_F_MASK ((uint32_t)0x8) | +
#define EF_SPI_STATUS_REG_TX_B_BIT ((uint32_t)4) | +
#define EF_SPI_STATUS_REG_TX_B_MASK ((uint32_t)0x10) | +
#define EF_SPI_STATUS_REG_TX_E_BIT ((uint32_t)0) | +
#define EF_SPI_STATUS_REG_TX_E_MASK ((uint32_t)0x1) | +
#define EF_SPI_STATUS_REG_TX_F_BIT ((uint32_t)1) | +
#define EF_SPI_STATUS_REG_TX_F_MASK ((uint32_t)0x2) | +
#define EF_SPI_TX_FIFO_FLUSH_REG_FLUSH_BIT ((uint32_t)0) | +
#define EF_SPI_TX_FIFO_FLUSH_REG_FLUSH_MASK ((uint32_t)0x1) | +
#define EF_SPI_TX_FIFO_LEVEL_REG_LEVEL_BIT ((uint32_t)0) | +
#define EF_SPI_TX_FIFO_LEVEL_REG_LEVEL_MASK ((uint32_t)0xf) | +
#define EF_SPI_TX_FIFO_THRESHOLD_REG_THRESHOLD_BIT ((uint32_t)0) | +
#define EF_SPI_TX_FIFO_THRESHOLD_REG_THRESHOLD_MASK ((uint32_t)0xf) | +
#define EF_SPI_TXB_FLAG ((uint32_t)0x10) | +
#define EF_SPI_TXE_FLAG ((uint32_t)0x1) | +
#define EF_SPI_TXF_FLAG ((uint32_t)0x2) | +
#define IO_TYPES | +
typedef struct _EF_SPI_TYPE_ EF_SPI_TYPE | +
typedef EF_SPI_TYPE* EF_SPI_TYPE_PTR | +
+ EF_SPI APIs
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+ EF_SPI APIs
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C_EF_SPI_TYPE_ |
+ EF_SPI APIs
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+ EF_SPI APIs
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EF_Driver_Common.h | C header file for common driver definitions and types |
EF_SPI.c | C file for SPI APIs which contains the function Implementations |
EF_SPI.h | C header file for SPI APIs which contains the function prototypes |
EF_SPI_regs.h |
+ EF_SPI APIs
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+ EF_SPI APIs
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+ EF_SPI APIs
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+ EF_SPI APIs
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+ EF_SPI APIs
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+ EF_SPI APIs
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+ EF_SPI APIs
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