From 786a080bb94803bf698807d156d9e0d54e016b8d Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Mon, 13 Jan 2025 17:43:11 +0200 Subject: [PATCH] run documentation with latest buswrap updates --- README.md | 19 +++++++++++-------- verify/README.md | 21 ++++----------------- 2 files changed, 15 insertions(+), 25 deletions(-) diff --git a/README.md b/README.md index 91dab43..4885a01 100644 --- a/README.md +++ b/README.md @@ -206,9 +206,9 @@ The following are the bit definitions for the interrupt registers: |4|TXB|1|Transmit FIFO level is Below Threshold.| |5|RXA|1|Receive FIFO level is Above Threshold.| ### Clock Gating -The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_util_gating_cell``, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the cell operates with a behavioral implementation, but when the ``CLKG_SKY130_HD`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used. +The IP includes a clock gating feature that allows selective activation and deactivation of the clock using the ``GCLK`` register. This capability is implemented through the ``ef_util_gating_cell`` module, which is part of the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the clock gating is disabled. To enable behavioral implmentation clock gating, only for simulation purposes, you should define the ``CLKG_GENERIC`` macro. Alternatively, define the ``CLKG_SKY130_HD`` macro if you wish to use the SKY130 HD library clock gating cell, ``sky130_fd_sc_hd__dlclkp_4``. -**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to add the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update the YAML configuration file as follows: +**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to enable the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update OpenLane2 YAML configuration file as follows: ``` VERILOG_DEFINES: - CLKG_SKY130_HD @@ -261,10 +261,13 @@ VERILOG_DEFINES: Firmware drivers for EF_SPI can be found in the [fw](https://github.com/efabless/EF_SPI/tree/main/fw) directory. EF_SPI driver documentation is available [here](https://github.com/efabless/EF_SPI/blob/main/fw/README.md). You can also find an example C application using the EF_SPI drivers [here](). ## Installation: -You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager -* To clone repo: -```git clone https://github.com/efabless/EF_SPI``` -> **Note:** If you choose this method, you need to clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, as it includes required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v) -* To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run -```ipm install EF_SPI``` +You can install the IP either by cloning this repository or by using [IPM](https://github.com/efabless/IPM). +##### 1. Using [IPM](https://github.com/efabless/IPM): +- [Optional] If you do not have IPM installed, follow the installation guide [here](https://github.com/efabless/IPM/blob/main/README.md) +- After installing IPM, execute the following command ```ipm install EF_SPI```. > **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency. +##### 2. Cloning this repo: +- Clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, which includes the required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). +```git clone https://github.com/efabless/EF_IP_UTIL.git``` +- Clone the IP repository +```git clone github.com/efabless/EF_SPI``` diff --git a/verify/README.md b/verify/README.md index 79a7572..303ccf1 100644 --- a/verify/README.md +++ b/verify/README.md @@ -3,29 +3,16 @@ In IP directory run: ```shell cd verify/uvm-python/ ``` - ##### To run testbench for design with APB + ##### To run testbench for design with certain bus type To run all tests: ```shell - make run_all_tests BUS_TYPE=APB + make run_all_tests BUS_TYPE= ``` To run a certain test: ```shell - make run_ BUS_TYPE=APB + make run_ BUS_TYPE= ``` To run all tests with a tag: ```shell - make run_all_tests TAG= BUS_TYPE=APB + make run_all_tests TAG= BUS_TYPE= ``` - ##### To run testbench for design with APB - To run all tests: - ```shell - make run_all_tests BUS_TYPE=AHB - ``` - To run a certain test: - ```shell - make run_ BUS_TYPE=AHB - ``` - To run all tests with a tag: - ```shell - make run_all_tests TAG= BUS_TYPE=AHB -```