diff --git a/EF_SPI.yaml b/EF_SPI.yaml index cbb0e56..713e5b1 100644 --- a/EF_SPI.yaml +++ b/EF_SPI.yaml @@ -140,7 +140,7 @@ external_interface: width: 1 direction: input description: SPI Master In Slave Out. - sync: True + sync: False - name: mosi port: mosi width: 1 diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v index d4e9a6b..13cae82 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v @@ -104,6 +104,10 @@ module EF_SPI_AHBL #( CDW = 8, FAW = 4 ) ( + + + + input wire HCLK, input wire HRESETn, input wire HWRITE, @@ -138,7 +142,21 @@ module EF_SPI_AHBL #( localparam MIS_REG_OFFSET = 16'hFF04; localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - wire clk = HCLK; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(HCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = HRESETn; @@ -251,6 +269,11 @@ module EF_SPI_AHBL #( else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG; + localparam GCLK_REG_OFFSET = 16'hFF10; + always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0; + else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET)) + GCLK_REG <= HWDATA[1-1:0]; + reg [5:0] IM_REG; reg [5:0] IC_REG; reg [5:0] RIS_REG; @@ -347,6 +370,7 @@ module EF_SPI_AHBL #( (last_HADDR[16-1:0] == MIS_REG_OFFSET) ? MIS_REG : (last_HADDR[16-1:0] == RIS_REG_OFFSET) ? RIS_REG : (last_HADDR[16-1:0] == IC_REG_OFFSET) ? IC_REG : + (last_HADDR[16-1:0] == GCLK_REG_OFFSET) ? GCLK_REG : 32'hDEADBEEF; assign HREADYOUT = 1'b1; diff --git a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v index 0d05325..bbd0711 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_AHBL.v @@ -31,6 +31,10 @@ module EF_SPI_AHBL #( CDW = 8, FAW = 4 ) ( +`ifdef USE_POWER_PINS + inout VPWR, + inout VGND, +`endif `AHBL_SLAVE_PORTS, input wire [1-1:0] miso, output wire [1-1:0] mosi, @@ -54,7 +58,21 @@ module EF_SPI_AHBL #( localparam MIS_REG_OFFSET = `AHBL_AW'hFF04; localparam RIS_REG_OFFSET = `AHBL_AW'hFF08; localparam IC_REG_OFFSET = `AHBL_AW'hFF0C; - wire clk = HCLK; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(HCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = HRESETn; @@ -133,6 +151,9 @@ module EF_SPI_AHBL #( assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0]; `AHBL_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0) + localparam GCLK_REG_OFFSET = `AHBL_AW'hFF10; + `AHBL_REG(GCLK_REG, 0, 1) + reg [5:0] IM_REG; reg [5:0] IC_REG; reg [5:0] RIS_REG; @@ -224,6 +245,7 @@ module EF_SPI_AHBL #( (last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET) ? MIS_REG : (last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET) ? RIS_REG : (last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET) ? IC_REG : + (last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET) ? GCLK_REG : 32'hDEADBEEF; assign HREADYOUT = 1'b1; diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v index 1b26145..6e66e07 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v @@ -102,10 +102,10 @@ module EF_SPI_APB #( CDW = 8, FAW = 4 ) ( -`ifdef USE_POWER_PINS - inout VPWR, - inout VGND, -`endif + + + + input wire PCLK, input wire PRESETn, input wire PWRITE, @@ -140,27 +140,20 @@ module EF_SPI_APB #( localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - reg [0:0] GCLK_REG; - wire clk_g; - wire clk_gated_en = GCLK_REG[0]; - - `ifdef FPGA - wire clk = PCLK; - `else - (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - `endif - .GCLK(clk_g), - .GATE(clk_gated_en), - .CLK(PCLK) - ); - - wire clk = clk_g; - `endif + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(PCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = PRESETn; @@ -310,17 +303,6 @@ module EF_SPI_APB #( assign IRQ = |MIS_REG; - reg [0:0] _miso_reg_[1:0]; - wire _miso_w_ = _miso_reg_[1]; - always@(posedge PCLK or negedge PRESETn) - if(PRESETn == 0) begin - _miso_reg_[0] <= 'b0; - _miso_reg_[1] <= 'b0; - end - else begin - _miso_reg_[0] <= miso; - _miso_reg_[1] <= _miso_reg_[0]; - end EF_SPI #( .CDW(CDW), .FAW(FAW) @@ -349,7 +331,7 @@ module EF_SPI_APB #( .tx_level(tx_level), .ss(ss), .enable(enable), - .miso(_miso_w_), + .miso(miso), .mosi(mosi), .csb(csb), .sclk(sclk) diff --git a/hdl/rtl/bus_wrappers/EF_SPI_APB.v b/hdl/rtl/bus_wrappers/EF_SPI_APB.v index 0d3e274..7ed1195 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_APB.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_APB.v @@ -59,27 +59,20 @@ module EF_SPI_APB #( localparam RIS_REG_OFFSET = `APB_AW'hFF08; localparam IC_REG_OFFSET = `APB_AW'hFF0C; - reg [0:0] GCLK_REG; - wire clk_g; - wire clk_gated_en = GCLK_REG[0]; - - `ifdef FPGA - wire clk = PCLK; - `else - (* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate( - `ifdef USE_POWER_PINS - .VPWR(VPWR), - .VGND(VGND), - .VNB(VGND), - .VPB(VPWR), - `endif - .GCLK(clk_g), - .GATE(clk_gated_en), - .CLK(PCLK) - ); - - wire clk = clk_g; - `endif + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(PCLK), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = PRESETn; @@ -201,17 +194,6 @@ module EF_SPI_APB #( assign IRQ = |MIS_REG; - reg [0:0] _miso_reg_[1:0]; - wire _miso_w_ = _miso_reg_[1]; - always@(posedge PCLK or negedge PRESETn) - if(PRESETn == 0) begin - _miso_reg_[0] <= 'b0; - _miso_reg_[1] <= 'b0; - end - else begin - _miso_reg_[0] <= miso; - _miso_reg_[1] <= _miso_reg_[0]; - end EF_SPI #( .CDW(CDW), .FAW(FAW) @@ -240,7 +222,7 @@ module EF_SPI_APB #( .tx_level(tx_level), .ss(ss), .enable(enable), - .miso(_miso_w_), + .miso(miso), .mosi(mosi), .csb(csb), .sclk(sclk) diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v index 3e16ec2..4bfc6db 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v @@ -81,6 +81,10 @@ module EF_SPI_WB #( CDW = 8, FAW = 4 ) ( + + + + input wire ext_clk, input wire clk_i, input wire rst_i, @@ -93,10 +97,10 @@ module EF_SPI_WB #( output reg ack_o, input wire we_i, output wire IRQ, - input wire [1-1:0] miso, - output wire [1-1:0] mosi, - output wire [1-1:0] csb, - output wire [1-1:0] sclk + input wire [1-1:0] miso, + output wire [1-1:0] mosi, + output wire [1-1:0] csb, + output wire [1-1:0] sclk ); localparam RXDATA_REG_OFFSET = 16'h0000; @@ -115,7 +119,21 @@ module EF_SPI_WB #( localparam MIS_REG_OFFSET = 16'hFF04; localparam RIS_REG_OFFSET = 16'hFF08; localparam IC_REG_OFFSET = 16'hFF0C; - wire clk = clk_i; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + + + + // USE_POWER_PINS + .clk(clk_i), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = (~rst_i); @@ -197,6 +215,9 @@ module EF_SPI_WB #( assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0]; always @(posedge clk_i or posedge rst_i) if(rst_i) TX_FIFO_FLUSH_REG <= 0; else if(wb_we & (adr_i[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET)) TX_FIFO_FLUSH_REG <= dat_i[1-1:0]; else TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG; + localparam GCLK_REG_OFFSET = 16'hFF10; + always @(posedge clk_i or posedge rst_i) if(rst_i) GCLK_REG <= 0; else if(wb_we & (adr_i[16-1:0]==GCLK_REG_OFFSET)) GCLK_REG <= dat_i[1-1:0]; + reg [5:0] IM_REG; reg [5:0] IC_REG; reg [5:0] RIS_REG; diff --git a/hdl/rtl/bus_wrappers/EF_SPI_WB.v b/hdl/rtl/bus_wrappers/EF_SPI_WB.v index 53c36bd..11b4ce1 100644 --- a/hdl/rtl/bus_wrappers/EF_SPI_WB.v +++ b/hdl/rtl/bus_wrappers/EF_SPI_WB.v @@ -31,6 +31,10 @@ module EF_SPI_WB #( CDW = 8, FAW = 4 ) ( +`ifdef USE_POWER_PINS + inout VPWR, + inout VGND, +`endif `WB_SLAVE_PORTS, input wire [1-1:0] miso, output wire [1-1:0] mosi, @@ -54,7 +58,21 @@ module EF_SPI_WB #( localparam MIS_REG_OFFSET = `WB_AW'hFF04; localparam RIS_REG_OFFSET = `WB_AW'hFF08; localparam IC_REG_OFFSET = `WB_AW'hFF0C; - wire clk = clk_i; + + reg [0:0] GCLK_REG; + wire clk_g; + wire clk_gated_en = GCLK_REG[0]; + ef_gating_cell clk_gate_cell( + `ifdef USE_POWER_PINS + .vpwr(VPWR), + .vgnd(VGND), + `endif // USE_POWER_PINS + .clk(clk_i), + .clk_en(clk_gated_en), + .clk_o(clk_g) + ); + + wire clk = clk_g; wire rst_n = (~rst_i); @@ -133,6 +151,9 @@ module EF_SPI_WB #( assign tx_flush = TX_FIFO_FLUSH_REG[0 : 0]; `WB_REG_AC(TX_FIFO_FLUSH_REG, 0, 1, 1'h0) + localparam GCLK_REG_OFFSET = `WB_AW'hFF10; + `WB_REG(GCLK_REG, 0, 1) + reg [5:0] IM_REG; reg [5:0] IC_REG; reg [5:0] RIS_REG; diff --git a/ip/.gitignore b/ip/.gitignore new file mode 100644 index 0000000..83fe78c --- /dev/null +++ b/ip/.gitignore @@ -0,0 +1,3 @@ +* +!dependencies.json +!.gitignore diff --git a/ip/dependencies.json b/ip/dependencies.json new file mode 100644 index 0000000..bc86f84 --- /dev/null +++ b/ip/dependencies.json @@ -0,0 +1,7 @@ +{ + "IP": [ + { + "IP_Utilities": "v1.0.0" + } + ] +} \ No newline at end of file diff --git a/verify/uvm-python/Makefile b/verify/uvm-python/Makefile index a9ad402..7afddfc 100644 --- a/verify/uvm-python/Makefile +++ b/verify/uvm-python/Makefile @@ -4,7 +4,7 @@ MODULE ?= top_module AHB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_AHBL.pp.v APB_FILES ?= $(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_APB.pp.v WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_SPI_WB.pp.v -HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v +HDL_FILES ?= $(PWD)/../../ip/IP_Utilities/rtl/aucohl_lib.v $(PWD)/../../ip/IP_Utilities/rtl/aucohl_rtl.vh $(PWD)/../../hdl/rtl/spi_master.v $(PWD)/../../hdl/rtl/EF_SPI.v VERILOG_SOURCES ?= $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES) RTL_MACROS += "" diff --git a/verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py b/verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py index d51961c..fb36d33 100644 --- a/verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_MOSI_MISO_seq.py @@ -36,6 +36,7 @@ def __init__( async def body(self): await super().body() + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) if not self.disable_control: await self.send_req( is_write=True, reg="CTRL", data_condition=lambda data: data == 0b0 diff --git a/verify/uvm-python/spi_seq_lib/spi_rx_dis_seq.py b/verify/uvm-python/spi_seq_lib/spi_rx_dis_seq.py index f60c4ea..c1d022d 100644 --- a/verify/uvm-python/spi_seq_lib/spi_rx_dis_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_rx_dis_seq.py @@ -32,6 +32,7 @@ async def body(self): # Add the sequqnce here # you could use method send_req to send a write or read using the register name # example for writing register by value > 5 + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.send_req( is_write=True, reg="CTRL", data_condition=lambda data: data == 0b011 ) diff --git a/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py b/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py index c3eec89..923c214 100644 --- a/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_send_MISO_seq.py @@ -30,6 +30,7 @@ async def body(self): # Add the sequqnce here # you could use method send_req to send a write or read using the register name # example for writing register by value > 5 + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.send_req( is_write=True, reg="CTRL", data_condition=lambda data: data == 0b111 ) diff --git a/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py b/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py index fb28dcb..23cd30c 100644 --- a/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py +++ b/verify/uvm-python/spi_seq_lib/spi_send_MOSI_seq.py @@ -30,6 +30,7 @@ async def body(self): # Add the sequqnce here # you could use method send_req to send a write or read using the register name # example for writing register by value > 5 + await self.send_req(is_write=True, reg="CLKGATE", data_condition=lambda data: data == 1) await self.send_req( is_write=True, reg="CTRL", data_condition=lambda data: data == 0b11 )