Configs.md

Rocket/coreplex/Configs

Config a core complex.

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class BaseCoreplexConfig

Default configuration for a core complex which may contain multiple homogeneous cores.

Tile parameters

• PAddrBits Int width of physical addresses.
• PgLevels Int number of page levels (Sv48:4, Sv39:3, Sv32:2).
• ASIdBits Int size of ASID (address space identifier, used in related to virtual memory).
• XLen Int size of default machine word (32/64).
• ResetVectorBits Int
  The reset address after power on is an input port to a tile. Here defines the width of this reset address.
• MaxHartIdBits Int digits needed to store hartid in hardware.
• BuildCore (Parameters) => CoreModule with HasCoreIO generation function to get a core for the complex.
• RocketTilesKey Seq[RocketTileParams] (lazy) the parameters for the cores inside the complex.

Interconnect parameters

• RocketCrossing CoreplexClockCrossing a parameter class to define the clock domain crossing (synchronous, asynchronous, rational).
• BroadcastParams BroadcastParams a parameter class to define the broadcasting coherence hub if it is chosen.
• BankedL2Params BankedL2Params a parameter class to define the banked L2 coherent cache if it is chosen.
• SystemBusParams SystemBusParams a parameter class to define the system bus (coherent bus for memory?).
• PeripheryBusParams PeripheryBusParams a parameter class to define the peripherial bus.
• MemoryBusParams MemoryBusParams a parameter class to define the memory bus at the backend of last level cache.
• CacheBlockBytes Int size of a cache block (nearly always set to 64).

Device parameters

• DebugModuleParams DebugModuleParams a parameter class to define the debug module.
• PLICParams PLICParams a parameter class to define the platform level interrupt controller.
• ClintParams ClintParams a parameter class to define the coreplex local interrupts (timer, software interrupts).

TileLink connection global parameters

• TLMonitorBuilder (TLMonitorArgs) => Option[TLMonitorBase]
  TileLink bus monitor generator which can also be sued to disable bus monitor altogether.
• TLCombinationalCheck Boolean
  Whether to enable simulation time combinational check on TileLink channels (ready generated by valid and then form a loop).

_{Last updated: 26/07/2017
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