From 2799596ffc8bed3eeb2195baa8d2a2fdc085d4ad Mon Sep 17 00:00:00 2001 From: Bhavin Umatiya Date: Tue, 24 Dec 2024 14:24:41 +0530 Subject: [PATCH] fixe #2278 --- .vscode/launch.json | 39 ++++++++++++++++++++++ verible/verilog/analysis/descriptions.h | 24 +++++++------ verible/verilog/analysis/verilog-linter.cc | 9 ++++- 3 files changed, 60 insertions(+), 12 deletions(-) create mode 100644 .vscode/launch.json diff --git a/.vscode/launch.json b/.vscode/launch.json new file mode 100644 index 000000000..3af66b728 --- /dev/null +++ b/.vscode/launch.json @@ -0,0 +1,39 @@ +{ + // Use IntelliSense to learn about possible attributes. + // Hover to view descriptions of existing attributes. + // For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 + "version": "0.2.0", + "configurations": [ + { + "name": "(gdb) Attach", + "type": "cppdbg", + "request": "attach", + "program": "enter program name, for example ${workspaceFolder}/a.exe", + "MIMode": "gdb", + "miDebuggerPath": "/path/to/gdb", + "setupCommands": [ + { + "description": "Enable pretty-printing for gdb", + "text": "-enable-pretty-printing", + "ignoreFailures": true + }, + { + "description": "Set Disassembly Flavor to Intel", + "text": "-gdb-set disassembly-flavor intel", + "ignoreFailures": true + } + ] + }, + { + "name": "(Windows) Launch", + "type": "cppvsdbg", + "request": "launch", + "program": "enter program name, for example ${workspaceFolder}/a.exe", + "args": [], + "stopAtEntry": false, + "cwd": "${fileDirname}", + "environment": [], + "console": "externalTerminal" + } + ] +} \ No newline at end of file diff --git a/verible/verilog/analysis/descriptions.h b/verible/verilog/analysis/descriptions.h index 973e28a3f..502dbf524 100644 --- a/verible/verilog/analysis/descriptions.h +++ b/verible/verilog/analysis/descriptions.h @@ -35,14 +35,16 @@ struct LintConfigParameterDescriptor { std::string description; }; -struct LintRuleDescriptor { - LintRuleId name; // ID/name of the rule. - absl::string_view topic; // section in style-guide - std::string desc; // Detailed description. - std::vector param; -}; - -} // namespace analysis -} // namespace verilog - -#endif // VERIBLE_VERILOG_ANALYSIS_DESCRIPTIONS_H_ +std::string format_long_description(const std::string& description) { + const size_t max_length = 80; + std::string formatted_desc; + size_t start = 0; + + while (start < description.size()) { + size_t end = std::min(start + max_length, description.size()); + formatted_desc += description.substr(start, end - start) + "\n "; + start = end; + } + + return formatted_desc; +} diff --git a/verible/verilog/analysis/verilog-linter.cc b/verible/verilog/analysis/verilog-linter.cc index 84d4431e1..e7a70aaa5 100644 --- a/verible/verilog/analysis/verilog-linter.cc +++ b/verible/verilog/analysis/verilog-linter.cc @@ -360,7 +360,8 @@ absl::Status PrintRuleInfo(std::ostream *os, } void GetLintRuleDescriptionsHelpFlag(std::ostream *os, - absl::string_view flag_value) { + absl::string_view flag_value, + bool verbose) { // Set up the map. auto rule_map = analysis::GetAllRuleDescriptions(); for (const auto &rule_id : analysis::kDefaultRuleSet) { @@ -380,9 +381,15 @@ void GetLintRuleDescriptionsHelpFlag(std::ostream *os, *os << status.message(); return; } + + // If verbose flag is set, print example for the rule + if (verbose) { + *os << "\nExample: " << rule.second.GetExample() << "\n"; // Assuming rule.second has GetExample() + } } } + void GetLintRuleFile(std::ostream *os, const LinterConfiguration &config) { // This rule bundle contains only a list of enabled rules. There // are also no param's defined (an empty string), unless the user