value emitVerilog is not a member of circt.stage.ChiselStage

[quantrpeter]

Hi
I got trouble to generate verilog, i got this error:

[info] welcome to sbt 1.10.1 (Oracle Corporation Java 23.0.1)
[info] loading project definition from /Users/peter/workspace/chisel-examples/hello-world/project

[info] loading settings for project hello-world from build.sbt ...
[info] set current project to hello-world (in build file:/Users/peter/workspace/chisel-examples/hello-world/)
[info] compiling 1 Scala source to /Users/peter/workspace/chisel-examples/hello-world/target/scala-2.13/classes ...
[error] /Users/peter/workspace/chisel-examples/hello-world/src/main/scala/Hello.scala:35:20: value emitVerilog is not a member of circt.stage.ChiselStage
[error]         new ChiselStage().emitVerilog(new Hello);
[error]                           ^
[error] one error found
[error] (Compile / compileIncremental) Compilation failed

new ChiselStage().emitVerilog(new Hello);

scalaVersion := "2.13.12"

scalacOptions ++= Seq(
  "-feature",
  "-language:reflectiveCalls",
)

// Chisel 3.5
// addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % "6.0.0" cross CrossVersion.full)
// libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "6.0.0"
// libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0"

val chiselVersion = "6.0.0"
addCompilerPlugin("org.chipsalliance" % "chisel-plugin" % chiselVersion cross CrossVersion.full)
libraryDependencies += "org.chipsalliance" %% "chisel" % chiselVersion
libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.6.0" % "test"

thanks