diff --git a/frontends/systolic-lang/gen_array_component.py b/frontends/systolic-lang/gen_array_component.py
index ab2ca39b3f..a3f9070f9a 100644
--- a/frontends/systolic-lang/gen_array_component.py
+++ b/frontends/systolic-lang/gen_array_component.py
@@ -246,23 +246,28 @@ def get_pe_invoke(r, c, mul_ready):
     )
 
 
-def init_iter_limit(comp: cb.ComponentBuilder, depth_port, partial_iter_limit):
+def init_iter_limit(
+    comp: cb.ComponentBuilder, depth_port, config: SystolicConfiguration
+):
     """
     Builds group that instantiates the dynamic/runtime values for the systolic
     array: its depth and iteration limit/count (since its iteration limit depends on
     its depth).
     iteration limit = depth + partial_iter_limit
     """
-    iter_limit = comp.reg("iter_limit", BITWIDTH)
-    iter_limit_add = comp.add(BITWIDTH, "iter_limit_add")
-    with comp.static_group("init_iter_limit", 1):
-        iter_limit_add.left = partial_iter_limit
-        iter_limit_add.right = depth_port
-        iter_limit.in_ = iter_limit_add.out
-        iter_limit.write_en = 1
+    # Only need to initalize this group if
+    if not config.static:
+        partial_iter_limit = config.top_length + config.left_length + 4
+        iter_limit = comp.reg("iter_limit", BITWIDTH)
+        iter_limit_add = comp.add(BITWIDTH, "iter_limit_add")
+        with comp.static_group("init_iter_limit", 1):
+            iter_limit_add.left = partial_iter_limit
+            iter_limit_add.right = depth_port
+            iter_limit.in_ = iter_limit_add.out
+            iter_limit.write_en = 1
 
 
-def instantiate_idx_groups(comp: cb.ComponentBuilder):
+def instantiate_idx_groups(comp: cb.ComponentBuilder, config: SystolicConfiguration):
     """
     Builds groups that instantiate idx to 0 and increment idx.
     Also builds groups that set cond_reg to 1 (runs before the while loop)
@@ -270,8 +275,6 @@ def instantiate_idx_groups(comp: cb.ComponentBuilder):
     """
     idx = comp.reg("idx", BITWIDTH)
     add = comp.add(BITWIDTH, "idx_add")
-    iter_limit = comp.get_cell("iter_limit")
-    lt_iter_limit = comp.lt(BITWIDTH, "lt_iter_limit")
 
     with comp.static_group("init_idx", 1):
         idx.in_ = 0
@@ -281,9 +284,12 @@ def instantiate_idx_groups(comp: cb.ComponentBuilder):
         add.right = 1
         idx.in_ = add.out
         idx.write_en = 1
-    with comp.continuous:
-        lt_iter_limit.left = idx.out
-        lt_iter_limit.right = iter_limit.out
+    if not config.static:
+        iter_limit = comp.get_cell("iter_limit")
+        lt_iter_limit = comp.lt(BITWIDTH, "lt_iter_limit")
+        with comp.continuous:
+            lt_iter_limit.left = idx.out
+            lt_iter_limit.right = iter_limit.out
 
 
 def instantiate_calyx_adds(comp, nec_ranges) -> list:
@@ -396,8 +402,22 @@ def gen_schedules(
     `pe_write_sched` contains when to "write" the PE value into the output ports
     (e.g., this.r0_valid)
     """
+
+    def depth_plus_const(const: int):
+        """
+        Returns depth + const. If config.static, then this is an int.
+        Otherwise, we need to perform a Calyx addition to figure this out.
+        """
+        if config.static:
+            # return an int
+            return config.get_contraction_dimension() + const
+        else:
+            # return a CalyxAdd object, whose value is determined after generation
+            depth_port = comp.this().depth
+            return CalyxAdd(depth_port, const)
+
     left_length, top_length = config.left_length, config.top_length
-    depth_port = comp.this().depth
+
     schedules = {}
     update_sched = np.zeros((left_length, top_length), dtype=object)
     pe_fill_sched = np.zeros((left_length, top_length), dtype=object)
@@ -407,13 +427,13 @@ def gen_schedules(
     for row in range(0, left_length):
         for col in range(0, top_length):
             pos = row + col
-            update_sched[row][col] = (pos, CalyxAdd(depth_port, pos))
+            update_sched[row][col] = (pos, depth_plus_const(pos))
             pe_fill_sched[row][col] = (pos + 1, pos + 5)
-            pe_accum_sched[row][col] = (pos + 5, CalyxAdd(depth_port, pos + 5))
-            pe_move_sched[row][col] = (pos + 1, CalyxAdd(depth_port, pos + 1))
+            pe_accum_sched[row][col] = (pos + 5, depth_plus_const(pos + 5))
+            pe_move_sched[row][col] = (pos + 1, depth_plus_const(pos + 1))
             pe_write_sched[row][col] = (
-                CalyxAdd(depth_port, pos + 5),
-                CalyxAdd(depth_port, pos + 6),
+                depth_plus_const(pos + 5),
+                depth_plus_const(pos + 6),
             )
     schedules["update_sched"] = update_sched
     schedules["fill_sched"] = pe_fill_sched
@@ -458,15 +478,12 @@ def generate_control(
     control = []
     top_length, left_length = config.top_length, config.left_length
 
-    # Initialize all memories.
-    control.append(
-        py_ast.StaticParComp(
-            [
-                py_ast.Enable("init_idx"),
-                py_ast.Enable("init_iter_limit"),
-            ]
-        )
-    )
+    # Initialize the idx and iteration_limit.
+    # We only need to initialize iteration_limit for dynamic configurations
+    init_groups = [py_ast.Enable("init_idx")]
+    if not config.static:
+        init_groups += [py_ast.Enable("init_iter_limit")]
+    control.append(py_ast.StaticParComp(init_groups))
 
     # source_pos metadata init
     init_tag = 0
@@ -532,11 +549,16 @@ def counter():
     while_body = py_ast.StaticParComp(while_body_stmts)
 
     # build the while loop with condition cond_reg.
-    cond_reg_port = comp.get_cell("lt_iter_limit").port("out")
-    while_loop = cb.while_(cond_reg_port, while_body)
+    if config.static:
+        while_loop = cb.static_repeat(config.get_iteration_count(), while_body)
+    else:
+        cond_reg_port = comp.get_cell("lt_iter_limit").port("out")
+        while_loop = cb.while_(cond_reg_port, while_body)
 
     control.append(while_loop)
 
+    if config.static:
+        return py_ast.StaticSeqComp(stmts=control), source_map
     return py_ast.SeqComp(stmts=control), source_map
 
 
@@ -551,9 +573,7 @@ def create_systolic_array(prog: cb.Builder, config: SystolicConfiguration):
     computational_unit = prog.component(SYSTOLIC_ARRAY_COMP)
     depth_port = computational_unit.input("depth", BITWIDTH)
     # initialize the iteration limit to top_length + left_length + depth + 4
-    init_iter_limit(
-        computational_unit, depth_port, config.top_length + config.left_length + 4
-    )
+    init_iter_limit(computational_unit, depth_port, config)
 
     schedules = gen_schedules(config, computational_unit)
     nec_ranges = set()
@@ -562,7 +582,7 @@ def create_systolic_array(prog: cb.Builder, config: SystolicConfiguration):
     instantiate_calyx_adds(computational_unit, nec_ranges)
 
     # instantiate groups that handles the idx variables
-    instantiate_idx_groups(computational_unit)
+    instantiate_idx_groups(computational_unit, config)
     list1, list2 = zip(*nec_ranges)
     nec_ranges_beg = set(list1)
     nec_ranges_end = set(list2)
diff --git a/frontends/systolic-lang/systolic_arg_parser.py b/frontends/systolic-lang/systolic_arg_parser.py
index c2461e2f19..0e30d601cf 100644
--- a/frontends/systolic-lang/systolic_arg_parser.py
+++ b/frontends/systolic-lang/systolic_arg_parser.py
@@ -27,6 +27,7 @@ def parse_arguments(self):
         parser.add_argument("-ll", "--left-length", type=int)
         parser.add_argument("-ld", "--left-depth", type=int)
         parser.add_argument("-p", "--post-op", type=str, default=None)
+        parser.add_argument("-s", "--static", action="store_true")
 
         args = parser.parse_args()
 
@@ -37,6 +38,7 @@ def parse_arguments(self):
             self.left_length = args.left_length
             self.left_depth = args.left_depth
             self.post_op = args.post_op
+            self.static = args.static
         elif args.file is not None:
             with open(args.file, "r") as f:
                 spec = json.load(f)
@@ -46,6 +48,8 @@ def parse_arguments(self):
                 self.left_depth = spec["left_depth"]
                 # default to not perform leaky_relu
                 self.post_op = spec.get("post_op", None)
+                # default to non-static (i.e., dynamic contraction dimension)
+                self.static = spec.get("static", False)
         else:
             parser.error(
                 "Need to pass either `FILE` or all of `"
@@ -63,3 +67,27 @@ def get_output_dimensions(self):
         of num_rows x num_cols)
         """
         return (self.left_length, self.top_length)
+
+    def get_contraction_dimension(self):
+        """
+        Returns the contraction dimension
+        """
+        assert (
+            self.left_depth == self.top_depth
+        ), "left_depth and top_depth should be same"
+        # Could have also returend self.top_depth
+        return self.left_depth
+
+    def get_iteration_count(self):
+        """
+        Returns the iteration count if self.static
+        Otherwise throws an error
+        """
+        # Could have also returend self.top_depth
+        if self.static:
+            (num_out_rows, num_out_cols) = self.get_output_dimensions()
+            return self.get_contraction_dimension() + num_out_rows + num_out_cols + 4
+        raise Exception(
+            "Cannot get iteration count for systolic array with dynamic \
+            contraction dimension"
+        )
diff --git a/runt.toml b/runt.toml
index 7ba72defcb..ca25f45b21 100644
--- a/runt.toml
+++ b/runt.toml
@@ -263,12 +263,77 @@ fud e --from systolic --to jq \
 """
 
 [[tests]]
-name = "[frontend] systolic array output correctness"
+name = "[frontend] systolic array mmult static correctness"
+paths = [
+  "tests/correctness/systolic/mmult-inputs/*.data"
+]
+cmd = """
+fud e --from systolic --to jq \
+      --through verilog \
+      --through dat \
+      -s verilog.data {} \
+      -s calyx.exec './target/debug/calyx' \
+      -s calyx.flags "-d well-formed" \
+      -s jq.expr ".memories" \
+      {}_static.systolic -q
+"""
+expect_dir="tests/correctness/systolic/mmult-expect"
+
+[[tests]]
+name = "[frontend] systolic array mmult dynamic correctness"
+paths = [
+  "tests/correctness/systolic/mmult-inputs/*.data"
+]
+cmd = """
+fud e --from systolic --to jq \
+      --through verilog \
+      --through dat \
+      -s verilog.data {} \
+      -s calyx.exec './target/debug/calyx' \
+      -s calyx.flags "-d well-formed" \
+      -s jq.expr ".memories" \
+      {}_dynamic.systolic -q
+"""
+expect_dir="tests/correctness/systolic/mmult-expect"
+
+[[tests]]
+name = "[frontend] systolic array relu static correctness"
+paths = [
+  "tests/correctness/systolic/relu-inputs/*.data"
+]
+cmd = """
+fud e --from systolic --to jq \
+      --through verilog \
+      --through dat \
+      -s verilog.data {} \
+      -s calyx.exec './target/debug/calyx' \
+      -s calyx.flags "-d well-formed" \
+      -s jq.expr ".memories" \
+      {}_static.systolic -q
+"""
+expect_dir="tests/correctness/systolic/relu-expect"
+
+[[tests]]
+name = "[frontend] systolic array relu dynamic correctness"
+paths = [
+  "tests/correctness/systolic/relu-inputs/*.data"
+]
+cmd = """
+fud e --from systolic --to jq \
+      --through verilog \
+      --through dat \
+      -s verilog.data {} \
+      -s calyx.exec './target/debug/calyx' \
+      -s calyx.flags "-d well-formed" \
+      -s jq.expr ".memories" \
+      {}_dynamic.systolic -q
+"""
+expect_dir="tests/correctness/systolic/relu-expect"
+
+[[tests]]
+name = "[frontend] systolic array leaky relu correctness"
 paths = [
-  "tests/correctness/systolic/output/*.systolic",
   "tests/correctness/systolic/leaky-relu/*.systolic",
-  "tests/correctness/systolic/relu/*.systolic",
-  "tests/correctness/systolic/relu-dynamic/*.systolic",
 ]
 cmd = """
 fud e --from systolic --to dat \
diff --git a/tests/correctness/systolic/mmult-expect/array-2-3-4.expect b/tests/correctness/systolic/mmult-expect/array-2-3-4.expect
new file mode 100644
index 0000000000..95f7bf1c2c
--- /dev/null
+++ b/tests/correctness/systolic/mmult-expect/array-2-3-4.expect
@@ -0,0 +1,44 @@
+{
+  "l0": [
+    "-1.5258636474609375",
+    "1.37969970703125",
+    "3.964019775390625"
+  ],
+  "l1": [
+    "-4.90814208984375",
+    "1.1556854248046875",
+    "0.088134765625"
+  ],
+  "out_mem_0": [
+    "17.829559326171875",
+    "-14.9852752685546875",
+    "-0.7954864501953125",
+    "-15.9398193359375"
+  ],
+  "out_mem_1": [
+    "13.2156982421875",
+    "-5.021575927734375",
+    "20.450347900390625",
+    "-28.945556640625"
+  ],
+  "t0": [
+    "-3.7752532958984375",
+    "-4.9618072509765625",
+    "4.771636962890625"
+  ],
+  "t1": [
+    "0.8634185791015625",
+    "-0.4265594482421875",
+    "-3.29949951171875"
+  ],
+  "t2": [
+    "-3.8273162841796875",
+    "1.6114501953125",
+    "-2.2347869873046875"
+  ],
+  "t3": [
+    "4.7815093994140625",
+    "-4.69775390625",
+    "-0.545501708984375"
+  ]
+}
diff --git a/tests/correctness/systolic/mmult-expect/array-8.expect b/tests/correctness/systolic/mmult-expect/array-8.expect
new file mode 100644
index 0000000000..7730da7203
--- /dev/null
+++ b/tests/correctness/systolic/mmult-expect/array-8.expect
@@ -0,0 +1,242 @@
+{
+  "l0": [
+    "3.3614654541015625",
+    "3.7810211181640625",
+    "-0.6595458984375",
+    "-2.00933837890625",
+    "-1.07269287109375",
+    "-1.7359161376953125",
+    "-2.23175048828125",
+    "3.242584228515625"
+  ],
+  "l1": [
+    "-3.66552734375",
+    "1.862274169921875",
+    "-4.5985107421875",
+    "1.737396240234375",
+    "1.5211181640625",
+    "2.481170654296875",
+    "4.3662261962890625",
+    "-4.712066650390625"
+  ],
+  "l2": [
+    "-0.1986236572265625",
+    "3.6620941162109375",
+    "-3.45025634765625",
+    "1.60711669921875",
+    "-4.554595947265625",
+    "1.3513336181640625",
+    "-3.6712799072265625",
+    "-1.1727142333984375"
+  ],
+  "l3": [
+    "-4.38427734375",
+    "3.6719970703125",
+    "4.325927734375",
+    "3.3654632568359375",
+    "-3.818634033203125",
+    "2.7002716064453125",
+    "0.1087799072265625",
+    "-1.949493408203125"
+  ],
+  "l4": [
+    "3.2269439697265625",
+    "-2.69219970703125",
+    "-3.09112548828125",
+    "-2.3430938720703125",
+    "2.85382080078125",
+    "1.8892059326171875",
+    "-0.634521484375",
+    "2.381866455078125"
+  ],
+  "l5": [
+    "0.4718017578125",
+    "0.8296356201171875",
+    "1.4714813232421875",
+    "3.4707183837890625",
+    "1.939208984375",
+    "-0.3958892822265625",
+    "-4.3639373779296875",
+    "0.86492919921875"
+  ],
+  "l6": [
+    "3.718292236328125",
+    "3.1377716064453125",
+    "1.5491790771484375",
+    "0.18115234375",
+    "-1.0565185546875",
+    "3.2894439697265625",
+    "-1.6756744384765625",
+    "-3.32159423828125"
+  ],
+  "l7": [
+    "0.4992523193359375",
+    "2.626922607421875",
+    "3.8421630859375",
+    "1.6167449951171875",
+    "0.4383544921875",
+    "2.735015869140625",
+    "4.4162750244140625",
+    "-0.7459259033203125"
+  ],
+  "out_mem_0": [
+    "-5.020233154296875",
+    "-17.630950927734375",
+    "-11.7227935791015625",
+    "-23.94586181640625",
+    "-20.5061187744140625",
+    "-18.622161865234375",
+    "19.1900177001953125",
+    "3.65228271484375"
+  ],
+  "out_mem_1": [
+    "21.97125244140625",
+    "47.741729736328125",
+    "5.975616455078125",
+    "-11.5402069091796875",
+    "24.655303955078125",
+    "10.3508758544921875",
+    "-7.2060546875",
+    "-35.2868194580078125"
+  ],
+  "out_mem_2": [
+    "-8.005645751953125",
+    "0.7089080810546875",
+    "-29.03765869140625",
+    "10.0974273681640625",
+    "-4.3226776123046875",
+    "-9.4420166015625",
+    "13.7893524169921875",
+    "-26.162811279296875"
+  ],
+  "out_mem_3": [
+    "-36.066314697265625",
+    "36.6315155029296875",
+    "-54.45623779296875",
+    "23.7673797607421875",
+    "55.8004302978515625",
+    "-17.01385498046875",
+    "-30.425079345703125",
+    "-36.1455841064453125"
+  ],
+  "out_mem_4": [
+    "11.5760345458984375",
+    "-43.1614990234375",
+    "32.2516937255859375",
+    "0.053802490234375",
+    "-51.6582183837890625",
+    "28.627716064453125",
+    "14.7799530029296875",
+    "31.807220458984375"
+  ],
+  "out_mem_5": [
+    "-2.5281982421875",
+    "19.660186767578125",
+    "-6.4005126953125",
+    "-3.746063232421875",
+    "-2.146728515625",
+    "7.682373046875",
+    "-15.31072998046875",
+    "-21.81353759765625"
+  ],
+  "out_mem_6": [
+    "-25.15228271484375",
+    "-9.1671295166015625",
+    "-17.158233642578125",
+    "-8.20404052734375",
+    "-3.4250640869140625",
+    "-17.01971435546875",
+    "19.3945770263671875",
+    "-2.08734130859375"
+  ],
+  "out_mem_7": [
+    "-16.15911865234375",
+    "17.7563323974609375",
+    "-19.4623260498046875",
+    "-7.7472381591796875",
+    "41.1004180908203125",
+    "-1.3080902099609375",
+    "-21.5960693359375",
+    "0.1708831787109375"
+  ],
+  "t0": [
+    "0.6451263427734375",
+    "-1.3166961669921875",
+    "-4.3086700439453125",
+    "2.2447357177734375",
+    "2.0837249755859375",
+    "-3.5662689208984375",
+    "1.9752197265625",
+    "-0.027435302734375"
+  ],
+  "t1": [
+    "-4.8111724853515625",
+    "4.71002197265625",
+    "0.4647674560546875",
+    "4.4236602783203125",
+    "3.9444732666015625",
+    "-3.5243377685546875",
+    "1.02667236328125",
+    "-2.981353759765625"
+  ],
+  "t2": [
+    "1.919586181640625",
+    "-4.0710296630859375",
+    "-2.6121063232421875",
+    "-0.96337890625",
+    "3.7477874755859375",
+    "-1.58636474609375",
+    "0.8641815185546875",
+    "-1.0011138916015625"
+  ],
+  "t3": [
+    "-2.434356689453125",
+    "-4.969268798828125",
+    "0.7401275634765625",
+    "1.02825927734375",
+    "-4.4361114501953125",
+    "3.98602294921875",
+    "-1.322235107421875",
+    "1.4773101806640625"
+  ],
+  "t4": [
+    "-2.4996795654296875",
+    "2.352020263671875",
+    "3.4475860595703125",
+    "4.74420166015625",
+    "-1.9682464599609375",
+    "-1.969635009765625",
+    "4.6419525146484375",
+    "-1.3448333740234375"
+  ],
+  "t5": [
+    "0.34259033203125",
+    "-3.76025390625",
+    "-2.579803466796875",
+    "3.9580230712890625",
+    "1.7683563232421875",
+    "3.40496826171875",
+    "0.968505859375",
+    "3.2888946533203125"
+  ],
+  "t6": [
+    "3.338348388671875",
+    "0.1703338623046875",
+    "-2.088653564453125",
+    "-4.548828125",
+    "-1.3649749755859375",
+    "-1.196014404296875",
+    "-1.540008544921875",
+    "-3.1365966796875"
+  ],
+  "t7": [
+    "4.767669677734375",
+    "-4.9486083984375",
+    "0.883941650390625",
+    "-2.3918609619140625",
+    "-2.087799072265625",
+    "1.2293701171875",
+    "2.376678466796875",
+    "2.2551116943359375"
+  ]
+}
diff --git a/tests/correctness/systolic/output/array-2-3-4.systolic.data b/tests/correctness/systolic/mmult-inputs/array-2-3-4.data
similarity index 100%
rename from tests/correctness/systolic/output/array-2-3-4.systolic.data
rename to tests/correctness/systolic/mmult-inputs/array-2-3-4.data
diff --git a/tests/correctness/systolic/output/array-2-3-4.systolic b/tests/correctness/systolic/mmult-inputs/array-2-3-4.data_dynamic.systolic
similarity index 100%
rename from tests/correctness/systolic/output/array-2-3-4.systolic
rename to tests/correctness/systolic/mmult-inputs/array-2-3-4.data_dynamic.systolic
diff --git a/tests/correctness/systolic/mmult-inputs/array-2-3-4.data_static.systolic b/tests/correctness/systolic/mmult-inputs/array-2-3-4.data_static.systolic
new file mode 100644
index 0000000000..3a7624bf8e
--- /dev/null
+++ b/tests/correctness/systolic/mmult-inputs/array-2-3-4.data_static.systolic
@@ -0,0 +1,7 @@
+{
+  "top_length": 4,
+  "top_depth": 3,
+  "left_length": 2,
+  "left_depth": 3,
+  "static": true
+}
\ No newline at end of file
diff --git a/tests/correctness/systolic/output/array-8.systolic.data b/tests/correctness/systolic/mmult-inputs/array-8.data
similarity index 100%
rename from tests/correctness/systolic/output/array-8.systolic.data
rename to tests/correctness/systolic/mmult-inputs/array-8.data
diff --git a/tests/correctness/systolic/output/array-8.systolic b/tests/correctness/systolic/mmult-inputs/array-8.data_dynamic.systolic
similarity index 100%
rename from tests/correctness/systolic/output/array-8.systolic
rename to tests/correctness/systolic/mmult-inputs/array-8.data_dynamic.systolic
diff --git a/tests/correctness/systolic/mmult-inputs/array-8.data_static.systolic b/tests/correctness/systolic/mmult-inputs/array-8.data_static.systolic
new file mode 100644
index 0000000000..86724f7bb5
--- /dev/null
+++ b/tests/correctness/systolic/mmult-inputs/array-8.data_static.systolic
@@ -0,0 +1,7 @@
+{
+  "top_length": 8,
+  "top_depth": 8,
+  "left_length": 8,
+  "left_depth": 8,
+  "static": true
+}
\ No newline at end of file
diff --git a/tests/correctness/systolic/output/array-2-3-4.expect b/tests/correctness/systolic/output/array-2-3-4.expect
deleted file mode 100644
index ca505ef07e..0000000000
--- a/tests/correctness/systolic/output/array-2-3-4.expect
+++ /dev/null
@@ -1,47 +0,0 @@
-{
-  "cycles": 15,
-  "memories": {
-    "l0": [
-      "-1.5258636474609375",
-      "1.37969970703125",
-      "3.964019775390625"
-    ],
-    "l1": [
-      "-4.90814208984375",
-      "1.1556854248046875",
-      "0.088134765625"
-    ],
-    "out_mem_0": [
-      "17.829559326171875",
-      "-14.9852752685546875",
-      "-0.7954864501953125",
-      "-15.9398193359375"
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-    "out_mem_1": [
-      "13.2156982421875",
-      "-5.021575927734375",
-      "20.450347900390625",
-      "-28.945556640625"
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-    "t0": [
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-    "t3": [
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diff --git a/tests/correctness/systolic/output/array-8.expect b/tests/correctness/systolic/output/array-8.expect
deleted file mode 100644
index 24be67b108..0000000000
--- a/tests/correctness/systolic/output/array-8.expect
+++ /dev/null
@@ -1,245 +0,0 @@
-{
-  "cycles": 30,
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diff --git a/tests/correctness/systolic/relu-dynamic/array-2-3-4.expect b/tests/correctness/systolic/relu-dynamic/array-2-3-4.expect
deleted file mode 100644
index f642045e3b..0000000000
--- a/tests/correctness/systolic/relu-dynamic/array-2-3-4.expect
+++ /dev/null
@@ -1,47 +0,0 @@
-{
-  "cycles": 19,
-  "memories": {
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-}
diff --git a/tests/correctness/systolic/relu-dynamic/array-8.expect b/tests/correctness/systolic/relu-dynamic/array-8.expect
deleted file mode 100644
index d8627be637..0000000000
--- a/tests/correctness/systolic/relu-dynamic/array-8.expect
+++ /dev/null
@@ -1,245 +0,0 @@
-{
-  "cycles": 38,
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diff --git a/tests/correctness/systolic/relu-expect/array-2-3-4.expect b/tests/correctness/systolic/relu-expect/array-2-3-4.expect
new file mode 100644
index 0000000000..b2f7962df6
--- /dev/null
+++ b/tests/correctness/systolic/relu-expect/array-2-3-4.expect
@@ -0,0 +1,44 @@
+{
+  "l0": [
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+}
diff --git a/tests/correctness/systolic/relu-expect/array-8.expect b/tests/correctness/systolic/relu-expect/array-8.expect
new file mode 100644
index 0000000000..d5f45df77d
--- /dev/null
+++ b/tests/correctness/systolic/relu-expect/array-8.expect
@@ -0,0 +1,242 @@
+{
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+    "-3.618682861328125",
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+    "-1.8860321044921875"
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+}
diff --git a/tests/correctness/systolic/relu-dynamic/array-2-3-4.systolic.data b/tests/correctness/systolic/relu-inputs/array-2-3-4.data
similarity index 100%
rename from tests/correctness/systolic/relu-dynamic/array-2-3-4.systolic.data
rename to tests/correctness/systolic/relu-inputs/array-2-3-4.data
diff --git a/tests/correctness/systolic/relu-dynamic/array-2-3-4.systolic b/tests/correctness/systolic/relu-inputs/array-2-3-4.data_dynamic.systolic
similarity index 100%
rename from tests/correctness/systolic/relu-dynamic/array-2-3-4.systolic
rename to tests/correctness/systolic/relu-inputs/array-2-3-4.data_dynamic.systolic
diff --git a/tests/correctness/systolic/relu/array-2-3-4.systolic b/tests/correctness/systolic/relu-inputs/array-2-3-4.data_static.systolic
similarity index 100%
rename from tests/correctness/systolic/relu/array-2-3-4.systolic
rename to tests/correctness/systolic/relu-inputs/array-2-3-4.data_static.systolic
diff --git a/tests/correctness/systolic/relu-dynamic/array-8.systolic.data b/tests/correctness/systolic/relu-inputs/array-8.data
similarity index 100%
rename from tests/correctness/systolic/relu-dynamic/array-8.systolic.data
rename to tests/correctness/systolic/relu-inputs/array-8.data
diff --git a/tests/correctness/systolic/relu-dynamic/array-8.systolic b/tests/correctness/systolic/relu-inputs/array-8.data_dynamic.systolic
similarity index 100%
rename from tests/correctness/systolic/relu-dynamic/array-8.systolic
rename to tests/correctness/systolic/relu-inputs/array-8.data_dynamic.systolic
diff --git a/tests/correctness/systolic/relu/array-8.systolic b/tests/correctness/systolic/relu-inputs/array-8.data_static.systolic
similarity index 100%
rename from tests/correctness/systolic/relu/array-8.systolic
rename to tests/correctness/systolic/relu-inputs/array-8.data_static.systolic
diff --git a/tests/correctness/systolic/relu/array-2-3-4.expect b/tests/correctness/systolic/relu/array-2-3-4.expect
deleted file mode 100644
index 63064e7a84..0000000000
--- a/tests/correctness/systolic/relu/array-2-3-4.expect
+++ /dev/null
@@ -1,47 +0,0 @@
-{
-  "cycles": 15,
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-}
diff --git a/tests/correctness/systolic/relu/array-2-3-4.systolic.data b/tests/correctness/systolic/relu/array-2-3-4.systolic.data
deleted file mode 100644
index 823b904b4e..0000000000
--- a/tests/correctness/systolic/relu/array-2-3-4.systolic.data
+++ /dev/null
@@ -1,108 +0,0 @@
-{
-  "l0": {
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\ No newline at end of file
diff --git a/tests/correctness/systolic/relu/array-8.expect b/tests/correctness/systolic/relu/array-8.expect
deleted file mode 100644
index c7ae4dd1fc..0000000000
--- a/tests/correctness/systolic/relu/array-8.expect
+++ /dev/null
@@ -1,245 +0,0 @@
-{
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deleted file mode 100644
index 34b8677274..0000000000
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