From a5e858ac361c1059a518390ca044efebf4f324b3 Mon Sep 17 00:00:00 2001 From: Nathaniel Navarro Date: Thu, 2 Jan 2025 16:27:25 +0200 Subject: [PATCH] remove extra ap_clk ports in axi_generator.py --- yxi/axi-calyx/axi_generator.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/yxi/axi-calyx/axi_generator.py b/yxi/axi-calyx/axi_generator.py index 97c5268a6..8f6000011 100644 --- a/yxi/axi-calyx/axi_generator.py +++ b/yxi/axi-calyx/axi_generator.py @@ -507,8 +507,6 @@ def add_main_comp(prog, mems): ] add_comp_ports(wrapper_comp, wrapper_inputs, wrapper_outputs) - # Naming the clock signal `ap_clk` ensures Xilinx tool compatability - wrapper_comp.input("ap_clk", 1, ["clk"]) # Cells # Read stuff