diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..abba353 --- /dev/null +++ b/.gitignore @@ -0,0 +1,98 @@ +# Logs +logs +*.log +npm-debug.log* + +# Runtime data +pids +*.pid +*.seed + +# Directory for instrumented libs generated by jscoverage/JSCover +lib-cov + +# Coverage directory used by tools like istanbul +coverage + +# Grunt intermediate storage (http://gruntjs.com/creating-plugins#storing-task-files) +.grunt + +# node-waf configuration +.lock-wscript + +# Compiled binary addons (http://nodejs.org/api/addons.html) +build/Release + +# Dependency directories +node_modules +jspm_packages + +# Optional npm cache directory +.npm + +# Optional REPL history +.node_repl_history + +# ========================= +# Operating System Files +# ========================= + +# OSX +# ========================= + +.DS_Store +.AppleDouble +.LSOverride + +# Thumbnails +._* + +# Files that might appear in the root of a volume +.DocumentRevisions-V100 +.fseventsd +.Spotlight-V100 +.TemporaryItems +.Trashes +.VolumeIcon.icns + +# Directories potentially created on remote AFP share +.AppleDB +.AppleDesktop +Network Trash Folder +Temporary Items +.apdisk + +# Windows +# ========================= + +# Windows image file caches +Thumbs.db +ehthumbs.db + +# Folder config file +Desktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Windows Installer files +*.cab +*.msi +*.msm +*.msp + +# Windows shortcuts +*.lnk + +# Quartus II intermediate files +*/db +*/*/db +*/.qsys_edit +*/devkits +*/greybox_tmp +*/*/incremental_db +*/incremental_db +*/*/output_files +*/output_files +*/*/output_file.map + diff --git a/testcircuit/README.md b/testcircuit/README.md index b58aecd..3e662d8 100644 --- a/testcircuit/README.md +++ b/testcircuit/README.md @@ -4,6 +4,8 @@ In case of a series production of the mod, you probably need some means to test the mod boards without actually installing them into a real C64. For this purpose, the necessary input signals can be generated by a second FPGA board, programmed to simulate the various VIC signals. +These are fed into the VIC adapter board (via a ZIF socket for example) +which will in turn drive the FPGA board to generate the test image. The provided firmware will turn a standard C64 video enhanchement board to a signal generator that uses the GPIO1 port and two additional pins for output @@ -11,13 +13,14 @@ instead of input. Be careful to use such a board only for this test purpose, as it will cause damage to connect some other signal source to these outputs. +![alt text](breadboard.jpg "Experimental setup using a breadboard") ## Wiring the power | Power input | Signal generator | VIC adapter | | ------------ | ---------------- | ----------- | | +5V | RFCONC2 1 | Pin 40 | -| GND | RFCONC2 3 | Pin 20 | +| GND | SW1 3 | Pin 20 | ## Wiring up the signal generator outputs to the VIC adapter @@ -46,3 +49,10 @@ it will cause damage to connect some other signal source to these outputs. | 75 | GPIO1 2 | Pin 37 | DB9 | | 39 | SW1 1 | Pin 38 | DB8 | | 40 | SW1 2 | Pin 39 | DB7 | + +## Firmware + +The signal generator board needs a dedicated firmware that turns +a standard C64 video enhancement board a signal generator for testing. +This file is called TestSignalGenerator.pof and can be found +right in this folder. diff --git a/testcircuit/TestSignalGenerator.pof b/testcircuit/TestSignalGenerator.pof new file mode 100644 index 0000000..be349ce Binary files /dev/null and b/testcircuit/TestSignalGenerator.pof differ diff --git a/testcircuit/breadboard.jpg b/testcircuit/breadboard.jpg new file mode 100644 index 0000000..a77029a Binary files /dev/null and b/testcircuit/breadboard.jpg differ diff --git a/testcircuit/quartus/PLL_7_882.cmp b/testcircuit/quartus/PLL_7_882.cmp new file mode 100644 index 0000000..9dfe82e --- /dev/null +++ b/testcircuit/quartus/PLL_7_882.cmp @@ -0,0 +1,22 @@ +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +component PLL_7_882 + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +end component; diff --git a/testcircuit/quartus/PLL_7_882.ppf b/testcircuit/quartus/PLL_7_882.ppf new file mode 100644 index 0000000..56b273e --- /dev/null +++ b/testcircuit/quartus/PLL_7_882.ppf @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/testcircuit/quartus/PLL_7_882.qip b/testcircuit/quartus/PLL_7_882.qip new file mode 100644 index 0000000..aea0ed9 --- /dev/null +++ b/testcircuit/quartus/PLL_7_882.qip @@ -0,0 +1,6 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "18.1" +set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{MAX 10}" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "PLL_7_882.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_7_882.cmp"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "PLL_7_882.ppf"] diff --git a/testcircuit/quartus/PLL_7_882.vhd b/testcircuit/quartus/PLL_7_882.vhd new file mode 100644 index 0000000..0370a38 --- /dev/null +++ b/testcircuit/quartus/PLL_7_882.vhd @@ -0,0 +1,354 @@ +-- megafunction wizard: %ALTPLL% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: altpll + +-- ============================================================ +-- File Name: PLL_7_882.vhd +-- Megafunction Name(s): +-- altpll +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 18.1.0 Build 625 09/12/2018 SJ Lite Edition +-- ************************************************************ + + +--Copyright (C) 2018 Intel Corporation. All rights reserved. +--Your use of Intel Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Intel Program License +--Subscription Agreement, the Intel Quartus Prime License Agreement, +--the Intel FPGA IP License Agreement, or other applicable license +--agreement, including, without limitation, that your use is for +--the sole purpose of programming logic devices manufactured by +--Intel and sold by Intel or its authorized distributors. Please +--refer to the applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY PLL_7_882 IS + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); +END PLL_7_882; + + +ARCHITECTURE SYN OF pll_7_882 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (1 DOWNTO 0); + SIGNAL sub_wire2_bv : BIT_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (0 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (4 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC ; + + + + COMPONENT altpll + GENERIC ( + bandwidth_type : STRING; + clk0_divide_by : NATURAL; + clk0_duty_cycle : NATURAL; + clk0_multiply_by : NATURAL; + clk0_phase_shift : STRING; + compensate_clock : STRING; + inclk0_input_frequency : NATURAL; + intended_device_family : STRING; + lpm_hint : STRING; + lpm_type : STRING; + operation_mode : STRING; + pll_type : STRING; + port_activeclock : STRING; + port_areset : STRING; + port_clkbad0 : STRING; + port_clkbad1 : STRING; + port_clkloss : STRING; + port_clkswitch : STRING; + port_configupdate : STRING; + port_fbin : STRING; + port_inclk0 : STRING; + port_inclk1 : STRING; + port_locked : STRING; + port_pfdena : STRING; + port_phasecounterselect : STRING; + port_phasedone : STRING; + port_phasestep : STRING; + port_phaseupdown : STRING; + port_pllena : STRING; + port_scanaclr : STRING; + port_scanclk : STRING; + port_scanclkena : STRING; + port_scandata : STRING; + port_scandataout : STRING; + port_scandone : STRING; + port_scanread : STRING; + port_scanwrite : STRING; + port_clk0 : STRING; + port_clk1 : STRING; + port_clk2 : STRING; + port_clk3 : STRING; + port_clk4 : STRING; + port_clk5 : STRING; + port_clkena0 : STRING; + port_clkena1 : STRING; + port_clkena2 : STRING; + port_clkena3 : STRING; + port_clkena4 : STRING; + port_clkena5 : STRING; + port_extclk0 : STRING; + port_extclk1 : STRING; + port_extclk2 : STRING; + port_extclk3 : STRING; + width_clock : NATURAL + ); + PORT ( + inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + sub_wire2_bv(0 DOWNTO 0) <= "0"; + sub_wire2 <= To_stdlogicvector(sub_wire2_bv); + sub_wire0 <= inclk0; + sub_wire1 <= sub_wire2(0 DOWNTO 0) & sub_wire0; + sub_wire4 <= sub_wire3(0); + c0 <= sub_wire4; + + altpll_component : altpll + GENERIC MAP ( + bandwidth_type => "AUTO", + clk0_divide_by => 12500, + clk0_duty_cycle => 50, + clk0_multiply_by => 3941, + clk0_phase_shift => "0", + compensate_clock => "CLK0", + inclk0_input_frequency => 40000, + intended_device_family => "MAX 10", + lpm_hint => "CBX_MODULE_PREFIX=PLL_7_882", + lpm_type => "altpll", + operation_mode => "NORMAL", + pll_type => "AUTO", + port_activeclock => "PORT_UNUSED", + port_areset => "PORT_UNUSED", + port_clkbad0 => "PORT_UNUSED", + port_clkbad1 => "PORT_UNUSED", + port_clkloss => "PORT_UNUSED", + port_clkswitch => "PORT_UNUSED", + port_configupdate => "PORT_UNUSED", + port_fbin => "PORT_UNUSED", + port_inclk0 => "PORT_USED", + port_inclk1 => "PORT_UNUSED", + port_locked => "PORT_UNUSED", + port_pfdena => "PORT_UNUSED", + port_phasecounterselect => "PORT_UNUSED", + port_phasedone => "PORT_UNUSED", + port_phasestep => "PORT_UNUSED", + port_phaseupdown => "PORT_UNUSED", + port_pllena => "PORT_UNUSED", + port_scanaclr => "PORT_UNUSED", + port_scanclk => "PORT_UNUSED", + port_scanclkena => "PORT_UNUSED", + port_scandata => "PORT_UNUSED", + port_scandataout => "PORT_UNUSED", + port_scandone => "PORT_UNUSED", + port_scanread => "PORT_UNUSED", + port_scanwrite => "PORT_UNUSED", + port_clk0 => "PORT_USED", + port_clk1 => "PORT_UNUSED", + port_clk2 => "PORT_UNUSED", + port_clk3 => "PORT_UNUSED", + port_clk4 => "PORT_UNUSED", + port_clk5 => "PORT_UNUSED", + port_clkena0 => "PORT_UNUSED", + port_clkena1 => "PORT_UNUSED", + port_clkena2 => "PORT_UNUSED", + port_clkena3 => "PORT_UNUSED", + port_clkena4 => "PORT_UNUSED", + port_clkena5 => "PORT_UNUSED", + port_extclk0 => "PORT_UNUSED", + port_extclk1 => "PORT_UNUSED", + port_extclk2 => "PORT_UNUSED", + port_extclk3 => "PORT_UNUSED", + width_clock => 5 + ) + PORT MAP ( + inclk => sub_wire1, + clk => sub_wire3 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0" +-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000" +-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" +-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" +-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" +-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" +-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" +-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" +-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" +-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" +-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" +-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "7.882000" +-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" +-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0" +-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575" +-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1" +-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "25.000" +-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000" +-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1" +-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0" +-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" +-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" +-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" +-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" +-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "7.88200000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" +-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" +-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" +-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" +-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" +-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "PLL_7_882.mif" +-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" +-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" +-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" +-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" +-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_USE STRING "0" +-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK3 STRING "0" +-- Retrieval info: PRIVATE: STICKY_CLK4 STRING "0" +-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" +-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: USE_CLK0 STRING "1" +-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" +-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "12500" +-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "3941" +-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" +-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "40000" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "MAX 10" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll" +-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" +-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" +-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" +-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" +-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" +-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" +-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]" +-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" +-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 +-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 +-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882.ppf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL PLL_7_882_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf +-- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/testcircuit/quartus/TestSignalGenerator.qpf b/testcircuit/quartus/TestSignalGenerator.qpf new file mode 100644 index 0000000..6900372 --- /dev/null +++ b/testcircuit/quartus/TestSignalGenerator.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 17:21:02 April 15, 2020 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "18.1" +DATE = "17:21:02 April 15, 2020" + +# Revisions + +PROJECT_REVISION = "TestSignalGenerator" diff --git a/testcircuit/quartus/TestSignalGenerator.qsf b/testcircuit/quartus/TestSignalGenerator.qsf new file mode 100644 index 0000000..c630300 --- /dev/null +++ b/testcircuit/quartus/TestSignalGenerator.qsf @@ -0,0 +1,88 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus Prime +# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition +# Date created = 17:21:02 April 15, 2020 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# TestSignalGenerator_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus Prime software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "MAX 10" +set_global_assignment -name DEVICE 10M02SCE144C8G +set_global_assignment -name TOP_LEVEL_ENTITY TestSignalGenerator +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:21:02 APRIL 15, 2020" +set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition" +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ENABLE_OCT_DONE OFF +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name CRC_ERROR_OPEN_DRAIN ON +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall +set_global_assignment -name VHDL_FILE TestSignalGenerator.vhd +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON +set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" +set_global_assignment -name QIP_FILE PLL_7_882.qip +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_location_assignment PIN_81 -to A[5] +set_location_assignment PIN_88 -to A[4] +set_location_assignment PIN_92 -to A[3] +set_location_assignment PIN_98 -to A[2] +set_location_assignment PIN_100 -to A[1] +set_location_assignment PIN_103 -to A[0] +set_location_assignment PIN_105 -to AEC +set_location_assignment PIN_25 -to CLK25 +set_location_assignment PIN_99 -to CS +set_location_assignment PIN_79 -to DB[11] +set_location_assignment PIN_77 -to DB[10] +set_location_assignment PIN_75 -to DB[9] +set_location_assignment PIN_39 -to DB[8] +set_location_assignment PIN_40 -to DB[7] +set_location_assignment PIN_74 -to DB[6] +set_location_assignment PIN_76 -to DB[5] +set_location_assignment PIN_78 -to DB[4] +set_location_assignment PIN_80 -to DB[3] +set_location_assignment PIN_87 -to DB[2] +set_location_assignment PIN_91 -to DB[1] +set_location_assignment PIN_97 -to DB[0] +set_location_assignment PIN_106 -to PHI0 +set_location_assignment PIN_101 -to RW +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/testcircuit/quartus/TestSignalGenerator.vhd b/testcircuit/quartus/TestSignalGenerator.vhd new file mode 100644 index 0000000..c8e0073 --- /dev/null +++ b/testcircuit/quartus/TestSignalGenerator.vhd @@ -0,0 +1,265 @@ +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +-- Test circuit to simulate the signals of a VIC in the C64 to drive +-- and test a C64 video enhancement board in PAL mode. +-- The program also runs on C64 video enhanchement board of its on and used the +-- GPIO1 pins and the two pins of the mode switch as and output. + +entity TestSignalGenerator is + port ( + -- reference clock + CLK25: in std_logic; + + -- generated signals + DB: out std_logic_vector(11 downto 0); + A: out std_logic_vector(5 downto 0); + CS: out std_logic; + RW: out std_logic; + -- BA: out std_logic; + AEC: out std_logic; + PHI0: out std_logic + ); +end entity; + + +architecture immediate of TestSignalGenerator is + + component PLL_7_882 is + PORT + ( + inclk0 : IN STD_LOGIC := '0'; + c0 : OUT STD_LOGIC + ); + end component; + + signal PIXELCLOCK : std_logic; + +begin + clkpll: PLL_7_882 port map ( CLK25, PIXELCLOCK ); + + + process (PIXELCLOCK) + variable displayline : integer range 0 to 311 := 0; + variable cycle : integer range 1 to 63 := 1; + variable pixel: integer range 0 to 7 := 0; + begin + + + if rising_edge(PIXELCLOCK) then + -- idle levels of all signals + DB <= "111111111111"; + A <= "111111"; + CS <= '1'; + RW <= '1'; + -- BA <= '1'; + + -- signals in first half of the c64 clock + if pixel<4 then + AEC <= '0'; + PHI0 <= '0'; + + -- dram refresh pattern (not the correct one, but the mod will detect it) + if cycle>=11 and cycle<=15 then + if displayline=311 then + A(1 downto 0) <= "11"; + elsif cycle=11 then + A(1 downto 0) <= "11"; + elsif cycle=12 then + A(1 downto 0) <= "10"; + elsif cycle=13 then + A(1 downto 0) <= "01"; + elsif cycle=14 then + A(1 downto 0) <= "00"; + else + A(1 downto 0) <= "11"; + end if; + end if; + + + -- signals in second half of the c64 clock + else + PHI0 <= '1'; + + -- vic accessing the video matrix data (every line, but that does not bother me now) + if displayline>=50 and displayline<250 and cycle>=15 and cycle<55 then + AEC <= '0'; + DB(11 downto 8) <= "0110"; -- dark blue text color, character data is all pixel set by default + -- add color stripes + if cycle>=20 and cycle<30 and displayline>=80 and displayline<208 then + DB(11 downto 8) <= std_logic_vector(to_unsigned((displayline-80) / 8, 4)); + end if; + + -- cpu may use the bus now + else + AEC <= '1'; + -- register writes + if displayline=0 and cycle<=5 then + CS <= '0'; + RW <= '0'; + case cycle is + when 1 => + A <= "010001"; -- control register 1 + DB(7 downto 0) <= "00011011"; -- enable display, text mode, 25 rows + when 2 => + A <= "010110"; -- control register 2 + DB(7 downto 0) <= "00001000"; -- no multicolor, 40 columns + when 3 => + A <= "100000"; -- Border color + DB(7 downto 0) <= "00001110"; -- light blue + when 4 => + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000001"; -- white + when 5 => + A <= "101001"; -- if A(3) were faulty, this writes to Background color 0 + -- otherwise it writes to sprite color 2, which is unused + DB(7 downto 0) <= "00001000"; -- orange + when others => + end case; + + -- try to provoke register writes with CS=1 or RW=1 + elsif displayline=1 and cycle<=3 then + case cycle is + when 1 => + CS <= '1'; + RW <= '0'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000100"; -- purple + when 2 => + CS <= '0'; + RW <= '1'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000101"; -- green + when 3 => + CS <= '1'; + RW <= '1'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000111"; -- yellow + when others => + end case; + end if; + end if; + end if; + + -- text graphics pattern fetch response would belong to first half of cycle, + -- but because the response is expected so late, we need to provide this on both halves + if displayline>=220 and displayline<229 then + if cycle=45 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111100"; + when 1 => DB(7 downto 0) <= "11111011"; + when 2 => DB(7 downto 0) <= "10001011"; + when 3 => DB(7 downto 0) <= "01111011"; + when 4 => DB(7 downto 0) <= "01111011"; + when 5 => DB(7 downto 0) <= "01111011"; + when 6 => DB(7 downto 0) <= "10001100"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=46 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "01111111"; + when 2 => DB(7 downto 0) <= "01000110"; + when 3 => DB(7 downto 0) <= "01011010"; + when 4 => DB(7 downto 0) <= "01011010"; + when 5 => DB(7 downto 0) <= "01011010"; + when 6 => DB(7 downto 0) <= "11000110"; + when 7 => DB(7 downto 0) <= "11011110"; + when others => DB(7 downto 0) <= "11011110"; + end case; + elsif cycle=47 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "00111001"; + when 3 => DB(7 downto 0) <= "11010110"; + when 4 => DB(7 downto 0) <= "11010000"; + when 5 => DB(7 downto 0) <= "11010111"; + when 6 => DB(7 downto 0) <= "00111000"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=48 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "10000110"; + when 3 => DB(7 downto 0) <= "10110101"; + when 4 => DB(7 downto 0) <= "10111101"; + when 5 => DB(7 downto 0) <= "10111101"; + when 6 => DB(7 downto 0) <= "10111110"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=49 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "10111111"; + when 1 => DB(7 downto 0) <= "10111111"; + when 2 => DB(7 downto 0) <= "00100001"; + when 3 => DB(7 downto 0) <= "10101101"; + when 4 => DB(7 downto 0) <= "10101111"; + when 5 => DB(7 downto 0) <= "10101111"; + when 6 => DB(7 downto 0) <= "00101111"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=50 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "10011100"; + when 3 => DB(7 downto 0) <= "01101011"; + when 4 => DB(7 downto 0) <= "01101011"; + when 5 => DB(7 downto 0) <= "01101011"; + when 6 => DB(7 downto 0) <= "10001100"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111100"; + end case; + elsif cycle=51 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "11100110"; + when 3 => DB(7 downto 0) <= "01011010"; + when 4 => DB(7 downto 0) <= "01011010"; + when 5 => DB(7 downto 0) <= "01011010"; + when 6 => DB(7 downto 0) <= "01100110"; + when 7 => DB(7 downto 0) <= "01111111"; + when others => DB(7 downto 0) <= "01111111"; + end case; + elsif cycle=52 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "00111111"; + when 3 => DB(7 downto 0) <= "11011111"; + when 4 => DB(7 downto 0) <= "11011111"; + when 5 => DB(7 downto 0) <= "11011111"; + when 6 => DB(7 downto 0) <= "11011111"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + end if; + end if; + + -- progress the counters + if pixel/=7 then + pixel := pixel+1; + else + pixel := 0; + if cycle/=63 then + cycle := cycle+1; + else + cycle := 1; + if displayline/=311 then + displayline := displayline +1; + else + displayline := 0; + end if; + end if; + end if; + end if; + end process; +end immediate; diff --git a/testcircuit/quartus/TestSignalGenerator.vhd.bak b/testcircuit/quartus/TestSignalGenerator.vhd.bak new file mode 100644 index 0000000..3d9080e --- /dev/null +++ b/testcircuit/quartus/TestSignalGenerator.vhd.bak @@ -0,0 +1,297 @@ +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +-- Test circuit to simulate the signals of a VIC in the C64 to drive +-- and test a C64 video enhancement board in PAL mode. +-- The program runs on an Delta Brd, which I got from another hobbyist, so +-- it is a super-special one-off. + +entity TestSignal is + port ( + -- reference clock + CLK100: in std_logic; + + -- generated signals + DB: out std_logic_vector(11 downto 0); + A: out std_logic_vector(5 downto 0); + CS: out std_logic; + RW: out std_logic; + BA: out std_logic; + AEC: out std_logic; + PHI0: out std_logic + ); +end entity; + + +architecture immediate of TestSignal is + + signal PIXELCLOCK : std_logic; + +begin + -- generate a 7.88 Mhz clock from the 100 Mhz input. + -- the duty cycle is very non-50%, but this makes no difference + process (CLK100, PIXELCLOCK) + variable tick : integer range 0 to 15 := 0; + variable needreset : boolean := false; + variable out_clock : std_logic := '0'; + + variable tmp_needreset : boolean; + variable tmp_tick : std_logic_vector(3 downto 0); + + variable compensationsequence : integer range 0 to 255 := 0; + variable longclock : boolean := false; + + begin + if rising_edge(CLK100) then + tmp_tick := std_logic_vector(to_unsigned(tick,4)); + out_clock := tmp_tick(3); + + tmp_needreset := (longclock and tick=11) or ((not longclock) and tick=10); + if needreset then + tick := 0; + else + tick := tick+1; + end if; + needreset := tmp_needreset; + end if; + + PIXELCLOCK <= out_clock; + + if falling_edge(PIXELCLOCK) then + longclock := ((compensationsequence mod 2) = 0) + or ((compensationsequence mod 16) = 3) + or ((compensationsequence mod 16) = 7) + or ((compensationsequence mod 16) = 11); + if compensationsequence/=251 then + compensationsequence := compensationsequence+1; + else + compensationsequence := 0; + end if; + end if; + end process; + + + process (PIXELCLOCK) + variable displayline : integer range 0 to 311 := 0; + variable cycle : integer range 1 to 63 := 1; + variable pixel: integer range 0 to 7 := 0; + begin + + + if rising_edge(PIXELCLOCK) then + -- idle levels of all signals + DB <= "111111111111"; + A <= "111111"; + CS <= '1'; + RW <= '1'; + BA <= '1'; + + -- signals in first half of the c64 clock + if pixel<4 then + AEC <= '0'; + PHI0 <= '0'; + + -- dram refresh pattern (not the correct one, but the mod will detect it) + if cycle>=11 and cycle<=15 then + if displayline=311 then + A(1 downto 0) <= "11"; + elsif cycle=11 then + A(1 downto 0) <= "11"; + elsif cycle=12 then + A(1 downto 0) <= "10"; + elsif cycle=13 then + A(1 downto 0) <= "01"; + elsif cycle=14 then + A(1 downto 0) <= "00"; + else + A(1 downto 0) <= "11"; + end if; + end if; + + + -- signals in second half of the c64 clock + else + PHI0 <= '1'; + + -- vic accessing the video matrix data (every line, but that does not bother me now) + if displayline>=50 and displayline<250 and cycle>=15 and cycle<55 then + AEC <= '0'; + DB(11 downto 8) <= "0110"; -- dark blue text color, character data is all pixel set by default + -- add color stripes + if cycle>=20 and cycle<30 and displayline>=80 and displayline<208 then + DB(11 downto 8) <= std_logic_vector(to_unsigned((displayline-80) / 8, 4)); + end if; + + -- cpu may use the bus now + else + AEC <= '1'; + -- register writes + if displayline=0 and cycle<=5 then + CS <= '0'; + RW <= '0'; + case cycle is + when 1 => + A <= "010001"; -- control register 1 + DB(7 downto 0) <= "00011011"; -- enable display, text mode, 25 rows + when 2 => + A <= "010110"; -- control register 2 + DB(7 downto 0) <= "00001000"; -- no multicolor, 40 columns + when 3 => + A <= "100000"; -- Border color + DB(7 downto 0) <= "00001110"; -- light blue + when 4 => + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000001"; -- white + when 5 => + A <= "101001"; -- if A(3) were faulty, this writes to Background color 0 + -- otherwise it writes to sprite color 2, which is unused + DB(7 downto 0) <= "00001000"; -- orange + when others => + end case; + + -- try to provoke register writes with CS=1 or RW=1 + elsif displayline=1 and cycle<=3 then + case cycle is + when 1 => + CS <= '1'; + RW <= '0'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000100"; -- purple + when 2 => + CS <= '0'; + RW <= '1'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000101"; -- green + when 3 => + CS <= '1'; + RW <= '1'; + A <= "100001"; -- Background color 0 + DB(7 downto 0) <= "00000111"; -- yellow + when others => + end case; + end if; + end if; + end if; + + -- text graphics pattern fetch response would belong to first half of cycle, + -- but because the response is expected so late, we need to provide this on both halves + if displayline>=220 and displayline<229 then + if cycle=45 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111100"; + when 1 => DB(7 downto 0) <= "11111011"; + when 2 => DB(7 downto 0) <= "10001011"; + when 3 => DB(7 downto 0) <= "01111011"; + when 4 => DB(7 downto 0) <= "01111011"; + when 5 => DB(7 downto 0) <= "01111011"; + when 6 => DB(7 downto 0) <= "10001100"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=46 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "01111111"; + when 2 => DB(7 downto 0) <= "01000110"; + when 3 => DB(7 downto 0) <= "01011010"; + when 4 => DB(7 downto 0) <= "01011010"; + when 5 => DB(7 downto 0) <= "01011010"; + when 6 => DB(7 downto 0) <= "11000110"; + when 7 => DB(7 downto 0) <= "11011110"; + when others => DB(7 downto 0) <= "11011110"; + end case; + elsif cycle=47 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "00111001"; + when 3 => DB(7 downto 0) <= "11010110"; + when 4 => DB(7 downto 0) <= "11010000"; + when 5 => DB(7 downto 0) <= "11010111"; + when 6 => DB(7 downto 0) <= "00111000"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=48 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "10000110"; + when 3 => DB(7 downto 0) <= "10110101"; + when 4 => DB(7 downto 0) <= "10111101"; + when 5 => DB(7 downto 0) <= "10111101"; + when 6 => DB(7 downto 0) <= "10111110"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=49 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "10111111"; + when 1 => DB(7 downto 0) <= "10111111"; + when 2 => DB(7 downto 0) <= "00100001"; + when 3 => DB(7 downto 0) <= "10101101"; + when 4 => DB(7 downto 0) <= "10101111"; + when 5 => DB(7 downto 0) <= "10101111"; + when 6 => DB(7 downto 0) <= "00101111"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + elsif cycle=50 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "10011100"; + when 3 => DB(7 downto 0) <= "01101011"; + when 4 => DB(7 downto 0) <= "01101011"; + when 5 => DB(7 downto 0) <= "01101011"; + when 6 => DB(7 downto 0) <= "10001100"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111100"; + end case; + elsif cycle=51 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "11100110"; + when 3 => DB(7 downto 0) <= "01011010"; + when 4 => DB(7 downto 0) <= "01011010"; + when 5 => DB(7 downto 0) <= "01011010"; + when 6 => DB(7 downto 0) <= "01100110"; + when 7 => DB(7 downto 0) <= "01111111"; + when others => DB(7 downto 0) <= "01111111"; + end case; + elsif cycle=52 then + case displayline-220 is + when 0 => DB(7 downto 0) <= "11111111"; + when 1 => DB(7 downto 0) <= "11111111"; + when 2 => DB(7 downto 0) <= "00111111"; + when 3 => DB(7 downto 0) <= "11011111"; + when 4 => DB(7 downto 0) <= "11011111"; + when 5 => DB(7 downto 0) <= "11011111"; + when 6 => DB(7 downto 0) <= "11011111"; + when 7 => DB(7 downto 0) <= "11111111"; + when others => DB(7 downto 0) <= "11111111"; + end case; + end if; + end if; + + -- progress the counters + if pixel/=7 then + pixel := pixel+1; + else + pixel := 0; + if cycle/=63 then + cycle := cycle+1; + else + cycle := 1; + if displayline/=311 then + displayline := displayline +1; + else + displayline := 0; + end if; + end if; + end if; + end if; + end process; +end immediate; diff --git a/testcircuit/quartus/greybox_tmp/cbx_args.txt b/testcircuit/quartus/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..cce8e3b --- /dev/null +++ b/testcircuit/quartus/greybox_tmp/cbx_args.txt @@ -0,0 +1,58 @@ +BANDWIDTH_TYPE=AUTO +CLK0_DIVIDE_BY=12500 +CLK0_DUTY_CYCLE=50 +CLK0_MULTIPLY_BY=3941 +CLK0_PHASE_SHIFT=0 +COMPENSATE_CLOCK=CLK0 +INCLK0_INPUT_FREQUENCY=40000 +INTENDED_DEVICE_FAMILY="MAX 10" +LPM_TYPE=altpll +OPERATION_MODE=NORMAL +PLL_TYPE=AUTO +PORT_ACTIVECLOCK=PORT_UNUSED +PORT_ARESET=PORT_UNUSED +PORT_CLKBAD0=PORT_UNUSED +PORT_CLKBAD1=PORT_UNUSED +PORT_CLKLOSS=PORT_UNUSED +PORT_CLKSWITCH=PORT_UNUSED +PORT_CONFIGUPDATE=PORT_UNUSED +PORT_FBIN=PORT_UNUSED +PORT_INCLK0=PORT_USED +PORT_INCLK1=PORT_UNUSED +PORT_LOCKED=PORT_UNUSED +PORT_PFDENA=PORT_UNUSED +PORT_PHASECOUNTERSELECT=PORT_UNUSED +PORT_PHASEDONE=PORT_UNUSED +PORT_PHASESTEP=PORT_UNUSED +PORT_PHASEUPDOWN=PORT_UNUSED +PORT_PLLENA=PORT_UNUSED +PORT_SCANACLR=PORT_UNUSED +PORT_SCANCLK=PORT_UNUSED +PORT_SCANCLKENA=PORT_UNUSED +PORT_SCANDATA=PORT_UNUSED +PORT_SCANDATAOUT=PORT_UNUSED +PORT_SCANDONE=PORT_UNUSED +PORT_SCANREAD=PORT_UNUSED +PORT_SCANWRITE=PORT_UNUSED +PORT_clk0=PORT_USED +PORT_clk1=PORT_UNUSED +PORT_clk2=PORT_UNUSED +PORT_clk3=PORT_UNUSED +PORT_clk4=PORT_UNUSED +PORT_clk5=PORT_UNUSED +PORT_clkena0=PORT_UNUSED +PORT_clkena1=PORT_UNUSED +PORT_clkena2=PORT_UNUSED +PORT_clkena3=PORT_UNUSED +PORT_clkena4=PORT_UNUSED +PORT_clkena5=PORT_UNUSED +PORT_extclk0=PORT_UNUSED +PORT_extclk1=PORT_UNUSED +PORT_extclk2=PORT_UNUSED +PORT_extclk3=PORT_UNUSED +WIDTH_CLOCK=5 +DEVICE_FAMILY="MAX 10" +CBX_AUTO_BLACKBOX=ALL +inclk +inclk +clk