diff --git a/src/V3AstNodeOther.h b/src/V3AstNodeOther.h
index d3f0aee1e8..ccfe5f78b8 100644
--- a/src/V3AstNodeOther.h
+++ b/src/V3AstNodeOther.h
@@ -1438,6 +1438,7 @@ class AstScope final : public AstNode {
 class AstSenItem final : public AstNode {
     // Parents:  SENTREE
     // @astgen op1 := sensp : Optional[AstNodeExpr] // Sensitivity expression
+    // @astgen op2 := condp : Optional[AstNodeExpr] // Sensitivity condition
     VEdgeType m_edgeType;  // Edge type
 public:
     class Combo {};  // for constructor type-overload selection
@@ -1446,10 +1447,11 @@ class AstSenItem final : public AstNode {
     class Initial {};  // for constructor type-overload selection
     class Final {};  // for constructor type-overload selection
     class Never {};  // for constructor type-overload selection
-    AstSenItem(FileLine* fl, VEdgeType edgeType, AstNodeExpr* senp)
+    AstSenItem(FileLine* fl, VEdgeType edgeType, AstNodeExpr* senp, AstNodeExpr* condp = nullptr)
         : ASTGEN_SUPER_SenItem(fl)
         , m_edgeType{edgeType} {
         this->sensp(senp);
+        this->condp(condp);
     }
     AstSenItem(FileLine* fl, Combo)
         : ASTGEN_SUPER_SenItem(fl)
diff --git a/src/V3SenExprBuilder.h b/src/V3SenExprBuilder.h
index 3928c7ea54..7a8e8533ea 100644
--- a/src/V3SenExprBuilder.h
+++ b/src/V3SenExprBuilder.h
@@ -223,7 +223,9 @@ class SenExprBuilder final {
         for (AstSenItem* senItemp = senTreep->sensesp(); senItemp;
              senItemp = VN_AS(senItemp->nextp(), SenItem)) {
             const auto& pair = createTerm(senItemp);
-            if (AstNodeExpr* const termp = pair.first) {
+            if (AstNodeExpr* termp = pair.first) {
+                AstNodeExpr* const condp = senItemp->condp();
+                if (condp) termp = new AstAnd{flp, condp->cloneTree(false), termp};
                 resultp = resultp ? new AstOr{flp, resultp, termp} : termp;
                 firedAtInitialization |= pair.second;
             }
diff --git a/src/verilog.y b/src/verilog.y
index 3d553f6675..e794d40ac1 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3348,8 +3348,7 @@ senitem<senItemp>:              // IEEE: part of event_expression, non-'OR' ','
         |       expr
                         { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1}; }
         |       expr yIFF expr
-                        { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1};
-                          if ($2) BBUNSUP($2, "Unsupported: event expression 'iff'"); }
+                        { $$ = new AstSenItem{$<fl>1, VEdgeType::ET_CHANGED, $1, $3}; }
         ;
 
 senitemVar<senItemp>:
@@ -3364,14 +3363,11 @@ senitemEdge<senItemp>:          // IEEE: part of event_expression
         |       yEDGE expr
                         { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2}; }
         |       yPOSEDGE expr yIFF expr
-                        { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2};
-                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_POSEDGE, $2, $4}; }
         |       yNEGEDGE expr yIFF expr
-                        { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2};
-                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_NEGEDGE, $2, $4}; }
         |       yEDGE expr yIFF expr
-                        { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2};
-                          BBUNSUP($3, "Unsupported: event expression 'iff'"); }
+                        { $$ = new AstSenItem{$1, VEdgeType::ET_BOTHEDGE, $2, $4}; }
         ;
 
 //************************************************
diff --git a/test_regress/t/t_iff.pl b/test_regress/t/t_iff.pl
index 2966ed9a21..9a15dd2ccb 100755
--- a/test_regress/t/t_iff.pl
+++ b/test_regress/t/t_iff.pl
@@ -11,14 +11,11 @@
 scenarios(simulator => 1);
 
 compile(
-    verilator_flags2 => ['--timing'],
-    fails => $Self->{vlt_all},  # Verilator unsupported, bug1482, iff not supported
-    expect_filename => $Self->{golden_filename},
     );
 
 execute(
     check_finished => 1,
-    ) if !$Self->{vlt_all};
+    );
 
 ok(1);
 1;
diff --git a/test_regress/t/t_iff.v b/test_regress/t/t_iff.v
index 833bf411f6..f7c72197cf 100644
--- a/test_regress/t/t_iff.v
+++ b/test_regress/t/t_iff.v
@@ -16,7 +16,7 @@ module t (/*AUTOARG*/
 
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire [31:0]          result;                 // From test of Test.v
+   wire [63:0]          result;                 // From test of Test.v
    // End of automatics
    Test test (.*);
 
@@ -42,7 +42,7 @@ module t (/*AUTOARG*/
          $write("[%0t] cyc==%0d crc=%x sum=%x\n", $time, cyc, crc, sum);
          if (crc !== 64'hc77bb9b3784ea091) $stop;
          // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'h390aa8652d33a691
+`define EXPECTED_SUM 64'hd55eb7da9ba3354a
          if (sum !== `EXPECTED_SUM) $stop;
          $write("*-* All Finished *-*\n");
          $finish;
@@ -56,7 +56,7 @@ module Test
    input              clk,
    input [63:0]       crc,
    input [31:0]       cyc,
-   output wire [31:0] result);
+   output wire [63:0] result);
 
    wire         enable = crc[32];
    wire [7:0]  d = crc[7:0];