From bd2983da02171b6d569d6eb737a8a85fef16939f Mon Sep 17 00:00:00 2001 From: Krzysztof Bieganski Date: Tue, 17 Oct 2023 12:06:07 +0200 Subject: [PATCH] Fix forks with jumpblocks and intra-assign delays Signed-off-by: Krzysztof Bieganski --- src/V3SchedTiming.cpp | 9 +++++---- test_regress/t/t_fork_jumpblock.pl | 23 +++++++++++++++++++++++ test_regress/t/t_fork_jumpblock.v | 23 +++++++++++++++++++++++ 3 files changed, 51 insertions(+), 4 deletions(-) create mode 100755 test_regress/t/t_fork_jumpblock.pl create mode 100644 test_regress/t/t_fork_jumpblock.v diff --git a/src/V3SchedTiming.cpp b/src/V3SchedTiming.cpp index e072814e72f..4aaba92c5a2 100644 --- a/src/V3SchedTiming.cpp +++ b/src/V3SchedTiming.cpp @@ -297,14 +297,15 @@ void transformForks(AstNetlist* const netlistp) { // Pass it by value to the new function, as otherwise there are issues with // -flocalize (see t_timing_intra_assign) passByValue = true; - } else if (!varp->user1() || !varp->isFuncLocal()) { - // Not func local, or not declared before the fork. Their lifetime is longer - // than the forked process. Skip - return; } else if (dtypep && dtypep->isForkSync()) { // We can just pass it by value to the new function passByValue = true; } + if (!varp->user1() || !varp->isFuncLocal()) { + // Not func local, or not declared before the fork. Their lifetime is longer + // than the forked process. Skip + return; + } // Remap the reference AstVarScope* const vscp = refp->varScopep(); if (!vscp->user2p()) { diff --git a/test_regress/t/t_fork_jumpblock.pl b/test_regress/t/t_fork_jumpblock.pl new file mode 100755 index 00000000000..bc632ee012e --- /dev/null +++ b/test_regress/t/t_fork_jumpblock.pl @@ -0,0 +1,23 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + verilator_flags2 => ["--exe --main --timing"], + make_main => 0, + ); + +execute( + check_finished => 1, + ); + +ok(1); +1; diff --git a/test_regress/t/t_fork_jumpblock.v b/test_regress/t/t_fork_jumpblock.v new file mode 100644 index 00000000000..13ef8e9f3d1 --- /dev/null +++ b/test_regress/t/t_fork_jumpblock.v @@ -0,0 +1,23 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2023 by Antmicro Ltd. +// SPDX-License-Identifier: CC0-1.0 + +class bar; + task foo(logic r); + int a, b; + if (r) return; + fork a = #1 b; join_none + endtask +endclass + +module t; + bar b = new; + + initial begin + b.foo(0); + $write("*-* All Finished *-*\n"); + $finish; + end +endmodule