diff --git a/src/V3Active.cpp b/src/V3Active.cpp
index f9c419314a..1b547f7619 100644
--- a/src/V3Active.cpp
+++ b/src/V3Active.cpp
@@ -349,7 +349,7 @@ class ActiveLatchCheckVisitor final : public VNVisitorConst {
 
 class ActiveDlyVisitor final : public VNVisitor {
 public:
-    enum CheckType : uint8_t { CT_SEQ, CT_COMB, CT_INITIAL };
+    enum CheckType : uint8_t { CT_SEQ, CT_COMB, CT_INITIAL, CT_SUSPENDABLE };
 
 private:
     // MEMBERS
@@ -358,7 +358,7 @@ class ActiveDlyVisitor final : public VNVisitor {
     // VISITORS
     void visit(AstAssignDly* nodep) override {
         // Non-blocking assignments are OK in sequential processes
-        if (m_check == CT_SEQ) return;
+        if (m_check == CT_SEQ || m_check == CT_SUSPENDABLE) return;
 
         // Issue appropriate warning
         if (m_check == CT_INITIAL) {
@@ -488,8 +488,9 @@ class ActiveVisitor final : public VNVisitor {
 
         // Warn and convert any delayed assignments
         {
-            ActiveDlyVisitor{nodep, m_clockedProcess ? ActiveDlyVisitor::CT_SEQ
-                                                     : ActiveDlyVisitor::CT_COMB};
+            ActiveDlyVisitor{nodep, !m_clockedProcess ? ActiveDlyVisitor::CT_COMB
+                                    : oldsensesp      ? ActiveDlyVisitor::CT_SEQ
+                                                      : ActiveDlyVisitor::CT_SUSPENDABLE};
         }
 
         // check combinational processes for latches
diff --git a/test_regress/t/t_timing_clkgen2.py b/test_regress/t/t_timing_clkgen2.py
index a4e75e7ad2..5003343847 100755
--- a/test_regress/t/t_timing_clkgen2.py
+++ b/test_regress/t/t_timing_clkgen2.py
@@ -11,7 +11,7 @@
 
 test.scenarios('simulator')
 
-test.compile(verilator_flags2=["--exe --main --timing"])
+test.compile(verilator_flags2=["--exe --main --timing -Wwarn-BLKSEQ"])
 
 test.execute()