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However, this is not general enough. For example, if we have func1_call()[0] || func2_call()[1], due to short circuit evaluation, func2_call[1] may not be executed. Hence, func2_call()[1] should be guarded by the result of the first condition to avoid any side effects in func2_call().
The most general way would be to expand all logical expressions and explicitly embed the short-circuit evaluation semantics.
logic[7:0] res1, res2;
res1= func1_call();
if(!res1) begin
res2= func2_call();
end
The text was updated successfully, but these errors were encountered:
Code in SystemC may exhibit the following pattern (see here), where the returned value is indexed.
Currently, the generated SystemVerilog code is as follows.
The code will work under simulation but will not work for synthesis.
One tentative solution is to generate a local variable that holds the function return value.
However, this is not general enough. For example, if we have
func1_call()[0] || func2_call()[1]
, due to short circuit evaluation,func2_call[1]
may not be executed. Hence,func2_call()[1]
should be guarded by the result of the first condition to avoid any side effects infunc2_call()
.The most general way would be to expand all logical expressions and explicitly embed the short-circuit evaluation semantics.
The text was updated successfully, but these errors were encountered: