From ff85c5bec8eb1110dd4e5dd8bc4f924f19db9efd Mon Sep 17 00:00:00 2001 From: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> Date: Mon, 16 Dec 2024 09:49:41 -0600 Subject: [PATCH] fix(CMSIS,PeriphDrivers): Add TMR RevB `CTRL1.async` field which allows asynchronous reads to the PWM and CNT registers (#1294) --- .../Maxim/MAX32655/Include/max32655.svd | 6 + .../Device/Maxim/MAX32655/Include/tmr_regs.h | 3 + .../Maxim/MAX32657/Include/max32657.svd | 6 + .../Device/Maxim/MAX32657/Include/tmr_regs.h | 3 + .../Maxim/MAX32670/Include/max32670.svd | 6 + .../Device/Maxim/MAX32670/Include/tmr_regs.h | 3 + .../Maxim/MAX32672/Include/max32672.svd | 6 + .../Device/Maxim/MAX32672/Include/tmr_regs.h | 3 + .../Maxim/MAX32675/Include/max32675.svd | 6 + .../Device/Maxim/MAX32675/Include/tmr_regs.h | 3 + .../Maxim/MAX32690/Include/max32690.svd | 6 + .../Device/Maxim/MAX32690/Include/tmr_regs.h | 3 + .../Maxim/MAX78000/Include/max78000.svd | 6 + .../Device/Maxim/MAX78000/Include/tmr_regs.h | 3 + .../Maxim/MAX78002/Include/max78002.svd | 6 + .../Device/Maxim/MAX78002/Include/tmr_regs.h | 3 + .../PeriphDrivers/Source/TMR/tmr_revb.svd | 1324 +++++++++-------- .../Source/TMR/tmr_revb_me15.svd | 1322 ++++++++-------- .../Source/TMR/tmr_revb_me17.svd | 1322 ++++++++-------- .../Source/TMR/tmr_revb_me21.svd | 1324 +++++++++-------- .../Source/TMR/tmr_revb_me30.svd | 1322 ++++++++-------- .../PeriphDrivers/Source/TMR/tmr_revb_regs.h | 486 +++--- .../Source/UART/uart_revb_regs.h | 299 ++-- 23 files changed, 3778 insertions(+), 3693 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd index fe453eda1b2..f4aadcba9ed 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd @@ -11168,6 +11168,12 @@ 14 1 + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h index 55a40a62d91..339d28299e3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 0beab42655e..919cf24974d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -10081,6 +10081,12 @@ 14 1 + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h index 94bf7f6dfcb..b1fe8a68d0f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -381,6 +381,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd index e9dc97607e2..fa418eaef48 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.svd @@ -8541,6 +8541,12 @@ 14 1 + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h index 7e88a04ed02..436c2ab548d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd index 98e5cbfeace..b8b9b253990 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.svd @@ -11666,6 +11666,12 @@ 14 1 + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h index 5bb43b39acf..b2838ddfd77 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd index a1951f062f0..e08e5782812 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.svd @@ -8547,6 +8547,12 @@ 14 1 + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h index 9fc3e78122f..2b4abe9e83a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd index 5a67f4cede8..6a19424aafe 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd @@ -19454,6 +19454,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se 14 1 + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h index 3d01330a99b..88f7530e2bf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd index 3ea4a1309c7..97003bf57c3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/max78000.svd @@ -11101,6 +11101,12 @@ 14 1 + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h index 33e8ce74a0e..cbd908bcfdb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd index 0919269cd44..8ce8846d2ba 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/max78002.svd @@ -16842,6 +16842,12 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se 14 1 + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + CLKSEL_B Timer Clock Select for Timer B diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h index 013b23f71e7..147ec9381d4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Include/tmr_regs.h @@ -383,6 +383,9 @@ typedef struct { #define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ #define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ + #define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ #define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd index 4e7fa6ebdc1..a05d5318acd 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb.svd @@ -1,662 +1,668 @@ - + - - TMR - Low-Power Configurable Timer - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR - - 1 - - - - - CNT - Timer Counter Register. - 0x00 - read-write - - - COUNT - The current count value for the timer. This field increments as the timer counts. - 0 - 32 - - - - - CMP - Timer Compare Register. - 0x04 - read-write - - - COMPARE - The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. - 0 - 32 - - - - - PWM - Timer PWM Register. - 0x08 - read-write - - - PWM - Timer PWM Match: + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. - 0 - 32 - - - - - INTFL - Timer Interrupt Status Register. - 0x0C - read-write - - - IRQ_A - Interrupt Flag for Timer A. - 0 - 1 - - - WRDONE_A - Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. - 8 - 1 - - - WR_DIS_A - Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. - 9 - 1 - - - IRQ_B - Interrupt Flag for Timer B. - 16 - 1 - - - WRDONE_B - Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. - 24 - 1 - - - WR_DIS_B - Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. - 25 - 1 - - - - - CTRL0 - Timer Control Register. - 0x10 - read-write - - - MODE_A - Mode Select for Timer A - 0 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_A - Clock Divider Select for Timer A - 4 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_A - Timer Polarity for Timer A - 8 - 1 - - - PWMSYNC_A - PWM Synchronization Mode for Timer A - 9 - 1 - - - NOLHPOL_A - PWM Phase A (Non-Overlapping High) Polarity for Timer A - 10 - 1 - - - NOLLPOL_A - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A - 11 - 1 - - - PWMCKBD_A - PWM Phase A-Prime Output Disable for Timer A - 12 - 1 - - - RST_A - Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. - 13 - 1 - - - CLKEN_A - Write 1 to Enable CLK_TMR for Timer A - 14 - 1 - - - EN_A - Enable for Timer A - 15 - 1 - - - MODE_B - Mode Select for Timer B - 16 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_B - Clock Divider Select for Timer B - 20 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_B - Timer Polarity for Timer B - 24 - 1 - - - PWMSYNC_B - PWM Synchronization Mode for Timer B - 25 - 1 - - - NOLHPOL_B - PWM Phase A (Non-Overlapping High) Polarity for Timer B - 26 - 1 - - - NOLLPOL_B - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B - 27 - 1 - - - PWMCKBD_B - PWM Phase A-Prime Output Disable for Timer B - 28 - 1 - - - RST_B - Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. - 29 - 1 - - - CLKEN_B - Write 1 to Enable CLK_TMR for Timer B - 30 - 1 - - - EN_B - Enable for Timer B - 31 - 1 - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - read-write - - - LO_A - Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 0 - 8 - - - HI_A - Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 8 - 8 - - - LO_B - Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 16 - 8 - - - HI_B - Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 24 - 8 - - - - - CTRL1 - Timer Configuration Register. - 0x18 - read-write - - - CLKSEL_A - Timer Clock Select for Timer A - 0 - 2 - - - CLKEN_A - Timer A Enable Status - 2 - 1 - - - CLKRDY_A - CLK_TMR Ready Flag for Timer A - 3 - 1 - - - EVENT_SEL_A - Event Select for Timer A - 4 - 3 - - - NEGTRIG_A - Negative Edge Trigger for Event for Timer A - 7 - 1 - - - IE_A - Interrupt Enable for Timer A - 8 - 1 - - - CAPEVENT_SEL_A - Capture Event Select for Timer A - 9 - 2 - - - SW_CAPEVENT_A - Software Capture Event for Timer A - 11 - 1 - - - WE_A - Wake-Up Enable for Timer A - 12 - 1 - - - OUTEN_A - OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A - 13 - 1 - - - OUTBEN_A - PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A - 14 - 1 - - - CLKSEL_B - Timer Clock Select for Timer B - 16 - 2 - - - CLKEN_B - Timer B Enable Status - 18 - 1 - - - CLKRDY_B - CLK_TMR Ready Flag for Timer B - 19 - 1 - - - EVENT_SEL_B - Event Select for Timer B - 20 - 3 - - - NEGTRIG_B - Negative Edge Trigger for Event for Timer B - 23 - 1 - - - IE_B - Interrupt Enable for Timer B - 24 - 1 - - - CAPEVENT_SEL_B - Capture Event Select for Timer B - 25 - 2 - - - SW_CAPEVENT_B - Software Capture Event for Timer B - 27 - 1 - - - WE_B - Wake-Up Enable for Timer B - 28 - 1 - - - CASCADE - Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. - 31 - 1 - - - - - WKFL - Timer Wakeup Status Register. - 0x1C - read-write - - - A - Wake-Up Flag for Timer A - 0 - 1 - - - B - Wake-Up Flag for Timer B - 16 - 1 - - - - - - - + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd index 5bb17764a0d..bb65faa3897 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me15.svd @@ -1,662 +1,668 @@  - - TMR - Low-Power Configurable Timer - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR - - 1 - - - - - CNT - Timer Counter Register. - 0x00 - read-write - - - COUNT - The current count value for the timer. This field increments as the timer counts. - 0 - 32 - - - - - CMP - Timer Compare Register. - 0x04 - read-write - - - COMPARE - The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. - 0 - 32 - - - - - PWM - Timer PWM Register. - 0x08 - read-write - - - PWM - Timer PWM Match: + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. - 0 - 32 - - - - - INTFL - Timer Interrupt Status Register. - 0x0C - read-write - - - IRQ_A - Interrupt Flag for Timer A. - 0 - 1 - - - WRDONE_A - Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. - 8 - 1 - - - WR_DIS_A - Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. - 9 - 1 - - - IRQ_B - Interrupt Flag for Timer B. - 16 - 1 - - - WRDONE_B - Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. - 24 - 1 - - - WR_DIS_B - Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. - 25 - 1 - - - - - CTRL0 - Timer Control Register. - 0x10 - read-write - - - MODE_A - Mode Select for Timer A - 0 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_A - Clock Divider Select for Timer A - 4 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_A - Timer Polarity for Timer A - 8 - 1 - - - PWMSYNC_A - PWM Synchronization Mode for Timer A - 9 - 1 - - - NOLHPOL_A - PWM Phase A (Non-Overlapping High) Polarity for Timer A - 10 - 1 - - - NOLLPOL_A - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A - 11 - 1 - - - PWMCKBD_A - PWM Phase A-Prime Output Disable for Timer A - 12 - 1 - - - RST_A - Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. - 13 - 1 - - - CLKEN_A - Write 1 to Enable CLK_TMR for Timer A - 14 - 1 - - - EN_A - Enable for Timer A - 15 - 1 - - - MODE_B - Mode Select for Timer B - 16 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_B - Clock Divider Select for Timer B - 20 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_B - Timer Polarity for Timer B - 24 - 1 - - - PWMSYNC_B - PWM Synchronization Mode for Timer B - 25 - 1 - - - NOLHPOL_B - PWM Phase A (Non-Overlapping High) Polarity for Timer B - 26 - 1 - - - NOLLPOL_B - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B - 27 - 1 - - - PWMCKBD_B - PWM Phase A-Prime Output Disable for Timer B - 28 - 1 - - - RST_B - Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. - 29 - 1 - - - CLKEN_B - Write 1 to Enable CLK_TMR for Timer B - 30 - 1 - - - EN_B - Enable for Timer B - 31 - 1 - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - read-write - - - LO_A - Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 0 - 8 - - - HI_A - Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 8 - 8 - - - LO_B - Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 16 - 8 - - - HI_B - Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 24 - 8 - - - - - CTRL1 - Timer Configuration Register. - 0x18 - read-write - - - CLKSEL_A - Timer Clock Select for Timer A - 0 - 2 - - - CLKEN_A - Timer A Enable Status - 2 - 1 - - - CLKRDY_A - CLK_TMR Ready Flag for Timer A - 3 - 1 - - - EVENT_SEL_A - Event Select for Timer A - 4 - 3 - - - NEGTRIG_A - Negative Edge Trigger for Event for Timer A - 7 - 1 - - - IE_A - Interrupt Enable for Timer A - 8 - 1 - - - CAPEVENT_SEL_A - Capture Event Select for Timer A - 9 - 2 - - - SW_CAPEVENT_A - Software Capture Event for Timer A - 11 - 1 - - - WE_A - Wake-Up Enable for Timer A - 12 - 1 - - - OUTEN_A - OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A - 13 - 1 - - - OUTBEN_A - PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A - 14 - 1 - - - CLKSEL_B - Timer Clock Select for Timer B - 16 - 2 - - - CLKEN_B - Timer B Enable Status - 18 - 1 - - - CLKRDY_B - CLK_TMR Ready Flag for Timer B - 19 - 1 - - - EVENT_SEL_B - Event Select for Timer B - 20 - 3 - - - NEGTRIG_B - Negative Edge Trigger for Event for Timer B - 23 - 1 - - - IE_B - Interrupt Enable for Timer B - 24 - 1 - - - CAPEVENT_SEL_B - Capture Event Select for Timer B - 25 - 2 - - - SW_CAPEVENT_B - Software Capture Event for Timer B - 27 - 1 - - - WE_B - Wake-Up Enable for Timer B - 28 - 1 - - - CASCADE - Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. - 31 - 1 - - - - - WKFL - Timer Wakeup Status Register. - 0x1C - read-write - - - A - Wake-Up Flag for Timer A - 0 - 1 - - - B - Wake-Up Flag for Timer B - 16 - 1 - - - - - - - + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd index 5bb17764a0d..a05d5318acd 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me17.svd @@ -1,662 +1,668 @@  - - TMR - Low-Power Configurable Timer - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR - - 1 - - - - - CNT - Timer Counter Register. - 0x00 - read-write - - - COUNT - The current count value for the timer. This field increments as the timer counts. - 0 - 32 - - - - - CMP - Timer Compare Register. - 0x04 - read-write - - - COMPARE - The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. - 0 - 32 - - - - - PWM - Timer PWM Register. - 0x08 - read-write - - - PWM - Timer PWM Match: + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. - 0 - 32 - - - - - INTFL - Timer Interrupt Status Register. - 0x0C - read-write - - - IRQ_A - Interrupt Flag for Timer A. - 0 - 1 - - - WRDONE_A - Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. - 8 - 1 - - - WR_DIS_A - Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. - 9 - 1 - - - IRQ_B - Interrupt Flag for Timer B. - 16 - 1 - - - WRDONE_B - Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. - 24 - 1 - - - WR_DIS_B - Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. - 25 - 1 - - - - - CTRL0 - Timer Control Register. - 0x10 - read-write - - - MODE_A - Mode Select for Timer A - 0 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_A - Clock Divider Select for Timer A - 4 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_A - Timer Polarity for Timer A - 8 - 1 - - - PWMSYNC_A - PWM Synchronization Mode for Timer A - 9 - 1 - - - NOLHPOL_A - PWM Phase A (Non-Overlapping High) Polarity for Timer A - 10 - 1 - - - NOLLPOL_A - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A - 11 - 1 - - - PWMCKBD_A - PWM Phase A-Prime Output Disable for Timer A - 12 - 1 - - - RST_A - Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. - 13 - 1 - - - CLKEN_A - Write 1 to Enable CLK_TMR for Timer A - 14 - 1 - - - EN_A - Enable for Timer A - 15 - 1 - - - MODE_B - Mode Select for Timer B - 16 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_B - Clock Divider Select for Timer B - 20 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_B - Timer Polarity for Timer B - 24 - 1 - - - PWMSYNC_B - PWM Synchronization Mode for Timer B - 25 - 1 - - - NOLHPOL_B - PWM Phase A (Non-Overlapping High) Polarity for Timer B - 26 - 1 - - - NOLLPOL_B - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B - 27 - 1 - - - PWMCKBD_B - PWM Phase A-Prime Output Disable for Timer B - 28 - 1 - - - RST_B - Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. - 29 - 1 - - - CLKEN_B - Write 1 to Enable CLK_TMR for Timer B - 30 - 1 - - - EN_B - Enable for Timer B - 31 - 1 - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - read-write - - - LO_A - Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 0 - 8 - - - HI_A - Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 8 - 8 - - - LO_B - Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 16 - 8 - - - HI_B - Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 24 - 8 - - - - - CTRL1 - Timer Configuration Register. - 0x18 - read-write - - - CLKSEL_A - Timer Clock Select for Timer A - 0 - 2 - - - CLKEN_A - Timer A Enable Status - 2 - 1 - - - CLKRDY_A - CLK_TMR Ready Flag for Timer A - 3 - 1 - - - EVENT_SEL_A - Event Select for Timer A - 4 - 3 - - - NEGTRIG_A - Negative Edge Trigger for Event for Timer A - 7 - 1 - - - IE_A - Interrupt Enable for Timer A - 8 - 1 - - - CAPEVENT_SEL_A - Capture Event Select for Timer A - 9 - 2 - - - SW_CAPEVENT_A - Software Capture Event for Timer A - 11 - 1 - - - WE_A - Wake-Up Enable for Timer A - 12 - 1 - - - OUTEN_A - OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A - 13 - 1 - - - OUTBEN_A - PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A - 14 - 1 - - - CLKSEL_B - Timer Clock Select for Timer B - 16 - 2 - - - CLKEN_B - Timer B Enable Status - 18 - 1 - - - CLKRDY_B - CLK_TMR Ready Flag for Timer B - 19 - 1 - - - EVENT_SEL_B - Event Select for Timer B - 20 - 3 - - - NEGTRIG_B - Negative Edge Trigger for Event for Timer B - 23 - 1 - - - IE_B - Interrupt Enable for Timer B - 24 - 1 - - - CAPEVENT_SEL_B - Capture Event Select for Timer B - 25 - 2 - - - SW_CAPEVENT_B - Software Capture Event for Timer B - 27 - 1 - - - WE_B - Wake-Up Enable for Timer B - 28 - 1 - - - CASCADE - Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. - 31 - 1 - - - - - WKFL - Timer Wakeup Status Register. - 0x1C - read-write - - - A - Wake-Up Flag for Timer A - 0 - 1 - - - B - Wake-Up Flag for Timer B - 16 - 1 - - - - - - - + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + ASYNC + Allows asynchronous reads of the PWM and CNT registers. + 15 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd index 03f4811b31f..d591d208d15 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me21.svd @@ -1,662 +1,668 @@ - + - - TMR - Low-Power Configurable Timer - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR - - 1 - - - - - CNT - Timer Counter Register. - 0x00 - read-write - - - COUNT - The current count value for the timer. This field increments as the timer counts. - 0 - 32 - - - - - CMP - Timer Compare Register. - 0x04 - read-write - - - COMPARE - The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. - 0 - 32 - - - - - PWM - Timer PWM Register. - 0x08 - read-write - - - PWM - Timer PWM Match: + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. - 0 - 32 - - - - - INTFL - Timer Interrupt Status Register. - 0x0C - read-write - - - IRQ_A - Interrupt Flag for Timer A. - 0 - 1 - - - WRDONE_A - Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. - 8 - 1 - - - WR_DIS_A - Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. - 9 - 1 - - - IRQ_B - Interrupt Flag for Timer B. - 16 - 1 - - - WRDONE_B - Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. - 24 - 1 - - - WR_DIS_B - Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. - 25 - 1 - - - - - CTRL0 - Timer Control Register. - 0x10 - read-write - - - MODE_A - Mode Select for Timer A - 0 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 12 - - - - - CLKDIV_A - Clock Divider Select for Timer A - 4 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_A - Timer Polarity for Timer A - 8 - 1 - - - PWMSYNC_A - PWM Synchronization Mode for Timer A - 9 - 1 - - - NOLHPOL_A - PWM Phase A (Non-Overlapping High) Polarity for Timer A - 10 - 1 - - - NOLLPOL_A - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A - 11 - 1 - - - PWMCKBD_A - PWM Phase A-Prime Output Disable for Timer A - 12 - 1 - - - RST_A - Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. - 13 - 1 - - - CLKEN_A - Write 1 to Enable CLK_TMR for Timer A - 14 - 1 - - - EN_A - Enable for Timer A - 15 - 1 - - - MODE_B - Mode Select for Timer B - 16 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_B - Clock Divider Select for Timer B - 20 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_B - Timer Polarity for Timer B - 24 - 1 - - - PWMSYNC_B - PWM Synchronization Mode for Timer B - 25 - 1 - - - NOLHPOL_B - PWM Phase A (Non-Overlapping High) Polarity for Timer B - 26 - 1 - - - NOLLPOL_B - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B - 27 - 1 - - - PWMCKBD_B - PWM Phase A-Prime Output Disable for Timer B - 28 - 1 - - - RST_B - Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. - 29 - 1 - - - CLKEN_B - Write 1 to Enable CLK_TMR for Timer B - 30 - 1 - - - EN_B - Enable for Timer B - 31 - 1 - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - read-write - - - LO_A - Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 0 - 8 - - - HI_A - Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 8 - 8 - - - LO_B - Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 16 - 8 - - - HI_B - Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 24 - 8 - - - - - CTRL1 - Timer Configuration Register. - 0x18 - read-write - - - CLKSEL_A - Timer Clock Select for Timer A - 0 - 2 - - - CLKEN_A - Timer A Enable Status - 2 - 1 - - - CLKRDY_A - CLK_TMR Ready Flag for Timer A - 3 - 1 - - - EVENT_SEL_A - Event Select for Timer A - 4 - 3 - - - NEGTRIG_A - Negative Edge Trigger for Event for Timer A - 7 - 1 - - - IE_A - Interrupt Enable for Timer A - 8 - 1 - - - CAPEVENT_SEL_A - Capture Event Select for Timer A - 9 - 2 - - - SW_CAPEVENT_A - Software Capture Event for Timer A - 11 - 1 - - - WE_A - Wake-Up Enable for Timer A - 12 - 1 - - - OUTEN_A - OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A - 13 - 1 - - - OUTBEN_A - PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A - 14 - 1 - - - CLKSEL_B - Timer Clock Select for Timer B - 16 - 2 - - - CLKEN_B - Timer B Enable Status - 18 - 1 - - - CLKRDY_B - CLK_TMR Ready Flag for Timer B - 19 - 1 - - - EVENT_SEL_B - Event Select for Timer B - 20 - 3 - - - NEGTRIG_B - Negative Edge Trigger for Event for Timer B - 23 - 1 - - - IE_B - Interrupt Enable for Timer B - 24 - 1 - - - CAPEVENT_SEL_B - Capture Event Select for Timer B - 25 - 2 - - - SW_CAPEVENT_B - Software Capture Event for Timer B - 27 - 1 - - - WE_B - Wake-Up Enable for Timer B - 28 - 1 - - - CASCADE - Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. - 31 - 1 - - - - - WKFL - Timer Wakeup Status Register. - 0x1C - read-write - - - A - Wake-Up Flag for Timer A - 0 - 1 - - - B - Wake-Up Flag for Timer B - 16 - 1 - - - - - - - + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 12 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd index 5bb17764a0d..bb65faa3897 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd @@ -1,662 +1,668 @@  - - TMR - Low-Power Configurable Timer - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR - - 1 - - - - - CNT - Timer Counter Register. - 0x00 - read-write - - - COUNT - The current count value for the timer. This field increments as the timer counts. - 0 - 32 - - - - - CMP - Timer Compare Register. - 0x04 - read-write - - - COMPARE - The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. - 0 - 32 - - - - - PWM - Timer PWM Register. - 0x08 - read-write - - - PWM - Timer PWM Match: + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. - 0 - 32 - - - - - INTFL - Timer Interrupt Status Register. - 0x0C - read-write - - - IRQ_A - Interrupt Flag for Timer A. - 0 - 1 - - - WRDONE_A - Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. - 8 - 1 - - - WR_DIS_A - Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. - 9 - 1 - - - IRQ_B - Interrupt Flag for Timer B. - 16 - 1 - - - WRDONE_B - Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. - 24 - 1 - - - WR_DIS_B - Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. - 25 - 1 - - - - - CTRL0 - Timer Control Register. - 0x10 - read-write - - - MODE_A - Mode Select for Timer A - 0 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_A - Clock Divider Select for Timer A - 4 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_A - Timer Polarity for Timer A - 8 - 1 - - - PWMSYNC_A - PWM Synchronization Mode for Timer A - 9 - 1 - - - NOLHPOL_A - PWM Phase A (Non-Overlapping High) Polarity for Timer A - 10 - 1 - - - NOLLPOL_A - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A - 11 - 1 - - - PWMCKBD_A - PWM Phase A-Prime Output Disable for Timer A - 12 - 1 - - - RST_A - Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. - 13 - 1 - - - CLKEN_A - Write 1 to Enable CLK_TMR for Timer A - 14 - 1 - - - EN_A - Enable for Timer A - 15 - 1 - - - MODE_B - Mode Select for Timer B - 16 - 4 - - - ONE_SHOT - One-Shot Mode - 0 - - - CONTINUOUS - Continuous Mode - 1 - - - COUNTER - Counter Mode - 2 - - - PWM - PWM Mode - 3 - - - CAPTURE - Capture Mode - 4 - - - COMPARE - Compare Mode - 5 - - - GATED - Gated Mode - 6 - - - CAPCOMP - Capture/Compare Mode - 7 - - - DUAL_EDGE - Dual Edge Capture Mode - 8 - - - IGATED - Inactive Gated Mode - 14 - - - - - CLKDIV_B - Clock Divider Select for Timer B - 20 - 4 - - - DIV_BY_1 - Prescaler Divide-By-1 - 0 - - - DIV_BY_2 - Prescaler Divide-By-2 - 1 - - - DIV_BY_4 - Prescaler Divide-By-4 - 2 - - - DIV_BY_8 - Prescaler Divide-By-8 - 3 - - - DIV_BY_16 - Prescaler Divide-By-16 - 4 - - - DIV_BY_32 - Prescaler Divide-By-32 - 5 - - - DIV_BY_64 - Prescaler Divide-By-64 - 6 - - - DIV_BY_128 - Prescaler Divide-By-128 - 7 - - - DIV_BY_256 - Prescaler Divide-By-256 - 8 - - - DIV_BY_512 - Prescaler Divide-By-512 - 9 - - - DIV_BY_1024 - Prescaler Divide-By-1024 - 10 - - - DIV_BY_2048 - Prescaler Divide-By-2048 - 11 - - - DIV_BY_4096 - TBD - 12 - - - - - POL_B - Timer Polarity for Timer B - 24 - 1 - - - PWMSYNC_B - PWM Synchronization Mode for Timer B - 25 - 1 - - - NOLHPOL_B - PWM Phase A (Non-Overlapping High) Polarity for Timer B - 26 - 1 - - - NOLLPOL_B - PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B - 27 - 1 - - - PWMCKBD_B - PWM Phase A-Prime Output Disable for Timer B - 28 - 1 - - - RST_B - Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. - 29 - 1 - - - CLKEN_B - Write 1 to Enable CLK_TMR for Timer B - 30 - 1 - - - EN_B - Enable for Timer B - 31 - 1 - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - read-write - - - LO_A - Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 0 - 8 - - - HI_A - Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 8 - 8 - - - LO_B - Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. - 16 - 8 - - - HI_B - Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. - 24 - 8 - - - - - CTRL1 - Timer Configuration Register. - 0x18 - read-write - - - CLKSEL_A - Timer Clock Select for Timer A - 0 - 2 - - - CLKEN_A - Timer A Enable Status - 2 - 1 - - - CLKRDY_A - CLK_TMR Ready Flag for Timer A - 3 - 1 - - - EVENT_SEL_A - Event Select for Timer A - 4 - 3 - - - NEGTRIG_A - Negative Edge Trigger for Event for Timer A - 7 - 1 - - - IE_A - Interrupt Enable for Timer A - 8 - 1 - - - CAPEVENT_SEL_A - Capture Event Select for Timer A - 9 - 2 - - - SW_CAPEVENT_A - Software Capture Event for Timer A - 11 - 1 - - - WE_A - Wake-Up Enable for Timer A - 12 - 1 - - - OUTEN_A - OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A - 13 - 1 - - - OUTBEN_A - PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A - 14 - 1 - - - CLKSEL_B - Timer Clock Select for Timer B - 16 - 2 - - - CLKEN_B - Timer B Enable Status - 18 - 1 - - - CLKRDY_B - CLK_TMR Ready Flag for Timer B - 19 - 1 - - - EVENT_SEL_B - Event Select for Timer B - 20 - 3 - - - NEGTRIG_B - Negative Edge Trigger for Event for Timer B - 23 - 1 - - - IE_B - Interrupt Enable for Timer B - 24 - 1 - - - CAPEVENT_SEL_B - Capture Event Select for Timer B - 25 - 2 - - - SW_CAPEVENT_B - Software Capture Event for Timer B - 27 - 1 - - - WE_B - Wake-Up Enable for Timer B - 28 - 1 - - - CASCADE - Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. - 31 - 1 - - - - - WKFL - Timer Wakeup Status Register. - 0x1C - read-write - - - A - Wake-Up Flag for Timer A - 0 - 1 - - - B - Wake-Up Flag for Timer B - 16 - 1 - - - - - - - + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + ASYNC + Allows asynchronous reads to the PWM and CNT registers. + 15 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h index 282738bdf30..ae3f65ca0e9 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_regs.h @@ -1,6 +1,8 @@ /** * @file tmr_revb_regs.h * @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module. + * @note This file is @generated. + * @ingroup tmr_revb_registers */ /****************************************************************************** @@ -23,8 +25,8 @@ * ******************************************************************************/ -#ifndef _TMR_REVB_REGS_H_ -#define _TMR_REVB_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_ /* **** Includes **** */ #include @@ -32,11 +34,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -48,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -64,7 +70,7 @@ extern "C" { * @ingroup tmr_revb * @defgroup tmr_revb_registers TMR_REVB_Registers * @brief Registers, Bit Masks and Bit Positions for the TMR_REVB Peripheral Module. - * @details Low-Power Configurable Timer + * @details Low-Power Configurable Timer */ /** @@ -82,31 +88,14 @@ typedef struct { __IO uint32_t wkfl; /**< \b 0x1C: TMR_REVB WKFL Register */ } mxc_tmr_revb_regs_t; -/* Register offsets for module TMR_REVB */ -/** - * @ingroup tmr_revb_registers - * @defgroup TMR_REVB_Register_Offsets Register Offsets - * @brief TMR_REVB Peripheral Register Offsets from the TMR_REVB Base Peripheral Address. - * @{ - */ - #define MXC_R_TMR_REVB_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR_REVB Base Address: 0x0000 */ - #define MXC_R_TMR_REVB_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR_REVB Base Address: 0x0004 */ - #define MXC_R_TMR_REVB_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR_REVB Base Address: 0x0008 */ - #define MXC_R_TMR_REVB_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR_REVB Base Address: 0x000C */ - #define MXC_R_TMR_REVB_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR_REVB Base Address: 0x0010 */ - #define MXC_R_TMR_REVB_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR_REVB Base Address: 0x0014 */ - #define MXC_R_TMR_REVB_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR_REVB Base Address: 0x0018 */ - #define MXC_R_TMR_REVB_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR_REVB Base Address: 0x001C */ -/**@} end of group tmr_revb_registers */ - /** * @ingroup tmr_revb_registers * @defgroup TMR_REVB_CNT TMR_REVB_CNT * @brief Timer Counter Register. * @{ */ - #define MXC_F_TMR_REVB_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ - #define MXC_F_TMR_REVB_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ +#define MXC_F_TMR_REVB_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_TMR_REVB_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ /**@} end of group TMR_REVB_CNT_Register */ @@ -116,8 +105,8 @@ typedef struct { * @brief Timer Compare Register. * @{ */ - #define MXC_F_TMR_REVB_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ - #define MXC_F_TMR_REVB_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ +#define MXC_F_TMR_REVB_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_TMR_REVB_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ /**@} end of group TMR_REVB_CMP_Register */ @@ -127,8 +116,8 @@ typedef struct { * @brief Timer PWM Register. * @{ */ - #define MXC_F_TMR_REVB_PWM_PWM_POS 0 /**< PWM_PWM Position */ - #define MXC_F_TMR_REVB_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_PWM_PWM_POS)) /**< PWM_PWM Mask */ +#define MXC_F_TMR_REVB_PWM_PWM_POS 0 /**< PWM_PWM Position */ +#define MXC_F_TMR_REVB_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_REVB_PWM_PWM_POS)) /**< PWM_PWM Mask */ /**@} end of group TMR_REVB_PWM_Register */ @@ -138,23 +127,23 @@ typedef struct { * @brief Timer Interrupt Status Register. * @{ */ - #define MXC_F_TMR_REVB_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ - #define MXC_F_TMR_REVB_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ +#define MXC_F_TMR_REVB_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ +#define MXC_F_TMR_REVB_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ - #define MXC_F_TMR_REVB_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ - #define MXC_F_TMR_REVB_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ +#define MXC_F_TMR_REVB_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ +#define MXC_F_TMR_REVB_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ - #define MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ - #define MXC_F_TMR_REVB_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ +#define MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ +#define MXC_F_TMR_REVB_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ - #define MXC_F_TMR_REVB_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ - #define MXC_F_TMR_REVB_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ +#define MXC_F_TMR_REVB_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ +#define MXC_F_TMR_REVB_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ - #define MXC_F_TMR_REVB_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ - #define MXC_F_TMR_REVB_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ +#define MXC_F_TMR_REVB_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ +#define MXC_F_TMR_REVB_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ - #define MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ - #define MXC_F_TMR_REVB_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ +#define MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ +#define MXC_F_TMR_REVB_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ /**@} end of group TMR_REVB_INTFL_Register */ @@ -164,157 +153,157 @@ typedef struct { * @brief Timer Control Register. * @{ */ - #define MXC_F_TMR_REVB_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ - #define MXC_F_TMR_REVB_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_PWM (MXC_V_TMR_REVB_CTRL0_MODE_A_PWM << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_GATED (MXC_V_TMR_REVB_CTRL0_MODE_A_GATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED ((uint32_t)0xCUL) /**< CTRL0_MODE_A_IGATED Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_A_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ - - #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ - #define MXC_F_TMR_REVB_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ - - #define MXC_F_TMR_REVB_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ - #define MXC_F_TMR_REVB_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ - #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ - #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ - #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ - #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ - #define MXC_F_TMR_REVB_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ - #define MXC_F_TMR_REVB_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ - #define MXC_F_TMR_REVB_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ - - #define MXC_F_TMR_REVB_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ - #define MXC_F_TMR_REVB_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_PWM (MXC_V_TMR_REVB_CTRL0_MODE_B_PWM << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_GATED (MXC_V_TMR_REVB_CTRL0_MODE_B_GATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ - #define MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ - #define MXC_S_TMR_REVB_CTRL0_MODE_B_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ - - #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ - #define MXC_F_TMR_REVB_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ - #define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ - #define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ - - #define MXC_F_TMR_REVB_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ - #define MXC_F_TMR_REVB_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ - #define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ - #define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ - #define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ - #define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ - #define MXC_F_TMR_REVB_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ - #define MXC_F_TMR_REVB_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ - - #define MXC_F_TMR_REVB_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ - #define MXC_F_TMR_REVB_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ +#define MXC_F_TMR_REVB_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ +#define MXC_F_TMR_REVB_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_A_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_PWM (MXC_V_TMR_REVB_CTRL0_MODE_A_PWM << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_A_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_GATED (MXC_V_TMR_REVB_CTRL0_MODE_A_GATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_A_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_A_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ + +#define MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ +#define MXC_F_TMR_REVB_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_REVB_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ +#define MXC_F_TMR_REVB_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ +#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ +#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ +#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ +#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ +#define MXC_F_TMR_REVB_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ +#define MXC_F_TMR_REVB_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ +#define MXC_F_TMR_REVB_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ + +#define MXC_F_TMR_REVB_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ +#define MXC_F_TMR_REVB_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_REVB_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_REVB_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_COUNTER (MXC_V_TMR_REVB_CTRL0_MODE_B_COUNTER << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_PWM (MXC_V_TMR_REVB_CTRL0_MODE_B_PWM << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_COMPARE (MXC_V_TMR_REVB_CTRL0_MODE_B_COMPARE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_GATED (MXC_V_TMR_REVB_CTRL0_MODE_B_GATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_REVB_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_REVB_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ +#define MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ +#define MXC_S_TMR_REVB_CTRL0_MODE_B_IGATED (MXC_V_TMR_REVB_CTRL0_MODE_B_IGATED << MXC_F_TMR_REVB_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ + +#define MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ +#define MXC_F_TMR_REVB_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ +#define MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ +#define MXC_S_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_REVB_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_REVB_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_REVB_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ +#define MXC_F_TMR_REVB_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ +#define MXC_F_TMR_REVB_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ +#define MXC_F_TMR_REVB_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ +#define MXC_F_TMR_REVB_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ +#define MXC_F_TMR_REVB_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ +#define MXC_F_TMR_REVB_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ +#define MXC_F_TMR_REVB_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ + +#define MXC_F_TMR_REVB_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ +#define MXC_F_TMR_REVB_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ /**@} end of group TMR_REVB_CTRL0_Register */ @@ -324,17 +313,17 @@ typedef struct { * @brief Timer Non-Overlapping Compare Register. * @{ */ - #define MXC_F_TMR_REVB_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ - #define MXC_F_TMR_REVB_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ +#define MXC_F_TMR_REVB_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ +#define MXC_F_TMR_REVB_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ - #define MXC_F_TMR_REVB_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ - #define MXC_F_TMR_REVB_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ +#define MXC_F_TMR_REVB_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ +#define MXC_F_TMR_REVB_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ - #define MXC_F_TMR_REVB_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ - #define MXC_F_TMR_REVB_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ +#define MXC_F_TMR_REVB_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ +#define MXC_F_TMR_REVB_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ - #define MXC_F_TMR_REVB_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ - #define MXC_F_TMR_REVB_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ +#define MXC_F_TMR_REVB_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ +#define MXC_F_TMR_REVB_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_REVB_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ /**@} end of group TMR_REVB_NOLCMP_Register */ @@ -344,68 +333,71 @@ typedef struct { * @brief Timer Configuration Register. * @{ */ - #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ + +#define MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ +#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ - #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ +#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ - #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ +#define MXC_F_TMR_REVB_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ - #define MXC_F_TMR_REVB_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ +#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ - #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ +#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ - #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ +#define MXC_F_TMR_REVB_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ - #define MXC_F_TMR_REVB_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ +#define MXC_F_TMR_REVB_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ - #define MXC_F_TMR_REVB_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ +#define MXC_F_TMR_REVB_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ - #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ - #define MXC_F_TMR_REVB_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ +#define MXC_F_TMR_REVB_CTRL1_ASYNC_POS 15 /**< CTRL1_ASYNC Position */ +#define MXC_F_TMR_REVB_CTRL1_ASYNC ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_ASYNC_POS)) /**< CTRL1_ASYNC Mask */ - #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ - #define MXC_F_TMR_REVB_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ +#define MXC_F_TMR_REVB_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ - #define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ +#define MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_REVB_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ - #define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ +#define MXC_F_TMR_REVB_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ - #define MXC_F_TMR_REVB_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ +#define MXC_F_TMR_REVB_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ - #define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ +#define MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_REVB_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ - #define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ +#define MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ - #define MXC_F_TMR_REVB_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ +#define MXC_F_TMR_REVB_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ +#define MXC_F_TMR_REVB_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ - #define MXC_F_TMR_REVB_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ - #define MXC_F_TMR_REVB_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ +#define MXC_F_TMR_REVB_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ +#define MXC_F_TMR_REVB_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_REVB_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ /**@} end of group TMR_REVB_CTRL1_Register */ @@ -415,11 +407,11 @@ typedef struct { * @brief Timer Wakeup Status Register. * @{ */ - #define MXC_F_TMR_REVB_WKFL_A_POS 0 /**< WKFL_A Position */ - #define MXC_F_TMR_REVB_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_A_POS)) /**< WKFL_A Mask */ +#define MXC_F_TMR_REVB_WKFL_A_POS 0 /**< WKFL_A Position */ +#define MXC_F_TMR_REVB_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_A_POS)) /**< WKFL_A Mask */ - #define MXC_F_TMR_REVB_WKFL_B_POS 16 /**< WKFL_B Position */ - #define MXC_F_TMR_REVB_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_B_POS)) /**< WKFL_B Mask */ +#define MXC_F_TMR_REVB_WKFL_B_POS 16 /**< WKFL_B Position */ +#define MXC_F_TMR_REVB_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_REVB_WKFL_B_POS)) /**< WKFL_B Mask */ /**@} end of group TMR_REVB_WKFL_Register */ @@ -427,4 +419,4 @@ typedef struct { } #endif -#endif /* _TMR_REVB_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_TMR_TMR_REVB_REGS_H_ diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h b/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h index 061aad630a1..b8cc0e9fba0 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb_regs.h @@ -1,6 +1,8 @@ /** * @file uart_revb_regs.h * @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module. + * @note This file is @generated. + * @ingroup uart_revb_registers */ /****************************************************************************** @@ -23,8 +25,8 @@ * ******************************************************************************/ -#ifndef _UART_REVB_REGS_H_ -#define _UART_REVB_REGS_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_ /* **** Includes **** */ #include @@ -32,11 +34,11 @@ #ifdef __cplusplus extern "C" { #endif - + #if defined (__ICCARM__) #pragma system_include #endif - + #if defined (__CC_ARM) #pragma anon_unions #endif @@ -48,7 +50,11 @@ extern "C" { #define __IO volatile #endif #ifndef __I -#define __I volatile const +#ifdef __cplusplus +#define __I volatile +#else +#define __I volatile const +#endif #endif #ifndef __O #define __O volatile @@ -64,7 +70,7 @@ extern "C" { * @ingroup uart_revb * @defgroup uart_revb_registers UART_REVB_Registers * @brief Registers, Bit Masks and Bit Positions for the UART_REVB Peripheral Module. - * @details UART Low Power Registers + * @details UART Low Power Registers */ /** @@ -87,102 +93,81 @@ typedef struct { __IO uint32_t wkfl; /**< \b 0x0038: UART_REVB WKFL Register */ } mxc_uart_revb_regs_t; -/* Register offsets for module UART_REVB */ -/** - * @ingroup uart_revb_registers - * @defgroup UART_REVB_Register_Offsets Register Offsets - * @brief UART_REVB Peripheral Register Offsets from the UART_REVB Base Peripheral Address. - * @{ - */ - #define MXC_R_UART_REVB_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART_REVB Base Address: 0x0000 */ - #define MXC_R_UART_REVB_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART_REVB Base Address: 0x0004 */ - #define MXC_R_UART_REVB_INT_EN ((uint32_t)0x00000008UL) /**< Offset from UART_REVB Base Address: 0x0008 */ - #define MXC_R_UART_REVB_INT_FL ((uint32_t)0x0000000CUL) /**< Offset from UART_REVB Base Address: 0x000C */ - #define MXC_R_UART_REVB_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART_REVB Base Address: 0x0010 */ - #define MXC_R_UART_REVB_OSR ((uint32_t)0x00000014UL) /**< Offset from UART_REVB Base Address: 0x0014 */ - #define MXC_R_UART_REVB_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART_REVB Base Address: 0x0018 */ - #define MXC_R_UART_REVB_PNR ((uint32_t)0x0000001CUL) /**< Offset from UART_REVB Base Address: 0x001C */ - #define MXC_R_UART_REVB_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART_REVB Base Address: 0x0020 */ - #define MXC_R_UART_REVB_DMA ((uint32_t)0x00000030UL) /**< Offset from UART_REVB Base Address: 0x0030 */ - #define MXC_R_UART_REVB_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART_REVB Base Address: 0x0034 */ - #define MXC_R_UART_REVB_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART_REVB Base Address: 0x0038 */ -/**@} end of group uart_revb_registers */ - /** * @ingroup uart_revb_registers * @defgroup UART_REVB_CTRL UART_REVB_CTRL * @brief Control register * @{ */ - #define MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ - #define MXC_F_UART_REVB_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ +#define MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ +#define MXC_F_UART_REVB_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ - #define MXC_F_UART_REVB_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ - #define MXC_F_UART_REVB_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ +#define MXC_F_UART_REVB_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ +#define MXC_F_UART_REVB_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ - #define MXC_F_UART_REVB_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ - #define MXC_F_UART_REVB_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ +#define MXC_F_UART_REVB_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ +#define MXC_F_UART_REVB_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ - #define MXC_F_UART_REVB_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ - #define MXC_F_UART_REVB_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ +#define MXC_F_UART_REVB_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ +#define MXC_F_UART_REVB_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ - #define MXC_F_UART_REVB_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ - #define MXC_F_UART_REVB_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ +#define MXC_F_UART_REVB_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ +#define MXC_F_UART_REVB_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ - #define MXC_F_UART_REVB_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ - #define MXC_F_UART_REVB_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ +#define MXC_F_UART_REVB_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ +#define MXC_F_UART_REVB_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ - #define MXC_F_UART_REVB_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ - #define MXC_F_UART_REVB_CTRL_RX_FLUSH ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ +#define MXC_F_UART_REVB_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ +#define MXC_F_UART_REVB_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ - #define MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ - #define MXC_F_UART_REVB_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ - #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ - #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ - #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ - #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ - #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ - #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ - #define MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ - #define MXC_S_UART_REVB_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ +#define MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ +#define MXC_F_UART_REVB_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ +#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ +#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ +#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ +#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ +#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ +#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ +#define MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ +#define MXC_S_UART_REVB_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_REVB_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_REVB_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ - #define MXC_F_UART_REVB_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ - #define MXC_F_UART_REVB_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ +#define MXC_F_UART_REVB_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ +#define MXC_F_UART_REVB_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ - #define MXC_F_UART_REVB_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ - #define MXC_F_UART_REVB_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ +#define MXC_F_UART_REVB_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ +#define MXC_F_UART_REVB_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ - #define MXC_F_UART_REVB_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ - #define MXC_F_UART_REVB_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ +#define MXC_F_UART_REVB_CTRL_RTSDC_POS 14 /**< CTRL_RTSDC Position */ +#define MXC_F_UART_REVB_CTRL_RTSDC ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_RTSDC_POS)) /**< CTRL_RTSDC Mask */ - #define MXC_F_UART_REVB_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ - #define MXC_F_UART_REVB_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ +#define MXC_F_UART_REVB_CTRL_BCLKEN_POS 15 /**< CTRL_BCLKEN Position */ +#define MXC_F_UART_REVB_CTRL_BCLKEN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKEN_POS)) /**< CTRL_BCLKEN Mask */ - #define MXC_F_UART_REVB_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ - #define MXC_F_UART_REVB_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ - #define MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ - #define MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ - #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */ - #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK1 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */ - #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ - #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ - #define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ - #define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ +#define MXC_F_UART_REVB_CTRL_BCLKSRC_POS 16 /**< CTRL_BCLKSRC Position */ +#define MXC_F_UART_REVB_CTRL_BCLKSRC ((uint32_t)(0x3UL << MXC_F_UART_REVB_CTRL_BCLKSRC_POS)) /**< CTRL_BCLKSRC Mask */ +#define MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Value */ +#define MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK (MXC_V_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_PERIPHERAL_CLOCK Setting */ +#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 ((uint32_t)0x1UL) /**< CTRL_BCLKSRC_CLK1 Value */ +#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK1 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK1 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK1 Setting */ +#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 ((uint32_t)0x2UL) /**< CTRL_BCLKSRC_CLK2 Value */ +#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK2 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK2 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK2 Setting */ +#define MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 ((uint32_t)0x3UL) /**< CTRL_BCLKSRC_CLK3 Value */ +#define MXC_S_UART_REVB_CTRL_BCLKSRC_CLK3 (MXC_V_UART_REVB_CTRL_BCLKSRC_CLK3 << MXC_F_UART_REVB_CTRL_BCLKSRC_POS) /**< CTRL_BCLKSRC_CLK3 Setting */ - #define MXC_F_UART_REVB_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ - #define MXC_F_UART_REVB_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ +#define MXC_F_UART_REVB_CTRL_DPFE_EN_POS 18 /**< CTRL_DPFE_EN Position */ +#define MXC_F_UART_REVB_CTRL_DPFE_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DPFE_EN_POS)) /**< CTRL_DPFE_EN Mask */ - #define MXC_F_UART_REVB_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ - #define MXC_F_UART_REVB_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ +#define MXC_F_UART_REVB_CTRL_BCLKRDY_POS 19 /**< CTRL_BCLKRDY Position */ +#define MXC_F_UART_REVB_CTRL_BCLKRDY ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_BCLKRDY_POS)) /**< CTRL_BCLKRDY Mask */ - #define MXC_F_UART_REVB_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ - #define MXC_F_UART_REVB_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ +#define MXC_F_UART_REVB_CTRL_UCAGM_POS 20 /**< CTRL_UCAGM Position */ +#define MXC_F_UART_REVB_CTRL_UCAGM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_UCAGM_POS)) /**< CTRL_UCAGM Mask */ - #define MXC_F_UART_REVB_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ - #define MXC_F_UART_REVB_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ +#define MXC_F_UART_REVB_CTRL_FDM_POS 21 /**< CTRL_FDM Position */ +#define MXC_F_UART_REVB_CTRL_FDM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_FDM_POS)) /**< CTRL_FDM Mask */ - #define MXC_F_UART_REVB_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ - #define MXC_F_UART_REVB_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ +#define MXC_F_UART_REVB_CTRL_DESM_POS 22 /**< CTRL_DESM Position */ +#define MXC_F_UART_REVB_CTRL_DESM ((uint32_t)(0x1UL << MXC_F_UART_REVB_CTRL_DESM_POS)) /**< CTRL_DESM Mask */ /**@} end of group UART_REVB_CTRL_Register */ @@ -192,29 +177,29 @@ typedef struct { * @brief Status register * @{ */ - #define MXC_F_UART_REVB_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ - #define MXC_F_UART_REVB_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ +#define MXC_F_UART_REVB_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ +#define MXC_F_UART_REVB_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ - #define MXC_F_UART_REVB_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ - #define MXC_F_UART_REVB_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ +#define MXC_F_UART_REVB_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ +#define MXC_F_UART_REVB_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ - #define MXC_F_UART_REVB_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ - #define MXC_F_UART_REVB_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ +#define MXC_F_UART_REVB_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ +#define MXC_F_UART_REVB_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - #define MXC_F_UART_REVB_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ - #define MXC_F_UART_REVB_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ +#define MXC_F_UART_REVB_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ +#define MXC_F_UART_REVB_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - #define MXC_F_UART_REVB_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ - #define MXC_F_UART_REVB_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ +#define MXC_F_UART_REVB_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ +#define MXC_F_UART_REVB_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - #define MXC_F_UART_REVB_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ - #define MXC_F_UART_REVB_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ +#define MXC_F_UART_REVB_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ +#define MXC_F_UART_REVB_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - #define MXC_F_UART_REVB_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ - #define MXC_F_UART_REVB_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ +#define MXC_F_UART_REVB_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ +#define MXC_F_UART_REVB_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ - #define MXC_F_UART_REVB_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ - #define MXC_F_UART_REVB_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ +#define MXC_F_UART_REVB_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ +#define MXC_F_UART_REVB_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_REVB_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ /**@} end of group UART_REVB_STATUS_Register */ @@ -224,23 +209,26 @@ typedef struct { * @brief Interrupt Enable control register * @{ */ - #define MXC_F_UART_REVB_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ - #define MXC_F_UART_REVB_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ +#define MXC_F_UART_REVB_INT_EN_RX_FERR_POS 0 /**< INT_EN_RX_FERR Position */ +#define MXC_F_UART_REVB_INT_EN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_FERR_POS)) /**< INT_EN_RX_FERR Mask */ - #define MXC_F_UART_REVB_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ - #define MXC_F_UART_REVB_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ +#define MXC_F_UART_REVB_INT_EN_RX_PAR_POS 1 /**< INT_EN_RX_PAR Position */ +#define MXC_F_UART_REVB_INT_EN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_PAR_POS)) /**< INT_EN_RX_PAR Mask */ - #define MXC_F_UART_REVB_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ - #define MXC_F_UART_REVB_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ +#define MXC_F_UART_REVB_INT_EN_CTS_EV_POS 2 /**< INT_EN_CTS_EV Position */ +#define MXC_F_UART_REVB_INT_EN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_CTS_EV_POS)) /**< INT_EN_CTS_EV Mask */ - #define MXC_F_UART_REVB_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ - #define MXC_F_UART_REVB_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ +#define MXC_F_UART_REVB_INT_EN_RX_OV_POS 3 /**< INT_EN_RX_OV Position */ +#define MXC_F_UART_REVB_INT_EN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_OV_POS)) /**< INT_EN_RX_OV Mask */ - #define MXC_F_UART_REVB_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ - #define MXC_F_UART_REVB_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ +#define MXC_F_UART_REVB_INT_EN_RX_THD_POS 4 /**< INT_EN_RX_THD Position */ +#define MXC_F_UART_REVB_INT_EN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_RX_THD_POS)) /**< INT_EN_RX_THD Mask */ - #define MXC_F_UART_REVB_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ - #define MXC_F_UART_REVB_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ +#define MXC_F_UART_REVB_INT_EN_TX_OB_POS 5 /**< INT_EN_TX_OB Position */ +#define MXC_F_UART_REVB_INT_EN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_OB_POS)) /**< INT_EN_TX_OB Mask */ + +#define MXC_F_UART_REVB_INT_EN_TX_HE_POS 6 /**< INT_EN_TX_HE Position */ +#define MXC_F_UART_REVB_INT_EN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_EN_TX_HE_POS)) /**< INT_EN_TX_HE Mask */ /**@} end of group UART_REVB_INT_EN_Register */ @@ -250,23 +238,26 @@ typedef struct { * @brief Interrupt status flags Control register * @{ */ - #define MXC_F_UART_REVB_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ - #define MXC_F_UART_REVB_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ +#define MXC_F_UART_REVB_INT_FL_RX_FERR_POS 0 /**< INT_FL_RX_FERR Position */ +#define MXC_F_UART_REVB_INT_FL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_FERR_POS)) /**< INT_FL_RX_FERR Mask */ + +#define MXC_F_UART_REVB_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ +#define MXC_F_UART_REVB_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ - #define MXC_F_UART_REVB_INT_FL_RX_PAR_POS 1 /**< INT_FL_RX_PAR Position */ - #define MXC_F_UART_REVB_INT_FL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_PAR_POS)) /**< INT_FL_RX_PAR Mask */ +#define MXC_F_UART_REVB_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ +#define MXC_F_UART_REVB_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ - #define MXC_F_UART_REVB_INT_FL_CTS_EV_POS 2 /**< INT_FL_CTS_EV Position */ - #define MXC_F_UART_REVB_INT_FL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_CTS_EV_POS)) /**< INT_FL_CTS_EV Mask */ +#define MXC_F_UART_REVB_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ +#define MXC_F_UART_REVB_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ - #define MXC_F_UART_REVB_INT_FL_RX_OV_POS 3 /**< INT_FL_RX_OV Position */ - #define MXC_F_UART_REVB_INT_FL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_OV_POS)) /**< INT_FL_RX_OV Mask */ +#define MXC_F_UART_REVB_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ +#define MXC_F_UART_REVB_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ - #define MXC_F_UART_REVB_INT_FL_RX_THD_POS 4 /**< INT_FL_RX_THD Position */ - #define MXC_F_UART_REVB_INT_FL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_RX_THD_POS)) /**< INT_FL_RX_THD Mask */ +#define MXC_F_UART_REVB_INT_FL_TX_OB_POS 5 /**< INT_FL_TX_OB Position */ +#define MXC_F_UART_REVB_INT_FL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_OB_POS)) /**< INT_FL_TX_OB Mask */ - #define MXC_F_UART_REVB_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ - #define MXC_F_UART_REVB_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ +#define MXC_F_UART_REVB_INT_FL_TX_HE_POS 6 /**< INT_FL_TX_HE Position */ +#define MXC_F_UART_REVB_INT_FL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_REVB_INT_FL_TX_HE_POS)) /**< INT_FL_TX_HE Mask */ /**@} end of group UART_REVB_INT_FL_Register */ @@ -276,8 +267,8 @@ typedef struct { * @brief Clock Divider register * @{ */ - #define MXC_F_UART_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ - #define MXC_F_UART_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ +#define MXC_F_UART_REVB_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_UART_REVB_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_REVB_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ /**@} end of group UART_REVB_CLKDIV_Register */ @@ -287,8 +278,8 @@ typedef struct { * @brief Over Sampling Rate register * @{ */ - #define MXC_F_UART_REVB_OSR_OSR_POS 0 /**< OSR_OSR Position */ - #define MXC_F_UART_REVB_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_REVB_OSR_OSR_POS)) /**< OSR_OSR Mask */ +#define MXC_F_UART_REVB_OSR_OSR_POS 0 /**< OSR_OSR Position */ +#define MXC_F_UART_REVB_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_REVB_OSR_OSR_POS)) /**< OSR_OSR Mask */ /**@} end of group UART_REVB_OSR_Register */ @@ -298,8 +289,8 @@ typedef struct { * @brief TX FIFO Output Peek register * @{ */ - #define MXC_F_UART_REVB_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ - #define MXC_F_UART_REVB_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ +#define MXC_F_UART_REVB_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ +#define MXC_F_UART_REVB_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ /**@} end of group UART_REVB_TXPEEK_Register */ @@ -309,11 +300,11 @@ typedef struct { * @brief Pin register * @{ */ - #define MXC_F_UART_REVB_PNR_CTS_POS 0 /**< PNR_CTS Position */ - #define MXC_F_UART_REVB_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_CTS_POS)) /**< PNR_CTS Mask */ +#define MXC_F_UART_REVB_PNR_CTS_POS 0 /**< PNR_CTS Position */ +#define MXC_F_UART_REVB_PNR_CTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_CTS_POS)) /**< PNR_CTS Mask */ - #define MXC_F_UART_REVB_PNR_RTS_POS 1 /**< PNR_RTS Position */ - #define MXC_F_UART_REVB_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_RTS_POS)) /**< PNR_RTS Mask */ +#define MXC_F_UART_REVB_PNR_RTS_POS 1 /**< PNR_RTS Position */ +#define MXC_F_UART_REVB_PNR_RTS ((uint32_t)(0x1UL << MXC_F_UART_REVB_PNR_RTS_POS)) /**< PNR_RTS Mask */ /**@} end of group UART_REVB_PNR_Register */ @@ -323,11 +314,11 @@ typedef struct { * @brief FIFO Read/Write register * @{ */ - #define MXC_F_UART_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ - #define MXC_F_UART_REVB_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ +#define MXC_F_UART_REVB_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_UART_REVB_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_REVB_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ - #define MXC_F_UART_REVB_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ - #define MXC_F_UART_REVB_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ +#define MXC_F_UART_REVB_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ +#define MXC_F_UART_REVB_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_REVB_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ /**@} end of group UART_REVB_FIFO_Register */ @@ -337,17 +328,17 @@ typedef struct { * @brief DMA Configuration register * @{ */ - #define MXC_F_UART_REVB_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ - #define MXC_F_UART_REVB_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ +#define MXC_F_UART_REVB_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_UART_REVB_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ - #define MXC_F_UART_REVB_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ - #define MXC_F_UART_REVB_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ +#define MXC_F_UART_REVB_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ +#define MXC_F_UART_REVB_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - #define MXC_F_UART_REVB_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ - #define MXC_F_UART_REVB_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ +#define MXC_F_UART_REVB_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_UART_REVB_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ - #define MXC_F_UART_REVB_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ - #define MXC_F_UART_REVB_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ +#define MXC_F_UART_REVB_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ +#define MXC_F_UART_REVB_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_REVB_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ /**@} end of group UART_REVB_DMA_Register */ @@ -357,14 +348,14 @@ typedef struct { * @brief Wake up enable Control register * @{ */ - #define MXC_F_UART_REVB_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ - #define MXC_F_UART_REVB_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ +#define MXC_F_UART_REVB_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ +#define MXC_F_UART_REVB_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ - #define MXC_F_UART_REVB_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ - #define MXC_F_UART_REVB_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ +#define MXC_F_UART_REVB_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ +#define MXC_F_UART_REVB_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ - #define MXC_F_UART_REVB_WKEN_RX_THD_POS 1 /**< WKEN_RX_THD Position */ - #define MXC_F_UART_REVB_WKEN_RX_THD ((uint32_t)(0x3UL << MXC_F_UART_REVB_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ +#define MXC_F_UART_REVB_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_UART_REVB_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ /**@} end of group UART_REVB_WKEN_Register */ @@ -374,14 +365,14 @@ typedef struct { * @brief Wake up Flags register * @{ */ - #define MXC_F_UART_REVB_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ - #define MXC_F_UART_REVB_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ +#define MXC_F_UART_REVB_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ +#define MXC_F_UART_REVB_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ - #define MXC_F_UART_REVB_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ - #define MXC_F_UART_REVB_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ +#define MXC_F_UART_REVB_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ +#define MXC_F_UART_REVB_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ - #define MXC_F_UART_REVB_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ - #define MXC_F_UART_REVB_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ +#define MXC_F_UART_REVB_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_UART_REVB_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_REVB_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ /**@} end of group UART_REVB_WKFL_Register */ @@ -389,4 +380,4 @@ typedef struct { } #endif -#endif /* _UART_REVB_REGS_H_ */ +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_UART_UART_REVB_REGS_H_