diff --git a/MAX/CMakeLists.txt b/MAX/CMakeLists.txt index d48409cd..717feffc 100644 --- a/MAX/CMakeLists.txt +++ b/MAX/CMakeLists.txt @@ -40,6 +40,8 @@ set(MSDK_PERIPH_INC_DIR ${MSDK_PERIPH_DIR}/Include/${TARGET_UC}) zephyr_include_directories( ./Include + ./Source/${TARGET_UC} + ${MSDK_LIBRARY_DIR}/CMSIS/Include ${MSDK_CMSIS_DIR}/Include ${MSDK_PERIPH_INC_DIR} ) @@ -49,6 +51,7 @@ add_subdirectory_ifdef(CONFIG_SOC_MAX32570 Source/MAX32570) add_subdirectory_ifdef(CONFIG_SOC_MAX32572 Source/MAX32572) add_subdirectory_ifdef(CONFIG_SOC_MAX32650 Source/MAX32650) add_subdirectory_ifdef(CONFIG_SOC_MAX32655 Source/MAX32655) +add_subdirectory_ifdef(CONFIG_SOC_MAX32657 Source/MAX32657) add_subdirectory_ifdef(CONFIG_SOC_MAX32660 Source/MAX32660) add_subdirectory_ifdef(CONFIG_SOC_MAX32662 Source/MAX32662) add_subdirectory_ifdef(CONFIG_SOC_MAX32665 Source/MAX32665) diff --git a/MAX/Include/wrap_max32_adc.h b/MAX/Include/wrap_max32_adc.h index aa1a4140..acd90ab0 100644 --- a/MAX/Include/wrap_max32_adc.h +++ b/MAX/Include/wrap_max32_adc.h @@ -153,7 +153,8 @@ static inline void Wrap_MXC_ADC_GetData(uint16_t **outdata) /* * MAX32690, related mapping */ -#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) +#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || \ + (CONFIG_SOC_MAX78002) #define WRAP_MXC_F_ADC_CONV_DONE_IE MXC_F_ADC_INTEN_SEQ_DONE #define WRAP_MXC_F_ADC_CONV_DONE_IF MXC_F_ADC_INTFL_SEQ_DONE diff --git a/MAX/Include/wrap_max32_dma.h b/MAX/Include/wrap_max32_dma.h index 191713b4..fe228dc3 100644 --- a/MAX/Include/wrap_max32_dma.h +++ b/MAX/Include/wrap_max32_dma.h @@ -26,11 +26,7 @@ extern "C" { #endif -/* - * MAX32665, MAX32666 related mapping - */ #if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - #define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CFG_CHDIEN #define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CFG_CTZIEN @@ -40,52 +36,7 @@ extern "C" { #define ADI_MAX32_DMA_STATUS_ST MXC_F_DMA_ST_CH_ST #define ADI_MAX32_DMA_CFG_REQ_POS MXC_F_DMA_CFG_REQSEL_POS - -static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma) -{ - return dma->intr; -} - -static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma) -{ - return MXC_DMA_Init(dma); -} - -static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma) -{ - MXC_DMA_DeInit(dma); -} - -static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) -{ - return MXC_DMA_AcquireChannel(dma); -} - -static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma) -{ - MXC_DMA_Handler(dma); -} - -static inline int Wrap_MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, - mxc_dma_complete_cb_t callback) -{ - return MXC_DMA_MemCpy(dma, dest, src, len, callback); -} - -static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, - mxc_dma_srcdst_t firstSrcDst, - mxc_dma_trans_chain_t callback) -{ - return MXC_DMA_DoTransfer(dma, config, firstSrcDst, callback); -} - -/* - * MAX32690, MAX32655 related mapping - */ -#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ - (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) - +#else #define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CTRL_DIS_IE #define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CTRL_CTZ_IE @@ -95,52 +46,89 @@ static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t #define ADI_MAX32_DMA_STATUS_ST MXC_F_DMA_STATUS_STATUS #define ADI_MAX32_DMA_CFG_REQ_POS MXC_F_DMA_CTRL_REQUEST_POS +#endif static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma) { +#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + return dma->intr; +#else return dma->intfl; +#endif } static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + return MXC_DMA_Init(dma); +#else (void)dma; return MXC_DMA_Init(); +#endif } static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + MXC_DMA_DeInit(dma); +#else (void)dma; MXC_DMA_DeInit(); +#endif } static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + return MXC_DMA_AcquireChannel(dma); +#else (void)dma; return MXC_DMA_AcquireChannel(); +#endif } static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + MXC_DMA_Handler(dma); +#else (void)dma; MXC_DMA_Handler(); +#endif } static inline int Wrap_MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + return MXC_DMA_MemCpy(dma, dest, src, len, callback); +#else (void)dma; return MXC_DMA_MemCpy(dest, src, len, callback); +#endif } static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { +#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + return MXC_DMA_DoTransfer(dma, config, firstSrcDst, callback); +#else (void)dma; return MXC_DMA_DoTransfer(config, firstSrcDst, callback); +#endif } -#endif // part number +static inline int Wrap_MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) +{ +#if defined(CONFIG_SOC_MAX32657) + return MXC_DMA_EnableInt(dma, ch); +#else + (void)dma; + return MXC_DMA_EnableInt(ch); +#endif +} #ifdef __cplusplus } diff --git a/MAX/Include/wrap_max32_i2c.h b/MAX/Include/wrap_max32_i2c.h index a3bf611e..b3a23108 100644 --- a/MAX/Include/wrap_max32_i2c.h +++ b/MAX/Include/wrap_max32_i2c.h @@ -130,7 +130,7 @@ static inline void Wrap_MXC_I2C_Stop(mxc_i2c_regs_t *i2c) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) /* * Control register bits */ diff --git a/MAX/Include/wrap_max32_lp.h b/MAX/Include/wrap_max32_lp.h index 3e4c22b0..2f3281f3 100644 --- a/MAX/Include/wrap_max32_lp.h +++ b/MAX/Include/wrap_max32_lp.h @@ -55,7 +55,8 @@ static inline void Wrap_MXC_LP_EnterPowerDownMode(void) /* * MAX32690, MAX32655 related mapping */ -#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) +#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || \ + (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) static inline void Wrap_MXC_LP_EnterLowPowerMode(void) { diff --git a/MAX/Include/wrap_max32_owm.h b/MAX/Include/wrap_max32_owm.h index e462abb4..21d5528e 100644 --- a/MAX/Include/wrap_max32_owm.h +++ b/MAX/Include/wrap_max32_owm.h @@ -40,7 +40,8 @@ static inline int Wrap_MXC_OWM_Init(const mxc_owm_cfg_t *cfg) /* * MAX32690, MAX32655 related mapping */ -#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) +#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || \ + (CONFIG_SOC_MAX78002) static inline int Wrap_MXC_OWM_Init(const mxc_owm_cfg_t *cfg) { diff --git a/MAX/Include/wrap_max32_spi.h b/MAX/Include/wrap_max32_spi.h index a756a318..bf2acbc9 100644 --- a/MAX/Include/wrap_max32_spi.h +++ b/MAX/Include/wrap_max32_spi.h @@ -75,15 +75,21 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) - + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_CONT_MODE +#else #define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_MST_MODE - +#endif #define ADI_MAX32_SPI_INT_FL_RX_UN MXC_F_SPI_INTFL_RX_UN #define ADI_MAX32_SPI_INT_FL_RX_OV MXC_F_SPI_INTFL_RX_OV #define ADI_MAX32_SPI_INT_FL_TX_UN MXC_F_SPI_INTFL_TX_UN #define ADI_MAX32_SPI_INT_FL_TX_OV MXC_F_SPI_INTFL_TX_OV +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_SPI_INT_FL_MST_DONE MXC_F_SPI_INTFL_CONT_DONE +#else #define ADI_MAX32_SPI_INT_FL_MST_DONE MXC_F_SPI_INTFL_MST_DONE +#endif #define ADI_MAX32_SPI_INT_FL_ABORT MXC_F_SPI_INTFL_ABORT #define ADI_MAX32_SPI_INT_FL_FAULT MXC_F_SPI_INTFL_FAULT #define ADI_MAX32_SPI_INT_FL_SSD MXC_F_SPI_INTFL_SSD @@ -96,7 +102,11 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua #define ADI_MAX32_SPI_INT_EN_RX_OV MXC_F_SPI_INTEN_RX_OV #define ADI_MAX32_SPI_INT_EN_TX_UN MXC_F_SPI_INTEN_TX_UN #define ADI_MAX32_SPI_INT_EN_TX_OV MXC_F_SPI_INTEN_TX_OV +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_SPI_INT_EN_MST_DONE MXC_F_SPI_INTEN_CONT_DONE +#else #define ADI_MAX32_SPI_INT_EN_MST_DONE MXC_F_SPI_INTEN_MST_DONE +#endif #define ADI_MAX32_SPI_INT_EN_ABORT MXC_F_SPI_INTEN_ABORT #define ADI_MAX32_SPI_INT_EN_FAULT MXC_F_SPI_INTEN_FAULT #define ADI_MAX32_SPI_INT_EN_SSD MXC_F_SPI_INTEN_SSD @@ -107,13 +117,13 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua #define ADI_MAX32_SPI_DMA_TX_FIFO_CLEAR MXC_F_SPI_DMA_TX_FLUSH #define ADI_MAX32_SPI_DMA_RX_FIFO_CLEAR MXC_F_SPI_DMA_RX_FLUSH -#if defined(CONFIG_SOC_MAX32662) +#if defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32662) #define ADI_MAX32_SPI_DMA_TX_DMA_EN MXC_F_SPI_DMA_TX_EN #define ADI_MAX32_SPI_DMA_RX_DMA_EN MXC_F_SPI_DMA_RX_EN #else #define ADI_MAX32_SPI_DMA_TX_DMA_EN MXC_F_SPI_DMA_DMA_TX_EN #define ADI_MAX32_SPI_DMA_RX_DMA_EN MXC_F_SPI_DMA_DMA_RX_EN -#endif /* defined(CONFIG_SOC_MAX32662) */ +#endif /* defined(CONFIG_SOC_MAX32657) || defined(CONFIG_SOC_MAX32662) */ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, unsigned ssPolarity, unsigned int hz) @@ -128,6 +138,12 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua #endif // part number +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_SPI_CTRL0_SS_CTRL MXC_F_SPI_CTRL0_TS_CTRL +#else +#define ADI_MAX32_SPI_CTRL0_SS_CTRL MXC_F_SPI_CTRL0_SS_CTRL +#endif + #ifdef __cplusplus } #endif diff --git a/MAX/Include/wrap_max32_sys.h b/MAX/Include/wrap_max32_sys.h index 7acc26eb..a1d3d14b 100644 --- a/MAX/Include/wrap_max32_sys.h +++ b/MAX/Include/wrap_max32_sys.h @@ -56,10 +56,15 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) #define ADI_MAX32_CLK_IPO MXC_SYS_CLOCK_IPO +#if defined(CONFIG_SOC_MAX78002) +#define ADI_MAX32_CLK_IPLL MXC_SYS_CLOCK_IPLL +#define ADI_MAX32_CLK_EBO MXC_SYS_CLOCK_EBO +#else #define ADI_MAX32_CLK_ERFO MXC_SYS_CLOCK_ERFO +#endif #define ADI_MAX32_CLK_IBRO MXC_SYS_CLOCK_IBRO #define ADI_MAX32_CLK_INRO MXC_SYS_CLOCK_INRO #define ADI_MAX32_CLK_ERTCO MXC_SYS_CLOCK_ERTCO diff --git a/MAX/Include/wrap_max32_tmr.h b/MAX/Include/wrap_max32_tmr.h index 7b10d6b2..310e90ed 100644 --- a/MAX/Include/wrap_max32_tmr.h +++ b/MAX/Include/wrap_max32_tmr.h @@ -103,9 +103,10 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) -#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) +#if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) || (CONFIG_SOC_MAX32657) || \ + (CONFIG_SOC_MAX32670) /* All timers are 32bits */ #define WRAP_MXC_IS_32B_TIMER(idx) (1) #elif defined(CONFIG_SOC_MAX32662) @@ -142,13 +143,16 @@ static inline int Wrap_MXC_TMR_GetClockIndex(int z_clock) return MXC_TMR_EXT_CLK; case 2: // ADI_MAX32_PRPH_CLK_SRC_IBRO return MXC_TMR_8M_CLK; +#if !defined(CONFIG_SOC_MAX78002) case 3: //ADI_MAX32_PRPH_CLK_SRC_ERFO return MXC_TMR_32M_CLK; +#endif case 4: //ADI_MAX32_PRPH_CLK_SRC_ERTCO return MXC_TMR_32K_CLK; case 5: //ADI_MAX32_PRPH_CLK_SRC_INRO return MXC_TMR_INRO_CLK; -#if defined(CONFIG_SOC_MAX32690) +#if defined(CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32690) || \ + (CONFIG_SOC_MAX78002) case 6: //ADI_MAX32_PRPH_CLK_SRC_ISO return MXC_TMR_ISO_CLK; #endif @@ -159,6 +163,10 @@ static inline int Wrap_MXC_TMR_GetClockIndex(int z_clock) void Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg) { +#if defined(CONFIG_SOC_MAX32657) + (void)tmr; + (void)cfg; +#else mxc_tmr_cfg_t mxc_cfg; mxc_cfg.pres = cfg->pres; @@ -172,6 +180,7 @@ void Wrap_MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, wrap_mxc_tmr_cfg_t *cfg) MXC_LP_EnableTimerWakeup(tmr); // Enable Timer wake-up source MXC_TMR_EnableWakeup(tmr, &mxc_cfg); +#endif } void Wrap_MXC_TMR_ClearWakeupFlags(mxc_tmr_regs_t *tmr) diff --git a/MAX/Include/wrap_max32_trng.h b/MAX/Include/wrap_max32_trng.h index 9ce5e4e4..b9f3a72e 100644 --- a/MAX/Include/wrap_max32_trng.h +++ b/MAX/Include/wrap_max32_trng.h @@ -46,7 +46,7 @@ static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data) { diff --git a/MAX/Include/wrap_max32_uart.h b/MAX/Include/wrap_max32_uart.h index 4501d442..713ec47a 100644 --- a/MAX/Include/wrap_max32_uart.h +++ b/MAX/Include/wrap_max32_uart.h @@ -119,12 +119,12 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) // status flags #define ADI_MAX32_UART_RX_EMPTY MXC_F_UART_STATUS_RX_EM #define ADI_MAX32_UART_TX_EMPTY MXC_F_UART_STATUS_TX_EM -#if defined(CONFIG_SOC_MAX32662) +#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657) // error flags #define ADI_MAX32_UART_ERROR_OVERRUN MXC_F_UART_INTFL_RX_OV #define ADI_MAX32_UART_ERROR_PARITY MXC_F_UART_INTFL_RX_PAR @@ -133,7 +133,11 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) #define ADI_MAX32_UART_INT_OE MXC_F_UART_INTEN_RX_OV // Overrun Error Interrupt #define ADI_MAX32_UART_INT_PE MXC_F_UART_INTEN_RX_PAR // Parity Error Interrupt #define ADI_MAX32_UART_INT_FE MXC_F_UART_INTEN_RX_FERR // Framing Error Interrupt +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_THD // Transmit Interrupt +#else #define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_HE // Transmit Interrupt +#endif #define ADI_MAX32_UART_INT_RX MXC_F_UART_INTEN_RX_THD // Receive Interrupt #define ADI_MAX32_UART_INT_CTS MXC_F_UART_INTEN_CTS_EV // CTS Modem Interrupt #define ADI_MAX32_UART_INT_TX_OEM MXC_F_UART_INTEN_TX_OB // TX FIFO Almost Empty Interrupt @@ -215,7 +219,7 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) static inline unsigned int Wrap_MXC_UART_GetRegINTEN(mxc_uart_regs_t *uart) { -#if defined(CONFIG_SOC_MAX32662) +#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657) return uart->inten; #else return uart->int_en; diff --git a/MAX/Include/wrap_max32_wdt.h b/MAX/Include/wrap_max32_wdt.h index 6bee4338..07823aff 100644 --- a/MAX/Include/wrap_max32_wdt.h +++ b/MAX/Include/wrap_max32_wdt.h @@ -85,7 +85,7 @@ static inline int Wrap_MXC_WDT_SelectClockSource(mxc_wdt_regs_t *wdt, uint32_t c */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX78002) #define WRAP_MXC_F_WDT_CTRL_EN MXC_F_WDT_CTRL_EN diff --git a/MAX/Include/wrap_max32xxx.h b/MAX/Include/wrap_max32xxx.h index fc8c250f..a8baaea0 100644 --- a/MAX/Include/wrap_max32xxx.h +++ b/MAX/Include/wrap_max32xxx.h @@ -57,6 +57,8 @@ extern "C" { #include #elif defined(CONFIG_SOC_MAX78002) #include +#elif defined(CONFIG_SOC_MAX32657) +#include #endif #ifdef __cplusplus diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/header_MAX32520.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/sla_header_MAX32520.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/header_MAX32520.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/sla_header_MAX32520.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c index cd165c50..4f98ee0c 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c @@ -91,6 +91,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -139,5 +150,6 @@ __weak void SystemInit(void) MXC_GPIO1->pdpu_sel0 |= 0xFFFFFFFF; MXC_GPIO1->pdpu_sel1 &= ~(0xFFFFFFFF); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/header_MAX32570.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/sla_header_MAX32570.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/header_MAX32570.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/sla_header_MAX32570.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c index 7355fed1..d437a2f9 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -138,5 +149,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header_MAX32572.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header_MAX32572.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c index ec43168f..c14d69d1 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -139,5 +150,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/header_MAX32650.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/sla_header_MAX32650.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/header_MAX32650.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/sla_header_MAX32650.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c index 7c917dbd..0cb9e419 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c @@ -96,6 +96,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -177,6 +188,7 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2S); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPIXIPR); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c index 80559e95..4409f35a 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c index 6b19dbf6..c735e55d 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c @@ -114,6 +114,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -164,6 +175,7 @@ __weak void SystemInit(void) MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); + PinInit(); Board_Init(); PalSysInit(); diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h new file mode 100644 index 00000000..d76e19f6 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h @@ -0,0 +1,218 @@ +/** + * @file aes_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @note This file is @generated. + * @ingroup aes_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aes + * @defgroup aes_registers AES_Registers + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @details AES Keys. + */ + +/** + * @ingroup aes_registers + * Structure type to access the AES Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: AES CTRL Register */ + __IO uint32_t status; /**< \b 0x0004: AES STATUS Register */ + __IO uint32_t intfl; /**< \b 0x0008: AES INTFL Register */ + __IO uint32_t inten; /**< \b 0x000C: AES INTEN Register */ + __IO uint32_t fifo; /**< \b 0x0010: AES FIFO Register */ +} mxc_aes_regs_t; + +/* Register offsets for module AES */ +/** + * @ingroup aes_registers + * @defgroup AES_Register_Offsets Register Offsets + * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. + * @{ + */ +#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: 0x0000 */ +#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: 0x0004 */ +#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: 0x0008 */ +#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: 0x000C */ +#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: 0x0010 */ +/**@} end of group aes_registers */ + +/** + * @ingroup aes_registers + * @defgroup AES_CTRL AES_CTRL + * @brief AES Control Register + * @{ + */ +#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ +#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ +#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ + +#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ +#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ + +#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ + +#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ +#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ + +/**@} end of group AES_CTRL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_STATUS AES_STATUS + * @brief AES Status Register + * @{ + */ +#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ +#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ + +#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ +#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ +#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ +#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ + +/**@} end of group AES_STATUS_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTFL AES_INTFL + * @brief AES Interrupt Flag Register + * @{ + */ +#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ +#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ + +#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ +#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ +#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ + +#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ +#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ + +#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */ +#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */ + +/**@} end of group AES_INTFL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTEN AES_INTEN + * @brief AES Interrupt Enable Register + * @{ + */ +#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ +#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ + +#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ +#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ +#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ + +#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ +#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ + +#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */ +#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */ + +/**@} end of group AES_INTEN_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_FIFO AES_FIFO + * @brief AES Data Register + * @{ + */ +#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group AES_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h new file mode 100644 index 00000000..3e030d4c --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h @@ -0,0 +1,107 @@ +/** + * @file aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @note This file is @generated. + * @ingroup aeskeys_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aeskeys + * @ingroup aes + * @defgroup aeskeys_registers AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @details AES Key Registers. + */ + +/** + * @ingroup aeskeys_registers + * Structure type to access the AESKEYS Registers. + */ +typedef struct { + __IO uint32_t key0; /**< \b 0x00: AESKEYS KEY0 Register */ + __IO uint32_t key1; /**< \b 0x04: AESKEYS KEY1 Register */ + __IO uint32_t key2; /**< \b 0x08: AESKEYS KEY2 Register */ + __IO uint32_t key3; /**< \b 0x0C: AESKEYS KEY3 Register */ + __IO uint32_t key4; /**< \b 0x10: AESKEYS KEY4 Register */ + __IO uint32_t key5; /**< \b 0x14: AESKEYS KEY5 Register */ + __IO uint32_t key6; /**< \b 0x18: AESKEYS KEY6 Register */ + __IO uint32_t key7; /**< \b 0x1C: AESKEYS KEY7 Register */ +} mxc_aeskeys_regs_t; + +/* Register offsets for module AESKEYS */ +/** + * @ingroup aeskeys_registers + * @defgroup AESKEYS_Register_Offsets Register Offsets + * @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: 0x0000 */ +#define MXC_R_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS Base Address: 0x0004 */ +#define MXC_R_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS Base Address: 0x0008 */ +#define MXC_R_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS Base Address: 0x000C */ +#define MXC_R_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: 0x0010 */ +#define MXC_R_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS Base Address: 0x0014 */ +#define MXC_R_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS Base Address: 0x0018 */ +#define MXC_R_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS Base Address: 0x001C */ +/**@} end of group aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h new file mode 100644 index 00000000..f501eddd --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/boost_regs.h @@ -0,0 +1,220 @@ +/** + * @file boost_regs.h + * @brief Registers, Bit Masks and Bit Positions for the BOOST Peripheral Module. + * @note This file is @generated. + * @ingroup boost_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup boost + * @defgroup boost_registers BOOST_Registers + * @brief Registers, Bit Masks and Bit Positions for the BOOST Peripheral Module. + * @details Boost Controller + */ + +/** + * @ingroup boost_registers + * Structure type to access the BOOST Registers. + */ +typedef struct { + __IO uint32_t disable; /**< \b 0x000: BOOST DISABLE Register */ + __IO uint32_t vregctrl; /**< \b 0x004: BOOST VREGCTRL Register */ + __I uint32_t ipeak; /**< \b 0x008: BOOST IPEAK Register */ + __I uint32_t maxton; /**< \b 0x00C: BOOST MAXTON Register */ + __I uint32_t iload; /**< \b 0x010: BOOST ILOAD Register */ + __IO uint32_t alert; /**< \b 0x014: BOOST ALERT Register */ + __I uint32_t rdy; /**< \b 0x018: BOOST RDY Register */ + __I uint32_t zxcal; /**< \b 0x01C: BOOST ZXCAL Register */ + __IO uint32_t inten; /**< \b 0x020: BOOST INTEN Register */ + __IO uint32_t intfl; /**< \b 0x024: BOOST INTFL Register */ +} mxc_boost_regs_t; + +/* Register offsets for module BOOST */ +/** + * @ingroup boost_registers + * @defgroup BOOST_Register_Offsets Register Offsets + * @brief BOOST Peripheral Register Offsets from the BOOST Base Peripheral Address. + * @{ + */ +#define MXC_R_BOOST_DISABLE ((uint32_t)0x00000000UL) /**< Offset from BOOST Base Address: 0x0000 */ +#define MXC_R_BOOST_VREGCTRL ((uint32_t)0x00000004UL) /**< Offset from BOOST Base Address: 0x0004 */ +#define MXC_R_BOOST_IPEAK ((uint32_t)0x00000008UL) /**< Offset from BOOST Base Address: 0x0008 */ +#define MXC_R_BOOST_MAXTON ((uint32_t)0x0000000CUL) /**< Offset from BOOST Base Address: 0x000C */ +#define MXC_R_BOOST_ILOAD ((uint32_t)0x00000010UL) /**< Offset from BOOST Base Address: 0x0010 */ +#define MXC_R_BOOST_ALERT ((uint32_t)0x00000014UL) /**< Offset from BOOST Base Address: 0x0014 */ +#define MXC_R_BOOST_RDY ((uint32_t)0x00000018UL) /**< Offset from BOOST Base Address: 0x0018 */ +#define MXC_R_BOOST_ZXCAL ((uint32_t)0x0000001CUL) /**< Offset from BOOST Base Address: 0x001C */ +#define MXC_R_BOOST_INTEN ((uint32_t)0x00000020UL) /**< Offset from BOOST Base Address: 0x0020 */ +#define MXC_R_BOOST_INTFL ((uint32_t)0x00000024UL) /**< Offset from BOOST Base Address: 0x0024 */ +/**@} end of group boost_registers */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_DISABLE BOOST_DISABLE + * @brief Boost Disable Register. + * @{ + */ +#define MXC_F_BOOST_DISABLE_DIS_POS 0 /**< DISABLE_DIS Position */ +#define MXC_F_BOOST_DISABLE_DIS ((uint32_t)(0x1UL << MXC_F_BOOST_DISABLE_DIS_POS)) /**< DISABLE_DIS Mask */ + +/**@} end of group BOOST_DISABLE_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_VREGCTRL BOOST_VREGCTRL + * @brief Boost Voltage Regulator Control Register. + * @{ + */ +#define MXC_F_BOOST_VREGCTRL_SET_POS 0 /**< VREGCTRL_SET Position */ +#define MXC_F_BOOST_VREGCTRL_SET ((uint32_t)(0x1FUL << MXC_F_BOOST_VREGCTRL_SET_POS)) /**< VREGCTRL_SET Mask */ + +/**@} end of group BOOST_VREGCTRL_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_IPEAK BOOST_IPEAK + * @brief Low Side FET Peak Current Register. + * @{ + */ +#define MXC_F_BOOST_IPEAK_SET_POS 0 /**< IPEAK_SET Position */ +#define MXC_F_BOOST_IPEAK_SET ((uint32_t)(0x7UL << MXC_F_BOOST_IPEAK_SET_POS)) /**< IPEAK_SET Mask */ + +/**@} end of group BOOST_IPEAK_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_MAXTON BOOST_MAXTON + * @brief Maximum Low Side FET Time-On Register. + * @{ + */ +#define MXC_F_BOOST_MAXTON_THD_POS 0 /**< MAXTON_THD Position */ +#define MXC_F_BOOST_MAXTON_THD ((uint32_t)(0xFUL << MXC_F_BOOST_MAXTON_THD_POS)) /**< MAXTON_THD Mask */ + +/**@} end of group BOOST_MAXTON_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ILOAD BOOST_ILOAD + * @brief Boost Cycle Count Register. + * @{ + */ +#define MXC_F_BOOST_ILOAD_CNT_POS 0 /**< ILOAD_CNT Position */ +#define MXC_F_BOOST_ILOAD_CNT ((uint32_t)(0xFFUL << MXC_F_BOOST_ILOAD_CNT_POS)) /**< ILOAD_CNT Mask */ + +/**@} end of group BOOST_ILOAD_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ALERT BOOST_ALERT + * @brief Boost Cycle Count Alert Register. + * @{ + */ +#define MXC_F_BOOST_ALERT_THD_POS 0 /**< ALERT_THD Position */ +#define MXC_F_BOOST_ALERT_THD ((uint32_t)(0xFFUL << MXC_F_BOOST_ALERT_THD_POS)) /**< ALERT_THD Mask */ + +/**@} end of group BOOST_ALERT_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_RDY BOOST_RDY + * @brief Boost Output Ready Register. + * @{ + */ +#define MXC_F_BOOST_RDY_OUT_POS 0 /**< RDY_OUT Position */ +#define MXC_F_BOOST_RDY_OUT ((uint32_t)(0x1UL << MXC_F_BOOST_RDY_OUT_POS)) /**< RDY_OUT Mask */ + +/**@} end of group BOOST_RDY_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_ZXCAL BOOST_ZXCAL + * @brief Zero Cross Calibration Register. + * @{ + */ +#define MXC_F_BOOST_ZXCAL_VAL_POS 0 /**< ZXCAL_VAL Position */ +#define MXC_F_BOOST_ZXCAL_VAL ((uint32_t)(0x1FUL << MXC_F_BOOST_ZXCAL_VAL_POS)) /**< ZXCAL_VAL Mask */ + +/**@} end of group BOOST_ZXCAL_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_INTEN BOOST_INTEN + * @brief Boost Alert Interrupt Enable Register. + * @{ + */ +#define MXC_F_BOOST_INTEN_ALERT_POS 0 /**< INTEN_ALERT Position */ +#define MXC_F_BOOST_INTEN_ALERT ((uint32_t)(0x1UL << MXC_F_BOOST_INTEN_ALERT_POS)) /**< INTEN_ALERT Mask */ + +/**@} end of group BOOST_INTEN_Register */ + +/** + * @ingroup boost_registers + * @defgroup BOOST_INTFL BOOST_INTFL + * @brief Boost Alert Interrupt Status Register. + * @{ + */ +#define MXC_F_BOOST_INTFL_ALERT_POS 0 /**< INTFL_ALERT Position */ +#define MXC_F_BOOST_INTFL_ALERT ((uint32_t)(0x1UL << MXC_F_BOOST_INTFL_ALERT_POS)) /**< INTFL_ALERT Mask */ + +/**@} end of group BOOST_INTFL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_BOOST_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h new file mode 100644 index 00000000..8f2430af --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -0,0 +1,185 @@ +/** + * @file crc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @note This file is @generated. + * @ingroup crc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup crc + * @defgroup crc_registers CRC_Registers + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @details CRC Registers. + */ + +/** + * @ingroup crc_registers + * Structure type to access the CRC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ + union { + __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ + }; + __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ + __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ +} mxc_crc_regs_t; + +/* Register offsets for module CRC */ +/** + * @ingroup crc_registers + * @defgroup CRC_Register_Offsets Register Offsets + * @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address. + * @{ + */ +#define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: 0x0000 */ +#define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: 0x0008 */ +#define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: 0x000C */ +/**@} end of group crc_registers */ + +/** + * @ingroup crc_registers + * @defgroup CRC_CTRL CRC_CTRL + * @brief CRC Control + * @{ + */ +#define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */ +#define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */ + +#define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */ +#define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */ + +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */ + +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */ + +#define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */ +#define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + +/**@} end of group CRC_CTRL_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN32 CRC_DATAIN32 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */ +#define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */ + +/**@} end of group CRC_DATAIN32_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN16 CRC_DATAIN16 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */ +#define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */ + +/**@} end of group CRC_DATAIN16_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN8 CRC_DATAIN8 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */ +#define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */ + +/**@} end of group CRC_DATAIN8_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_POLY CRC_POLY + * @brief CRC Polynomial + * @{ + */ +#define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */ +#define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */ + +/**@} end of group CRC_POLY_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_VAL CRC_VAL + * @brief Current CRC Value + * @{ + */ +#define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */ +#define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */ + +/**@} end of group CRC_VAL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h new file mode 100644 index 00000000..7c196348 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -0,0 +1,382 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @note This file is @generated. + * @ingroup dma_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x004: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x014: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x018: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x01C: DMA CNTRLD Register */ +} mxc_dma_ch_regs_t; + +typedef struct { + __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ + __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ +#define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0008 */ +#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x000C */ +#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0010 */ +#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0014 */ +#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0018 */ +#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x001C */ +#define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTEN DMA_INTEN + * @brief DMA Control Register. + * @{ + */ +#define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ +#define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ + +#define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ +#define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ + +#define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ +#define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ + +#define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ +#define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ + +/**@} end of group DMA_INTEN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTFL DMA_INTFL + * @brief DMA Interrupt Register. + * @{ + */ +#define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ +#define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ + +#define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ +#define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ + +#define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ +#define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ + +#define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ +#define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ + +/**@} end of group DMA_INTFL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CTRL DMA_CTRL + * @brief DMA Channel Control Register. + * @{ + */ +#define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ +#define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ + +#define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ +#define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ +#define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ +#define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ +#define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ +#define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ +#define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ +#define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ + +#define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ +#define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ +#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ +#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPIRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UARTRX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UARTRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UARTRX (MXC_V_DMA_CTRL_REQUEST_UARTRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX_CONT Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CRX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_CONT Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG ((uint32_t)0x8UL) /**< CTRL_REQUEST_I3CRX_TARG Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CRX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX_TARG Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPITX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UARTTX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UARTTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UARTTX (MXC_V_DMA_CTRL_REQUEST_UARTTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX_CONT Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT (MXC_V_DMA_CTRL_REQUEST_I3CTX_CONT << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_CONT Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG ((uint32_t)0x28UL) /**< CTRL_REQUEST_I3CTX_TARG Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG (MXC_V_DMA_CTRL_REQUEST_I3CTX_TARG << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX_TARG Setting */ +#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ + +#define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ +#define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ + +#define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ +#define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ +#define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ + +#define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ +#define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ + +#define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ +#define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ +#define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ +#define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ + +#define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ +#define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ + +#define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ +#define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ +#define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ +#define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ + +#define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ +#define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ + +#define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ +#define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ + +#define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ +#define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ + +#define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ +#define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ + +/**@} end of group DMA_CTRL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_STATUS DMA_STATUS + * @brief DMA Channel Status Register. + * @{ + */ +#define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ +#define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ + +#define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ +#define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ + +#define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ +#define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ + +#define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ +#define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ + +#define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ +#define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ + +#define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ +#define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ + +/**@} end of group DMA_STATUS_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ +#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ +#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ +#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ +#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ +#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ +#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRCRLD DMA_SRCRLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ +#define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ +#define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ + +/**@} end of group DMA_SRCRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DSTRLD DMA_DSTRLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ +#define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ +#define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ + +/**@} end of group DMA_DSTRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNTRLD DMA_CNTRLD + * @brief DMA Channel Count Reload Register. + * @{ + */ +#define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ +#define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ + +#define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ +#define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ + +/**@} end of group DMA_CNTRLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h new file mode 100644 index 00000000..62b4e1f2 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -0,0 +1,314 @@ +/** + * @file fcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @note This file is @generated. + * @ingroup fcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup fcr + * @defgroup fcr_registers FCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @details Function Control Register. + */ + +/** + * @ingroup fcr_registers + * Structure type to access the FCR Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: FCR CTRL Register */ + __IO uint32_t autocal0; /**< \b 0x04: FCR AUTOCAL0 Register */ + __IO uint32_t autocal1; /**< \b 0x08: FCR AUTOCAL1 Register */ + __IO uint32_t autocal2; /**< \b 0x0C: FCR AUTOCAL2 Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t erfoks; /**< \b 0x18: FCR ERFOKS Register */ + __IO uint32_t intfl; /**< \b 0x1C: FCR INTFL Register */ + __IO uint32_t inten; /**< \b 0x20: FCR INTEN Register */ + __IO uint32_t erfoctrl; /**< \b 0x24: FCR ERFOCTRL Register */ + __IO uint32_t frqcntctrl; /**< \b 0x28: FCR FRQCNTCTRL Register */ + __IO uint32_t frqcntcmp; /**< \b 0x2C: FCR FRQCNTCMP Register */ + __I uint32_t refclk; /**< \b 0x30: FCR REFCLK Register */ + __I uint32_t cmpclk; /**< \b 0x34: FCR CMPCLK Register */ +} mxc_fcr_regs_t; + +/* Register offsets for module FCR */ +/** + * @ingroup fcr_registers + * @defgroup FCR_Register_Offsets Register Offsets + * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. + * @{ + */ +#define MXC_R_FCR_CTRL ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +#define MXC_R_FCR_AUTOCAL0 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ +#define MXC_R_FCR_AUTOCAL1 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ +#define MXC_R_FCR_AUTOCAL2 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ +#define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ +#define MXC_R_FCR_INTFL ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ +#define MXC_R_FCR_INTEN ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_ERFOCTRL ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ +#define MXC_R_FCR_FRQCNTCTRL ((uint32_t)0x00000028UL) /**< Offset from FCR Base Address: 0x0028 */ +#define MXC_R_FCR_FRQCNTCMP ((uint32_t)0x0000002CUL) /**< Offset from FCR Base Address: 0x002C */ +#define MXC_R_FCR_REFCLK ((uint32_t)0x00000030UL) /**< Offset from FCR Base Address: 0x0030 */ +#define MXC_R_FCR_CMPCLK ((uint32_t)0x00000034UL) /**< Offset from FCR Base Address: 0x0034 */ +/**@} end of group fcr_registers */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_CTRL FCR_CTRL + * @brief Function Control 0 Register. + * @{ + */ +#define MXC_F_FCR_CTRL_BTLELDO_RF_POS 0 /**< CTRL_BTLELDO_RF Position */ +#define MXC_F_FCR_CTRL_BTLELDO_RF ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_RF_POS)) /**< CTRL_BTLELDO_RF Mask */ + +#define MXC_F_FCR_CTRL_BTLELDO_BB_POS 8 /**< CTRL_BTLELDO_BB Position */ +#define MXC_F_FCR_CTRL_BTLELDO_BB ((uint32_t)(0x1FUL << MXC_F_FCR_CTRL_BTLELDO_BB_POS)) /**< CTRL_BTLELDO_BB Mask */ + +#define MXC_F_FCR_CTRL_I3CDGEN0_POS 20 /**< CTRL_I3CDGEN0 Position */ +#define MXC_F_FCR_CTRL_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_CTRL_I3CDGEN0_POS)) /**< CTRL_I3CDGEN0 Mask */ + +#define MXC_F_FCR_CTRL_I3CDGEN1_POS 21 /**< CTRL_I3CDGEN1 Position */ +#define MXC_F_FCR_CTRL_I3CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_CTRL_I3CDGEN1_POS)) /**< CTRL_I3CDGEN1 Mask */ + +/**@} end of group FCR_CTRL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_AUTOCAL0 FCR_AUTOCAL0 + * @brief Automatic Calibration 0 Register. + * @{ + */ +#define MXC_F_FCR_AUTOCAL0_EN_POS 0 /**< AUTOCAL0_EN Position */ +#define MXC_F_FCR_AUTOCAL0_EN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_EN_POS)) /**< AUTOCAL0_EN Mask */ + +#define MXC_F_FCR_AUTOCAL0_RUN_POS 1 /**< AUTOCAL0_RUN Position */ +#define MXC_F_FCR_AUTOCAL0_RUN ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_RUN_POS)) /**< AUTOCAL0_RUN Mask */ + +#define MXC_F_FCR_AUTOCAL0_LOAD_TRIM_POS 2 /**< AUTOCAL0_LOAD_TRIM Position */ +#define MXC_F_FCR_AUTOCAL0_LOAD_TRIM ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_LOAD_TRIM_POS)) /**< AUTOCAL0_LOAD_TRIM Mask */ + +#define MXC_F_FCR_AUTOCAL0_GAIN_INV_POS 3 /**< AUTOCAL0_GAIN_INV Position */ +#define MXC_F_FCR_AUTOCAL0_GAIN_INV ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_GAIN_INV_POS)) /**< AUTOCAL0_GAIN_INV Mask */ + +#define MXC_F_FCR_AUTOCAL0_ATOMIC_POS 4 /**< AUTOCAL0_ATOMIC Position */ +#define MXC_F_FCR_AUTOCAL0_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_AUTOCAL0_ATOMIC_POS)) /**< AUTOCAL0_ATOMIC Mask */ + +#define MXC_F_FCR_AUTOCAL0_MU_POS 8 /**< AUTOCAL0_MU Position */ +#define MXC_F_FCR_AUTOCAL0_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_AUTOCAL0_MU_POS)) /**< AUTOCAL0_MU Mask */ + +#define MXC_F_FCR_AUTOCAL0_TRIM_OUT_POS 23 /**< AUTOCAL0_TRIM_OUT Position */ +#define MXC_F_FCR_AUTOCAL0_TRIM_OUT ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL0_TRIM_OUT_POS)) /**< AUTOCAL0_TRIM_OUT Mask */ + +/**@} end of group FCR_AUTOCAL0_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_AUTOCAL1 FCR_AUTOCAL1 + * @brief Automatic Calibration 1 Register. + * @{ + */ +#define MXC_F_FCR_AUTOCAL1_INIT_TRIM_POS 0 /**< AUTOCAL1_INIT_TRIM Position */ +#define MXC_F_FCR_AUTOCAL1_INIT_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_AUTOCAL1_INIT_TRIM_POS)) /**< AUTOCAL1_INIT_TRIM Mask */ + +/**@} end of group FCR_AUTOCAL1_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_AUTOCAL2 FCR_AUTOCAL2 + * @brief Automatic Calibration 2 Register. + * @{ + */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME_POS 0 /**< AUTOCAL2_RUNTIME Position */ +#define MXC_F_FCR_AUTOCAL2_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_AUTOCAL2_RUNTIME_POS)) /**< AUTOCAL2_RUNTIME Mask */ + +#define MXC_F_FCR_AUTOCAL2_DIV_POS 8 /**< AUTOCAL2_DIV Position */ +#define MXC_F_FCR_AUTOCAL2_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_AUTOCAL2_DIV_POS)) /**< AUTOCAL2_DIV Mask */ + +/**@} end of group FCR_AUTOCAL2_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_ERFOKS FCR_ERFOKS + * @brief ERFO Kick Start Register. + * @{ + */ +#define MXC_F_FCR_ERFOKS_CNT_POS 0 /**< ERFOKS_CNT Position */ +#define MXC_F_FCR_ERFOKS_CNT ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOKS_CNT_POS)) /**< ERFOKS_CNT Mask */ + +#define MXC_F_FCR_ERFOKS_EN_POS 7 /**< ERFOKS_EN Position */ +#define MXC_F_FCR_ERFOKS_EN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_EN_POS)) /**< ERFOKS_EN Mask */ + +#define MXC_F_FCR_ERFOKS_DRVSTR_POS 8 /**< ERFOKS_DRVSTR Position */ +#define MXC_F_FCR_ERFOKS_DRVSTR ((uint32_t)(0x7UL << MXC_F_FCR_ERFOKS_DRVSTR_POS)) /**< ERFOKS_DRVSTR Mask */ + +#define MXC_F_FCR_ERFOKS_X2_PLEN_POS 11 /**< ERFOKS_X2_PLEN Position */ +#define MXC_F_FCR_ERFOKS_X2_PLEN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_X2_PLEN_POS)) /**< ERFOKS_X2_PLEN Mask */ + +#define MXC_F_FCR_ERFOKS_CLKSEL_POS 12 /**< ERFOKS_CLKSEL Position */ +#define MXC_F_FCR_ERFOKS_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_ERFOKS_CLKSEL_POS)) /**< ERFOKS_CLKSEL Mask */ +#define MXC_V_FCR_ERFOKS_CLKSEL_NO_CLK ((uint32_t)0x0UL) /**< ERFOKS_CLKSEL_NO_CLK Value */ +#define MXC_S_FCR_ERFOKS_CLKSEL_NO_CLK (MXC_V_FCR_ERFOKS_CLKSEL_NO_CLK << MXC_F_FCR_ERFOKS_CLKSEL_POS) /**< ERFOKS_CLKSEL_NO_CLK Setting */ +#define MXC_V_FCR_ERFOKS_CLKSEL_IPO ((uint32_t)0x3UL) /**< ERFOKS_CLKSEL_IPO Value */ +#define MXC_S_FCR_ERFOKS_CLKSEL_IPO (MXC_V_FCR_ERFOKS_CLKSEL_IPO << MXC_F_FCR_ERFOKS_CLKSEL_POS) /**< ERFOKS_CLKSEL_IPO Setting */ + +/**@} end of group FCR_ERFOKS_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_INTFL FCR_INTFL + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_FCR_INTFL_ERTOC_RDY_POS 0 /**< INTFL_ERTOC_RDY Position */ +#define MXC_F_FCR_INTFL_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_ERTOC_RDY_POS)) /**< INTFL_ERTOC_RDY Mask */ + +#define MXC_F_FCR_INTFL_FRQCNT_POS 1 /**< INTFL_FRQCNT Position */ +#define MXC_F_FCR_INTFL_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTFL_FRQCNT_POS)) /**< INTFL_FRQCNT Mask */ + +/**@} end of group FCR_INTFL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_INTEN FCR_INTEN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_FCR_INTEN_ERTOC_RDY_POS 0 /**< INTEN_ERTOC_RDY Position */ +#define MXC_F_FCR_INTEN_ERTOC_RDY ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_ERTOC_RDY_POS)) /**< INTEN_ERTOC_RDY Mask */ + +#define MXC_F_FCR_INTEN_FRQCNT_POS 1 /**< INTEN_FRQCNT Position */ +#define MXC_F_FCR_INTEN_FRQCNT ((uint32_t)(0x1UL << MXC_F_FCR_INTEN_FRQCNT_POS)) /**< INTEN_FRQCNT Mask */ + +/**@} end of group FCR_INTEN_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_ERFOCTRL FCR_ERFOCTRL + * @brief ERFO Control Register. + * @{ + */ +#define MXC_F_FCR_ERFOCTRL_CAP_X1_POS 0 /**< ERFOCTRL_CAP_X1 Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_X1 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X1_POS)) /**< ERFOCTRL_CAP_X1 Mask */ + +#define MXC_F_FCR_ERFOCTRL_CAP_X2_POS 7 /**< ERFOCTRL_CAP_X2 Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_X2 ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOCTRL_CAP_X2_POS)) /**< ERFOCTRL_CAP_X2 Mask */ + +#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS 14 /**< ERFOCTRL_CAP_BYPASS Position */ +#define MXC_F_FCR_ERFOCTRL_CAP_BYPASS ((uint32_t)(0x1UL << MXC_F_FCR_ERFOCTRL_CAP_BYPASS_POS)) /**< ERFOCTRL_CAP_BYPASS Mask */ + +/**@} end of group FCR_ERFOCTRL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FRQCNTCTRL FCR_FRQCNTCTRL + * @brief Frequency Counter Control Register. + * @{ + */ +#define MXC_F_FCR_FRQCNTCTRL_START_POS 0 /**< FRQCNTCTRL_START Position */ +#define MXC_F_FCR_FRQCNTCTRL_START ((uint32_t)(0x1UL << MXC_F_FCR_FRQCNTCTRL_START_POS)) /**< FRQCNTCTRL_START Mask */ + +#define MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS 1 /**< FRQCNTCTRL_CMP_CLKSEL Position */ +#define MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS)) /**< FRQCNTCTRL_CMP_CLKSEL Mask */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC ((uint32_t)0x0UL) /**< FRQCNTCTRL_CMP_CLKSEL_RTC Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_RTC << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_RTC Setting */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO ((uint32_t)0x2UL) /**< FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_EXT_GPIO Setting */ +#define MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO ((uint32_t)0x3UL) /**< FRQCNTCTRL_CMP_CLKSEL_INRO Value */ +#define MXC_S_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO (MXC_V_FCR_FRQCNTCTRL_CMP_CLKSEL_INRO << MXC_F_FCR_FRQCNTCTRL_CMP_CLKSEL_POS) /**< FRQCNTCTRL_CMP_CLKSEL_INRO Setting */ + +/**@} end of group FCR_FRQCNTCTRL_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FRQCNTCMP FCR_FRQCNTCMP + * @brief Frequency Counter Compared Target Register. + * @{ + */ +#define MXC_F_FCR_FRQCNTCMP_TARGET_POS 0 /**< FRQCNTCMP_TARGET Position */ +#define MXC_F_FCR_FRQCNTCMP_TARGET ((uint32_t)(0x3FFFUL << MXC_F_FCR_FRQCNTCMP_TARGET_POS)) /**< FRQCNTCMP_TARGET Mask */ + +/**@} end of group FCR_FRQCNTCMP_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_REFCLK FCR_REFCLK + * @brief Reference Clock Result Register. + * @{ + */ +#define MXC_F_FCR_REFCLK_RESULT_POS 0 /**< REFCLK_RESULT Position */ +#define MXC_F_FCR_REFCLK_RESULT ((uint32_t)(0xFFFFFUL << MXC_F_FCR_REFCLK_RESULT_POS)) /**< REFCLK_RESULT Mask */ + +/**@} end of group FCR_REFCLK_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_CMPCLK FCR_CMPCLK + * @brief Compared Clock Result Register. + * @{ + */ +#define MXC_F_FCR_CMPCLK_RESULT_POS 0 /**< CMPCLK_RESULT Position */ +#define MXC_F_FCR_CMPCLK_RESULT ((uint32_t)(0x3FFFUL << MXC_F_FCR_CMPCLK_RESULT_POS)) /**< CMPCLK_RESULT Mask */ + +/**@} end of group FCR_CMPCLK_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h new file mode 100644 index 00000000..491a9573 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -0,0 +1,228 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @note This file is @generated. + * @ingroup flc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __R uint32_t rsv_0x28; + __IO uint32_t eccdata; /**< \b 0x2C: FLC ECCDATA Register */ + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ +#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ +#define MXC_R_FLC_ECCDATA ((uint32_t)0x0000002CUL) /**< Offset from FLC Base Address: 0x002C */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ +#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL FLC_CTRL + * @brief Flash Control Register. + * @{ + */ +#define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ + +#define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ + +#define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ + +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ + +#define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ + +#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ + +#define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_CTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ +#define MXC_F_FLC_INTR_DONE_IF_POS 0 /**< INTR_DONE_IF Position */ +#define MXC_F_FLC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ + +#define MXC_F_FLC_INTR_AF_IF_POS 1 /**< INTR_AF_IF Position */ +#define MXC_F_FLC_INTR_AF_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IF_POS)) /**< INTR_AF_IF Mask */ + +#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ +#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ + +#define MXC_F_FLC_INTR_AF_IE_POS 9 /**< INTR_AF_IE Position */ +#define MXC_F_FLC_INTR_AF_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IE_POS)) /**< INTR_AF_IE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ECCDATA FLC_ECCDATA + * @brief ECC Data Register. + * @{ + */ +#define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ + +#define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ + +/**@} end of group FLC_ECCDATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACTRL FLC_ACTRL + * @brief Access Control Register. Writing the ACTRL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl + * = 0x9608b2c1. When unlocked, a write of any word will disable access to system + * and user information block. Readback of this register is always zero. + * @{ + */ +#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ + +/**@} end of group FLC_ACTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h new file mode 100644 index 00000000..d49be0aa --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -0,0 +1,631 @@ +/** + * @file gcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @note This file is @generated. + * @ingroup gcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +typedef struct { + __IO uint32_t sysctrl; /**< \b 0x00: GCR SYSCTRL Register */ + __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ + __IO uint32_t clkctrl; /**< \b 0x08: GCR CLKCTRL Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t pclkdiv; /**< \b 0x18: GCR PCLKDIV Register */ + __R uint32_t rsv_0x1c_0x23[2]; + __IO uint32_t pclkdis0; /**< \b 0x24: GCR PCLKDIS0 Register */ + __IO uint32_t memctrl; /**< \b 0x28: GCR MEMCTRL Register */ + __IO uint32_t memz; /**< \b 0x2C: GCR MEMZ Register */ + __R uint32_t rsv_0x30_0x3f[4]; + __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ + __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ + __IO uint32_t pclkdis1; /**< \b 0x48: GCR PCLKDIS1 Register */ + __IO uint32_t eventen; /**< \b 0x4C: GCR EVENTEN Register */ + __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ + __IO uint32_t sysinten; /**< \b 0x54: GCR SYSINTEN Register */ + __R uint32_t rsv_0x58_0x63[3]; + __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ + __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ + __IO uint32_t eccinten; /**< \b 0x6C: GCR ECCINTEN Register */ + __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ + __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ + __IO uint32_t btleldodly; /**< \b 0x78: GCR BTLELDODLY Register */ + __R uint32_t rsv_0x7c; + __IO uint32_t gpr; /**< \b 0x80: GCR GPR Register */ +} mxc_gcr_regs_t; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ +#define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ +#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ +#define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ +#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ +#define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ +#define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ +#define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ +#define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ +#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ +#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ +#define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ +#define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ +#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ +#define MXC_R_GCR_SYSINTEN ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ +#define MXC_R_GCR_ECCINTEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ +#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ +#define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ +#define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: 0x0078 */ +#define MXC_R_GCR_GPR ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: 0x0080 */ +/**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSCTRL GCR_SYSCTRL + * @brief System Control. + * @{ + */ +#define MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS 6 /**< SYSCTRL_ICC_FLUSH Position */ +#define MXC_F_GCR_SYSCTRL_ICC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS)) /**< SYSCTRL_ICC_FLUSH Mask */ + +#define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ +#define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ + +#define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ + +#define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ +#define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ + +/**@} end of group GCR_SYSCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST0 GCR_RST0 + * @brief Reset. + * @{ + */ +#define MXC_F_GCR_RST0_DMA0_POS 0 /**< RST0_DMA0 Position */ +#define MXC_F_GCR_RST0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA0_POS)) /**< RST0_DMA0 Mask */ + +#define MXC_F_GCR_RST0_WDT_POS 1 /**< RST0_WDT Position */ +#define MXC_F_GCR_RST0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT_POS)) /**< RST0_WDT Mask */ + +#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ +#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ + +#define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ +#define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ + +#define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ +#define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ + +#define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ +#define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ + +#define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ +#define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ + +#define MXC_F_GCR_RST0_TMR4_POS 9 /**< RST0_TMR4 Position */ +#define MXC_F_GCR_RST0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR4_POS)) /**< RST0_TMR4 Mask */ + +#define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ +#define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ + +#define MXC_F_GCR_RST0_UART_POS 11 /**< RST0_UART Position */ +#define MXC_F_GCR_RST0_UART ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART_POS)) /**< RST0_UART Mask */ + +#define MXC_F_GCR_RST0_SPI_POS 13 /**< RST0_SPI Position */ +#define MXC_F_GCR_RST0_SPI ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI_POS)) /**< RST0_SPI Mask */ + +#define MXC_F_GCR_RST0_I3C_POS 16 /**< RST0_I3C Position */ +#define MXC_F_GCR_RST0_I3C ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I3C_POS)) /**< RST0_I3C Mask */ + +#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ +#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ + +#define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ +#define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ + +#define MXC_F_GCR_RST0_DMA1_POS 27 /**< RST0_DMA1 Position */ +#define MXC_F_GCR_RST0_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA1_POS)) /**< RST0_DMA1 Mask */ + +#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ +#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ + +#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ +#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ + +#define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ +#define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ + +/**@} end of group GCR_RST0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLKCTRL GCR_CLKCTRL + * @brief Clock Control. + * @{ + */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ + +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ + +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 18 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ + +#define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 26 /**< CLKCTRL_IPO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ + +/**@} end of group GCR_CLKCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ +#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ +#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ +#define MXC_V_GCR_PM_MODE_PDM ((uint32_t)0xAUL) /**< PM_MODE_PDM Value */ +#define MXC_S_GCR_PM_MODE_PDM (MXC_V_GCR_PM_MODE_PDM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_PDM Setting */ + +#define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ +#define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ + +#define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ +#define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ + +#define MXC_F_GCR_PM_WUT_WE_POS 7 /**< PM_WUT_WE Position */ +#define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) /**< PM_WUT_WE Mask */ + +#define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ +#define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIV GCR_PCLKDIV + * @brief Peripheral Clock Divider. + * @{ + */ +#define MXC_F_GCR_PCLKDIV_CLKDIV_POS 0 /**< PCLKDIV_CLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_CLKDIV ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_PCLKDIV_CLKDIV_POS)) /**< PCLKDIV_CLKDIV Mask */ + +/**@} end of group GCR_PCLKDIV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ +#define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_DMA0_POS 5 /**< PCLKDIS0_DMA0 Position */ +#define MXC_F_GCR_PCLKDIS0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA0_POS)) /**< PCLKDIS0_DMA0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_SPI_POS 6 /**< PCLKDIS0_SPI Position */ +#define MXC_F_GCR_PCLKDIS0_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI_POS)) /**< PCLKDIS0_SPI Mask */ + +#define MXC_F_GCR_PCLKDIS0_UART_POS 9 /**< PCLKDIS0_UART Position */ +#define MXC_F_GCR_PCLKDIS0_UART ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART_POS)) /**< PCLKDIS0_UART Mask */ + +#define MXC_F_GCR_PCLKDIS0_I3C_POS 13 /**< PCLKDIS0_I3C Position */ +#define MXC_F_GCR_PCLKDIS0_I3C ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I3C_POS)) /**< PCLKDIS0_I3C Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR4_POS 19 /**< PCLKDIS0_TMR4 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR4_POS)) /**< PCLKDIS0_TMR4 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ + +/**@} end of group GCR_PCLKDIS0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMCTRL GCR_MEMCTRL + * @brief Memory Clock Control Register. + * @{ + */ +#define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ +#define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ + +/**@} end of group GCR_MEMCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMZ GCR_MEMZ + * @brief Memory Zeroize Control. + * @{ + */ +#define MXC_F_GCR_MEMZ_SRAM0_POS 0 /**< MEMZ_SRAM0 Position */ +#define MXC_F_GCR_MEMZ_SRAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM0_POS)) /**< MEMZ_SRAM0 Mask */ + +#define MXC_F_GCR_MEMZ_SRAM1_POS 1 /**< MEMZ_SRAM1 Position */ +#define MXC_F_GCR_MEMZ_SRAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM1_POS)) /**< MEMZ_SRAM1 Mask */ + +#define MXC_F_GCR_MEMZ_SRAM2_POS 2 /**< MEMZ_SRAM2 Position */ +#define MXC_F_GCR_MEMZ_SRAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM2_POS)) /**< MEMZ_SRAM2 Mask */ + +#define MXC_F_GCR_MEMZ_SRAM3_POS 3 /**< MEMZ_SRAM3 Position */ +#define MXC_F_GCR_MEMZ_SRAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM3_POS)) /**< MEMZ_SRAM3 Mask */ + +#define MXC_F_GCR_MEMZ_SRAM4_POS 4 /**< MEMZ_SRAM4 Position */ +#define MXC_F_GCR_MEMZ_SRAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM4_POS)) /**< MEMZ_SRAM4 Mask */ + +#define MXC_F_GCR_MEMZ_ICC_POS 5 /**< MEMZ_ICC Position */ +#define MXC_F_GCR_MEMZ_ICC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC_POS)) /**< MEMZ_ICC Mask */ + +/**@} end of group GCR_MEMZ_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSST GCR_SYSST + * @brief System Status Register. + * @{ + */ +#define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ +#define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ + +/**@} end of group GCR_SYSST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST1 GCR_RST1 + * @brief Reset 1. + * @{ + */ +#define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ +#define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ + +#define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ +#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ + +#define MXC_F_GCR_RST1_AUTOCAL_POS 12 /**< RST1_AUTOCAL Position */ +#define MXC_F_GCR_RST1_AUTOCAL ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AUTOCAL_POS)) /**< RST1_AUTOCAL Mask */ + +#define MXC_F_GCR_RST1_BTLE_POS 18 /**< RST1_BTLE Position */ +#define MXC_F_GCR_RST1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_BTLE_POS)) /**< RST1_BTLE Mask */ + +/**@} end of group GCR_RST1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ +#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ + +#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ +#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ + +#define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ +#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ + +#define MXC_F_GCR_PCLKDIS1_DMA1_POS 21 /**< PCLKDIS1_DMA1 Position */ +#define MXC_F_GCR_PCLKDIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_DMA1_POS)) /**< PCLKDIS1_DMA1 Mask */ + +#define MXC_F_GCR_PCLKDIS1_WDT_POS 27 /**< PCLKDIS1_WDT Position */ +#define MXC_F_GCR_PCLKDIS1_WDT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT_POS)) /**< PCLKDIS1_WDT Mask */ + +/**@} end of group GCR_PCLKDIS1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVENTEN GCR_EVENTEN + * @brief Event Enable Register. + * @{ + */ +#define MXC_F_GCR_EVENTEN_DMA0_POS 0 /**< EVENTEN_DMA0 Position */ +#define MXC_F_GCR_EVENTEN_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA0_POS)) /**< EVENTEN_DMA0 Mask */ + +#define MXC_F_GCR_EVENTEN_DMA1_POS 1 /**< EVENTEN_DMA1 Position */ +#define MXC_F_GCR_EVENTEN_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA1_POS)) /**< EVENTEN_DMA1 Mask */ + +#define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ +#define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ + +/**@} end of group GCR_EVENTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REVISION GCR_REVISION + * @brief Revision Register. + * @{ + */ +#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ +#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ + +/**@} end of group GCR_REVISION_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSINTEN GCR_SYSINTEN + * @brief System Status Interrupt Enable Register. + * @{ + */ +#define MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS 0 /**< SYSINTEN_ICEUNLOCK Position */ +#define MXC_F_GCR_SYSINTEN_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS)) /**< SYSINTEN_ICEUNLOCK Mask */ + +/**@} end of group GCR_SYSINTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCERR GCR_ECCERR + * @brief ECC Error Register + * @{ + */ +#define MXC_F_GCR_ECCERR_FLASH_POS 0 /**< ECCERR_FLASH Position */ +#define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ + +/**@} end of group GCR_ECCERR_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCCED GCR_ECCCED + * @brief ECC Correctable Error Detect Register. + * @{ + */ +#define MXC_F_GCR_ECCCED_FLASH_POS 0 /**< ECCCED_FLASH Position */ +#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ + +/**@} end of group GCR_ECCCED_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCINTEN GCR_ECCINTEN + * @brief ECC Interrupt Enable Register + * @{ + */ +#define MXC_F_GCR_ECCINTEN_FLASH_POS 0 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ + +/**@} end of group GCR_ECCINTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCADDR GCR_ECCADDR + * @brief ECC Error Address Register + * @{ + */ +#define MXC_F_GCR_ECCADDR_DADDR_POS 0 /**< ECCADDR_DADDR Position */ +#define MXC_F_GCR_ECCADDR_DADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DADDR_POS)) /**< ECCADDR_DADDR Mask */ + +#define MXC_F_GCR_ECCADDR_DB_POS 14 /**< ECCADDR_DB Position */ +#define MXC_F_GCR_ECCADDR_DB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DB_POS)) /**< ECCADDR_DB Mask */ + +#define MXC_F_GCR_ECCADDR_DE_POS 15 /**< ECCADDR_DE Position */ +#define MXC_F_GCR_ECCADDR_DE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DE_POS)) /**< ECCADDR_DE Mask */ + +#define MXC_F_GCR_ECCADDR_TADDR_POS 16 /**< ECCADDR_TADDR Position */ +#define MXC_F_GCR_ECCADDR_TADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TADDR_POS)) /**< ECCADDR_TADDR Mask */ + +#define MXC_F_GCR_ECCADDR_TB_POS 30 /**< ECCADDR_TB Position */ +#define MXC_F_GCR_ECCADDR_TB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TB_POS)) /**< ECCADDR_TB Mask */ + +#define MXC_F_GCR_ECCADDR_TE_POS 31 /**< ECCADDR_TE Position */ +#define MXC_F_GCR_ECCADDR_TE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TE_POS)) /**< ECCADDR_TE Mask */ + +/**@} end of group GCR_ECCADDR_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_BTLELDOCTRL GCR_BTLELDOCTRL + * @brief BTLE LDO Control Register + * @{ + */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 0 /**< BTLELDOCTRL_BB_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 1 /**< BTLELDOCTRL_BB_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 2 /**< BTLELDOCTRL_BB_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 4 /**< BTLELDOCTRL_RF_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 5 /**< BTLELDOCTRL_RF_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 6 /**< BTLELDOCTRL_RF_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 8 /**< BTLELDOCTRL_RF_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 9 /**< BTLELDOCTRL_RF_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 10 /**< BTLELDOCTRL_BB_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 11 /**< BTLELDOCTRL_BB_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 12 /**< BTLELDOCTRL_BB_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 13 /**< BTLELDOCTRL_RF_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */ + +/**@} end of group GCR_BTLELDOCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_BTLELDODLY GCR_BTLELDODLY + * @brief BTLE LDO Delay Register + * @{ + */ +#define MXC_F_GCR_BTLELDODLY_BP_CNT_POS 0 /**< BTLELDODLY_BP_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_BP_CNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BP_CNT_POS)) /**< BTLELDODLY_BP_CNT Mask */ + +#define MXC_F_GCR_BTLELDODLY_BB_CNT_POS 8 /**< BTLELDODLY_BB_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_BB_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_BB_CNT_POS)) /**< BTLELDODLY_BB_CNT Mask */ + +#define MXC_F_GCR_BTLELDODLY_RF_CNT_POS 20 /**< BTLELDODLY_RF_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_RF_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RF_CNT_POS)) /**< BTLELDODLY_RF_CNT Mask */ + +/**@} end of group GCR_BTLELDODLY_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h new file mode 100644 index 00000000..6005fb79 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -0,0 +1,657 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @note This file is @generated. + * @ingroup gpio_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ + __IO uint32_t outen; /**< \b 0x0C: GPIO OUTEN Register */ + __IO uint32_t outen_set; /**< \b 0x10: GPIO OUTEN_SET Register */ + __IO uint32_t outen_clr; /**< \b 0x14: GPIO OUTEN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t intmode; /**< \b 0x28: GPIO INTMODE Register */ + __IO uint32_t intpol; /**< \b 0x2C: GPIO INTPOL Register */ + __IO uint32_t inen; /**< \b 0x30: GPIO INEN Register */ + __IO uint32_t inten; /**< \b 0x34: GPIO INTEN Register */ + __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ + __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ + __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ + __R uint32_t rsv_0x44; + __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ + __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ + __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ + __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ + __R uint32_t rsv_0x58; + __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ + __IO uint32_t padctrl; /**< \b 0x60: GPIO PADCTRL Register */ + __R uint32_t rsv_0x64; + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __R uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ + __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t pssel; /**< \b 0xB8: GPIO PSSEL Register */ + __R uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ +#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ +#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ +#define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ +#define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ +#define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ +#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ +#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ +#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ +#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ +#define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ +#define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ +#define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ +#define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ +#define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ +#define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ +#define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ +#define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ +#define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ +#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ +#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ +#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ +#define MXC_R_GPIO_PADCTRL ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ +#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ +#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ +#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ +#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ +#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ +#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ +#define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ +#define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ +#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ +#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ +#define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ +#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0 GPIO_EN0 + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ +#define MXC_F_GPIO_EN0_ALL_POS 0 /**< EN0_ALL Position */ +#define MXC_F_GPIO_EN0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_ALL_POS)) /**< EN0_ALL Mask */ +#define MXC_V_GPIO_EN0_ALL_ALTERNATE ((uint32_t)0x0UL) /**< EN0_ALL_ALTERNATE Value */ +#define MXC_S_GPIO_EN0_ALL_ALTERNATE (MXC_V_GPIO_EN0_ALL_ALTERNATE << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_ALTERNATE Setting */ +#define MXC_V_GPIO_EN0_ALL_GPIO ((uint32_t)0x1UL) /**< EN0_ALL_GPIO Value */ +#define MXC_S_GPIO_EN0_ALL_GPIO (MXC_V_GPIO_EN0_ALL_GPIO << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_GPIO Setting */ + +/**@} end of group GPIO_EN0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ + +/**@} end of group GPIO_EN0_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ + +/**@} end of group GPIO_EN0_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN GPIO_OUTEN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ +#define MXC_F_GPIO_OUTEN_ALL_POS 0 /**< OUTEN_ALL Position */ +#define MXC_F_GPIO_OUTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_ALL_POS)) /**< OUTEN_ALL Mask */ +#define MXC_V_GPIO_OUTEN_ALL_DIS ((uint32_t)0x0UL) /**< OUTEN_ALL_DIS Value */ +#define MXC_S_GPIO_OUTEN_ALL_DIS (MXC_V_GPIO_OUTEN_ALL_DIS << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_DIS Setting */ +#define MXC_V_GPIO_OUTEN_ALL_EN ((uint32_t)0x1UL) /**< OUTEN_ALL_EN Value */ +#define MXC_S_GPIO_OUTEN_ALL_EN (MXC_V_GPIO_OUTEN_ALL_EN << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_EN Setting */ + +/**@} end of group GPIO_OUTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ +#define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ + +/**@} end of group GPIO_OUTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ +#define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ +#define MXC_F_GPIO_OUT_ALL_POS 0 /**< OUT_ALL Position */ +#define MXC_F_GPIO_OUT_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_ALL_POS)) /**< OUT_ALL Mask */ +#define MXC_V_GPIO_OUT_ALL_LOW ((uint32_t)0x0UL) /**< OUT_ALL_LOW Value */ +#define MXC_S_GPIO_OUT_ALL_LOW (MXC_V_GPIO_OUT_ALL_LOW << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_LOW Setting */ +#define MXC_V_GPIO_OUT_ALL_HIGH ((uint32_t)0x1UL) /**< OUT_ALL_HIGH Value */ +#define MXC_S_GPIO_OUT_ALL_HIGH (MXC_V_GPIO_OUT_ALL_HIGH << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ +#define MXC_F_GPIO_OUT_SET_ALL_POS 0 /**< OUT_SET_ALL Position */ +#define MXC_F_GPIO_OUT_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_ALL_POS)) /**< OUT_SET_ALL Mask */ +#define MXC_V_GPIO_OUT_SET_ALL_NO ((uint32_t)0x0UL) /**< OUT_SET_ALL_NO Value */ +#define MXC_S_GPIO_OUT_SET_ALL_NO (MXC_V_GPIO_OUT_SET_ALL_NO << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_NO Setting */ +#define MXC_V_GPIO_OUT_SET_ALL_SET ((uint32_t)0x1UL) /**< OUT_SET_ALL_SET Value */ +#define MXC_S_GPIO_OUT_SET_ALL_SET (MXC_V_GPIO_OUT_SET_ALL_SET << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ +#define MXC_F_GPIO_OUT_CLR_ALL_POS 0 /**< OUT_CLR_ALL Position */ +#define MXC_F_GPIO_OUT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_ALL_POS)) /**< OUT_CLR_ALL Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ +#define MXC_F_GPIO_IN_ALL_POS 0 /**< IN_ALL Position */ +#define MXC_F_GPIO_IN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_ALL_POS)) /**< IN_ALL Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTMODE GPIO_INTMODE + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ +#define MXC_F_GPIO_INTMODE_ALL_POS 0 /**< INTMODE_ALL Position */ +#define MXC_F_GPIO_INTMODE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_ALL_POS)) /**< INTMODE_ALL Mask */ +#define MXC_V_GPIO_INTMODE_ALL_LEVEL ((uint32_t)0x0UL) /**< INTMODE_ALL_LEVEL Value */ +#define MXC_S_GPIO_INTMODE_ALL_LEVEL (MXC_V_GPIO_INTMODE_ALL_LEVEL << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_LEVEL Setting */ +#define MXC_V_GPIO_INTMODE_ALL_EDGE ((uint32_t)0x1UL) /**< INTMODE_ALL_EDGE Value */ +#define MXC_S_GPIO_INTMODE_ALL_EDGE (MXC_V_GPIO_INTMODE_ALL_EDGE << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_EDGE Setting */ + +/**@} end of group GPIO_INTMODE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTPOL GPIO_INTPOL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ +#define MXC_F_GPIO_INTPOL_ALL_POS 0 /**< INTPOL_ALL Position */ +#define MXC_F_GPIO_INTPOL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_ALL_POS)) /**< INTPOL_ALL Mask */ +#define MXC_V_GPIO_INTPOL_ALL_FALLING ((uint32_t)0x0UL) /**< INTPOL_ALL_FALLING Value */ +#define MXC_S_GPIO_INTPOL_ALL_FALLING (MXC_V_GPIO_INTPOL_ALL_FALLING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_FALLING Setting */ +#define MXC_V_GPIO_INTPOL_ALL_RISING ((uint32_t)0x1UL) /**< INTPOL_ALL_RISING Value */ +#define MXC_S_GPIO_INTPOL_ALL_RISING (MXC_V_GPIO_INTPOL_ALL_RISING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_RISING Setting */ + +/**@} end of group GPIO_INTPOL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN GPIO_INTEN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ +#define MXC_F_GPIO_INTEN_ALL_POS 0 /**< INTEN_ALL Position */ +#define MXC_F_GPIO_INTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_ALL_POS)) /**< INTEN_ALL Mask */ +#define MXC_V_GPIO_INTEN_ALL_DIS ((uint32_t)0x0UL) /**< INTEN_ALL_DIS Value */ +#define MXC_S_GPIO_INTEN_ALL_DIS (MXC_V_GPIO_INTEN_ALL_DIS << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_DIS Setting */ +#define MXC_V_GPIO_INTEN_ALL_EN ((uint32_t)0x1UL) /**< INTEN_ALL_EN Value */ +#define MXC_S_GPIO_INTEN_ALL_EN (MXC_V_GPIO_INTEN_ALL_EN << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_EN Setting */ + +/**@} end of group GPIO_INTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ +#define MXC_F_GPIO_INTEN_SET_ALL_POS 0 /**< INTEN_SET_ALL Position */ +#define MXC_F_GPIO_INTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_ALL_POS)) /**< INTEN_SET_ALL Mask */ +#define MXC_V_GPIO_INTEN_SET_ALL_NO ((uint32_t)0x0UL) /**< INTEN_SET_ALL_NO Value */ +#define MXC_S_GPIO_INTEN_SET_ALL_NO (MXC_V_GPIO_INTEN_SET_ALL_NO << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_NO Setting */ +#define MXC_V_GPIO_INTEN_SET_ALL_SET ((uint32_t)0x1UL) /**< INTEN_SET_ALL_SET Value */ +#define MXC_S_GPIO_INTEN_SET_ALL_SET (MXC_V_GPIO_INTEN_SET_ALL_SET << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_SET Setting */ + +/**@} end of group GPIO_INTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ +#define MXC_F_GPIO_INTEN_CLR_ALL_POS 0 /**< INTEN_CLR_ALL Position */ +#define MXC_F_GPIO_INTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_ALL_POS)) /**< INTEN_CLR_ALL Mask */ +#define MXC_V_GPIO_INTEN_CLR_ALL_NO ((uint32_t)0x0UL) /**< INTEN_CLR_ALL_NO Value */ +#define MXC_S_GPIO_INTEN_CLR_ALL_NO (MXC_V_GPIO_INTEN_CLR_ALL_NO << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_NO Setting */ +#define MXC_V_GPIO_INTEN_CLR_ALL_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_ALL_CLEAR Value */ +#define MXC_S_GPIO_INTEN_CLR_ALL_CLEAR (MXC_V_GPIO_INTEN_CLR_ALL_CLEAR << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_CLEAR Setting */ + +/**@} end of group GPIO_INTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL GPIO_INTFL + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_INTFL_ALL_POS 0 /**< INTFL_ALL Position */ +#define MXC_F_GPIO_INTFL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_ALL_POS)) /**< INTFL_ALL Mask */ +#define MXC_V_GPIO_INTFL_ALL_NO ((uint32_t)0x0UL) /**< INTFL_ALL_NO Value */ +#define MXC_S_GPIO_INTFL_ALL_NO (MXC_V_GPIO_INTFL_ALL_NO << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_NO Setting */ +#define MXC_V_GPIO_INTFL_ALL_PENDING ((uint32_t)0x1UL) /**< INTFL_ALL_PENDING Value */ +#define MXC_S_GPIO_INTFL_ALL_PENDING (MXC_V_GPIO_INTFL_ALL_PENDING << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_PENDING Setting */ + +/**@} end of group GPIO_INTFL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ +#define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ +#define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ + +/**@} end of group GPIO_INTFL_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN GPIO_WKEN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_WKEN_ALL_POS 0 /**< WKEN_ALL Position */ +#define MXC_F_GPIO_WKEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_ALL_POS)) /**< WKEN_ALL Mask */ +#define MXC_V_GPIO_WKEN_ALL_DIS ((uint32_t)0x0UL) /**< WKEN_ALL_DIS Value */ +#define MXC_S_GPIO_WKEN_ALL_DIS (MXC_V_GPIO_WKEN_ALL_DIS << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_DIS Setting */ +#define MXC_V_GPIO_WKEN_ALL_EN ((uint32_t)0x1UL) /**< WKEN_ALL_EN Value */ +#define MXC_S_GPIO_WKEN_ALL_EN (MXC_V_GPIO_WKEN_ALL_EN << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_EN Setting */ + +/**@} end of group GPIO_WKEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ +#define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ +#define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ + +/**@} end of group GPIO_WKEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ +#define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ + +/**@} end of group GPIO_WKEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_DUALEDGE_ALL_POS 0 /**< DUALEDGE_ALL Position */ +#define MXC_F_GPIO_DUALEDGE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_ALL_POS)) /**< DUALEDGE_ALL Mask */ +#define MXC_V_GPIO_DUALEDGE_ALL_NO ((uint32_t)0x0UL) /**< DUALEDGE_ALL_NO Value */ +#define MXC_S_GPIO_DUALEDGE_ALL_NO (MXC_V_GPIO_DUALEDGE_ALL_NO << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_NO Setting */ +#define MXC_V_GPIO_DUALEDGE_ALL_EN ((uint32_t)0x1UL) /**< DUALEDGE_ALL_EN Value */ +#define MXC_S_GPIO_DUALEDGE_ALL_EN (MXC_V_GPIO_DUALEDGE_ALL_EN << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_EN Setting */ + +/**@} end of group GPIO_DUALEDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PADCTRL GPIO_PADCTRL + * @brief GPIO Pad Control. Each bit in this register configures the pad for the + * associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_PADCTRL_ALL_POS 0 /**< PADCTRL_ALL Position */ +#define MXC_F_GPIO_PADCTRL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL_ALL_POS)) /**< PADCTRL_ALL Mask */ +#define MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL_ALL_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL_ALL_PU Value */ +#define MXC_S_GPIO_PADCTRL_ALL_PU (MXC_V_GPIO_PADCTRL_ALL_PU << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PU Setting */ +#define MXC_V_GPIO_PADCTRL_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL_ALL_PD Value */ +#define MXC_S_GPIO_PADCTRL_ALL_PD (MXC_V_GPIO_PADCTRL_ALL_PD << MXC_F_GPIO_PADCTRL_ALL_POS) /**< PADCTRL_ALL_PD Setting */ + +/**@} end of group GPIO_PADCTRL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_EN1_ALL_POS 0 /**< EN1_ALL Position */ +#define MXC_F_GPIO_EN1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_ALL_POS)) /**< EN1_ALL Mask */ +#define MXC_V_GPIO_EN1_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN1_ALL_PRIMARY Value */ +#define MXC_S_GPIO_EN1_ALL_PRIMARY (MXC_V_GPIO_EN1_ALL_PRIMARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_PRIMARY Setting */ +#define MXC_V_GPIO_EN1_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN1_ALL_SECONDARY Value */ +#define MXC_S_GPIO_EN1_ALL_SECONDARY (MXC_V_GPIO_EN1_ALL_SECONDARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_EN2_ALL_POS 0 /**< EN2_ALL Position */ +#define MXC_F_GPIO_EN2_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_ALL_POS)) /**< EN2_ALL Mask */ +#define MXC_V_GPIO_EN2_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN2_ALL_PRIMARY Value */ +#define MXC_S_GPIO_EN2_ALL_PRIMARY (MXC_V_GPIO_EN2_ALL_PRIMARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_PRIMARY Setting */ +#define MXC_V_GPIO_EN2_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN2_ALL_SECONDARY Value */ +#define MXC_S_GPIO_EN2_ALL_SECONDARY (MXC_V_GPIO_EN2_ALL_SECONDARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_HYSEN GPIO_HYSEN + * @brief GPIO Input Hysteresis Enable. + * @{ + */ +#define MXC_F_GPIO_HYSEN_ALL_POS 0 /**< HYSEN_ALL Position */ +#define MXC_F_GPIO_HYSEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_ALL_POS)) /**< HYSEN_ALL Mask */ + +/**@} end of group GPIO_HYSEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_SRSEL GPIO_SRSEL + * @brief GPIO Slew Rate Enable Register. + * @{ + */ +#define MXC_F_GPIO_SRSEL_ALL_POS 0 /**< SRSEL_ALL Position */ +#define MXC_F_GPIO_SRSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_ALL_POS)) /**< SRSEL_ALL Mask */ +#define MXC_V_GPIO_SRSEL_ALL_FAST ((uint32_t)0x0UL) /**< SRSEL_ALL_FAST Value */ +#define MXC_S_GPIO_SRSEL_ALL_FAST (MXC_V_GPIO_SRSEL_ALL_FAST << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_FAST Setting */ +#define MXC_V_GPIO_SRSEL_ALL_SLOW ((uint32_t)0x1UL) /**< SRSEL_ALL_SLOW Value */ +#define MXC_S_GPIO_SRSEL_ALL_SLOW (MXC_V_GPIO_SRSEL_ALL_SLOW << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_SLOW Setting */ + +/**@} end of group GPIO_SRSEL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS0 GPIO_DS0 + * @brief GPIO Drive Strength 0 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ +#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ +#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ +#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ +#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ +#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ +#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ + +/**@} end of group GPIO_DS0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ +#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ +#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PSSEL GPIO_PSSEL + * @brief GPIO Pull Select Mode. + * @{ + */ +#define MXC_F_GPIO_PSSEL_ALL_POS 0 /**< PSSEL_ALL Position */ +#define MXC_F_GPIO_PSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PSSEL_ALL_POS)) /**< PSSEL_ALL Mask */ + +/**@} end of group GPIO_PSSEL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ +#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ +#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h new file mode 100644 index 00000000..02d2f94e --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h @@ -0,0 +1,1619 @@ +/** + * @file i3c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I3C Peripheral Module. + * @note This file is @generated. + * @ingroup i3c_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i3c + * @defgroup i3c_registers I3C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I3C Peripheral Module. + * @details Improved Inter-Integrated Circuit. + */ + +/** + * @ingroup i3c_registers + * Structure type to access the I3C Registers. + */ +typedef struct { + __IO uint32_t cont_ctrl0; /**< \b 0x000: I3C CONT_CTRL0 Register */ + __IO uint32_t targ_ctrl0; /**< \b 0x004: I3C TARG_CTRL0 Register */ + __IO uint32_t targ_status; /**< \b 0x008: I3C TARG_STATUS Register */ + __IO uint32_t targ_ctrl1; /**< \b 0x00C: I3C TARG_CTRL1 Register */ + __IO uint32_t targ_inten; /**< \b 0x010: I3C TARG_INTEN Register */ + __O uint32_t targ_intclr; /**< \b 0x014: I3C TARG_INTCLR Register */ + __I uint32_t targ_intfl; /**< \b 0x018: I3C TARG_INTFL Register */ + __IO uint32_t targ_errwarn; /**< \b 0x01C: I3C TARG_ERRWARN Register */ + __IO uint32_t targ_dmactrl; /**< \b 0x020: I3C TARG_DMACTRL Register */ + __R uint32_t rsv_0x24_0x2b[2]; + __IO uint32_t targ_fifoctrl; /**< \b 0x02C: I3C TARG_FIFOCTRL Register */ + __O uint32_t targ_txfifo8; /**< \b 0x030: I3C TARG_TXFIFO8 Register */ + __O uint32_t targ_txfifo8e; /**< \b 0x034: I3C TARG_TXFIFO8E Register */ + __O uint32_t targ_txfifo16; /**< \b 0x038: I3C TARG_TXFIFO16 Register */ + __O uint32_t targ_txfifo16e; /**< \b 0x03C: I3C TARG_TXFIFO16E Register */ + __I uint32_t targ_rxfifo8; /**< \b 0x040: I3C TARG_RXFIFO8 Register */ + __R uint32_t rsv_0x44; + __I uint32_t targ_rxfifo16; /**< \b 0x048: I3C TARG_RXFIFO16 Register */ + __R uint32_t rsv_0x4c_0x53[2]; + __O uint32_t targ_txfifo8o; /**< \b 0x054: I3C TARG_TXFIFO8O Register */ + __R uint32_t rsv_0x58; + __I uint32_t targ_cap0; /**< \b 0x05C: I3C TARG_CAP0 Register */ + __I uint32_t targ_cap1; /**< \b 0x060: I3C TARG_CAP1 Register */ + __IO uint32_t targ_dynaddr; /**< \b 0x064: I3C TARG_DYNADDR Register */ + __IO uint32_t targ_maxlimits; /**< \b 0x068: I3C TARG_MAXLIMITS Register */ + __R uint32_t rsv_0x6c; + __IO uint32_t targ_idext; /**< \b 0x070: I3C TARG_IDEXT Register */ + __R uint32_t rsv_0x74_0x7b[2]; + __I uint32_t targ_msglast; /**< \b 0x07C: I3C TARG_MSGLAST Register */ + __R uint32_t rsv_0x80; + __IO uint32_t cont_ctrl1; /**< \b 0x084: I3C CONT_CTRL1 Register */ + __IO uint32_t cont_status; /**< \b 0x088: I3C CONT_STATUS Register */ + __IO uint32_t cont_ibirules; /**< \b 0x08C: I3C CONT_IBIRULES Register */ + __IO uint32_t cont_inten; /**< \b 0x090: I3C CONT_INTEN Register */ + __O uint32_t cont_intclr; /**< \b 0x094: I3C CONT_INTCLR Register */ + __I uint32_t cont_intfl; /**< \b 0x098: I3C CONT_INTFL Register */ + __IO uint32_t cont_errwarn; /**< \b 0x09C: I3C CONT_ERRWARN Register */ + __IO uint32_t cont_dmactrl; /**< \b 0x0A0: I3C CONT_DMACTRL Register */ + __R uint32_t rsv_0xa4_0xab[2]; + __IO uint32_t cont_fifoctrl; /**< \b 0x0AC: I3C CONT_FIFOCTRL Register */ + __O uint32_t cont_txfifo8; /**< \b 0x0B0: I3C CONT_TXFIFO8 Register */ + __O uint32_t cont_txfifo8e; /**< \b 0x0B4: I3C CONT_TXFIFO8E Register */ + __O uint32_t cont_txfifo16; /**< \b 0x0B8: I3C CONT_TXFIFO16 Register */ + __O uint32_t cont_txfifo16e; /**< \b 0x0BC: I3C CONT_TXFIFO16E Register */ + __I uint32_t cont_rxfifo8; /**< \b 0x0C0: I3C CONT_RXFIFO8 Register */ + __R uint32_t rsv_0xc4; + __I uint32_t cont_rxfifo16; /**< \b 0x0C8: I3C CONT_RXFIFO16 Register */ + __O uint32_t cont_txfifo8o; /**< \b 0x0CC: I3C CONT_TXFIFO8O Register */ + union { + __IO uint32_t cont_txsdrmsg_ctrl; /**< \b 0x0D0: I3C CONT_TXSDRMSG_CTRL Register */ + __O uint32_t cont_txsdrmsg_fifo; /**< \b 0x0D0: I3C CONT_TXSDRMSG_FIFO Register */ + }; + __I uint32_t cont_rxsdrmsg; /**< \b 0x0D4: I3C CONT_RXSDRMSG Register */ + __O uint32_t cont_txddrmsg; /**< \b 0x0D8: I3C CONT_TXDDRMSG Register */ + __I uint32_t cont_rxddr16; /**< \b 0x0DC: I3C CONT_RXDDR16 Register */ + __R uint32_t rsv_0xe0; + __IO uint32_t cont_dynaddr; /**< \b 0x0E4: I3C CONT_DYNADDR Register */ + __R uint32_t rsv_0xe8_0x113[11]; + __I uint32_t targ_groupdef; /**< \b 0x114: I3C TARG_GROUPDEF Register */ + __R uint32_t rsv_0x118; + __IO uint32_t targ_mapctrl0; /**< \b 0x11C: I3C TARG_MAPCTRL0 Register */ + __IO uint32_t targ_mapctrl1; /**< \b 0x120: I3C TARG_MAPCTRL1 Register */ + __IO uint32_t targ_mapctrl2; /**< \b 0x124: I3C TARG_MAPCTRL2 Register */ +} mxc_i3c_regs_t; + +/* Register offsets for module I3C */ +/** + * @ingroup i3c_registers + * @defgroup I3C_Register_Offsets Register Offsets + * @brief I3C Peripheral Register Offsets from the I3C Base Peripheral Address. + * @{ + */ +#define MXC_R_I3C_CONT_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I3C Base Address: 0x0000 */ +#define MXC_R_I3C_TARG_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from I3C Base Address: 0x0004 */ +#define MXC_R_I3C_TARG_STATUS ((uint32_t)0x00000008UL) /**< Offset from I3C Base Address: 0x0008 */ +#define MXC_R_I3C_TARG_CTRL1 ((uint32_t)0x0000000CUL) /**< Offset from I3C Base Address: 0x000C */ +#define MXC_R_I3C_TARG_INTEN ((uint32_t)0x00000010UL) /**< Offset from I3C Base Address: 0x0010 */ +#define MXC_R_I3C_TARG_INTCLR ((uint32_t)0x00000014UL) /**< Offset from I3C Base Address: 0x0014 */ +#define MXC_R_I3C_TARG_INTFL ((uint32_t)0x00000018UL) /**< Offset from I3C Base Address: 0x0018 */ +#define MXC_R_I3C_TARG_ERRWARN ((uint32_t)0x0000001CUL) /**< Offset from I3C Base Address: 0x001C */ +#define MXC_R_I3C_TARG_DMACTRL ((uint32_t)0x00000020UL) /**< Offset from I3C Base Address: 0x0020 */ +#define MXC_R_I3C_TARG_FIFOCTRL ((uint32_t)0x0000002CUL) /**< Offset from I3C Base Address: 0x002C */ +#define MXC_R_I3C_TARG_TXFIFO8 ((uint32_t)0x00000030UL) /**< Offset from I3C Base Address: 0x0030 */ +#define MXC_R_I3C_TARG_TXFIFO8E ((uint32_t)0x00000034UL) /**< Offset from I3C Base Address: 0x0034 */ +#define MXC_R_I3C_TARG_TXFIFO16 ((uint32_t)0x00000038UL) /**< Offset from I3C Base Address: 0x0038 */ +#define MXC_R_I3C_TARG_TXFIFO16E ((uint32_t)0x0000003CUL) /**< Offset from I3C Base Address: 0x003C */ +#define MXC_R_I3C_TARG_RXFIFO8 ((uint32_t)0x00000040UL) /**< Offset from I3C Base Address: 0x0040 */ +#define MXC_R_I3C_TARG_RXFIFO16 ((uint32_t)0x00000048UL) /**< Offset from I3C Base Address: 0x0048 */ +#define MXC_R_I3C_TARG_TXFIFO8O ((uint32_t)0x00000054UL) /**< Offset from I3C Base Address: 0x0054 */ +#define MXC_R_I3C_TARG_CAP0 ((uint32_t)0x0000005CUL) /**< Offset from I3C Base Address: 0x005C */ +#define MXC_R_I3C_TARG_CAP1 ((uint32_t)0x00000060UL) /**< Offset from I3C Base Address: 0x0060 */ +#define MXC_R_I3C_TARG_DYNADDR ((uint32_t)0x00000064UL) /**< Offset from I3C Base Address: 0x0064 */ +#define MXC_R_I3C_TARG_MAXLIMITS ((uint32_t)0x00000068UL) /**< Offset from I3C Base Address: 0x0068 */ +#define MXC_R_I3C_TARG_IDEXT ((uint32_t)0x00000070UL) /**< Offset from I3C Base Address: 0x0070 */ +#define MXC_R_I3C_TARG_MSGLAST ((uint32_t)0x0000007CUL) /**< Offset from I3C Base Address: 0x007C */ +#define MXC_R_I3C_CONT_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from I3C Base Address: 0x0084 */ +#define MXC_R_I3C_CONT_STATUS ((uint32_t)0x00000088UL) /**< Offset from I3C Base Address: 0x0088 */ +#define MXC_R_I3C_CONT_IBIRULES ((uint32_t)0x0000008CUL) /**< Offset from I3C Base Address: 0x008C */ +#define MXC_R_I3C_CONT_INTEN ((uint32_t)0x00000090UL) /**< Offset from I3C Base Address: 0x0090 */ +#define MXC_R_I3C_CONT_INTCLR ((uint32_t)0x00000094UL) /**< Offset from I3C Base Address: 0x0094 */ +#define MXC_R_I3C_CONT_INTFL ((uint32_t)0x00000098UL) /**< Offset from I3C Base Address: 0x0098 */ +#define MXC_R_I3C_CONT_ERRWARN ((uint32_t)0x0000009CUL) /**< Offset from I3C Base Address: 0x009C */ +#define MXC_R_I3C_CONT_DMACTRL ((uint32_t)0x000000A0UL) /**< Offset from I3C Base Address: 0x00A0 */ +#define MXC_R_I3C_CONT_FIFOCTRL ((uint32_t)0x000000ACUL) /**< Offset from I3C Base Address: 0x00AC */ +#define MXC_R_I3C_CONT_TXFIFO8 ((uint32_t)0x000000B0UL) /**< Offset from I3C Base Address: 0x00B0 */ +#define MXC_R_I3C_CONT_TXFIFO8E ((uint32_t)0x000000B4UL) /**< Offset from I3C Base Address: 0x00B4 */ +#define MXC_R_I3C_CONT_TXFIFO16 ((uint32_t)0x000000B8UL) /**< Offset from I3C Base Address: 0x00B8 */ +#define MXC_R_I3C_CONT_TXFIFO16E ((uint32_t)0x000000BCUL) /**< Offset from I3C Base Address: 0x00BC */ +#define MXC_R_I3C_CONT_RXFIFO8 ((uint32_t)0x000000C0UL) /**< Offset from I3C Base Address: 0x00C0 */ +#define MXC_R_I3C_CONT_RXFIFO16 ((uint32_t)0x000000C8UL) /**< Offset from I3C Base Address: 0x00C8 */ +#define MXC_R_I3C_CONT_TXFIFO8O ((uint32_t)0x000000CCUL) /**< Offset from I3C Base Address: 0x00CC */ +#define MXC_R_I3C_CONT_TXSDRMSG_CTRL ((uint32_t)0x000000D0UL) /**< Offset from I3C Base Address: 0x00D0 */ +#define MXC_R_I3C_CONT_TXSDRMSG_FIFO ((uint32_t)0x000000D0UL) /**< Offset from I3C Base Address: 0x00D0 */ +#define MXC_R_I3C_CONT_RXSDRMSG ((uint32_t)0x000000D4UL) /**< Offset from I3C Base Address: 0x00D4 */ +#define MXC_R_I3C_CONT_TXDDRMSG ((uint32_t)0x000000D8UL) /**< Offset from I3C Base Address: 0x00D8 */ +#define MXC_R_I3C_CONT_RXDDR16 ((uint32_t)0x000000DCUL) /**< Offset from I3C Base Address: 0x00DC */ +#define MXC_R_I3C_CONT_DYNADDR ((uint32_t)0x000000E4UL) /**< Offset from I3C Base Address: 0x00E4 */ +#define MXC_R_I3C_TARG_GROUPDEF ((uint32_t)0x00000114UL) /**< Offset from I3C Base Address: 0x0114 */ +#define MXC_R_I3C_TARG_MAPCTRL0 ((uint32_t)0x0000011CUL) /**< Offset from I3C Base Address: 0x011C */ +#define MXC_R_I3C_TARG_MAPCTRL1 ((uint32_t)0x00000120UL) /**< Offset from I3C Base Address: 0x0120 */ +#define MXC_R_I3C_TARG_MAPCTRL2 ((uint32_t)0x00000124UL) /**< Offset from I3C Base Address: 0x0124 */ +/**@} end of group i3c_registers */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_CTRL0 I3C_CONT_CTRL0 + * @brief Controller Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_CONT_CTRL0_EN_POS 0 /**< CONT_CTRL0_EN Position */ +#define MXC_F_I3C_CONT_CTRL0_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL0_EN_POS)) /**< CONT_CTRL0_EN Mask */ +#define MXC_V_I3C_CONT_CTRL0_EN_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_EN_OFF Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_OFF (MXC_V_I3C_CONT_CTRL0_EN_OFF << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_OFF Setting */ +#define MXC_V_I3C_CONT_CTRL0_EN_ON ((uint32_t)0x1UL) /**< CONT_CTRL0_EN_ON Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_ON (MXC_V_I3C_CONT_CTRL0_EN_ON << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_ON Setting */ +#define MXC_V_I3C_CONT_CTRL0_EN_CAP ((uint32_t)0x2UL) /**< CONT_CTRL0_EN_CAP Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_CAP (MXC_V_I3C_CONT_CTRL0_EN_CAP << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_CAP Setting */ + +#define MXC_F_I3C_CONT_CTRL0_TO_DIS_POS 3 /**< CONT_CTRL0_TO_DIS Position */ +#define MXC_F_I3C_CONT_CTRL0_TO_DIS ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_TO_DIS_POS)) /**< CONT_CTRL0_TO_DIS Mask */ + +#define MXC_F_I3C_CONT_CTRL0_HKEEP_POS 4 /**< CONT_CTRL0_HKEEP Position */ +#define MXC_F_I3C_CONT_CTRL0_HKEEP ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL0_HKEEP_POS)) /**< CONT_CTRL0_HKEEP Mask */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_HKEEP_OFF Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_OFF (MXC_V_I3C_CONT_CTRL0_HKEEP_OFF << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_OFF Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_ON_CHIP ((uint32_t)0x1UL) /**< CONT_CTRL0_HKEEP_ON_CHIP Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_ON_CHIP (MXC_V_I3C_CONT_CTRL0_HKEEP_ON_CHIP << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_ON_CHIP Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SDA ((uint32_t)0x2UL) /**< CONT_CTRL0_HKEEP_EXT_SDA Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SDA (MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SDA << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SDA Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA ((uint32_t)0x3UL) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA (MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Setting */ + +#define MXC_F_I3C_CONT_CTRL0_OD_STOP_POS 6 /**< CONT_CTRL0_OD_STOP Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_STOP ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_OD_STOP_POS)) /**< CONT_CTRL0_OD_STOP Mask */ + +#define MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS 8 /**< CONT_CTRL0_PP_BAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS)) /**< CONT_CTRL0_PP_BAUD Mask */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_1_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_BAUD_1_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_1_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_1_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_1_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_2_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_BAUD_2_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_2_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_2_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_2_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_3_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_BAUD_3_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_3_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_3_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_3_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_4_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_BAUD_4_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_4_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_4_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_4_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_5_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_BAUD_5_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_5_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_5_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_5_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_6_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_BAUD_6_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_6_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_6_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_6_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_7_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_BAUD_7_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_7_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_7_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_7_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_8_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_BAUD_8_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_8_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_8_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_8_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_9_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_BAUD_9_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_9_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_9_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_9_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_10_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_BAUD_10_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_10_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_10_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_10_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_11_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_BAUD_11_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_11_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_11_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_11_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_12_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_BAUD_12_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_12_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_12_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_12_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_13_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_BAUD_13_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_13_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_13_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_13_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_14_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_BAUD_14_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_14_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_14_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_14_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_15_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_BAUD_15_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_15_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_15_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_15_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_16_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_BAUD_16_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_16_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_16_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_16_FCLK Setting */ + +#define MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS 12 /**< CONT_CTRL0_PP_ADD_LBAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS)) /**< CONT_CTRL0_PP_ADD_LBAUD Mask */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Setting */ + +#define MXC_F_I3C_CONT_CTRL0_OD_LBAUD_POS 16 /**< CONT_CTRL0_OD_LBAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_LBAUD ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_CTRL0_OD_LBAUD_POS)) /**< CONT_CTRL0_OD_LBAUD Mask */ + +#define MXC_F_I3C_CONT_CTRL0_OD_HP_POS 24 /**< CONT_CTRL0_OD_HP Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_HP ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_OD_HP_POS)) /**< CONT_CTRL0_OD_HP Mask */ + +#define MXC_F_I3C_CONT_CTRL0_PP_SKEW_POS 25 /**< CONT_CTRL0_PP_SKEW Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_SKEW ((uint32_t)(0x7UL << MXC_F_I3C_CONT_CTRL0_PP_SKEW_POS)) /**< CONT_CTRL0_PP_SKEW Mask */ + +#define MXC_F_I3C_CONT_CTRL0_I2C_BAUD_POS 28 /**< CONT_CTRL0_I2C_BAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_I2C_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_I2C_BAUD_POS)) /**< CONT_CTRL0_I2C_BAUD Mask */ + +/**@} end of group I3C_CONT_CTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CTRL0 I3C_TARG_CTRL0 + * @brief Target Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_TARG_CTRL0_EN_POS 0 /**< TARG_CTRL0_EN Position */ +#define MXC_F_I3C_TARG_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_EN_POS)) /**< TARG_CTRL0_EN Mask */ + +#define MXC_F_I3C_TARG_CTRL0_MATCHSS_POS 2 /**< TARG_CTRL0_MATCHSS Position */ +#define MXC_F_I3C_TARG_CTRL0_MATCHSS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_MATCHSS_POS)) /**< TARG_CTRL0_MATCHSS Mask */ + +#define MXC_F_I3C_TARG_CTRL0_TO_IGN_POS 3 /**< TARG_CTRL0_TO_IGN Position */ +#define MXC_F_I3C_TARG_CTRL0_TO_IGN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_TO_IGN_POS)) /**< TARG_CTRL0_TO_IGN Mask */ + +#define MXC_F_I3C_TARG_CTRL0_OFFLINE_POS 9 /**< TARG_CTRL0_OFFLINE Position */ +#define MXC_F_I3C_TARG_CTRL0_OFFLINE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_OFFLINE_POS)) /**< TARG_CTRL0_OFFLINE Mask */ + +/**@} end of group I3C_TARG_CTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_STATUS I3C_TARG_STATUS + * @brief Target Status Register. + * @{ + */ +#define MXC_F_I3C_TARG_STATUS_BUSY_POS 0 /**< TARG_STATUS_BUSY Position */ +#define MXC_F_I3C_TARG_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_BUSY_POS)) /**< TARG_STATUS_BUSY Mask */ + +#define MXC_F_I3C_TARG_STATUS_LIST_RESP_POS 1 /**< TARG_STATUS_LIST_RESP Position */ +#define MXC_F_I3C_TARG_STATUS_LIST_RESP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_LIST_RESP_POS)) /**< TARG_STATUS_LIST_RESP Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCCH_POS 2 /**< TARG_STATUS_CCCH Position */ +#define MXC_F_I3C_TARG_STATUS_CCCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCCH_POS)) /**< TARG_STATUS_CCCH Mask */ + +#define MXC_F_I3C_TARG_STATUS_RX_SDR_POS 3 /**< TARG_STATUS_RX_SDR Position */ +#define MXC_F_I3C_TARG_STATUS_RX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_RX_SDR_POS)) /**< TARG_STATUS_RX_SDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_TX_SDR_POS 4 /**< TARG_STATUS_TX_SDR Position */ +#define MXC_F_I3C_TARG_STATUS_TX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TX_SDR_POS)) /**< TARG_STATUS_TX_SDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_DAA_POS 5 /**< TARG_STATUS_DAA Position */ +#define MXC_F_I3C_TARG_STATUS_DAA ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_DAA_POS)) /**< TARG_STATUS_DAA Mask */ + +#define MXC_F_I3C_TARG_STATUS_HDR_POS 6 /**< TARG_STATUS_HDR Position */ +#define MXC_F_I3C_TARG_STATUS_HDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_HDR_POS)) /**< TARG_STATUS_HDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_START_POS 8 /**< TARG_STATUS_START Position */ +#define MXC_F_I3C_TARG_STATUS_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_START_POS)) /**< TARG_STATUS_START Mask */ + +#define MXC_F_I3C_TARG_STATUS_ADDRMATCH_POS 9 /**< TARG_STATUS_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_STATUS_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_ADDRMATCH_POS)) /**< TARG_STATUS_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_STATUS_STOP_POS 10 /**< TARG_STATUS_STOP Position */ +#define MXC_F_I3C_TARG_STATUS_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_STOP_POS)) /**< TARG_STATUS_STOP Mask */ + +#define MXC_F_I3C_TARG_STATUS_RX_RDY_POS 11 /**< TARG_STATUS_RX_RDY Position */ +#define MXC_F_I3C_TARG_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_RX_RDY_POS)) /**< TARG_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_STATUS_TX_NFULL_POS 12 /**< TARG_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_TARG_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TX_NFULL_POS)) /**< TARG_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_STATUS_DYNADDR_CHG_POS 13 /**< TARG_STATUS_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_STATUS_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_DYNADDR_CHG_POS)) /**< TARG_STATUS_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCC_POS 14 /**< TARG_STATUS_CCC Position */ +#define MXC_F_I3C_TARG_STATUS_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCC_POS)) /**< TARG_STATUS_CCC Mask */ + +#define MXC_F_I3C_TARG_STATUS_ERRWARN_POS 15 /**< TARG_STATUS_ERRWARN Position */ +#define MXC_F_I3C_TARG_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_ERRWARN_POS)) /**< TARG_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCCH_DONE_POS 17 /**< TARG_STATUS_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_STATUS_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCCH_DONE_POS)) /**< TARG_STATUS_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_STATUS_EVENT_REQ_POS 18 /**< TARG_STATUS_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_STATUS_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_EVENT_REQ_POS)) /**< TARG_STATUS_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_STATUS_TARG_RST_POS 19 /**< TARG_STATUS_TARG_RST Position */ +#define MXC_F_I3C_TARG_STATUS_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TARG_RST_POS)) /**< TARG_STATUS_TARG_RST Mask */ + +#define MXC_F_I3C_TARG_STATUS_EVENT_POS 20 /**< TARG_STATUS_EVENT Position */ +#define MXC_F_I3C_TARG_STATUS_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_EVENT_POS)) /**< TARG_STATUS_EVENT Mask */ +#define MXC_V_I3C_TARG_STATUS_EVENT_NONE ((uint32_t)0x0UL) /**< TARG_STATUS_EVENT_NONE Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_NONE (MXC_V_I3C_TARG_STATUS_EVENT_NONE << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_NONE Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_PEND ((uint32_t)0x1UL) /**< TARG_STATUS_EVENT_REQ_PEND Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_PEND (MXC_V_I3C_TARG_STATUS_EVENT_REQ_PEND << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_PEND Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_NACK ((uint32_t)0x2UL) /**< TARG_STATUS_EVENT_REQ_NACK Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_NACK (MXC_V_I3C_TARG_STATUS_EVENT_REQ_NACK << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_NACK Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_ACK ((uint32_t)0x3UL) /**< TARG_STATUS_EVENT_REQ_ACK Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_ACK (MXC_V_I3C_TARG_STATUS_EVENT_REQ_ACK << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_ACK Setting */ + +#define MXC_F_I3C_TARG_STATUS_IBI_DIS_POS 24 /**< TARG_STATUS_IBI_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_IBI_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_IBI_DIS_POS)) /**< TARG_STATUS_IBI_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_CONTREQ_DIS_POS 25 /**< TARG_STATUS_CONTREQ_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_CONTREQ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CONTREQ_DIS_POS)) /**< TARG_STATUS_CONTREQ_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_HJ_DIS_POS 27 /**< TARG_STATUS_HJ_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_HJ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_HJ_DIS_POS)) /**< TARG_STATUS_HJ_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_ACTSTATE_POS 28 /**< TARG_STATUS_ACTSTATE Position */ +#define MXC_F_I3C_TARG_STATUS_ACTSTATE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS)) /**< TARG_STATUS_ACTSTATE Mask */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_NORMAL ((uint32_t)0x0UL) /**< TARG_STATUS_ACTSTATE_NORMAL Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_NORMAL (MXC_V_I3C_TARG_STATUS_ACTSTATE_NORMAL << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_NORMAL Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_1MS_LAT ((uint32_t)0x1UL) /**< TARG_STATUS_ACTSTATE_1MS_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_1MS_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_1MS_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_1MS_LAT Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_100MS_LAT ((uint32_t)0x2UL) /**< TARG_STATUS_ACTSTATE_100MS_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_100MS_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_100MS_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_100MS_LAT Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_10S_LAT ((uint32_t)0x3UL) /**< TARG_STATUS_ACTSTATE_10S_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_10S_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_10S_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_10S_LAT Setting */ + +#define MXC_F_I3C_TARG_STATUS_TIMECTRL_POS 30 /**< TARG_STATUS_TIMECTRL Position */ +#define MXC_F_I3C_TARG_STATUS_TIMECTRL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS)) /**< TARG_STATUS_TIMECTRL Mask */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_DIS ((uint32_t)0x0UL) /**< TARG_STATUS_TIMECTRL_DIS Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_DIS (MXC_V_I3C_TARG_STATUS_TIMECTRL_DIS << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_DIS Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_SYNC ((uint32_t)0x1UL) /**< TARG_STATUS_TIMECTRL_SYNC Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_SYNC (MXC_V_I3C_TARG_STATUS_TIMECTRL_SYNC << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_SYNC Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_ASYNC ((uint32_t)0x2UL) /**< TARG_STATUS_TIMECTRL_ASYNC Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_ASYNC (MXC_V_I3C_TARG_STATUS_TIMECTRL_ASYNC << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_ASYNC Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_BOTH ((uint32_t)0x3UL) /**< TARG_STATUS_TIMECTRL_BOTH Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_BOTH (MXC_V_I3C_TARG_STATUS_TIMECTRL_BOTH << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_BOTH Setting */ + +/**@} end of group I3C_TARG_STATUS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CTRL1 I3C_TARG_CTRL1 + * @brief Target Control 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CTRL1_EVENT_POS 0 /**< TARG_CTRL1_EVENT Position */ +#define MXC_F_I3C_TARG_CTRL1_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CTRL1_EVENT_POS)) /**< TARG_CTRL1_EVENT Mask */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_NORMAL ((uint32_t)0x0UL) /**< TARG_CTRL1_EVENT_NORMAL Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_NORMAL (MXC_V_I3C_TARG_CTRL1_EVENT_NORMAL << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_NORMAL Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_IBI ((uint32_t)0x1UL) /**< TARG_CTRL1_EVENT_IBI Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_IBI (MXC_V_I3C_TARG_CTRL1_EVENT_IBI << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_IBI Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_CONTREQ ((uint32_t)0x2UL) /**< TARG_CTRL1_EVENT_CONTREQ Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_CONTREQ (MXC_V_I3C_TARG_CTRL1_EVENT_CONTREQ << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_CONTREQ Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_HJ ((uint32_t)0x3UL) /**< TARG_CTRL1_EVENT_HJ Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_HJ (MXC_V_I3C_TARG_CTRL1_EVENT_HJ << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_HJ Setting */ + +#define MXC_F_I3C_TARG_CTRL1_EXTIBI_POS 3 /**< TARG_CTRL1_EXTIBI Position */ +#define MXC_F_I3C_TARG_CTRL1_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL1_EXTIBI_POS)) /**< TARG_CTRL1_EXTIBI Mask */ + +#define MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX_POS 4 /**< TARG_CTRL1_DYNADDR_IDX Position */ +#define MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX_POS)) /**< TARG_CTRL1_DYNADDR_IDX Mask */ + +#define MXC_F_I3C_TARG_CTRL1_IBIDATA_POS 8 /**< TARG_CTRL1_IBIDATA Position */ +#define MXC_F_I3C_TARG_CTRL1_IBIDATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_CTRL1_IBIDATA_POS)) /**< TARG_CTRL1_IBIDATA Mask */ + +/**@} end of group I3C_TARG_CTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTEN I3C_TARG_INTEN + * @brief Target Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTEN_START_POS 8 /**< TARG_INTEN_START Position */ +#define MXC_F_I3C_TARG_INTEN_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_START_POS)) /**< TARG_INTEN_START Mask */ + +#define MXC_F_I3C_TARG_INTEN_ADDRMATCH_POS 9 /**< TARG_INTEN_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTEN_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_ADDRMATCH_POS)) /**< TARG_INTEN_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTEN_STOP_POS 10 /**< TARG_INTEN_STOP Position */ +#define MXC_F_I3C_TARG_INTEN_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_STOP_POS)) /**< TARG_INTEN_STOP Mask */ + +#define MXC_F_I3C_TARG_INTEN_RX_RDY_POS 11 /**< TARG_INTEN_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_RX_RDY_POS)) /**< TARG_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTEN_TX_NFULL_POS 12 /**< TARG_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_TX_NFULL_POS)) /**< TARG_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTEN_DYNADDR_CHG_POS 13 /**< TARG_INTEN_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTEN_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_DYNADDR_CHG_POS)) /**< TARG_INTEN_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTEN_CCC_POS 14 /**< TARG_INTEN_CCC Position */ +#define MXC_F_I3C_TARG_INTEN_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_CCC_POS)) /**< TARG_INTEN_CCC Mask */ + +#define MXC_F_I3C_TARG_INTEN_ERRWARN_POS 15 /**< TARG_INTEN_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_ERRWARN_POS)) /**< TARG_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTEN_CCCH_DONE_POS 17 /**< TARG_INTEN_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTEN_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_CCCH_DONE_POS)) /**< TARG_INTEN_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTEN_EVENT_REQ_POS 18 /**< TARG_INTEN_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTEN_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_EVENT_REQ_POS)) /**< TARG_INTEN_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTEN_TARG_RST_POS 19 /**< TARG_INTEN_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTEN_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_TARG_RST_POS)) /**< TARG_INTEN_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTEN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTCLR I3C_TARG_INTCLR + * @brief Target Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTCLR_START_POS 8 /**< TARG_INTCLR_START Position */ +#define MXC_F_I3C_TARG_INTCLR_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_START_POS)) /**< TARG_INTCLR_START Mask */ + +#define MXC_F_I3C_TARG_INTCLR_ADDRMATCH_POS 9 /**< TARG_INTCLR_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTCLR_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_ADDRMATCH_POS)) /**< TARG_INTCLR_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTCLR_STOP_POS 10 /**< TARG_INTCLR_STOP Position */ +#define MXC_F_I3C_TARG_INTCLR_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_STOP_POS)) /**< TARG_INTCLR_STOP Mask */ + +#define MXC_F_I3C_TARG_INTCLR_RX_RDY_POS 11 /**< TARG_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_RX_RDY_POS)) /**< TARG_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTCLR_TX_NFULL_POS 12 /**< TARG_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_TX_NFULL_POS)) /**< TARG_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG_POS 13 /**< TARG_INTCLR_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG_POS)) /**< TARG_INTCLR_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTCLR_CCC_POS 14 /**< TARG_INTCLR_CCC Position */ +#define MXC_F_I3C_TARG_INTCLR_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_CCC_POS)) /**< TARG_INTCLR_CCC Mask */ + +#define MXC_F_I3C_TARG_INTCLR_ERRWARN_POS 15 /**< TARG_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_ERRWARN_POS)) /**< TARG_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTCLR_CCCH_DONE_POS 17 /**< TARG_INTCLR_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTCLR_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_CCCH_DONE_POS)) /**< TARG_INTCLR_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTCLR_EVENT_REQ_POS 18 /**< TARG_INTCLR_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTCLR_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_EVENT_REQ_POS)) /**< TARG_INTCLR_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTCLR_TARG_RST_POS 19 /**< TARG_INTCLR_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTCLR_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_TARG_RST_POS)) /**< TARG_INTCLR_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTCLR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTFL I3C_TARG_INTFL + * @brief Target Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTFL_START_POS 8 /**< TARG_INTFL_START Position */ +#define MXC_F_I3C_TARG_INTFL_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_START_POS)) /**< TARG_INTFL_START Mask */ + +#define MXC_F_I3C_TARG_INTFL_ADDRMATCH_POS 9 /**< TARG_INTFL_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTFL_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_ADDRMATCH_POS)) /**< TARG_INTFL_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTFL_STOP_POS 10 /**< TARG_INTFL_STOP Position */ +#define MXC_F_I3C_TARG_INTFL_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_STOP_POS)) /**< TARG_INTFL_STOP Mask */ + +#define MXC_F_I3C_TARG_INTFL_RX_RDY_POS 11 /**< TARG_INTFL_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_RX_RDY_POS)) /**< TARG_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTFL_TX_NFULL_POS 12 /**< TARG_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_TX_NFULL_POS)) /**< TARG_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTFL_DYNADDR_CHG_POS 13 /**< TARG_INTFL_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTFL_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_DYNADDR_CHG_POS)) /**< TARG_INTFL_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTFL_CCC_POS 14 /**< TARG_INTFL_CCC Position */ +#define MXC_F_I3C_TARG_INTFL_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_CCC_POS)) /**< TARG_INTFL_CCC Mask */ + +#define MXC_F_I3C_TARG_INTFL_ERRWARN_POS 15 /**< TARG_INTFL_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_ERRWARN_POS)) /**< TARG_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTFL_CCCH_DONE_POS 17 /**< TARG_INTFL_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTFL_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_CCCH_DONE_POS)) /**< TARG_INTFL_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTFL_EVENT_REQ_POS 18 /**< TARG_INTFL_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTFL_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_EVENT_REQ_POS)) /**< TARG_INTFL_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTFL_TARG_RST_POS 19 /**< TARG_INTFL_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTFL_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_TARG_RST_POS)) /**< TARG_INTFL_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTFL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_ERRWARN I3C_TARG_ERRWARN + * @brief Target Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_TARG_ERRWARN_OVR_POS 0 /**< TARG_ERRWARN_OVR Position */ +#define MXC_F_I3C_TARG_ERRWARN_OVR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_OVR_POS)) /**< TARG_ERRWARN_OVR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_UNR_POS 1 /**< TARG_ERRWARN_UNR Position */ +#define MXC_F_I3C_TARG_ERRWARN_UNR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_UNR_POS)) /**< TARG_ERRWARN_UNR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_UNR_NACK_POS 2 /**< TARG_ERRWARN_UNR_NACK Position */ +#define MXC_F_I3C_TARG_ERRWARN_UNR_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_UNR_NACK_POS)) /**< TARG_ERRWARN_UNR_NACK Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM_POS 3 /**< TARG_ERRWARN_CONT_RX_TERM Position */ +#define MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM_POS)) /**< TARG_ERRWARN_CONT_RX_TERM Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_INVSTART_POS 4 /**< TARG_ERRWARN_INVSTART Position */ +#define MXC_F_I3C_TARG_ERRWARN_INVSTART ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_INVSTART_POS)) /**< TARG_ERRWARN_INVSTART Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_SDR_PAR_POS 8 /**< TARG_ERRWARN_SDR_PAR Position */ +#define MXC_F_I3C_TARG_ERRWARN_SDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_SDR_PAR_POS)) /**< TARG_ERRWARN_SDR_PAR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_TO_POS 11 /**< TARG_ERRWARN_TO Position */ +#define MXC_F_I3C_TARG_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_TO_POS)) /**< TARG_ERRWARN_TO Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_RX_UNR_POS 16 /**< TARG_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_TARG_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_RX_UNR_POS)) /**< TARG_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_TX_OVR_POS 17 /**< TARG_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_TARG_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_TX_OVR_POS)) /**< TARG_ERRWARN_TX_OVR Mask */ + +/**@} end of group I3C_TARG_ERRWARN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_DMACTRL I3C_TARG_DMACTRL + * @brief Target DMA Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_DMACTRL_RX_EN_POS 0 /**< TARG_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_TARG_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS)) /**< TARG_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_DIS (MXC_V_I3C_TARG_DMACTRL_RX_EN_DIS << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_TARG_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_EN (MXC_V_I3C_TARG_DMACTRL_RX_EN_EN << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_TARG_DMACTRL_TX_EN_POS 2 /**< TARG_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_TARG_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS)) /**< TARG_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_DIS (MXC_V_I3C_TARG_DMACTRL_TX_EN_DIS << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_TARG_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_EN (MXC_V_I3C_TARG_DMACTRL_TX_EN_EN << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_TARG_DMACTRL_WIDTH_POS 4 /**< TARG_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_TARG_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS)) /**< TARG_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_TARG_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< TARG_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_TARG_DMACTRL_WIDTH_BYTE (MXC_V_I3C_TARG_DMACTRL_WIDTH_BYTE << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_TARG_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< TARG_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_TARG_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_TARG_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_TARG_DMACTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_FIFOCTRL I3C_TARG_FIFOCTRL + * @brief Target FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH_POS 0 /**< TARG_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH_POS)) /**< TARG_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH_POS 1 /**< TARG_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH_POS)) /**< TARG_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_UNLOCK_POS 3 /**< TARG_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_UNLOCK_POS)) /**< TARG_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS 4 /**< TARG_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS)) /**< TARG_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS 6 /**< TARG_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS)) /**< TARG_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_LVL_POS 16 /**< TARG_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_TARG_FIFOCTRL_TX_LVL_POS)) /**< TARG_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_LVL_POS 24 /**< TARG_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_TARG_FIFOCTRL_RX_LVL_POS)) /**< TARG_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FULL_POS 30 /**< TARG_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_TX_FULL_POS)) /**< TARG_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_EM_POS 31 /**< TARG_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_RX_EM_POS)) /**< TARG_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_TARG_FIFOCTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8 I3C_TARG_TXFIFO8 + * @brief Target Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8_DATA_POS 0 /**< TARG_TXFIFO8_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8_DATA_POS)) /**< TARG_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_TARG_TXFIFO8_END_POS 8 /**< TARG_TXFIFO8_END Position */ +#define MXC_F_I3C_TARG_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO8_END_POS)) /**< TARG_TXFIFO8_END Mask */ + +#define MXC_F_I3C_TARG_TXFIFO8_END2_POS 16 /**< TARG_TXFIFO8_END2 Position */ +#define MXC_F_I3C_TARG_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO8_END2_POS)) /**< TARG_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_TARG_TXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8E I3C_TARG_TXFIFO8E + * @brief Target Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8E_DATA_POS 0 /**< TARG_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8E_DATA_POS)) /**< TARG_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO8E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO16 I3C_TARG_TXFIFO16 + * @brief Target Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO16_DATA_POS 0 /**< TARG_TXFIFO16_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_TXFIFO16_DATA_POS)) /**< TARG_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_TARG_TXFIFO16_END_POS 16 /**< TARG_TXFIFO16_END Position */ +#define MXC_F_I3C_TARG_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO16_END_POS)) /**< TARG_TXFIFO16_END Mask */ + +/**@} end of group I3C_TARG_TXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO16E I3C_TARG_TXFIFO16E + * @brief Target Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO16E_DATA_POS 0 /**< TARG_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_TXFIFO16E_DATA_POS)) /**< TARG_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO16E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_RXFIFO8 I3C_TARG_RXFIFO8 + * @brief Target Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_RXFIFO8_DATA_POS 0 /**< TARG_RXFIFO8_DATA Position */ +#define MXC_F_I3C_TARG_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_RXFIFO8_DATA_POS)) /**< TARG_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_TARG_RXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_RXFIFO16 I3C_TARG_RXFIFO16 + * @brief Target Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_RXFIFO16_DATA_POS 0 /**< TARG_RXFIFO16_DATA Position */ +#define MXC_F_I3C_TARG_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_RXFIFO16_DATA_POS)) /**< TARG_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_TARG_RXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8O I3C_TARG_TXFIFO8O + * @brief Target Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8O_DATA_POS 0 /**< TARG_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8O_DATA_POS)) /**< TARG_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO8O_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CAP0 I3C_TARG_CAP0 + * @brief Target Capabilities 0 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CAP0_MAPCNT_POS 0 /**< TARG_CAP0_MAPCNT Position */ +#define MXC_F_I3C_TARG_CAP0_MAPCNT ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP0_MAPCNT_POS)) /**< TARG_CAP0_MAPCNT Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_10BADDR_POS 4 /**< TARG_CAP0_I2C_10BADDR Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_10BADDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_10BADDR_POS)) /**< TARG_CAP0_I2C_10BADDR Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_SWRST_POS 5 /**< TARG_CAP0_I2C_SWRST Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_SWRST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_SWRST_POS)) /**< TARG_CAP0_I2C_SWRST Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_DEVID_POS 6 /**< TARG_CAP0_I2C_DEVID Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_DEVID ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_DEVID_POS)) /**< TARG_CAP0_I2C_DEVID Mask */ + +#define MXC_F_I3C_TARG_CAP0_FIFO32_REG_POS 7 /**< TARG_CAP0_FIFO32_REG Position */ +#define MXC_F_I3C_TARG_CAP0_FIFO32_REG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_FIFO32_REG_POS)) /**< TARG_CAP0_FIFO32_REG Mask */ + +#define MXC_F_I3C_TARG_CAP0_EXTIBI_POS 8 /**< TARG_CAP0_EXTIBI Position */ +#define MXC_F_I3C_TARG_CAP0_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_EXTIBI_POS)) /**< TARG_CAP0_EXTIBI Mask */ + +#define MXC_F_I3C_TARG_CAP0_EXTIBI_REG_POS 9 /**< TARG_CAP0_EXTIBI_REG Position */ +#define MXC_F_I3C_TARG_CAP0_EXTIBI_REG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_EXTIBI_REG_POS)) /**< TARG_CAP0_EXTIBI_REG Mask */ + +#define MXC_F_I3C_TARG_CAP0_HDRBT_LANES_POS 12 /**< TARG_CAP0_HDRBT_LANES Position */ +#define MXC_F_I3C_TARG_CAP0_HDRBT_LANES ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP0_HDRBT_LANES_POS)) /**< TARG_CAP0_HDRBT_LANES Mask */ + +#define MXC_F_I3C_TARG_CAP0_CCC_V1_1_POS 16 /**< TARG_CAP0_CCC_V1_1 Position */ +#define MXC_F_I3C_TARG_CAP0_CCC_V1_1 ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_CCC_V1_1_POS)) /**< TARG_CAP0_CCC_V1_1 Mask */ + +#define MXC_F_I3C_TARG_CAP0_TARG_RST_POS 17 /**< TARG_CAP0_TARG_RST Position */ +#define MXC_F_I3C_TARG_CAP0_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_TARG_RST_POS)) /**< TARG_CAP0_TARG_RST Mask */ + +#define MXC_F_I3C_TARG_CAP0_GROUPADDR_POS 18 /**< TARG_CAP0_GROUPADDR Position */ +#define MXC_F_I3C_TARG_CAP0_GROUPADDR ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP0_GROUPADDR_POS)) /**< TARG_CAP0_GROUPADDR Mask */ + +#define MXC_F_I3C_TARG_CAP0_AASA_CCC_POS 21 /**< TARG_CAP0_AASA_CCC Position */ +#define MXC_F_I3C_TARG_CAP0_AASA_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_AASA_CCC_POS)) /**< TARG_CAP0_AASA_CCC Mask */ + +#define MXC_F_I3C_TARG_CAP0_T2T_SUBSC_POS 22 /**< TARG_CAP0_T2T_SUBSC Position */ +#define MXC_F_I3C_TARG_CAP0_T2T_SUBSC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_T2T_SUBSC_POS)) /**< TARG_CAP0_T2T_SUBSC Mask */ + +#define MXC_F_I3C_TARG_CAP0_T2T_WR_POS 23 /**< TARG_CAP0_T2T_WR Position */ +#define MXC_F_I3C_TARG_CAP0_T2T_WR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_T2T_WR_POS)) /**< TARG_CAP0_T2T_WR Mask */ + +/**@} end of group I3C_TARG_CAP0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CAP1 I3C_TARG_CAP1 + * @brief TARG_Capabilities 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CAP1_PROVID_POS 0 /**< TARG_CAP1_PROVID Position */ +#define MXC_F_I3C_TARG_CAP1_PROVID ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_PROVID_POS)) /**< TARG_CAP1_PROVID Mask */ + +#define MXC_F_I3C_TARG_CAP1_PROVID_REG_POS 2 /**< TARG_CAP1_PROVID_REG Position */ +#define MXC_F_I3C_TARG_CAP1_PROVID_REG ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP1_PROVID_REG_POS)) /**< TARG_CAP1_PROVID_REG Mask */ + +#define MXC_F_I3C_TARG_CAP1_HDR_MODES_POS 6 /**< TARG_CAP1_HDR_MODES Position */ +#define MXC_F_I3C_TARG_CAP1_HDR_MODES ((uint32_t)(0x7UL << MXC_F_I3C_TARG_CAP1_HDR_MODES_POS)) /**< TARG_CAP1_HDR_MODES Mask */ + +#define MXC_F_I3C_TARG_CAP1_CONT_POS 9 /**< TARG_CAP1_CONT Position */ +#define MXC_F_I3C_TARG_CAP1_CONT ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_CONT_POS)) /**< TARG_CAP1_CONT Mask */ + +#define MXC_F_I3C_TARG_CAP1_STATADDR_POS 10 /**< TARG_CAP1_STATADDR Position */ +#define MXC_F_I3C_TARG_CAP1_STATADDR ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_STATADDR_POS)) /**< TARG_CAP1_STATADDR Mask */ + +#define MXC_F_I3C_TARG_CAP1_CCCH_POS 12 /**< TARG_CAP1_CCCH Position */ +#define MXC_F_I3C_TARG_CAP1_CCCH ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP1_CCCH_POS)) /**< TARG_CAP1_CCCH Mask */ +#define MXC_V_I3C_TARG_CAP1_CCCH_BASIC ((uint32_t)0x1UL) /**< TARG_CAP1_CCCH_BASIC Value */ +#define MXC_S_I3C_TARG_CAP1_CCCH_BASIC (MXC_V_I3C_TARG_CAP1_CCCH_BASIC << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_BASIC Setting */ +#define MXC_V_I3C_TARG_CAP1_CCCH_LIMITS ((uint32_t)0x2UL) /**< TARG_CAP1_CCCH_LIMITS Value */ +#define MXC_S_I3C_TARG_CAP1_CCCH_LIMITS (MXC_V_I3C_TARG_CAP1_CCCH_LIMITS << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_LIMITS Setting */ +#define MXC_V_I3C_TARG_CAP1_CCCH_INTACT ((uint32_t)0x4UL) /**< TARG_CAP1_CCCH_INTACT Value */ +#define MXC_S_I3C_TARG_CAP1_CCCH_INTACT (MXC_V_I3C_TARG_CAP1_CCCH_INTACT << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_INTACT Setting */ +#define MXC_V_I3C_TARG_CAP1_CCCH_VENDOR ((uint32_t)0x8UL) /**< TARG_CAP1_CCCH_VENDOR Value */ +#define MXC_S_I3C_TARG_CAP1_CCCH_VENDOR (MXC_V_I3C_TARG_CAP1_CCCH_VENDOR << MXC_F_I3C_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_VENDOR Setting */ + +#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS 16 /**< TARG_CAP1_IBI_EVENTS Position */ +#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS ((uint32_t)(0x1FUL << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS)) /**< TARG_CAP1_IBI_EVENTS Mask */ +#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_IBI ((uint32_t)0x1UL) /**< TARG_CAP1_IBI_EVENTS_IBI Value */ +#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_IBI (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_IBI << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_IBI Setting */ +#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD ((uint32_t)0x2UL) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Value */ +#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_PAYLOAD << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Setting */ +#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ ((uint32_t)0x4UL) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Value */ +#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_CONTREQ << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Setting */ +#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_HJ ((uint32_t)0x8UL) /**< TARG_CAP1_IBI_EVENTS_HJ Value */ +#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_HJ (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_HJ << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_HJ Setting */ +#define MXC_V_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH ((uint32_t)0x10UL) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Value */ +#define MXC_S_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH (MXC_V_I3C_TARG_CAP1_IBI_EVENTS_BAMATCH << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Setting */ + +#define MXC_F_I3C_TARG_CAP1_TIMECTRL_POS 21 /**< TARG_CAP1_TIMECTRL Position */ +#define MXC_F_I3C_TARG_CAP1_TIMECTRL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_TIMECTRL_POS)) /**< TARG_CAP1_TIMECTRL Mask */ + +#define MXC_F_I3C_TARG_CAP1_EXTFIFO_POS 23 /**< TARG_CAP1_EXTFIFO Position */ +#define MXC_F_I3C_TARG_CAP1_EXTFIFO ((uint32_t)(0x7UL << MXC_F_I3C_TARG_CAP1_EXTFIFO_POS)) /**< TARG_CAP1_EXTFIFO Mask */ + +#define MXC_F_I3C_TARG_CAP1_TXFIFO_CFG_POS 26 /**< TARG_CAP1_TXFIFO_CFG Position */ +#define MXC_F_I3C_TARG_CAP1_TXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_TXFIFO_CFG_POS)) /**< TARG_CAP1_TXFIFO_CFG Mask */ + +#define MXC_F_I3C_TARG_CAP1_RXFIFO_CFG_POS 28 /**< TARG_CAP1_RXFIFO_CFG Position */ +#define MXC_F_I3C_TARG_CAP1_RXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_RXFIFO_CFG_POS)) /**< TARG_CAP1_RXFIFO_CFG Mask */ + +#define MXC_F_I3C_TARG_CAP1_INTR_POS 30 /**< TARG_CAP1_INTR Position */ +#define MXC_F_I3C_TARG_CAP1_INTR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_INTR_POS)) /**< TARG_CAP1_INTR Mask */ + +#define MXC_F_I3C_TARG_CAP1_DMA_POS 31 /**< TARG_CAP1_DMA Position */ +#define MXC_F_I3C_TARG_CAP1_DMA ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_DMA_POS)) /**< TARG_CAP1_DMA Mask */ + +/**@} end of group I3C_TARG_CAP1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_DYNADDR I3C_TARG_DYNADDR + * @brief Target Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_TARG_DYNADDR_VALID_POS 0 /**< TARG_DYNADDR_VALID Position */ +#define MXC_F_I3C_TARG_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_TARG_DYNADDR_VALID_POS)) /**< TARG_DYNADDR_VALID Mask */ + +#define MXC_F_I3C_TARG_DYNADDR_ADDR_POS 1 /**< TARG_DYNADDR_ADDR Position */ +#define MXC_F_I3C_TARG_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_DYNADDR_ADDR_POS)) /**< TARG_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_TARG_DYNADDR_CAUSE_POS 8 /**< TARG_DYNADDR_CAUSE Position */ +#define MXC_F_I3C_TARG_DYNADDR_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_TARG_DYNADDR_CAUSE_POS)) /**< TARG_DYNADDR_CAUSE Mask */ + +/**@} end of group I3C_TARG_DYNADDR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAXLIMITS I3C_TARG_MAXLIMITS + * @brief Maximum Limits Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAXLIMITS_RX_POS 0 /**< TARG_MAXLIMITS_RX Position */ +#define MXC_F_I3C_TARG_MAXLIMITS_RX ((uint32_t)(0xFFFUL << MXC_F_I3C_TARG_MAXLIMITS_RX_POS)) /**< TARG_MAXLIMITS_RX Mask */ + +#define MXC_F_I3C_TARG_MAXLIMITS_TX_POS 16 /**< TARG_MAXLIMITS_TX Position */ +#define MXC_F_I3C_TARG_MAXLIMITS_TX ((uint32_t)(0xFFFUL << MXC_F_I3C_TARG_MAXLIMITS_TX_POS)) /**< TARG_MAXLIMITS_TX Mask */ + +/**@} end of group I3C_TARG_MAXLIMITS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_IDEXT I3C_TARG_IDEXT + * @brief ID Extension Register. + * @{ + */ +#define MXC_F_I3C_TARG_IDEXT_DEVCHAR_POS 8 /**< TARG_IDEXT_DEVCHAR Position */ +#define MXC_F_I3C_TARG_IDEXT_DEVCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_IDEXT_DEVCHAR_POS)) /**< TARG_IDEXT_DEVCHAR Mask */ + +#define MXC_F_I3C_TARG_IDEXT_BUSCHAR_POS 16 /**< TARG_IDEXT_BUSCHAR Position */ +#define MXC_F_I3C_TARG_IDEXT_BUSCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_IDEXT_BUSCHAR_POS)) /**< TARG_IDEXT_BUSCHAR Mask */ + +/**@} end of group I3C_TARG_IDEXT_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MSGLAST I3C_TARG_MSGLAST + * @brief Target Matching Address Index Register. + * @{ + */ +#define MXC_F_I3C_TARG_MSGLAST_IDX_POS 0 /**< TARG_MSGLAST_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_IDX_POS)) /**< TARG_MSGLAST_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_STATADDR_POS 4 /**< TARG_MSGLAST_STATADDR Position */ +#define MXC_F_I3C_TARG_MSGLAST_STATADDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_STATADDR_POS)) /**< TARG_MSGLAST_STATADDR Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_GROUP_POS 5 /**< TARG_MSGLAST_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_GROUP_POS)) /**< TARG_MSGLAST_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_MODE_POS 6 /**< TARG_MSGLAST_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_MODE_POS)) /**< TARG_MSGLAST_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_IDX_POS 8 /**< TARG_MSGLAST_PREV_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_PREV_IDX_POS)) /**< TARG_MSGLAST_PREV_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_GROUP_POS 13 /**< TARG_MSGLAST_PREV_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_PREV_GROUP_POS)) /**< TARG_MSGLAST_PREV_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS 14 /**< TARG_MSGLAST_PREV_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS)) /**< TARG_MSGLAST_PREV_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX_POS 16 /**< TARG_MSGLAST_SECPREV_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX_POS)) /**< TARG_MSGLAST_SECPREV_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP_POS 21 /**< TARG_MSGLAST_SECPREV_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP_POS)) /**< TARG_MSGLAST_SECPREV_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS 22 /**< TARG_MSGLAST_SECPREV_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS)) /**< TARG_MSGLAST_SECPREV_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Setting */ + +/**@} end of group I3C_TARG_MSGLAST_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_CTRL1 I3C_CONT_CTRL1 + * @brief Controller Control 1 Register. + * @{ + */ +#define MXC_F_I3C_CONT_CTRL1_REQ_POS 0 /**< CONT_CTRL1_REQ Position */ +#define MXC_F_I3C_CONT_CTRL1_REQ ((uint32_t)(0x7UL << MXC_F_I3C_CONT_CTRL1_REQ_POS)) /**< CONT_CTRL1_REQ Mask */ +#define MXC_V_I3C_CONT_CTRL1_REQ_NONE ((uint32_t)0x0UL) /**< CONT_CTRL1_REQ_NONE Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_NONE (MXC_V_I3C_CONT_CTRL1_REQ_NONE << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_NONE Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EMIT_START ((uint32_t)0x1UL) /**< CONT_CTRL1_REQ_EMIT_START Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EMIT_START (MXC_V_I3C_CONT_CTRL1_REQ_EMIT_START << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_START Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EMIT_STOP ((uint32_t)0x2UL) /**< CONT_CTRL1_REQ_EMIT_STOP Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EMIT_STOP (MXC_V_I3C_CONT_CTRL1_REQ_EMIT_STOP << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_STOP Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_IBI_ACKNACK ((uint32_t)0x3UL) /**< CONT_CTRL1_REQ_IBI_ACKNACK Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_IBI_ACKNACK (MXC_V_I3C_CONT_CTRL1_REQ_IBI_ACKNACK << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_IBI_ACKNACK Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_PROCESS_DAA ((uint32_t)0x4UL) /**< CONT_CTRL1_REQ_PROCESS_DAA Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_PROCESS_DAA (MXC_V_I3C_CONT_CTRL1_REQ_PROCESS_DAA << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_PROCESS_DAA Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EXIT_RST ((uint32_t)0x6UL) /**< CONT_CTRL1_REQ_EXIT_RST Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EXIT_RST (MXC_V_I3C_CONT_CTRL1_REQ_EXIT_RST << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EXIT_RST Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_AUTO_IBI ((uint32_t)0x7UL) /**< CONT_CTRL1_REQ_AUTO_IBI Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_AUTO_IBI (MXC_V_I3C_CONT_CTRL1_REQ_AUTO_IBI << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_AUTO_IBI Setting */ + +#define MXC_F_I3C_CONT_CTRL1_TYPE_POS 4 /**< CONT_CTRL1_TYPE Position */ +#define MXC_F_I3C_CONT_CTRL1_TYPE ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL1_TYPE_POS)) /**< CONT_CTRL1_TYPE Mask */ + +#define MXC_F_I3C_CONT_CTRL1_IBIRESP_POS 6 /**< CONT_CTRL1_IBIRESP Position */ +#define MXC_F_I3C_CONT_CTRL1_IBIRESP ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL1_IBIRESP_POS)) /**< CONT_CTRL1_IBIRESP Mask */ + +#define MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS 8 /**< CONT_CTRL1_RDWR_DIR Position */ +#define MXC_F_I3C_CONT_CTRL1_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS)) /**< CONT_CTRL1_RDWR_DIR Mask */ + +#define MXC_F_I3C_CONT_CTRL1_ADDR_POS 9 /**< CONT_CTRL1_ADDR Position */ +#define MXC_F_I3C_CONT_CTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_CTRL1_ADDR_POS)) /**< CONT_CTRL1_ADDR Mask */ + +#define MXC_F_I3C_CONT_CTRL1_TERM_RD_POS 16 /**< CONT_CTRL1_TERM_RD Position */ +#define MXC_F_I3C_CONT_CTRL1_TERM_RD ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_CTRL1_TERM_RD_POS)) /**< CONT_CTRL1_TERM_RD Mask */ + +/**@} end of group I3C_CONT_CTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_STATUS I3C_CONT_STATUS + * @brief Controller Status Register. + * @{ + */ +#define MXC_F_I3C_CONT_STATUS_STATE_POS 0 /**< CONT_STATUS_STATE Position */ +#define MXC_F_I3C_CONT_STATUS_STATE ((uint32_t)(0x7UL << MXC_F_I3C_CONT_STATUS_STATE_POS)) /**< CONT_STATUS_STATE Mask */ +#define MXC_V_I3C_CONT_STATUS_STATE_IDLE ((uint32_t)0x0UL) /**< CONT_STATUS_STATE_IDLE Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IDLE (MXC_V_I3C_CONT_STATUS_STATE_IDLE << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IDLE Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_TARG_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_STATE_TARG_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_TARG_REQ (MXC_V_I3C_CONT_STATUS_STATE_TARG_REQ << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_TARG_REQ Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG ((uint32_t)0x2UL) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG (MXC_V_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_SDR_NORM ((uint32_t)0x3UL) /**< CONT_STATUS_STATE_SDR_NORM Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_SDR_NORM (MXC_V_I3C_CONT_STATUS_STATE_SDR_NORM << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_NORM Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_DDR ((uint32_t)0x4UL) /**< CONT_STATUS_STATE_DDR Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_DDR (MXC_V_I3C_CONT_STATUS_STATE_DDR << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DDR Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_DAA ((uint32_t)0x5UL) /**< CONT_STATUS_STATE_DAA Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_DAA (MXC_V_I3C_CONT_STATUS_STATE_DAA << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DAA Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_IBI_ACKNACK ((uint32_t)0x6UL) /**< CONT_STATUS_STATE_IBI_ACKNACK Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IBI_ACKNACK (MXC_V_I3C_CONT_STATUS_STATE_IBI_ACKNACK << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_ACKNACK Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_IBI_RX ((uint32_t)0x7UL) /**< CONT_STATUS_STATE_IBI_RX Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IBI_RX (MXC_V_I3C_CONT_STATUS_STATE_IBI_RX << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_RX Setting */ + +#define MXC_F_I3C_CONT_STATUS_WAIT_POS 4 /**< CONT_STATUS_WAIT Position */ +#define MXC_F_I3C_CONT_STATUS_WAIT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_WAIT_POS)) /**< CONT_STATUS_WAIT Mask */ + +#define MXC_F_I3C_CONT_STATUS_NACK_POS 5 /**< CONT_STATUS_NACK Position */ +#define MXC_F_I3C_CONT_STATUS_NACK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_NACK_POS)) /**< CONT_STATUS_NACK Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBITYPE_POS 6 /**< CONT_STATUS_IBITYPE Position */ +#define MXC_F_I3C_CONT_STATUS_IBITYPE ((uint32_t)(0x3UL << MXC_F_I3C_CONT_STATUS_IBITYPE_POS)) /**< CONT_STATUS_IBITYPE Mask */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_NONE ((uint32_t)0x0UL) /**< CONT_STATUS_IBITYPE_NONE Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_NONE (MXC_V_I3C_CONT_STATUS_IBITYPE_NONE << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_NONE Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_IBI ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_IBI Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_IBI (MXC_V_I3C_CONT_STATUS_IBITYPE_IBI << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_IBI Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x2UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_CONT_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_CONT_REQ Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x3UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Setting */ + +#define MXC_F_I3C_CONT_STATUS_TARG_START_POS 8 /**< CONT_STATUS_TARG_START Position */ +#define MXC_F_I3C_CONT_STATUS_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_TARG_START_POS)) /**< CONT_STATUS_TARG_START Mask */ + +#define MXC_F_I3C_CONT_STATUS_REQ_DONE_POS 9 /**< CONT_STATUS_REQ_DONE Position */ +#define MXC_F_I3C_CONT_STATUS_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_REQ_DONE_POS)) /**< CONT_STATUS_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_STATUS_DONE_POS 10 /**< CONT_STATUS_DONE Position */ +#define MXC_F_I3C_CONT_STATUS_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_DONE_POS)) /**< CONT_STATUS_DONE Mask */ + +#define MXC_F_I3C_CONT_STATUS_RX_RDY_POS 11 /**< CONT_STATUS_RX_RDY Position */ +#define MXC_F_I3C_CONT_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_RX_RDY_POS)) /**< CONT_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_STATUS_TX_NFULL_POS 12 /**< CONT_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_CONT_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_TX_NFULL_POS)) /**< CONT_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBI_WON_POS 13 /**< CONT_STATUS_IBI_WON Position */ +#define MXC_F_I3C_CONT_STATUS_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_IBI_WON_POS)) /**< CONT_STATUS_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_STATUS_ERRWARN_POS 15 /**< CONT_STATUS_ERRWARN Position */ +#define MXC_F_I3C_CONT_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_ERRWARN_POS)) /**< CONT_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_STATUS_CONT_TRANS_POS 19 /**< CONT_STATUS_CONT_TRANS Position */ +#define MXC_F_I3C_CONT_STATUS_CONT_TRANS ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_CONT_TRANS_POS)) /**< CONT_STATUS_CONT_TRANS Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBI_ADDR_POS 24 /**< CONT_STATUS_IBI_ADDR Position */ +#define MXC_F_I3C_CONT_STATUS_IBI_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_STATUS_IBI_ADDR_POS)) /**< CONT_STATUS_IBI_ADDR Mask */ + +/**@} end of group I3C_CONT_STATUS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_IBIRULES I3C_CONT_IBIRULES + * @brief Controller IBI Registry and Rules Register. + * @{ + */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR0_POS 0 /**< CONT_IBIRULES_ADDR0 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR0 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR0_POS)) /**< CONT_IBIRULES_ADDR0 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR1_POS 6 /**< CONT_IBIRULES_ADDR1 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR1 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR1_POS)) /**< CONT_IBIRULES_ADDR1 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR2_POS 12 /**< CONT_IBIRULES_ADDR2 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR2 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR2_POS)) /**< CONT_IBIRULES_ADDR2 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR3_POS 18 /**< CONT_IBIRULES_ADDR3 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR3 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR3_POS)) /**< CONT_IBIRULES_ADDR3 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR4_POS 24 /**< CONT_IBIRULES_ADDR4 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR4 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR4_POS)) /**< CONT_IBIRULES_ADDR4 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_MSB0_POS 30 /**< CONT_IBIRULES_MSB0 Position */ +#define MXC_F_I3C_CONT_IBIRULES_MSB0 ((uint32_t)(0x1UL << MXC_F_I3C_CONT_IBIRULES_MSB0_POS)) /**< CONT_IBIRULES_MSB0 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_NOBYTE_POS 31 /**< CONT_IBIRULES_NOBYTE Position */ +#define MXC_F_I3C_CONT_IBIRULES_NOBYTE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_IBIRULES_NOBYTE_POS)) /**< CONT_IBIRULES_NOBYTE Mask */ + +/**@} end of group I3C_CONT_IBIRULES_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTEN I3C_CONT_INTEN + * @brief Controller Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTEN_TARG_START_POS 8 /**< CONT_INTEN_TARG_START Position */ +#define MXC_F_I3C_CONT_INTEN_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_TARG_START_POS)) /**< CONT_INTEN_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTEN_REQ_DONE_POS 9 /**< CONT_INTEN_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTEN_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_REQ_DONE_POS)) /**< CONT_INTEN_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTEN_DONE_POS 10 /**< CONT_INTEN_DONE Position */ +#define MXC_F_I3C_CONT_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_DONE_POS)) /**< CONT_INTEN_DONE Mask */ + +#define MXC_F_I3C_CONT_INTEN_RX_RDY_POS 11 /**< CONT_INTEN_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_RX_RDY_POS)) /**< CONT_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTEN_TX_NFULL_POS 12 /**< CONT_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_TX_NFULL_POS)) /**< CONT_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTEN_IBI_WON_POS 13 /**< CONT_INTEN_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTEN_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_IBI_WON_POS)) /**< CONT_INTEN_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTEN_ERRWARN_POS 15 /**< CONT_INTEN_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_ERRWARN_POS)) /**< CONT_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTEN_NOW_CONT_POS 19 /**< CONT_INTEN_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTEN_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_NOW_CONT_POS)) /**< CONT_INTEN_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTEN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTCLR I3C_CONT_INTCLR + * @brief Controller Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTCLR_TARG_START_POS 8 /**< CONT_INTCLR_TARG_START Position */ +#define MXC_F_I3C_CONT_INTCLR_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_TARG_START_POS)) /**< CONT_INTCLR_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTCLR_REQ_DONE_POS 9 /**< CONT_INTCLR_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTCLR_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_REQ_DONE_POS)) /**< CONT_INTCLR_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTCLR_DONE_POS 10 /**< CONT_INTCLR_DONE Position */ +#define MXC_F_I3C_CONT_INTCLR_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_DONE_POS)) /**< CONT_INTCLR_DONE Mask */ + +#define MXC_F_I3C_CONT_INTCLR_RX_RDY_POS 11 /**< CONT_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_RX_RDY_POS)) /**< CONT_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTCLR_TX_NFULL_POS 12 /**< CONT_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_TX_NFULL_POS)) /**< CONT_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTCLR_IBI_WON_POS 13 /**< CONT_INTCLR_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTCLR_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_IBI_WON_POS)) /**< CONT_INTCLR_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTCLR_ERRWARN_POS 15 /**< CONT_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_ERRWARN_POS)) /**< CONT_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTCLR_NOW_CONT_POS 19 /**< CONT_INTCLR_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTCLR_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_NOW_CONT_POS)) /**< CONT_INTCLR_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTCLR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTFL I3C_CONT_INTFL + * @brief Controller Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTFL_TARG_START_POS 8 /**< CONT_INTFL_TARG_START Position */ +#define MXC_F_I3C_CONT_INTFL_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_TARG_START_POS)) /**< CONT_INTFL_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTFL_REQ_DONE_POS 9 /**< CONT_INTFL_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTFL_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_REQ_DONE_POS)) /**< CONT_INTFL_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTFL_DONE_POS 10 /**< CONT_INTFL_DONE Position */ +#define MXC_F_I3C_CONT_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_DONE_POS)) /**< CONT_INTFL_DONE Mask */ + +#define MXC_F_I3C_CONT_INTFL_RX_RDY_POS 11 /**< CONT_INTFL_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_RX_RDY_POS)) /**< CONT_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTFL_TX_NFULL_POS 12 /**< CONT_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_TX_NFULL_POS)) /**< CONT_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTFL_IBI_WON_POS 13 /**< CONT_INTFL_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTFL_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_IBI_WON_POS)) /**< CONT_INTFL_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTFL_ERRWARN_POS 15 /**< CONT_INTFL_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_ERRWARN_POS)) /**< CONT_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTFL_NOW_CONT_POS 19 /**< CONT_INTFL_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTFL_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_NOW_CONT_POS)) /**< CONT_INTFL_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTFL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_ERRWARN I3C_CONT_ERRWARN + * @brief Controller Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_CONT_ERRWARN_NACK_POS 2 /**< CONT_ERRWARN_NACK Position */ +#define MXC_F_I3C_CONT_ERRWARN_NACK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_NACK_POS)) /**< CONT_ERRWARN_NACK Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TX_ABT_POS 3 /**< CONT_ERRWARN_TX_ABT Position */ +#define MXC_F_I3C_CONT_ERRWARN_TX_ABT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TX_ABT_POS)) /**< CONT_ERRWARN_TX_ABT Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_RX_TERM_POS 4 /**< CONT_ERRWARN_RX_TERM Position */ +#define MXC_F_I3C_CONT_ERRWARN_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_RX_TERM_POS)) /**< CONT_ERRWARN_RX_TERM Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_HDR_PAR_POS 9 /**< CONT_ERRWARN_HDR_PAR Position */ +#define MXC_F_I3C_CONT_ERRWARN_HDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_HDR_PAR_POS)) /**< CONT_ERRWARN_HDR_PAR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_HDR_CRC_POS 10 /**< CONT_ERRWARN_HDR_CRC Position */ +#define MXC_F_I3C_CONT_ERRWARN_HDR_CRC ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_HDR_CRC_POS)) /**< CONT_ERRWARN_HDR_CRC Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_RX_UNR_POS 16 /**< CONT_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_CONT_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_RX_UNR_POS)) /**< CONT_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TX_OVR_POS 17 /**< CONT_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_CONT_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TX_OVR_POS)) /**< CONT_ERRWARN_TX_OVR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_MSG_POS 18 /**< CONT_ERRWARN_MSG Position */ +#define MXC_F_I3C_CONT_ERRWARN_MSG ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_MSG_POS)) /**< CONT_ERRWARN_MSG Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_INV_REQ_POS 19 /**< CONT_ERRWARN_INV_REQ Position */ +#define MXC_F_I3C_CONT_ERRWARN_INV_REQ ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_INV_REQ_POS)) /**< CONT_ERRWARN_INV_REQ Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TO_POS 20 /**< CONT_ERRWARN_TO Position */ +#define MXC_F_I3C_CONT_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TO_POS)) /**< CONT_ERRWARN_TO Mask */ + +/**@} end of group I3C_CONT_ERRWARN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_DMACTRL I3C_CONT_DMACTRL + * @brief Controller DMA Control Register. + * @{ + */ +#define MXC_F_I3C_CONT_DMACTRL_RX_EN_POS 0 /**< CONT_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_CONT_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS)) /**< CONT_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_DIS (MXC_V_I3C_CONT_DMACTRL_RX_EN_DIS << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_CONT_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_EN (MXC_V_I3C_CONT_DMACTRL_RX_EN_EN << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_CONT_DMACTRL_TX_EN_POS 2 /**< CONT_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_CONT_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS)) /**< CONT_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_DIS (MXC_V_I3C_CONT_DMACTRL_TX_EN_DIS << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_CONT_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_EN (MXC_V_I3C_CONT_DMACTRL_TX_EN_EN << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_CONT_DMACTRL_WIDTH_POS 4 /**< CONT_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_CONT_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS)) /**< CONT_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_CONT_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< CONT_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_CONT_DMACTRL_WIDTH_BYTE (MXC_V_I3C_CONT_DMACTRL_WIDTH_BYTE << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_CONT_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< CONT_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_CONT_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_CONT_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_CONT_DMACTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_FIFOCTRL I3C_CONT_FIFOCTRL + * @brief Controller FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH_POS 0 /**< CONT_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH_POS)) /**< CONT_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH_POS 1 /**< CONT_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH_POS)) /**< CONT_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_UNLOCK_POS 3 /**< CONT_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_UNLOCK_POS)) /**< CONT_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS 4 /**< CONT_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS)) /**< CONT_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS 6 /**< CONT_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS)) /**< CONT_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_LVL_POS 16 /**< CONT_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_FIFOCTRL_TX_LVL_POS)) /**< CONT_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_LVL_POS 24 /**< CONT_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_FIFOCTRL_RX_LVL_POS)) /**< CONT_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FULL_POS 30 /**< CONT_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_TX_FULL_POS)) /**< CONT_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_EM_POS 31 /**< CONT_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_RX_EM_POS)) /**< CONT_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_CONT_FIFOCTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8 I3C_CONT_TXFIFO8 + * @brief Controller Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8_DATA_POS 0 /**< CONT_TXFIFO8_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8_DATA_POS)) /**< CONT_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_CONT_TXFIFO8_END_POS 8 /**< CONT_TXFIFO8_END Position */ +#define MXC_F_I3C_CONT_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO8_END_POS)) /**< CONT_TXFIFO8_END Mask */ + +#define MXC_F_I3C_CONT_TXFIFO8_END2_POS 16 /**< CONT_TXFIFO8_END2 Position */ +#define MXC_F_I3C_CONT_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO8_END2_POS)) /**< CONT_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_CONT_TXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8E I3C_CONT_TXFIFO8E + * @brief Controller Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8E_DATA_POS 0 /**< CONT_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8E_DATA_POS)) /**< CONT_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO8E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO16 I3C_CONT_TXFIFO16 + * @brief Controller Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO16_DATA_POS 0 /**< CONT_TXFIFO16_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXFIFO16_DATA_POS)) /**< CONT_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_CONT_TXFIFO16_END_POS 16 /**< CONT_TXFIFO16_END Position */ +#define MXC_F_I3C_CONT_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO16_END_POS)) /**< CONT_TXFIFO16_END Mask */ + +/**@} end of group I3C_CONT_TXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO16E I3C_CONT_TXFIFO16E + * @brief Controller Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO16E_DATA_POS 0 /**< CONT_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXFIFO16E_DATA_POS)) /**< CONT_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO16E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXFIFO8 I3C_CONT_RXFIFO8 + * @brief Controller Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXFIFO8_DATA_POS 0 /**< CONT_RXFIFO8_DATA Position */ +#define MXC_F_I3C_CONT_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_RXFIFO8_DATA_POS)) /**< CONT_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_CONT_RXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXFIFO16 I3C_CONT_RXFIFO16 + * @brief Controller Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXFIFO16_DATA_POS 0 /**< CONT_RXFIFO16_DATA Position */ +#define MXC_F_I3C_CONT_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXFIFO16_DATA_POS)) /**< CONT_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_CONT_RXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8O I3C_CONT_TXFIFO8O + * @brief Controller Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8O_DATA_POS 0 /**< CONT_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8O_DATA_POS)) /**< CONT_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO8O_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXSDRMSG_CTRL I3C_CONT_TXSDRMSG_CTRL + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS 0 /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS)) /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR_POS 1 /**< CONT_TXSDRMSG_CTRL_ADDR Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR_POS)) /**< CONT_TXSDRMSG_CTRL_ADDR Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_END_POS 8 /**< CONT_TXSDRMSG_CTRL_END Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_END_POS)) /**< CONT_TXSDRMSG_CTRL_END Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN_POS 10 /**< CONT_TXSDRMSG_CTRL_I2C_EN Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN_POS)) /**< CONT_TXSDRMSG_CTRL_I2C_EN Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN_POS 11 /**< CONT_TXSDRMSG_CTRL_LEN Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN ((uint32_t)(0x1FUL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN_POS)) /**< CONT_TXSDRMSG_CTRL_LEN Mask */ + +/**@} end of group I3C_CONT_TXSDRMSG_CTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXSDRMSG_FIFO I3C_CONT_TXSDRMSG_FIFO + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA_POS 0 /**< CONT_TXSDRMSG_FIFO_DATA Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA_POS)) /**< CONT_TXSDRMSG_FIFO_DATA Mask */ + +/**@} end of group I3C_CONT_TXSDRMSG_FIFO_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXSDRMSG I3C_CONT_RXSDRMSG + * @brief Controller Read SDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXSDRMSG_DATA_POS 0 /**< CONT_RXSDRMSG_DATA Position */ +#define MXC_F_I3C_CONT_RXSDRMSG_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXSDRMSG_DATA_POS)) /**< CONT_RXSDRMSG_DATA Mask */ + +/**@} end of group I3C_CONT_RXSDRMSG_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXDDRMSG I3C_CONT_TXDDRMSG + * @brief Controller Start or Continue DDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXDDRMSG_MSG_POS 0 /**< CONT_TXDDRMSG_MSG Position */ +#define MXC_F_I3C_CONT_TXDDRMSG_MSG ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXDDRMSG_MSG_POS)) /**< CONT_TXDDRMSG_MSG Mask */ + +/**@} end of group I3C_CONT_TXDDRMSG_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXDDR16 I3C_CONT_RXDDR16 + * @brief Controller Read DDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXDDR16_DATA_POS 0 /**< CONT_RXDDR16_DATA Position */ +#define MXC_F_I3C_CONT_RXDDR16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXDDR16_DATA_POS)) /**< CONT_RXDDR16_DATA Mask */ + +/**@} end of group I3C_CONT_RXDDR16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_DYNADDR I3C_CONT_DYNADDR + * @brief Controller Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_CONT_DYNADDR_ADDR_POS 1 /**< CONT_DYNADDR_ADDR Position */ +#define MXC_F_I3C_CONT_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_DYNADDR_ADDR_POS)) /**< CONT_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_CONT_DYNADDR_VALID_POS 8 /**< CONT_DYNADDR_VALID Position */ +#define MXC_F_I3C_CONT_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_CONT_DYNADDR_VALID_POS)) /**< CONT_DYNADDR_VALID Mask */ + +/**@} end of group I3C_CONT_DYNADDR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_GROUPDEF I3C_TARG_GROUPDEF + * @brief Target Group Definition Register. + * @{ + */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_EN_POS 0 /**< TARG_GROUPDEF_ADDR_EN Position */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_GROUPDEF_ADDR_EN_POS)) /**< TARG_GROUPDEF_ADDR_EN Mask */ + +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_POS 1 /**< TARG_GROUPDEF_ADDR Position */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_GROUPDEF_ADDR_POS)) /**< TARG_GROUPDEF_ADDR Mask */ + +/**@} end of group I3C_TARG_GROUPDEF_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL0 I3C_TARG_MAPCTRL0 + * @brief Target Primary Map Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN_POS 0 /**< TARG_MAPCTRL0_DYNADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN_POS)) /**< TARG_MAPCTRL0_DYNADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_POS 1 /**< TARG_MAPCTRL0_DYNADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_POS)) /**< TARG_MAPCTRL0_DYNADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL0_CAUSE_POS 8 /**< TARG_MAPCTRL0_CAUSE Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_TARG_MAPCTRL0_CAUSE_POS)) /**< TARG_MAPCTRL0_CAUSE Mask */ + +/**@} end of group I3C_TARG_MAPCTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL1 I3C_TARG_MAPCTRL1 + * @brief Target Map Control 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL1_EN_POS 0 /**< TARG_MAPCTRL1_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_EN_POS)) /**< TARG_MAPCTRL1_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_ADDR_POS 1 /**< TARG_MAPCTRL1_ADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL1_ADDR_POS)) /**< TARG_MAPCTRL1_ADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN_POS 8 /**< TARG_MAPCTRL1_STATADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN_POS)) /**< TARG_MAPCTRL1_STATADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B_POS 9 /**< TARG_MAPCTRL1_STATADDR_10B Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B ((uint32_t)(0x7UL << MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B_POS)) /**< TARG_MAPCTRL1_STATADDR_10B Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_NACK_POS 12 /**< TARG_MAPCTRL1_NACK Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_NACK_POS)) /**< TARG_MAPCTRL1_NACK Mask */ + +/**@} end of group I3C_TARG_MAPCTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL2 I3C_TARG_MAPCTRL2 + * @brief Target Map Control 2 Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL2_EN_POS 0 /**< TARG_MAPCTRL2_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_EN_POS)) /**< TARG_MAPCTRL2_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_ADDR_POS 1 /**< TARG_MAPCTRL2_ADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL2_ADDR_POS)) /**< TARG_MAPCTRL2_ADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN_POS 8 /**< TARG_MAPCTRL2_STATADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN_POS)) /**< TARG_MAPCTRL2_STATADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_NACK_POS 12 /**< TARG_MAPCTRL2_NACK Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_NACK_POS)) /**< TARG_MAPCTRL2_NACK Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN_POS 13 /**< TARG_MAPCTRL2_AUTO_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN_POS)) /**< TARG_MAPCTRL2_AUTO_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_PID_POS 14 /**< TARG_MAPCTRL2_PID Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_PID ((uint32_t)(0x3FFFFUL << MXC_F_I3C_TARG_MAPCTRL2_PID_POS)) /**< TARG_MAPCTRL2_PID Mask */ + +/**@} end of group I3C_TARG_MAPCTRL2_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h new file mode 100644 index 00000000..e7691d55 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -0,0 +1,250 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @note This file is @generated. + * @ingroup icc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __IO uint32_t lbound; /**< \b 0x0000: ICC LBOUND Register */ + __IO uint32_t hbound; /**< \b 0x004: ICC HBOUND Register */ +} mxc_icc_reg_regs_t; + +typedef struct { + __I uint32_t info; /**< \b 0x0000: ICC INFO Register */ + __I uint32_t sz; /**< \b 0x0004: ICC SZ Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t ctrl; /**< \b 0x0100: ICC CTRL Register */ + __R uint32_t rsv_0x104_0x1ff[63]; + __IO uint32_t way; /**< \b 0x0200: ICC WAY Register */ + __IO uint32_t regctrl; /**< \b 0x0204: ICC REGCTRL Register */ + __IO mxc_icc_reg_regs_t region[4]; /**< \b 0x0208: ICC REGION Register */ + __R uint32_t rsv_0x228_0x2ff[54]; + __IO uint32_t pfmctrl; /**< \b 0x0300: ICC PFMCTRL Register */ + __IO uint32_t pfmcnt; /**< \b 0x0304: ICC PFMCNT Register */ + __R uint32_t rsv_0x308_0x6ff[254]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ +#define MXC_R_ICC_LBOUND ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_HBOUND ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_WAY ((uint32_t)0x00000200UL) /**< Offset from ICC Base Address: 0x0200 */ +#define MXC_R_ICC_REGCTRL ((uint32_t)0x00000204UL) /**< Offset from ICC Base Address: 0x0204 */ +#define MXC_R_ICC_REGION ((uint32_t)0x00000208UL) /**< Offset from ICC Base Address: 0x0208 */ +#define MXC_R_ICC_PFMCTRL ((uint32_t)0x00000300UL) /**< Offset from ICC Base Address: 0x0300 */ +#define MXC_R_ICC_PFMCNT ((uint32_t)0x00000304UL) /**< Offset from ICC Base Address: 0x0304 */ +#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INFO ICC_INFO + * @brief Cache ID Register. + * @{ + */ +#define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ + +#define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ + +#define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ + +/**@} end of group ICC_INFO_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_SZ ICC_SZ + * @brief Memory Configuration Register. + * @{ + */ +#define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ + +#define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ + +/**@} end of group ICC_SZ_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CTRL ICC_CTRL + * @brief Cache Control and Status Register. + * @{ + */ +#define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +/**@} end of group ICC_CTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_WAY ICC_WAY + * @brief Cache Way Control Register. + * @{ + */ +#define MXC_F_ICC_WAY_WAY_POS 0 /**< WAY_WAY Position */ +#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x7UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ +#define MXC_V_ICC_WAY_WAY_1 ((uint32_t)0x1UL) /**< WAY_WAY_1 Value */ +#define MXC_S_ICC_WAY_WAY_1 (MXC_V_ICC_WAY_WAY_1 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_1 Setting */ +#define MXC_V_ICC_WAY_WAY_2 ((uint32_t)0x2UL) /**< WAY_WAY_2 Value */ +#define MXC_S_ICC_WAY_WAY_2 (MXC_V_ICC_WAY_WAY_2 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_2 Setting */ +#define MXC_V_ICC_WAY_WAY_4 ((uint32_t)0x4UL) /**< WAY_WAY_4 Value */ +#define MXC_S_ICC_WAY_WAY_4 (MXC_V_ICC_WAY_WAY_4 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_4 Setting */ + +/**@} end of group ICC_WAY_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_REGCTRL ICC_REGCTRL + * @brief Regional Control Register. + * @{ + */ +#define MXC_F_ICC_REGCTRL_EN_POS 0 /**< REGCTRL_EN Position */ +#define MXC_F_ICC_REGCTRL_EN ((uint32_t)(0xFFUL << MXC_F_ICC_REGCTRL_EN_POS)) /**< REGCTRL_EN Mask */ + +#define MXC_F_ICC_REGCTRL_EXC_POS 8 /**< REGCTRL_EXC Position */ +#define MXC_F_ICC_REGCTRL_EXC ((uint32_t)(0xFFUL << MXC_F_ICC_REGCTRL_EXC_POS)) /**< REGCTRL_EXC Mask */ + +/**@} end of group ICC_REGCTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_PFMCTRL ICC_PFMCTRL + * @brief Performance Control Register. + * @{ + */ +#define MXC_F_ICC_PFMCTRL_EN_POS 0 /**< PFMCTRL_EN Position */ +#define MXC_F_ICC_PFMCTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_PFMCTRL_EN_POS)) /**< PFMCTRL_EN Mask */ + +/**@} end of group ICC_PFMCTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_PFMCNT ICC_PFMCNT + * @brief Performance Counter Register. + * @{ + */ +#define MXC_F_ICC_PFMCNT_CNT_POS 0 /**< PFMCNT_CNT Position */ +#define MXC_F_ICC_PFMCNT_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_PFMCNT_CNT_POS)) /**< PFMCNT_CNT Mask */ + +/**@} end of group ICC_PFMCNT_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INVALIDATE ICC_INVALIDATE + * @brief Invalidate All Registers. + * @{ + */ +#define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ + +/**@} end of group ICC_INVALIDATE_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_LBOUND ICC_LBOUND + * @brief Regional Low Bound Register. + * @{ + */ +#define MXC_F_ICC_REG_LBOUND_BOUND_POS 0 /**< REG_LBOUND_BOUND Position */ +#define MXC_F_ICC_REG_LBOUND_BOUND ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_REG_LBOUND_BOUND_POS)) /**< REG_LBOUND_BOUND Mask */ + +/**@} end of group ICC_REG_LBOUND_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_HBOUND ICC_HBOUND + * @brief DMA Channel Status Register. + * @{ + */ +#define MXC_F_ICC_REG_HBOUND_BOUND_POS 0 /**< REG_HBOUND_BOUND Position */ +#define MXC_F_ICC_REG_HBOUND_BOUND ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_REG_HBOUND_BOUND_POS)) /**< REG_HBOUND_BOUND Mask */ + +/**@} end of group ICC_REG_HBOUND_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h new file mode 100644 index 00000000..5b38135c --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -0,0 +1,968 @@ +/** + * @file max32657.h + * @brief Device-specific perhiperal header file + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ + +#ifndef TARGET_NUM +#define TARGET_NUM 32657 +#endif + +#define MXC_NUMCORES 1 + +#include +#include "system_max32657.h" + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined(__GNUC__) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif + +#elif defined(__CC_ARM) + +#define inline __inline +#pragma anon_unions + +#endif + +/* ================================================================================ */ +/* ================== Interrupt Number Table Section ================== */ +/* ================================================================================ */ + +// clang-format off +typedef enum { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Device-specific interrupt sources (external to ARM core) */ + /* table entry number */ + /* |||| */ + /* |||| table offset address */ + /* vvvv vvvvvv */ + + ICE_IRQn = 0, /* 0x10 0x0040 16: ICE Unlock */ + WDT_IRQn, /* 0x11 0x0044 17: Watchdog Timer */ + RTC_IRQn, /* 0x12 0x0048 18: RTC */ + TRNG_IRQn, /* 0x13 0x004C 19: True Random Number Generator */ + TMR0_IRQn, /* 0x14 0x0050 20: Timer 0 */ + TMR1_IRQn, /* 0x15 0x0054 21: Timer 1 */ + TMR2_IRQn, /* 0x16 0x0058 22: Timer 2 */ + TMR3_IRQn, /* 0x17 0x005C 23: Timer 3 */ + TMR4_IRQn, /* 0x18 0x0060 24: Timer 4 */ + TMR5_IRQn, /* 0x19 0x0064 25: Timer 5 */ + I3C_IRQn, /* 0x1A 0x0068 26: I3C */ + UART_IRQn, /* 0x1B 0x006C 27: UART */ + SPI_IRQn, /* 0x1C 0x0070 28: SPI */ + FLC_IRQn, /* 0x1D 0x0074 29: FLC */ + GPIO0_IRQn, /* 0x1E 0x0078 30: GPIO0 */ + RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ + DMA0_CH0_IRQn, /* 0x20 0x0080 32: DMA0 Channel 0 */ + DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ + DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ + DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 (Secure) */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 (Secure) */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 (Secure) */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 (Secure) */ + WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ + WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ + GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ + CRC_IRQn, /* 0x2B 0x00AC 43: CRC */ + AES_IRQn, /* 0x2C 0x00B0 44: AES */ + ERFO_IRQn, /* 0x2D 0x00B4 45: ERFO Ready */ + BOOST_IRQn, /* 0x2E 0x00B8 46: Boost Controller */ + ECC_IRQn, /* 0x2F 0x00BC 47: ECC */ + BTLE_TX_DONE_IRQn, /* 0x30 0x00C0 48: BTLE TX Done */ + BTLE_RX_RCVD_IRQn, /* 0x31 0x00C4 49: BTLE RX Received */ + BTLE_RX_ENG_DET_IRQn, /* 0x32 0x00C8 50: BTLE RX Energy Detected */ + BTLE_SFD_DET_IRQn, /* 0x33 0x00CC 51: BTLE SFD Detected */ + BTLE_SFD_TO_IRQn, /* 0x34 0x00D0 52: BTLE SFD Timeout */ + BTLE_GP_EVENT_IRQn, /* 0x35 0x00D4 53: BTLE BTLE Timestamp */ + BTLE_CFO_IRQn, /* 0x36 0x00D8 54: BTLE CFO Done */ + BTLE_SIG_DET_IRQn, /* 0x37 0x00DC 55: BTLE Signal Detected */ + BTLE_AGC_EVENT_IRQn, /* 0x38 0x00E0 56: BTLE AGC Event */ + BTLE_RFFE_SPIM_IRQn, /* 0x39 0x00E4 57: BTLE RFFE SPIM Done */ + BTLE_TX_AES_IRQn, /* 0x3A 0x00E8 58: BTLE TX AES Done */ + BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ + BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ + BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ + BTLE_RX_CRC_IRQn, /* 0x3E 0x00F8 62: BTLE RX CRC */ + RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ + MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ + PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ + FRQCNT_IRQn, /* 0x42 0x0108 66: Frequency Counter */ + RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ + RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ + RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; +// clang-format on + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================== Processor Section ================== */ +/* ================================================================================ */ + +#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 3U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +#include +#if (__CM_CMSIS_VERSION == 0x60000) +/* If CMSIS version 6.0 use cmsis_gcc_m.h */ +#include +#else +#include +#endif +#include + +#if defined(__GNUC__) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +// Type used for secure code to call non-secure code. +#define __ns_call __attribute((cmse_nonsecure_call)) +typedef void __ns_call (*mxc_ns_call_t)(void); +// Type used for non-secure code to call secure code. +#define __ns_entry __attribute((cmse_nonsecure_entry)) +#endif +#endif + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +/* Physical Memory Definitions */ +/* Bit 28 (security alias bit) of address is cleared. */ +#define MXC_PHY_FLASH_MEM_BASE 0x01000000UL +#define MXC_PHY_FLASH_MEM_SIZE 0x00100000UL +#define MXC_PHY_FLASH_PAGE_SIZE 0x00002000UL + +#define MXC_PHY_SRAM_MEM_BASE 0x20000000UL +#define MXC_PHY_SRAM_MEM_SIZE 0x00040000UL + +#define MXC_PHY_SRAM0_MEM_BASE 0x20000000UL +#define MXC_PHY_SRAM0_MEM_SIZE 0x00008000UL // 32KB +#define MXC_PHY_SRAM1_MEM_BASE 0x20008000UL +#define MXC_PHY_SRAM1_MEM_SIZE 0x00008000UL // 32KB +#define MXC_PHY_SRAM2_MEM_BASE 0x20010000UL +#define MXC_PHY_SRAM2_MEM_SIZE 0x00010000UL // 64KB +#define MXC_PHY_SRAM3_MEM_BASE 0x20020000UL +#define MXC_PHY_SRAM3_MEM_SIZE 0x00010000UL // 64KB +#define MXC_PHY_SRAM4_MEM_BASE 0x20030000UL +#define MXC_PHY_SRAM4_MEM_SIZE 0x00010000UL // 64KB + +/** + * Memory settings are defined accordingly by build system: max32657_memory.mk + * + * Definitions that start with the '__' are defined by the build system. + * For example, '__MXC_FLASH_MEM_BASE' + */ + +#if CONFIG_TRUSTED_EXECUTION_SECURE +/* Non-secure Regions that secure code knows about. */ +#define MXC_FLASH_NS_MEM_BASE __MXC_FLASH_NS_MEM_BASE +#define MXC_FLASH_NS_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE +#define MXC_FLASH_NS_MEM_SIZE __MXC_FLASH_NS_MEM_SIZE +#define MXC_SRAM_NS_MEM_BASE __MXC_SRAM_NS_MEM_BASE +#define MXC_SRAM_NS_MEM_SIZE __MXC_SRAM_NS_MEM_SIZE + +/* Secure Regions */ +/* ROM is always in secure region. */ +#define MXC_ROM_MEM_BASE 0x00000000UL +#define MXC_ROM_MEM_SIZE 0x00010000UL +/* Flash info is always in secure region */ +#define MXC_INFO_S_MEM_BASE 0x12000000UL +#define MXC_INFO_S_MEM_SIZE 0x00004000UL + +#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE +#endif + +#define MXC_FLASH_MEM_BASE __MXC_FLASH_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_PHY_FLASH_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE __MXC_FLASH_MEM_SIZE +#define MXC_SRAM_MEM_BASE __MXC_SRAM_MEM_BASE +#define MXC_SRAM_MEM_SIZE __MXC_SRAM_MEM_SIZE + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* + Base addresses and configuration settings for all MAX78000 peripheral modules. +*/ + +/******************************************************************************/ +/* Global control */ + +/* Non-secure Mapping */ +#define MXC_BASE_GCR_NS ((uint32_t)0x40000000UL) +#define MXC_GCR_NS ((mxc_gcr_regs_t *)MXC_BASE_GCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) +#define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_GCR MXC_GCR_S +#else +#define MXC_GCR MXC_GCR_NS +#endif + +/******************************************************************************/ +/* Non-battery backed SI Registers */ + +/* Non-secure Mapping */ +#define MXC_BASE_SIR_NS ((uint32_t)0x40000400UL) +#define MXC_SIR_NS ((mxc_sir_regs_t *)MXC_BASE_SIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) +#define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_SIR MXC_BASE_SIR_S +#define MXC_SIR MXC_SIR_S +#else +#define MXC_BASE_SIR MXC_BASE_SIR_NS +#define MXC_SIR MXC_SIR_NS +#endif + +/******************************************************************************/ +/* Non-Battery Backed Function Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_FCR_NS ((uint32_t)0x40000800UL) +#define MXC_FCR_NS ((mxc_fcr_regs_t *)MXC_BASE_FCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) +#define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_FCR MXC_BASE_FCR_S +#define MXC_FCR MXC_FCR_S +#else +#define MXC_BASE_FCR MXC_BASE_FCR_NS +#define MXC_FCR MXC_FCR_NS +#endif + +/******************************************************************************/ +/* Windowed Watchdog Timer */ +#define MXC_CFG_WDT_INSTANCES (1) + +/* Non-secure Mapping */ +#define MXC_BASE_WDT_NS ((uint32_t)0x40003000UL) +#define MXC_WDT_NS ((mxc_wdt_regs_t *)MXC_BASE_WDT_NS) + +/* Secure Mapping */ +#define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) +#define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_WDT MXC_BASE_WDT_S +#define MXC_WDT MXC_WDT_S +#else +#define MXC_BASE_WDT MXC_BASE_WDT_NS +#define MXC_WDT MXC_WDT_NS +#endif + +/******************************************************************************/ +/* RSTZ Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_RSTZ_NS ((uint32_t)0x40004800UL) +#define MXC_RSTZ_NS ((mxc_rstz_regs_t *)MXC_BASE_RSTZ_NS) + +/* Secure Mapping */ +#define MXC_BASE_RSTZ_S ((uint32_t)0x50004800UL) +#define MXC_RSTZ_S ((mxc_rstz_regs_t *)MXC_BASE_RSTZ_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_RSTZ MXC_BASE_RSTZ_S +#define MXC_RSTZ MXC_RSTZ_S //TODO(ME30): Add SVM controller registers +#else +#define MXC_BASE_RSTZ MXC_BASE_RSTZ_NS +#define MXC_RSTZ MXC_RSTZ_NS +#endif + +/******************************************************************************/ +/* Boost Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) +#define MXC_BOOST_NS ((mxc_boost_regs_t *)MXC_BASE_BOOST_NS) + +/* Secure Mapping */ +#define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) +#define MXC_BOOST_S ((mxc_boost_regs_t *)MXC_BASE_BOOST_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_BOOST MXC_BASE_BOOST_S +#define MXC_BOOST MXC_BOOST_S +#else +#define MXC_BASE_BOOST MXC_BASE_BOOST_NS +#define MXC_BOOST MXC_BOOST_NS +#endif + +/******************************************************************************/ +/* Trim System Initalization Register */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRIMSIR_NS ((uint32_t)0x40005400UL) +#define MXC_TRIMSIR_NS ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) +#define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S +#define MXC_TRIMSIR MXC_TRIMSIR_S +#else +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_NS +#define MXC_TRIMSIR MXC_TRIMSIR_NS +#endif + +/******************************************************************************/ +/* Real Time Clock */ + +/* Non-secure Mapping */ +#define MXC_BASE_RTC_NS ((uint32_t)0x40006000UL) +#define MXC_RTC_NS ((mxc_rtc_regs_t *)MXC_BASE_RTC_NS) + +/* Secure Mapping */ +#define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) +#define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_RTC MXC_BASE_RTC_S +#define MXC_RTC MXC_RTC_S +#else +#define MXC_BASE_RTC MXC_BASE_RTC_NS +#define MXC_RTC MXC_RTC_NS +#endif + +/******************************************************************************/ +/* Wake-Up Timer (WUT) */ +#define MXC_CFG_WUT_INSTANCES (2) + +/* Non-secure Mapping */ +#define MXC_BASE_WUT0_NS ((uint32_t)0x40006400UL) +#define MXC_WUT0_NS ((mxc_wut_regs_t *)MXC_BASE_WUT0_NS) +#define MXC_BASE_WUT1_NS ((uint32_t)0x40006600UL) +#define MXC_WUT1_NS ((mxc_wut_regs_t *)MXC_BASE_WUT1_NS) + +/* Secure Mapping */ +#define MXC_BASE_WUT0_S ((uint32_t)0x50006400UL) +#define MXC_WUT0_S ((mxc_wut_regs_t *)MXC_BASE_WUT0_S) +#define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) +#define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_WUT0 MXC_BASE_WUT0_S +#define MXC_WUT0 MXC_WUT0_S +#define MXC_BASE_WUT1 MXC_BASE_WUT1_S +#define MXC_WUT1 MXC_WUT1_S +#else +#define MXC_BASE_WUT0 MXC_BASE_WUT0_NS +#define MXC_WUT0 MXC_WUT0_NS +#define MXC_BASE_WUT1 MXC_BASE_WUT1_NS +#define MXC_WUT1 MXC_WUT1_NS +#endif + +/******************************************************************************/ +/* Power Sequencer */ + +/* Non-secure Mapping */ +#define MXC_BASE_PWRSEQ_NS ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ_NS ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_NS) + +/* Secure Mapping */ +#define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) +#define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S +#define MXC_PWRSEQ MXC_PWRSEQ_S +#else +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_NS +#define MXC_PWRSEQ MXC_PWRSEQ_NS +#endif + +/******************************************************************************/ +/* Misc Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_MCR_NS ((uint32_t)0x40006C00UL) +#define MXC_MCR_NS ((mxc_mcr_regs_t *)MXC_BASE_MCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) +#define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_MCR MXC_BASE_MCR_S +#define MXC_MCR MXC_MCR_S +#else +#define MXC_BASE_MCR MXC_BASE_MCR_NS +#define MXC_MCR MXC_MCR_NS +#endif + +/******************************************************************************/ +/* AES */ + +/* Non-secure Mapping */ +#define MXC_BASE_AES_NS ((uint32_t)0x40007400UL) +#define MXC_AES_NS ((mxc_aes_regs_t *)MXC_BASE_AES_NS) + +/* Secure Mapping */ +#define MXC_BASE_AES_S ((uint32_t)0x50007400UL) +#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_AES MXC_BASE_AES_S +#define MXC_AES MXC_AES_S +#else +#define MXC_BASE_AES MXC_BASE_AES_NS +#define MXC_AES MXC_AES_NS +#endif + +/******************************************************************************/ +/* AES Keys */ + +/* Non-secure Mapping */ +#define MXC_BASE_AESKEYS_NS ((uint32_t)0x40007800UL) +#define MXC_AESKEYS_NS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_NS) + +/* Secure Mapping */ +#define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) +#define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S +#define MXC_AESKEYS MXC_AESKEYS_S +#else +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_NS +#define MXC_AESKEYS MXC_AESKEYS_NS +#endif + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (32) + +/* Non-secure Mapping */ +#define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) +#define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) + +#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) +#define MXC_GPIO_NS_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) +#define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S +#define MXC_GPIO0 MXC_GPIO0_S +#else +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_NS +#define MXC_GPIO0 MXC_GPIO0_NS +#endif + +/* +Note(JC): There is only 1 GPIO instance, but for driver compatibility these must be +implemented. + +For GET_IRQ we follow precedent and return the base 0 IRQn, which is the ICE unlock. +We may want to handle GET_IRQ better... +*/ +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : 0) +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (IRQn_Type)0) + +/******************************************************************************/ +/* CRC */ + +/* Non-secure Mapping */ +#define MXC_BASE_CRC_NS ((uint32_t)0x4000F000UL) +#define MXC_CRC_NS ((mxc_crc_regs_t *)MXC_BASE_CRC_NS) + +/* Secure Mapping */ +#define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) +#define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_CRC MXC_BASE_CRC_S +#define MXC_CRC MXC_CRC_S +#else +#define MXC_BASE_CRC MXC_BASE_CRC_NS +#define MXC_CRC MXC_CRC_NS +#endif + +/******************************************************************************/ +/* Timer */ +#define SEC(s) (((uint32_t)s) * 1000000UL) +#define MSEC(ms) (ms * 1000UL) +#define USEC(us) (us) + +#define MXC_CFG_TMR_INSTANCES (6) + +/* Non-secure Mapping */ +#define MXC_BASE_TMR0_NS ((uint32_t)0x40010000UL) +#define MXC_TMR0_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR0_NS) +#define MXC_BASE_TMR1_NS ((uint32_t)0x40011000UL) +#define MXC_TMR1_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR1_NS) +#define MXC_BASE_TMR2_NS ((uint32_t)0x40012000UL) +#define MXC_TMR2_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR2_NS) +#define MXC_BASE_TMR3_NS ((uint32_t)0x40013000UL) +#define MXC_TMR3_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR3_NS) +#define MXC_BASE_TMR4_NS ((uint32_t)0x40014000UL) +#define MXC_TMR4_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR4_NS) +#define MXC_BASE_TMR5_NS ((uint32_t)0x40015000UL) +#define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) + +/* Secure Mapping */ +#define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) +#define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) +#define MXC_BASE_TMR1_S ((uint32_t)0x50011000UL) +#define MXC_TMR1_S ((mxc_tmr_regs_t *)MXC_BASE_TMR1_S) +#define MXC_BASE_TMR2_S ((uint32_t)0x50012000UL) +#define MXC_TMR2_S ((mxc_tmr_regs_t *)MXC_BASE_TMR2_S) +#define MXC_BASE_TMR3_S ((uint32_t)0x50013000UL) +#define MXC_TMR3_S ((mxc_tmr_regs_t *)MXC_BASE_TMR3_S) +#define MXC_BASE_TMR4_S ((uint32_t)0x50014000UL) +#define MXC_TMR4_S ((mxc_tmr_regs_t *)MXC_BASE_TMR4_S) +#define MXC_BASE_TMR5_S ((uint32_t)0x50015000UL) +#define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_TMR0 MXC_TMR0_S +#define MXC_TMR1 MXC_TMR1_S +#define MXC_TMR2 MXC_TMR2_S +#define MXC_TMR3 MXC_TMR3_S +#define MXC_TMR4 MXC_TMR4_S +#define MXC_TMR5 MXC_TMR5_S +#else +#define MXC_TMR0 MXC_TMR0_NS +#define MXC_TMR1 MXC_TMR1_NS +#define MXC_TMR2 MXC_TMR2_NS +#define MXC_TMR3 MXC_TMR3_NS +#define MXC_TMR4 MXC_TMR4_NS +#define MXC_TMR5 MXC_TMR5_NS +#endif + +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : \ + 0) + +#define MXC_TMR_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : \ + (i) == 4 ? MXC_TMR4 : \ + (i) == 5 ? MXC_TMR5 : \ + 0) + +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR4_IRQn : \ + (i) == 5 ? TMR5_IRQn : \ + 0) + +#define MXC_TMR_GET_IDX(p) \ + ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : \ + -1) + +/******************************************************************************/ +/* I3C */ +#define MXC_CFG_I3C_INSTANCES (1) +#define MXC_I3C_FIFO_DEPTH (8) + +/* Non-secure Mapping */ +#define MXC_BASE_I3C_NS ((uint32_t)0x40018000UL) +#define MXC_I3C_NS ((mxc_i3c_regs_t *)MXC_BASE_I3C_NS) + +/* Secure Mapping */ +#define MXC_BASE_I3C_S ((uint32_t)0x50018000UL) +#define MXC_I3C_S ((mxc_i3c_regs_t *)MXC_BASE_I3C_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_I3C MXC_BASE_I3C_S +#define MXC_I3C MXC_I3C_S +#else +#define MXC_BASE_I3C MXC_BASE_I3C_NS +#define MXC_I3C MXC_I3C_NS +#endif + +#define MXC_I3C_GET_BASE(i) ((i) == 0 ? MXC_BASE_I3C : 0) +#define MXC_I3C_GET_I3C(i) ((i) == 0 ? MXC_I3C : 0) +#define MXC_I3C_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I3C_IRQn : 0) +#define MXC_I3C_GET_IDX(p) ((p) == MXC_I3C_NS ? 0 : (p) == MXC_I3C_S ? 0 : -1) + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (4) +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_DMA_INSTANCES (2) +#else +#define MXC_DMA_INSTANCES (1) +#endif + +/* Non-secure Mapping */ +/* DMA0 Security Attribution hardwired to Non-Secure and not configurable via SPC. */ +#define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) +#define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) + +/* Secure Mapping */ +/* DMA1 Security Attribution hardwired to Secure and not configurable via SPC. */ +#define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) +#define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_DMA1 MXC_BASE_DMA1_S +#define MXC_DMA1 MXC_DMA1_S +/** + * MXC_DMA0 is not defined because DMA0 has no Secure mapping. + * Following ARM naming convention: if Secure world wants to access Non-Secure DMA (DMAO), + * then use MXC_DMA0_NS. Similar to how the Secure world accesses the Non-Secure MSP + * and VTOR registers using 'MSP_NS' and 'VTOR_NS', respectively. + */ +#ifdef MXC_DMA0 +#warning "Non-Secure DMA (DMA0) has no secure mapping. Please use MXC_DMA0_NS from Secure world." +#endif + +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0_NS && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 3) ? DMA0_CH3_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 0) ? DMA1_CH0_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 1) ? DMA1_CH1_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 2) ? DMA1_CH2_IRQn : \ + ((p) == MXC_DMA1_S && (i) == 3) ? DMA1_CH3_IRQn : \ + 0)) + +#else +#define MXC_BASE_DMA0 MXC_BASE_DMA0_NS +#define MXC_DMA0 MXC_DMA0_NS +/* MXC_DMA1 is not defined because Non-Secure Code can only access DMA0. */ +#if MXC_DMA1 +#warning "Secure DMA (DMA1) is not accessible from Non-Secure world." +#endif + +/* DMA1 IRQs not usable in Non-Secure state. */ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0_NS && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0_NS && (i) == 3) ? DMA0_CH3_IRQn : \ + 0)) +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + +#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0_NS ? 0 : (p) == MXC_BASE_DMA1_S ? 1 : -1) + +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0_NS ? 0 : (p) == MXC_DMA1_S ? 1 : -1) + +/******************************************************************************/ +/* Flash Controller */ +#define MXC_FLC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_FLC ((uint32_t)0x50029000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) + +/* Added for consistency and explicitness */ +#define MXC_BASE_FLC_S MXC_BASE_FLC +#define MXC_FLC_S MXC_FLC + +/** + * There is only one flash instance, but some bottom-level RevX implementations + * depend on MXC_FLC_GET_FLC + */ +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) + +/******************************************************************************/ +/* Internal Cache Controller */ +#define MXC_ICC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) + +/* Added for consistency and explicitness */ +#define MXC_BASE_ICC_S MXC_BASE_ICC +#define MXC_ICC_S MXC_ICC + +/******************************************************************************/ +/* UART / Serial Port Interface */ +#define MXC_UART_INSTANCES (1) +#define MXC_UART_FIFO_DEPTH (8) // TODO(ME30): Check this is correct. + +/* Non-secure Mapping */ +#define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) +#define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) + +/* Secure Mapping */ +#define MXC_BASE_UART_S ((uint32_t)0x50042000UL) +#define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_UART MXC_BASE_UART_S +#define MXC_UART MXC_UART_S +#else +#define MXC_BASE_UART MXC_BASE_UART_NS +#define MXC_UART MXC_UART_NS +#endif + +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART : 0) +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART_IRQn : 0) +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) + +/******************************************************************************/ +/* SPI */ +#define MXC_SPI_INSTANCES (1) +#define MXC_SPI_SS_INSTANCES (4) +#define MXC_SPI_FIFO_DEPTH (32) + +/* Non-secure Mapping */ +#define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) +#define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) + +/* Secure Mapping */ +#define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) +#define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_SPI MXC_BASE_SPI_S +#define MXC_SPI MXC_SPI_S +#else +#define MXC_BASE_SPI MXC_BASE_SPI_S +#define MXC_SPI MXC_SPI_NS +#endif + +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI : 0) +#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) + +/******************************************************************************/ +/* TRNG */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRNG_NS ((uint32_t)0x4004D000UL) +#define MXC_TRNG_NS ((mxc_trng_regs_t *)MXC_BASE_TRNG_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) +#define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) + +#if CONFIG_TRUSTED_EXECUTION_SECURE +#define MXC_BASE_TRNG MXC_BASE_TRNG_S +#define MXC_TRNG MXC_TRNG_S +#else +#define MXC_BASE_TRNG MXC_BASE_TRNG_NS +#define MXC_TRNG MXC_TRNG_NS +#endif + +/******************************************************************************/ +/* Non-Secure and Secure Privilege Controller (NSPC/SPC TZ) */ + +#if CONFIG_TRUSTED_EXECUTION_SECURE + +/* Secure Mapping Only */ +#define MXC_BASE_SPC ((uint32_t)0x50090000UL) +#define MXC_SPC ((mxc_spc_regs_t *)MXC_BASE_SPC) +#define MXC_SPC_S MXC_SPC + +#endif + +/* Non-Secure Mapping Only */ +#define MXC_BASE_NSPC ((uint32_t)0x40090000UL) +#define MXC_NSPC ((mxc_nspc_regs_t *)MXC_BASE_NSPC) +#define MXC_NSPC_NS MXC_NSPC + +/******************************************************************************/ +/* MPC */ + +/* Secure Mapping Only */ +#define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) +#define MXC_MPC_SRAM0 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM0) +#define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) +#define MXC_MPC_SRAM1 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM1) +#define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) +#define MXC_MPC_SRAM2 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM2) +#define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) +#define MXC_MPC_SRAM3 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM3) +#define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) +#define MXC_MPC_SRAM4 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM4) +#define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) +#define MXC_MPC_FLASH ((mxc_mpc_regs_t *)MXC_BASE_MPC_FLASH) + +/* Added for consistency and explicitness */ +#define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 +#define MXC_MPC_SRAM0_S MXC_MPC_SRAM0 +#define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 +#define MXC_MPC_SRAM1_S MXC_MPC_SRAM1 +#define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 +#define MXC_MPC_SRAM2_S MXC_MPC_SRAM2 +#define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 +#define MXC_MPC_SRAM3_S MXC_MPC_SRAM3 +#define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 +#define MXC_MPC_SRAM4_S MXC_MPC_SRAM4 +#define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH +#define MXC_MPC_FLASH_S MXC_MPC_FLASH + +/* Grab the index associated with each memory region. */ +#define MXC_MPC_GET_PHY_MEM_BASE(p) \ + ((p) == MXC_MPC_FLASH ? MXC_PHY_FLASH_MEM_BASE : \ + (p) == MXC_MPC_SRAM0 ? MXC_PHY_SRAM0_MEM_BASE : \ + (p) == MXC_MPC_SRAM1 ? MXC_PHY_SRAM1_MEM_BASE : \ + (p) == MXC_MPC_SRAM2 ? MXC_PHY_SRAM2_MEM_BASE : \ + (p) == MXC_MPC_SRAM3 ? MXC_PHY_SRAM3_MEM_BASE : \ + (p) == MXC_MPC_SRAM4 ? MXC_PHY_SRAM4_MEM_BASE : \ + 0) + +#define MXC_MPC_GET_PHY_MEM_SIZE(p) \ + ((p) == MXC_MPC_FLASH ? MXC_PHY_FLASH_MEM_SIZE : \ + (p) == MXC_MPC_SRAM0 ? MXC_PHY_SRAM0_MEM_SIZE : \ + (p) == MXC_MPC_SRAM1 ? MXC_PHY_SRAM1_MEM_SIZE : \ + (p) == MXC_MPC_SRAM2 ? MXC_PHY_SRAM2_MEM_SIZE : \ + (p) == MXC_MPC_SRAM3 ? MXC_PHY_SRAM3_MEM_SIZE : \ + (p) == MXC_MPC_SRAM4 ? MXC_PHY_SRAM4_MEM_SIZE : \ + 0) + +#define MXC_MPC_GET_IDX(p) \ + ((p) == MXC_MPC_FLASH ? 0 : \ + (p) == MXC_MPC_SRAM0 ? 0 : \ + (p) == MXC_MPC_SRAM1 ? 1 : \ + (p) == MXC_MPC_SRAM2 ? 2 : \ + (p) == MXC_MPC_SRAM3 ? 3 : \ + (p) == MXC_MPC_SRAM4 ? 4 : \ + -1) + +#define MXC_MPC_FLASH_GET_BASE(i) ((i) == 0 ? MXC_MPC_FLASH : 0) + +#define MXC_MPC_SRAM_GET_BASE(i) \ + ((i) == 0 ? MXC_MPC_SRAM0 : \ + (i) == 1 ? MXC_MPC_SRAM1 : \ + (i) == 2 ? MXC_MPC_SRAM2 : \ + (i) == 3 ? MXC_MPC_SRAM3 : \ + (i) == 4 ? MXC_MPC_SRAM4 : \ + 0) + +/******************************************************************************/ +/* Bit Shifting */ +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/******************************************************************************/ +/* Bit Banding */ +#define BITBAND(reg, bit) \ + ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ + ((bit) << 2)) + +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +#define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) + +/******************************************************************************/ +/* CPACR Definitions */ +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm33.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd new file mode 100644 index 00000000..ecfcfda3 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -0,0 +1,11896 @@ + + + Maxim-Integrated + Maxim + max32657 + ARMCM33 + 1.0 + TBD + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + AESKEYS + AES Key Registers. + 0x50007800 + + 0x00 + 0x400 + registers + + + + KEY0 + AES Key 0. + 0x00 + 32 + + + KEY1 + AES Key 1. + 0x04 + 32 + + + KEY2 + AES Key 2. + 0x08 + 32 + + + KEY3 + AES Key 3. + 0x0C + 32 + + + KEY4 + AES Key 4. + 0x10 + 32 + + + KEY5 + AES Key 5. + 0x14 + 32 + + + KEY6 + AES Key 6. + 0x18 + 32 + + + KEY7 + AES Key 7. + 0x1C + 32 + + + + + + AES + AES Keys. + 0x50007400 + + 0x00 + 0x400 + registers + + + + CTRL + AES Control Register + 0x0000 + 32 + + + EN + AES Enable + [0:0] + read-write + + + DMA_RX_EN + DMA Request To Read Data Output FIFO + [1:1] + read-write + + + DMA_TX_EN + DMA Request To Write Data Input FIFO + [2:2] + read-write + + + START + Start AES Calculation + [3:3] + read-write + + + INPUT_FLUSH + Flush the data input FIFO + [4:4] + read-write + + + OUTPUT_FLUSH + Flush the data output FIFO + [5:5] + read-write + + + KEY_SIZE + Encryption Key Size + [7:6] + read-write + + + AES128 + 128 Bits. + 0 + + + AES192 + 192 Bits. + 1 + + + AES256 + 256 Bits. + 2 + + + + + TYPE + Encryption Type Selection + [9:8] + read-write + + + + + STATUS + AES Status Register + 0x0004 + + + BUSY + AES Busy Status + [0:0] + read-write + + + INPUT_EM + Data input FIFO empty status + [1:1] + read-write + + + INPUT_FULL + Data input FIFO full status + [2:2] + read-write + + + OUTPUT_EM + Data output FIFO empty status + [3:3] + read-write + + + OUTPUT_FULL + Data output FIFO full status + [4:4] + read-write + + + + + INTFL + AES Interrupt Flag Register + 0x0008 + + + DONE + AES Done Interrupt + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + INTEN + AES Interrupt Enable Register + 0x000C + + + DONE + AES Done Interrupt Enable + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt Enable + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt Enable + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt Enable + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + FIFO + AES Data Register + 0x0010 + + + DATA + AES FIFO + [0:0] + read-write + + + + + + + + BOOST + Boost Controller + 0x50004C00 + + 0x00 + 0x400 + registers + + + BOOST + 46 + + + + DISABLE + Boost Disable Register. + 0x000 + 32 + + + DIS + This bit allows softwaree to disable the boost regulator for the VDD18 supply. + [0:0] + read-write + + + + + VREGCTRL + Boost Voltage Regulator Control Register. + 0x004 + + + SET + Sets the target voltage for the boost regulator output. + [4:0] + read-write + + + + + IPEAK + Low Side FET Peak Current Register. + 0x008 + read-only + + + SET + Sets the peak current threshold for the regulator. + [2:0] + read-only + + + + + MAXTON + Maximum Low Side FET Time-On Register. + 0x00C + read-only + + + THD + Sets a threshold for when time-on out toggles. + [3:0] + read-only + + + + + ILOAD + Boost Cycle Count Register. + 0x010 + read-only + + + CNT + Indicates the last load cycle count value. + [7:0] + read-only + + + + + ALERT + Boost Cycle Count Alert Register. + 0x014 + + + THD + Determines the threshold for when the boost alert interruptis fired. + [7:0] + read-write + + + + + RDY + Boost Output Ready Register. + 0x018 + read-only + + + OUT + Indicates ready out status for boost regulator. + [0:0] + read-only + + + + + ZXCAL + Zero Cross Calibration Register. + 0x01C + read-only + + + VAL + Read back of auto-calibration values. + [4:0] + read-only + + + + + INTEN + Boost Alert Interrupt Enable Register. + 0x020 + read-write + + + ALERT + Boost alert enable/ + [0:0] + read-write + + + + + INTFL + Boost Alert Interrupt Status Register. + 0x024 + read-write + + + ALERT + Boost alert has occurred. + [0:0] + read-write + + + + + + + + CRC + CRC Registers. + 0x5000F000 + + 0x00 + 0x1000 + registers + + + + CTRL + CRC Control + 0x0000 + 32 + + + EN + CRC Enable + [0:0] + read-write + + + DMA_EN + DMA Request Enable + [1:1] + read-write + + + MSB + MSB Select + [2:2] + read-write + + + BYTE_SWAP_IN + Byte Swap CRC Data Input + [3:3] + read-write + + + BYTE_SWAP_OUT + Byte Swap CRC Value Output + [4:4] + read-write + + + BUSY + CRC Busy + [16:16] + read-write + + + + + DATAIN32 + CRC Data Input + 0x0004 + + + DATA + CRC Data + [31:0] + read-write + + + + + DATAIN16 + CRC Data Input + 0x0004 + 16 + read-write + + + DATA + CRC Data + 0 + 16 + read-write + + + + + DATAIN8 + CRC Data Input + 0x0004 + 8 + read-write + + + DATA + CRC Data + 0 + 8 + read-write + + + + + POLY + CRC Polynomial + 0x0008 + + + POLY + CRC Polynomial + [31:0] + read-write + + + + + VAL + Current CRC Value + 0x000C + + + VALUE + Current CRC Value + [31:0] + read-write + + + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x50028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0_CH0 + 32 + + + DMA0_CH1 + 33 + + + DMA0_CH2 + 34 + + + DMA0_CH3 + 35 + + + + INTEN + DMA Control Register. + 0x000 + + + CH0 + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1 + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2 + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3 + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTFL + DMA Interrupt Register. + 0x004 + read-only + + + CH0 + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1 + 1 + 1 + + + CH2 + 2 + 1 + + + CH3 + 3 + 1 + + + + + 4 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CTRL + DMA Channel Control Register. + 0x000 + + + EN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQUEST + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPIRX + SPI RX + 0x01 + + + UARTRX + UART RX + 0x04 + + + I3CRX_CONT + I3C RX Controller + 0x07 + + + I3CRX_TARG + I3C RX Target + 0x08 + + + AESRX + AES RX + 0x10 + + + SPITX + SPI TX + 0x21 + + + UARTTX + UART TX + 0x24 + + + I3CTX_CONT + I3C TX + 0x27 + + + I3CTX_TARG + I3C TX + 0x28 + + + CRCTX + CRC TX + 0x2C + + + AESTX + AES TX + 0x30 + + + + + TO_WAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TO_PER + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + TO_CLKDIV + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BURST_SIZE + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + DIS_IE + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZ_IE + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STATUS + DMA Channel Status Register. + 0x004 + + + STATUS + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_IF + Count-to-Zero (CTZ) Interrupt Flag + 2 + 1 + oneToClear + + + RLD_IF + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_IF + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRCRLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + ADDR + Source Address Reload Value. + 0 + 31 + + + + + DSTRLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + ADDR + Destination Address Reload Value. + 0 + 31 + + + + + CNTRLD + DMA Channel Count Reload Register. + 0x01C + + + CNT + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + EN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + DMA1 + DMA Controller Fully programmable, chaining capable DMA channels. 1 + 0x50035000 + + DMA1_CH0 + DMA1_CH0 + 36 + + + DMA1_CH1 + DMA1_CH1 + 37 + + + DMA1_CH2 + DMA1_CH2 + 38 + + + DMA1_CH3 + DMA1_CH3 + 39 + + + + + FCR + Function Control Register. + 0x50000800 + + 0x00 + 0x400 + registers + + + + CTRL + Function Control 0 Register. + 0x00 + read-write + + + BTLELDO_RF + BTLE LDO RF Trim. + 0 + 5 + + + BTLELDO_BB + BTLE LDO BB Trim. + 8 + 5 + + + I3CDGEN0 + I3C SDA Glitch Filter Enable. + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I3CDGEN1 + I3C SCL Glitch Filter Enable. + 21 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + + + AUTOCAL0 + Automatic Calibration 0 Register. + 0x04 + read-write + + + EN + Auto-calibration Enable. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RUN + Autocalibration Run. + 1 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + LOAD_TRIM + Load Trim. + 2 + 1 + + + GAIN_INV + Invert Gain. + 3 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + ATOMIC + Atomic mode. + 4 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + MU + MU value. + 8 + 12 + + + TRIM_OUT + IPO Auto Calibration Trim + 23 + 9 + + + + + AUTOCAL1 + Automatic Calibration 1 Register. + 0x08 + read-write + + + INIT_TRIM + IPO Trim Automatic Calibration Initial Trim. + 0 + 9 + + + + + AUTOCAL2 + Automatic Calibration 2 Register. + 0x0C + read-write + + + RUNTIME + IPO Trim Autocal Run Time + 0 + 8 + + + DIV + IPO Trim Automatic Calibration Divide Factor. + 8 + 13 + + + + + ERFOKS + ERFO Kick Start Register. + 0x18 + read-write + + + CNT + Kick Start ERFO Counter. + 0 + 7 + + + EN + Kick Start ERFO Enable. + 7 + 1 + + + DRVSTR + Kick Start ERFO Drive Strength. + 8 + 3 + + + X2_PLEN + ERFO Kick Start Enable Double Pulse Length. + 11 + 1 + + + CLKSEL + Kick Start Clock Select for ERFO + 12 + 2 + + + NO_CLK + No kick start clock. + 0 + + + IPO + IPO. + 3 + + + + + + + INTFL + Interrupt Flag Register. + 0x1C + read-write + + + ERTOC_RDY + ERTCO 32K Ready. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Flag. + 1 + 1 + + + + + INTEN + Interrupt Enable Register. + 0x20 + read-write + + + ERTOC_RDY + ERTCO 32K Ready Interrupt Enable. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Enable. + 1 + 1 + + + + + ERFOCTRL + ERFO Control Register. + 0x24 + read-write + + + CAP_X1 + Load capacitor tuning bit for X1. + 0 + 7 + + + CAP_X2 + Load capacitor tuning bit for X2. + 7 + 7 + + + CAP_BYPASS + Bypass (disable) load capacitors. + 14 + 1 + + + + + FRQCNTCTRL + Frequency Counter Control Register. + 0x28 + read-write + + + START + Start Compare. + 0 + 1 + + + CMP_CLKSEL + Compared Clock Select. + 1 + 2 + + + RTC + RTC. + 0 + + + EXT_GPIO + External GPIO. + 2 + + + INRO + INRO. + 3 + + + + + + + FRQCNTCMP + Frequency Counter Compared Target Register. + 0x2C + read-write + + + TARGET + Compared Clock Target. + 0 + 14 + + + + + REFCLK + Reference Clock Result Register. + 0x30 + read-only + + + RESULT + Reference Clock Result. + 0 + 20 + + + + + CMPCLK + Compared Clock Result Register. + 0x34 + read-only + + + RESULT + Compared Clock Result. + 0 + 14 + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x50029000 + + 0x00 + 0x400 + registers + + + FLC + + FLC Interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE_IF + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF_IF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONE_IE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AF_IE + 9 + 1 + + + + + ECCDATA + ECC Data Register. + 0x2C + + + EVEN + Error Correction Code Odd Data. + 0 + 9 + + + ODD + Error Correction Code Even Data. + 16 + 9 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + + + + GCR + Global Control Registers. + 0x50000000 + + 0 + 0x400 + registers + + + + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE + + + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CHKRES + ROM Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + OVR + Operating Voltage Range. + 16 + 2 + + + + + RST0 + Reset. + 0x04 + + + DMA0 + DMA Reset. + 0 + 1 + + + WDT + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + TMR0 + Timer0 Reset. + 5 + 1 + + + TMR1 + Timer1 Reset. + 6 + 1 + + + TMR2 + Timer2 Reset. + 7 + 1 + + + TMR3 + Timer3 Reset. + 8 + 1 + + + TMR4 + Timer4 Reset. + 9 + 1 + + + TMR5 + Timer5 Reset. + 10 + 1 + + + UART + UART Reset. + 11 + 1 + + + SPI + SPI Reset. + 13 + 1 + + + I3C + I3C Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + TRNG + TRNG Reset. + 24 + 1 + + + DMA1 + DMA1 Reset. + 27 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + + + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + IPO + The internal Primary oscillator is used for the system clock. + 0 + + + ERFO + 27MHz Crystal is used for the system clock. + 2 + + + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + + EXTCLK + External Clock. + 7 + + + + + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + IPO_EN + 50MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 + 1 + + + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + + + IPO_RDY + Internal Primary Oscillator Ready. + 26 + 1 + + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 + 1 + + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 4 + + + ACTIVE + Active Mode. + 0 + + + BACKUP + Backup Mode. + 4 + + + PDM + DeepSleep Mode. + 10 + + + + + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + WUT_WE + Enable Wakeup Timer as wakeup source. + 7 + 1 + + + ERFO_BP + XTAL Bypass + 20 + 1 + + + normal + Normal + 0 + + + bypass + Bypass + 1 + + + + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + + + CLKDIV + Clock Divide Value. + 0 + 32 + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + DMA0 + DMA0 Disable. + 5 + 1 + + + SPI + SPI Disable. + 6 + 1 + + + UART + UART Disable. + 9 + 1 + + + I3C + I3C Disable. + 13 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + TMR4 + Timer 4 Disable. + 19 + 1 + + + TMR5 + Timer 5 Disable. + 20 + 1 + + + + + MEMCTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + + + MEMZ + Memory Zeroize Control. + 0x2C + + + SRAM0 + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SRAM1 + System RAM Block 1. + 1 + 1 + + + SRAM2 + System RAM Block 2. + 2 + 1 + + + SRAM3 + System RAM Block 3. + 3 + 1 + + + SRAM4 + System RAM Block 4. + 4 + 1 + + + ICC + Internal Cache. + 5 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 + 1 + + + AUTOCAL + Auto calibration Reset. + 12 + 1 + + + BTLE + BTLE Reset. + 18 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + TRNG + TRNG Clock Disable. + 2 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + CRC + CRC Disable. + 14 + 1 + + + AES + AES Clock Disable + 15 + 1 + + + DMA1 + DMA1 Clock Disable + 21 + 1 + + + WDT + WDT Clock Disable + 27 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA0 + Enable DMA0 event. When this bit is set, a DMA0 event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + DMA1 + Enable DMA1 event. When this bit is set, a DMA1 event will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSINTEN + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + ECCERR + ECC Error Register + 0x64 + + + FLASH + ECC Flash Error Flag. Write 1 to clear. + 0 + 1 + + + + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + + + ECCINTEN + ECC Interrupt Enable Register + 0x6C + + + FLASH + ECC Flash0 Interrupt Enable. + 0 + 1 + + + + + ECCADDR + ECC Error Address Register + 0x70 + + + DADDR + Address of Error in Data RAM. + 0 + 14 + + + DB + Data Bank, + 14 + 1 + + + DE + Data Error Flag. + 15 + 1 + + + TADDR + Address of Error in Tag RAM. + 16 + 14 + + + TB + Tag Bank. + 30 + 1 + + + TE + Tag Error Flag. + 31 + 1 + + + + + BTLELDOCTRL + BTLE LDO Control Register + 0x74 + + + BB_EN + LDO BB enable. + 0 + 1 + + + BB_PD_EN + LDO BB Pull Down. + 1 + 1 + + + BB_VSEL + Voltage Selection for BB LDO. + 2 + 2 + + + RF_EN + LDO RF enable. + 4 + 1 + + + RF_PD_EN + LDO RF Pull DOwn. + 5 + 1 + + + RF_VSEL + LDO RF Voltage Setting. + 6 + 2 + + + RF_BP_EN + LDO RF Bypass Enable. + 8 + 1 + + + RF_DISCH + LDO RF Discharge. + 9 + 1 + + + BB_BP_EN + LDO BB Bypass Enable. + 10 + 1 + + + BB_DISCH + LDO BB Discharge. + 11 + 1 + + + BB_EN_DLY + LDO BB Enable Delay. + 12 + 1 + + + RF_EN_DLY + LDO RF Enable Delay. + 13 + 1 + + + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. + 14 + 1 + + + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. + 15 + 1 + + + + + BTLELDODLY + BTLE LDO Delay Register + 0x78 + + + BP_CNT + Bypass delay count. + 0 + 8 + + + BB_CNT + BB delay count. + 8 + 9 + + + RF_CNT + RF delay count. + 20 + 9 + + + + + GPR + General Purpose Register 0. + 0x80 + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x50008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ALTERNATE + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PADCTRL + GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port. + 0x60 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + FAST + Fast Slew Rate selected. + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + + + + + + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PSSEL + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + I3C0 + Improved Inter-Integrated Circuit. + I3C + 0x50018000 + 32 + + 0x00 + 0x1000 + registers + + + I3C0 + I3C0 IRQ + 26 + + + + CONT_CTRL0 + Controller Control 0 (Configuration) Register. + 0x000 + + + EN + I3C Device Enable. + [1:0] + read-write + + + OFF + Off. + 0 + + + ON + On. + 1 + + + CAP + I23 Bug Target with secondary controller capability. + 2 + + + + + TO_DIS + Disable Timeout error. + [3:3] + read-write + + + HKEEP + High-keepr implementation. + [5:4] + read-write + + + OFF + No high-keeper support. + 0 + + + ON_CHIP + On-chip high-keeper support. + 1 + + + EXT_SDA + External high-keeper support for SDA. + 2 + + + EXT_SCL_SDA + External high-keeper support for SCL and SDA. + 3 + + + + + OD_STOP + Use open-drain speed for STOP. + [6:6] + read-write + + + PP_BAUD + SCL Frequency for push-pull drive. + [11:8] + read-write + + + 1_FCLK + SCL High Period is one FCLK Period. + 0 + + + 2_FCLK + SCL High Period is two FLCK Periods. + 1 + + + 3_FCLK + SCL High Period is three FCLK Period. + 2 + + + 4_FCLK + SCL High Period is four FCLK Period. + 3 + + + 5_FCLK + SCL High Period is five FCLK Period. + 4 + + + 6_FCLK + SCL High Period is six FCLK Period. + 5 + + + 7_FCLK + SCL High Period is seven FCLK Period. + 6 + + + 8_FCLK + SCL High Period is eight FCLK Period. + 7 + + + 9_FCLK + SCL High Period is nine FCLK Period. + 8 + + + 10_FCLK + SCL High Period is ten FCLK Period. + 9 + + + 11_FCLK + SCL High Period is eleven FCLK Period. + 10 + + + 12_FCLK + SCL High Period is twelve FCLK Period. + 11 + + + 13_FCLK + SCL High Period is thirteen FCLK Period. + 12 + + + 14_FCLK + SCL High Period is fourteen FCLK Period. + 13 + + + 15_FCLK + SCL High Period is fifthteen FCLK Period. + 14 + + + 16_FCLK + SCL High Period is sixteen FCLK Period. + 15 + + + + + PP_ADD_LBAUD + Number of FCLK periods to add to the base of SCL low period. + [15:12] + read-write + + + 0_FCLK + Adds zero FCLK periods to the SCL low period. + 0 + + + 1_FCLK + Adds one FCLK period to the SCL low period. + 1 + + + 2_FCLK + Adds two FCLK periods to the SCL low period. + 2 + + + 3_FCLK + Adds three FCLK periods to the SCL low period. + 3 + + + 4_FCLK + Adds four FCLK periods to the SCL low period. + 4 + + + 5_FCLK + Adds five FCLK periods to the SCL low period. + 5 + + + 6_FCLK + Adds six FCLK periods to the SCL low period. + 6 + + + 7_FCLK + Adds seven FCLK periods to the SCL low period. + 7 + + + 8_FCLK + Adds eight FCLK periods to the SCL low period. + 8 + + + 9_FCLK + Adds nine FCLK periods to the SCL low period. + 9 + + + 10_FCLK + Adds ten FCLK periods to the SCL low period. + 10 + + + 11_FCLK + Adds eleven FCLK periods to the SCL low period. + 11 + + + 12_FCLK + Adds twelve FCLK periods to the SCL low period. + 12 + + + 13_FCLK + Adds thirteen FCLK periods to the SCL low period. + 13 + + + 14_FCLK + Adds fourteen FCLK periods to the SCL low period. + 14 + + + 15_FCLK + Adds fifthteen FCLK periods to the SCL low period. + 15 + + + + + OD_LBAUD + Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods. + [23:16] + read-write + + + OD_HP + Controls SCL high period for I3C oepn-drain operation. + [24:24] + read-write + + + PP_SKEW + Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation. + [27:25] + read-write + + + I2C_BAUD + Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period. + [31:28] + read-write + + + + + TARG_CTRL0 + Target Control 0 (Configuration) Register. + 0x004 + + + EN + Target device enable. + [0:0] + read-write + + + MATCHSS + Match STOP and START. + [2:2] + read-write + + + TO_IGN + Ignore Timeout Errors. + [3:3] + read-write + + + OFFLINE + Rejoin I3C bus with existing dynamic address. + [9:9] + read-write + + + + + TARG_STATUS + Target Status Register. + 0x008 + + + BUSY + Not stopped. + [0:0] + read-only + + + LIST_RESP + Message status - listening/responding or not. + [1:1] + read-only + + + CCCH + CCC is being handled. + [2:2] + read-only + + + RX_SDR + SDR Read. + [3:3] + + + TX_SDR + SDR Write. + [4:4] + + + DAA + Dynamic Address Assignment Mode. + [5:5] + read-only + + + HDR + HDR Mode. + [6:6] + read-only + + + START + START Detected. + [8:8] + read-write + + + ADDRMATCH + Address Matched. + [9:9] + read-write + + + STOP + STOP Detected. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO is not full, ready to accept more data. + [12:12] + read-write + + + DYNADDR_CHG + Dynamic address changed. + [13:13] + read-write + + + CCC + CCC received. + [14:14] + read-write + + + ERRWARN + An error or warning has occurred. + [15:15] + read-only + + + CCCH_DONE + CCC Handled. + [17:17] + read-write + + + EVENT_REQ + Event Requested. + [18:18] + read-write + + + TARG_RST + Target Reset. + [19:19] + read-write + + + EVENT + Event Status. + [21:20] + read-only + + + NONE + No event. + 0 + + + REQ_PEND + Request not yet sent. + 1 + + + REQ_NACK + Request was sent and NACKed and will be tried again. + 2 + + + REQ_ACK + Request was sent and ACKed. + 3 + + + + + IBI_DIS + Indicates whether IBI events are disabled. + [24:24] + read-only + + + CONTREQ_DIS + Indicates whether bus controller request events are disabled. + [25:25] + read-only + + + HJ_DIS + Indicates whether Hot-Joinevents are disabled. + [27:27] + read-only + + + ACTSTATE + Holds the current activity state. + [29:28] + read-only + + + NORMAL + No latency, normal bus operation. + 0 + + + 1MS_LAT + 1 ms latency. + 1 + + + 100MS_LAT + 100 ms latency. + 2 + + + 10S_LAT + 10 s latency. + 3 + + + + + TIMECTRL + Time Control mode. + [31:30] + read-only + + + DIS + No timing control mode is enabled. + 0 + + + SYNC + Synchronous Mode is enabled. + 1 + + + ASYNC + Asynchronous Mode is enabled. + 2 + + + BOTH + Both synchronous and asynchronous modes are enabled. + 3 + + + + + + + TARG_CTRL1 + Target Control 1 Register. + 0x00C + + + EVENT + Sets respecive I3C target event request. + [1:0] + read-write + + + NORMAL + Normal mode. + 0 + + + IBI + Generate an IBI on the I3C bus. + 1 + + + CONTREQ + Request control of the I3C bus. + 2 + + + HJ + Generate a Hot-Join request. + 3 + + + + + EXTIBI + Indicates there are extended IBI data bytes. + [3:3] + read-write + + + DYNADDR_IDX + Index of dynamic address for the current IBI request. + [7:4] + read-write + + + IBIDATA + Contains the mandatory data byte to be sent when generating an IBI. + [15:8] + read-write + + + + + TARG_INTEN + Target Interrupt Enable Register. + 0x010 + read-write + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTCLR + Target Interrupt Clear Register. + 0x014 + write-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTFL + Target Interrupt Flag Register. + 0x018 + read-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_ERRWARN + Target Error and Warning Register. + 0x01C + read-write + + + OVR + Internal FIFO overrun flag. + [0:0] + + + UNR + Internal FIFO underrun flag. + [1:1] + + + UNR_NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + CONT_RX_TERM + Controller terminated read in message mode. + [3:3] + + + INVSTART + Invalid START. + [4:4] + + + SDR_PAR + SDR Parity Error. + [8:8] + + + TO + Timeout Error. + [11:11] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + + + TARG_DMACTRL + Target DMA Control Register. + 0x020 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + TARG_FIFOCTRL + Target FIFO Control Register. + 0x02C + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + TARG_TXFIFO8 + Target Write Byte Data Register. + 0x030 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + TARG_TXFIFO8E + Target Write Byte Data as End Register. + 0x034 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + TARG_TXFIFO16 + Target Write Half-Word Data Register. + 0x038 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + TARG_TXFIFO16E + Target Write Half-Word Data as End Register. + 0x03C + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + TARG_RXFIFO8 + Target Read Byte Data Register. + 0x040 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + TARG_RXFIFO16 + Target Read Half-Word Data Register. + 0x048 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + TARG_TXFIFO8O + Target Byte-Only Write Byte Data Register. + 0x054 + write-only + + + DATA + Data byte to send. + [7:0] + + + + + TARG_CAP0 + Target Capabilities 0 Register. + 0x05C + read-only + + + MAPCNT + Number of mapped target addresses supported. + [3:0] + + + I2C_10BADDR + I2C 10-bit address support. + [4:4] + + + I2C_SWRST + I2C Software Reset Support. + [5:5] + + + I2C_DEVID + I2C Device ID Support. + [6:6] + + + FIFO32_REG + FIFO 32 registers available. + [7:7] + + + EXTIBI + Extended IBI data support. + [8:8] + + + EXTIBI_REG + Extended IBI data register support. + [9:9] + + + HDRBT_LANES + Multi-lane support for HDR-BT mode. + [13:12] + + + CCC_V1_1 + CCC V1.1 Support. + [16:16] + + + TARG_RST + Target Reset Support. + [17:17] + + + GROUPADDR + Group address support. + [19:18] + + + AASA_CCC + SETAASA CCC Support. + [21:21] + + + T2T_SUBSC + Target-to-target subscriber support. + [22:22] + + + T2T_WR + Target-to-target write support. + [23:23] + + + + + TARG_CAP1 + TARG_Capabilities 1 Register. + 0x060 + read-only + + + PROVID + Provisioned ID implementation. + [1:0] + + + PROVID_REG + Provision ID, Bus Characteristics, Device Characteristics implementation. + [5:2] + + + HDR_MODES + Supported HDR modes. + [8:6] + + + CONT + Controller mode capable. + [9:9] + + + STATADDR + I2C-style static address implementation. + [11:10] + + + CCCH + CCC Handled by IP. + [15:12] + + + BASIC + Basic CCCs. + 1 + + + LIMITS + CCCs related to maximum transfer lengths and speed. + 2 + + + INTACT + Pending Interrupt and Activity Mode fields of GETSTATUS CCC. + 4 + + + VENDOR + Vendor Reserved field of GETSTATUS CCC. + 8 + + + + + IBI_EVENTS + Supported IBI events. + [20:16] + + + IBI + IBI support. + 1 + + + PAYLOAD + IBI has payload. + 2 + + + CONTREQ + Controller request support. + 4 + + + HJ + Hot-Join support. + 8 + + + BAMATCH + Use BAMATCH field of CONFIG register to measure 1us Bus Available timing. + 16 + + + + + TIMECTRL + Timing Control Support. + [21:21] + + + EXTFIFO + External FIFO configuration. + [25:23] + + + TXFIFO_CFG + TX FIFO configuration. + [27:26] + + + RXFIFO_CFG + RX FIFO configuration. + [29:28] + + + INTR + Interrupt support. + [30:30] + + + DMA + DMA support. + [31:31] + + + + + TARG_DYNADDR + Target Dynamic Address Register. + 0x064 + read-write + + + VALID + Address valid check. + [0:0] + + + ADDR + The assigned dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynnamic address value change occurred. + [10:8] + + + + + TARG_MAXLIMITS + Maximum Limits Register. + 0x068 + read-write + + + RX + The maximum number of bytes that the I3C controller may read from this I3C target device per message. + [11:0] + + + TX + The maximum number of bytes that the I3C controller may write from this I3C target device per message. + [27:16] + + + + + TARG_IDEXT + ID Extension Register. + 0x070 + read-write + + + DEVCHAR + Device Characteristics Register. + [15:8] + + + BUSCHAR + Bus Characteristics Register. + [23:16] + + + + + TARG_MSGLAST + Target Matching Address Index Register. + 0x07C + read-only + + + IDX + Index or group number of last matched address. + [3:0] + + + STATADDR + Last matched address was a I2C static address. + [4:4] + + + GROUP + Last matched address was a group address. + [5:5] + + + MODE + Indicates the mode of the last access. + [7:6] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + PREV_IDX + Index or group number of previous matched address. + [11:8] + + + PREV_GROUP + Last matched address was a previous group address. + [13:13] + + + PREV_MODE + Indicates the mode of the previous access. + [15:14] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + SECPREV_IDX + Index or group number of secondary previous matched address. + [19:16] + + + SECPREV_GROUP + Last matched address was a secondary previous group address. + [21:21] + + + SECPREV_MODE + Indicates the mode of the secondary previous access. + [23:22] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + + + CONT_CTRL1 + Controller Control 1 Register. + 0x084 + + + REQ + Requests an I3C or I2C bus operation. + [2:0] + read-write + + + NONE + None operation. + 0 + + + EMIT_START + Emit a START with address and read-write bit from stopped state or in the middle of an SDR message. + 1 + + + EMIT_STOP + Emit a STOP. + 2 + + + IBI_ACKNACK + Manually ACK or NACK an IBI. + 3 + + + PROCESS_DAA + Process Dynamic Address Assignment. + 4 + + + EXIT_RST + Emit HDR Exit Pattern or Target Reset pattern. + 6 + + + AUTO_IBI + Automatic IBI response. + 7 + + + + + TYPE + Controls type of operation for REQ field. + [5:4] + read-write + + + IBIRESP + Response to use when an IBI occurs. + [7:6] + read-write + + + RDWR_DIR + Direction of the transfer. + [8:8] + read-write + + + ADDR + Address to send with START. + [15:9] + read-write + + + TERM_RD + Termination count for read. + [23:16] + read-write + + + + + CONT_STATUS + Controller Status Register. + 0x088 + + + STATE + Current working state. + [2:0] + read-only + + + IDLE + Bus Idle. + 0 + + + TARG_REQ + I3C Bus i stopped and a target is holding SDA low. + 1 + + + SDR_TXSDRMSG + SDR Message Mode using SDRMSG registers. + 2 + + + SDR_NORM + Normal SDR message mode. + 3 + + + DDR + DDR Message mode + 4 + + + DAA + Dynamic Address Assignment mode. + 5 + + + IBI_ACKNACK + IP is waiting for the application to provide an ACK or NACK decision. + 6 + + + IBI_RX + IP is receiving an IBI. + 7 + + + + + WAIT + Depending on STATE, WAIT is 1 when it's waiting in an intermediary state. + [4:4] + read-only + + + NACK + Address was NACKed. + [5:5] + read-only + + + IBITYPE + The type of event for which arbitration was last won. + [7:6] + + + NONE + None. + 0 + + + IBI + In-band Interrupt. + 1 + + + CONT_REQ + Controller request. + 2 + + + HOTJOIN_REQ + Hot-Join request. + 3 + + + + + TARG_START + Target START detected. + [8:8] + + + REQ_DONE + CTRL1 Request completed. + [9:9] + read-only + + + DONE + Message completed. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO Not Full flag. + [12:12] + read-only + + + IBI_WON + IBI Arbitration won. + [13:13] + read-write + + + ERRWARN + Error or warning status. + [15:15] + read-only + + + CONT_TRANS + IP transitioned from I3C target to controller. + [19:19] + read-write + + + IBI_ADDR + The address of a received IBI or dcontroller request. + [30:24] + read-only + + + + + CONT_IBIRULES + Controller IBI Registry and Rules Register. + 0x08C + + + ADDR0 + Target 0 dynamic address. + [5:0] + read-write + + + ADDR1 + Target 1 dynamic address. + [11:6] + read-write + + + ADDR2 + Target 2 dynamic address. + [17:12] + read-write + + + ADDR3 + Target 3 dynamic address. + [23:18] + read-write + + + ADDR4 + Target 4 dynamic address. + [29:24] + read-write + + + MSB0 + Implementation of MSb for I3C dynamic addresses. + [30:30] + read-write + + + NOBYTE + Specifies the function of ADDR0 to ADDR4 + [31:31] + read-write + + + + + CONT_INTEN + Controller Interrupt Enable Register. + 0x090 + read-write + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTCLR + Controller Interrupt Clear Register. + 0x094 + write-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTFL + Controller Interrupt Flag Register. + 0x098 + read-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_ERRWARN + Controller Error and Warning Register. + 0x09C + read-write + + + NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + TX_ABT + Write aborted due to data NACK. + [3:3] + + + RX_TERM + Controller terminated read in messaage mode. + [4:4] + + + HDR_PAR + HDR Parity Error. + [9:9] + + + HDR_CRC + HDR-DDR CRC Error. + [10:10] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + MSG + Message mode error. + [18:18] + + + INV_REQ + Invalid use of request from CTRL register. + [19:19] + + + TO + Timeout error. + [20:20] + + + + + CONT_DMACTRL + Controller DMA Control Register. + 0x0A0 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + CONT_FIFOCTRL + Controller FIFO Control Register. + 0x0AC + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + CONT_TXFIFO8 + Controller Write Byte Data Register. + 0x0B0 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + CONT_TXFIFO8E + Controller Write Byte Data as End Register. + 0x0B4 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + CONT_TXFIFO16 + Controller Write Half-Word Data Register. + 0x0B8 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + CONT_TXFIFO16E + Controller Write Half-Word Data as End Register. + 0x0BC + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + CONT_RXFIFO8 + Controller Read Byte Data Register. + 0x0C0 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + CONT_RXFIFO16 + Controller Read Half-Word Data Register. + 0x0C8 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + CONT_TXFIFO8O + Controller Byte-Only Write Byte Data Register. + 0x0CC + write-only + + + DATA + Data byte to send. + [7:0] + + + + + CONT_TXSDRMSG_CTRL + Controller Start or Continue SDR Message Register. + 0x0D0 + read-write + + + RDWR_DIR + Direction of the transfer. + [0:0] + + + ADDR + Destination address of message. + [7:1] + + + END + Select how to end message. + [8:8] + + + I2C_EN + I2C Mode Enable. + [10:10] + + + LEN + Message length in bytes. + [15:11] + + + + + CONT_TXSDRMSG_FIFO + Controller Start or Continue SDR Message Register. + 0x0D0 + write-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_RXSDRMSG + Controller Read SDR Message Data Register. + 0x0D4 + read-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_TXDDRMSG + Controller Start or Continue DDR Message Register. + 0x0D8 + write-only + + + MSG + Data, address/command, and control information. + [15:0] + + + + + CONT_RXDDR16 + Controller Read DDR Message Data Register. + 0x0DC + read-only + + + DATA + Read data (16bits). + [15:0] + + + + + CONT_DYNADDR + Controller Dynamic Address Register. + 0x0E4 + read-write + + + ADDR + The assigned dynamic address. + [7:1] + + + VALID + Address valid check. + [8:8] + + + + + TARG_GROUPDEF + Target Group Definition Register. + 0x114 + read-only + + + ADDR_EN + Group Address enable. + [0:0] + + + ADDR + Group Address . + [7:1] + + + + + TARG_MAPCTRL0 + Target Primary Map Control Register. + 0x11C + read-write + + + DYNADDR_EN + Dynamic address is enabled. + [0:0] + + + DYNADDR + Dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynamic address value change occurred. + [10:8] + + + + + TARG_MAPCTRL1 + Target Map Control 1 Register. + 0x120 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + STATADDR_10B + Contains the upper 3 bits of a 10-bit I2C Static Address. + [11:9] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + + + TARG_MAPCTRL2 + Target Map Control 2 Register. + 0x124 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + AUTO_EN + Enable slot for automatic dynamic address assignment. + [13:13] + + + PID + Indicates how the last primary dynamic address value change occurred. + [31:14] + + + + + + + + ICC + Instruction Cache Controller Registers + 0x5002A000 + + 0x00 + 0x1000 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + 32 + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + 32 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + 32 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + WAY + Cache Way Control Register. + 0x0200 + 32 + + + WAY + Number of cache way, default is always 2. Allowed values are 1,2,4. + 0 + 3 + + + 1 + 1 + 1 + + + 2 + 2 + 2 + + + 4 + 4 + 4 + + + + + + + REGCTRL + Regional Control Register. + 0x0204 + 32 + + + EN + Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. + 0 + 8 + + + EXC + Cache the data only if the TAG content is excluded in the high and low bound. + 8 + 8 + + + + + 4 + 8 + REGION[%s] + Regional Low and High Bound Registers. + icc_reg + 0x0208 + 64 + read-write + + LBOUND + Regional Low Bound Register. + 0x0000 + 32 + + + BOUND + Low Bound. + 0 + 32 + + + + + HBOUND + DMA Channel Status Register. + 0x004 + 32 + + + BOUND + High Bound. + 0 + 32 + + + + + + PFMCTRL + Performance Control Register. + 0x0300 + 32 + + + EN + Enable performance counter. Clear to 0 when AHB access counter reach 0. + 0 + 1 + + + + + PFMCNT + Performance Counter Register. + 0x0304 + 32 + + + CNT + Write the total AHB access counter. Read the current performance hit count. + 0 + 32 + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + 32 + + + INVALID + Invalidate. + 0 + 32 + + + + + + + + MCR + Misc Control. + 0x50006C00 + + 0x00 + 0x400 + registers + + + + RST + Reset Register. + 0x04 + + + BOOST + Reset BOOST Controller. + 0 + 1 + + + + + OUTEN + Output Enable Register. + 0x08 + + + SQWOUT_EN + Square Wave Output Enable. + 0 + 1 + + + + + CTRL + Control Register + 0x10 + + + CLKSEL + Clcok Select for the RTC, System, WUT, and Timer. + 0 + 2 + + + ERTCO + ERTCO as clock source. + 0 + + + INRO_DIV4 + INRO as clock source. + 1 + + + RTC_IN_DIV8 + P0.12 div 8 as clock source. + 2 + + + + + ERTCO32K_EN + Enable the 32KHz ERTCO. + 3 + 1 + + + ERTCO_EN + Enable the ERTCO. + 5 + 1 + + + + + BYPASS0 + This register is used by firmware to bypass chain of trust on a Warm Boot. + 0x30 + + + BYPASS1 + This register is used by firmware to bypass chain of trust on a Warm Boot. + 0x34 + + + DATA0 + Battery Back Data0 Register. Retains value in all modes. + 0x40 + + + DATA1 + Battery Back Data1 Register. Retains value in all modes. + 0x44 + + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x50006800 + + 0x00 + 0x400 + registers + + + + LPCTRL + Low Power Control Register. + 0x00 + + + SRAMRET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 5 + + + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + RETLDO_EN + Retention LDO Enable. + 12 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LDO_EN_DLY + Core LDO Enable Delay. + 13 + 1 + + + dis + Disable. + 0 + + + en + Enable delay LDO power up to smooth LDO voltage drop. + 1 + + + + + LPWKFL_CLR + LP wakeup flag register clear. + 31 + 1 + + + + + LPWKFL0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + PINS + Wakeup Flags. + 0 + 12 + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + PINS + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 12 + + + + + LPPWST + Low Power Peripheral Wakeup Status Register. + 0x30 + + + BACKUP + BACKUP Wakeful Flag. + 16 + 1 + + + RESET + Reset Detected Wakeup Flag. + 17 + 1 + + + + + GP0 + General Purpose Register 0 + 0x48 + + + GP1 + General Purpose Register 1 + 0x4C + + + + + + MPC + Memory Protection Controller. + 0x50091000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + 32 + + + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. + 0 + 32 + + + + + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only + + + SIZE + Block Size. + 0 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 + + + + + BLK_IDX + Block Index Register. + 0x0018 + + + IDX + Index value for accessing block-based lookup table. + 0 + 32 + + + + + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C + + + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. + 0 + 32 + + + + + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only + + + MPC_IRQ + MPC IRQ triggered. + 0 + 1 + + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + + + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 + 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR5 + Peripheral ID 5 Register. + 0x0FD4 + read-only + + + PIDR6 + Peripheral ID 6 Register. + 0x0FD8 + read-only + + + PIDR7 + Peripheral ID 6 Register. + 0x0FDC + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + CIDR0 + Component ID register. + 0x0FF0 + read-only + + + CIDR1 + Component ID register. + 0x0FF4 + read-only + + + CIDR2 + Component ID register. + 0x0FF8 + read-only + + + CIDR3 + Component ID register. + 0x0FFC + read-only + + + + + + MPC1 + Memory Protection Controller. 1 + 0x50092000 + + + + MPC2 + Memory Protection Controller. 2 + 0x50093000 + + + + MPC3 + Memory Protection Controller. 3 + 0x50094000 + + + + MPC4 + Memory Protection Controller. 4 + 0x50095000 + + + + MPC5 + Memory Protection Controller. 5 + 0x50096000 + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + + + + + + RSTZ + RSTZ Controller + 0x50004800 + + 0x00 + 0x400 + registers + + + + CTRL + RSTZ Control Register. + 0x000 + 32 + + + EN + Enable channels. + [0:0] + read-write + + + SVC_EN + Enable the SVC. + [1:1] + read-write + + + CH_SEL + Channel Select. + [4:2] + read-write + + + CAL_EN + Calibration mode enable. + [5:5] + read-write + + + DMEASURE_EN + Direct Measure mode enable. + [6:6] + read-write + + + OFFTR_P + Offset Trim for positive comparator. + [11:7] + read-write + + + OFFTR_N + Offset Trim for negative comparator. + [16:12] + read-write + + + DOUT + Comparator Result. + [17:17] + read-write + + + CAL_DOUT_POL + Calibration DOUT Polarity. + [18:18] + read-write + + + NUM_SAMP + Number of captures per sample. + [27:24] + read-write + + + TRIP_TOL + Number of failed DOUT captures (tolerance) before corresponding RSTZ signal is tripped. + [31:28] + read-write + + + + + BOOST_CLKCTRL + Boost Clock Control Register. + 0x004 + + + EXIT_NUM_SAMP + Defines how many samples needed of boost output channel to perform when exiting low-power mode before returning to normal active operation. + [1:0] + read-write + + + CH_SEL + Select when channel the output of the boost converter is monitored on. + [4:2] + read-write + + + + + 8 + 4 + STATUS_CH[%s] + Channel X Status Register. + 0x028 + 32 + read-write + + + RSTZ + Result of most recent sample result. + [0:0] + read-only + + + DOUT + Store the most recent DOUT capture for a given channel. + [1:1] + read-only + + + RSTZ_FL + RSTZ Flag indicates the RSTZ was tripped at some point since the last time being cleared. + [31:31] + read-write + + + + + + + + RTC + Real Time Clock and Alarm. + 0x50006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + Sub-Seconds Counter (12-bit). + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDY_IE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SSEC_ALARM_IF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SQW_EN + Square Wave Output Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + + + RD_EN + Asynchronous Counter Read Enable. + 14 + 1 + + + sync + Synchronous. + 0 + + + async + Asynchronous. + 1 + + + + + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + ignore + Ignored. + 0 + + + allow + Allowed. + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBAT_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enable Filter. + 0 + 1 + + + IBIAS_SEL + IBIAS Select. + 1 + 1 + + + 2x + 2x + 0 + + + 4x + 4x + 1 + + + + + HYST_EN + RTC Hysteresis Enable. + 2 + 1 + + + IBIAS_EN + RTC IBIAS Enable. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_32K + RTC 32kHz Square Wave Output + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + SIR + System Initialization Registers. + 0x50000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x000 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x004 + read-only + + + ERRADDR + 0 + 32 + + + + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + + + SFSTAT + Security function status register. + 0x104 + read-only + + + SECBOOT_EN + Security Boot. + 0 + 1 + + + SECEXT_EN + M33 SecExt Function Enable. + 1 + 1 + + + + + + + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Security Access for GCR. + 0x01 + + + SIR + Security Access for SIR. + 0x02 + + + FCR + Security Access for FCR. + 0x04 + + + WDT + Security Access for WDT. + 0x08 + + + AES + Security Access for AES. + 0x010 + + + AESKEYS + Security Access for AESKEYS. + 0x020 + + + CRC + Security Access for CRC. + 0x040 + + + GPIO0 + Security Access for GPIO0. + 0x080 + + + TMR0 + Security Access for TMR0. + 0x0100 + + + TMR1 + Security Access for TMR1. + 0x0200 + + + TMR2 + Security Access for TMR2. + 0x0400 + + + TMR3 + Security Access for TMR3. + 0x0800 + + + TMR4 + Security Access for TMR4. + 0x01000 + + + TMR5 + Security Access for TMR5. + 0x02000 + + + I3C + Security Access for I3C. + 0x04000 + + + UART + Security Access for UART. + 0x08000 + + + SPI + Security Access for SPI. + 0x010000 + + + TRNG + Security Access for TRNG. + 0x020000 + + + BTLE_DBB + Security Access for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Security Access for BTLE RFFE. + 0x080000 + + + RSTZ + Security Access for RSTZ. + 0x0100000 + + + BOOST + Security Access for Boost Controller. + 0x0200000 + + + TRIMSIR + Security Access for TRIMSIR. + 0x0400000 + + + RTC + Security Access for RTC. + 0x01000000 + + + WUT0 + Security Access for WUT0. + 0x02000000 + + + WUT1 + Security Access for WUT1. + 0x04000000 + + + PWRSEQ + Security Access for Power Sequencer. + 0x08000000 + + + MCR + Security Access for MCR. + 0x10000000 + + + ALL + Security Access for all peripherals. + 0x1F7FFFFF + + + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 + + + DMA + Controls access of transactions coming from the Secure DMA. + 0 + 1 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secure or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 14 + + + + + + + + SPI + SPI peripheral. + 0x500BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 56 + + + + FIFO32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + FIFO16[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + FIFO8[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + CONT_MODE + Controller Mode Enable. + 1 + 1 + + + dis + SPI is Target mode. + 0 + + + en + SPI is Controller mode. + 1 + + + + + TS_IO + Target Select 0, IO direction, to support Multi-Controller mode,Target Select 0 can be input in Controller mode. This bit has no effect in target mode. + 4 + 1 + + + output + Target select 0 is output. + 0 + + + input + Target Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Controller Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Controller halts, if a transaction completes, and the TX FIFO is not empty, the Controller initiates another transaction. + 1 + + + + + TS_CTRL + Start Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Target Select at the end of a transaction. + 0 + + + ATSERT + SPI leaves Target Select asserted at the end of a transaction. + 1 + + + + + TS_ACTIVE + Target Select, when in Controller mode selects which Target devices are selected. More than one Target device can be selected. + 16 + 4 + + + TS0 + TS0 is selected. + 0x1 + + + TS1 + TS1 is selected. + 0x2 + + + TS2 + TS2 is selected. + 0x4 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLKPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLKPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_FB_INV + Clock Polarity. + 4 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 16 + 16 bits per character. + 0 + + + 1 + 1 bits per character. + 1 + + + 2 + 2 bits per character. + 2 + + + 3 + 3 bits per character. + 3 + + + 4 + 4 bits per character. + 4 + + + 5 + 5 bits per character. + 5 + + + 6 + 6 bits per character. + 6 + + + 7 + 7 bits per character. + 7 + + + 8 + 8 bits per character. + 8 + + + 9 + 9 bits per character. + 9 + + + 10 + 10 bits per character. + 10 + + + 11 + 11 bits per character. + 11 + + + 12 + 12 bits per character. + 12 + + + 13 + 13 bits per character. + 13 + + + 14 + 14 bits per character. + 14 + + + 15 + 15 bits per character. + 15 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + TSPOL + Target Select Polarity, each Target Select can have unique polarity. + 16 + 3 + + + TS0_high + TS0 active high. + 0x1 + + + TS1_high + TS1 active high. + 0x2 + + + TS2_high + TS2 active high. + 0x4 + + + + + + + TSTIME + Register for controlling SPI peripheral/Target Select Timing. + 0x10 + read-write + + + PRE + Target Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between TS active and first serial clock edge. + 0 + + + + + POST + Target Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and TS inactive. + 0 + + + + + INACT + Target Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLKCTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + CLKDIV + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_THD_VAL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FLUSH + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_LVL + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_THD_VAL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FLUSH + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_LVL + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INTFL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THD + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TSA + Target Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TSD + Target Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Controller Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Target Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + CONT_DONE + Controller Done, set when SPI Controller has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OV + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UN + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OV + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UN + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INTEN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THD + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EM + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TSA + Target Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TSD + Target Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Controller Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Target Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + CONT_DONE + Controller Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OV + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UN + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OV + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UN + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WKFL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WKEN + Register for wake up enable. + 0x2C + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EM + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STATUS + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Controller mode, set when transaction starts, cleared when last bit of last character is acted upon and Target Select de-assertion would occur. In Target mode, set when Target Select is asserted, cleared when Target Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + TMR + Low-Power Configurable Timer + 0x50010000 + + 0x00 + 0x1000 + registers + + + TMR + 5 + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + + TMR1 + Low-Power Configurable Timer 1 + 0x50011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + Low-Power Configurable Timer 2 + 0x50012000 + + TMR2 + TMR2 IRQ + 7 + + + + + TMR3 + Low-Power Configurable Timer 3 + 0x50013000 + + TMR3 + TMR3 IRQ + 8 + + + + + TMR4 + Low-Power Configurable Timer 4 + 0x50080C00 + + TMR4 + TMR4 IRQ + 9 + + + + + TMR5 + Low-Power Configurable Timer 5 + 0x50081000 + + TMR5 + TMR5 IRQ + 10 + + + + + TRIMSIR + Trim System Initilazation Registers. + 0x50005400 + + 0x00 + 0x400 + registers + + + + RTCX1 + RTC X1 Capacitor Setting. + 0x3C + + + CAP + RTC X1 Load Capacitor Setting. + 0 + 5 + + + + + RTCX2 + RTC X2 Capacitor Setting. + 0x44 + + + CAP + RTC X2 Load Capacitor Setting. + 0 + 5 + + + + + + + + TRNG + Random Number Generator. + 0x5004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CTRL + TRNG Control Register. + 0x00 + 0x00000003 + + + OD_HEALTH + Start On-Demand health test. + 0 + 1 + + + RND_IE + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_IE + Enable IRQ generation when a health test fails. + 2 + 1 + + + AESKG_MEU + Generate and transfer 256 bit MEU key to AES Key storage. + 3 + 1 + + + AESKG_MEMPROT_XIP + Generate and transfer 128 bit MEMPROT_XIP key to AES key storage. + 4 + 1 + + + AESKG_MEMPROT_DIP + Generate and transfer 128 bit MEMPROT_DIP key to AES key storage. + 5 + 1 + + + OD_ROMON + Start ring oscillator monitor on demand test. + 6 + 1 + + + OD_EE + Start entropy estimator on demand test. + 7 + 1 + + + ROMON_EE_FOE + Ring Oscillator Monitors and Entropy Estimator Freeze on Error. + 8 + 1 + + + ROMON_EE_FOD + Ring Oscillator Monitors and Entropy Estimator Freeze on Done. + 9 + 1 + + + EBLS + Entropy Bit Load Select. + 10 + 1 + + + KEYWIPE + To wipe the Battery Backed key. + 15 + 1 + + + GET_TERO_CNT + Get Tero Count. + 16 + 1 + + + EE_DONE_IE + Entropy Estimator Done Interrupt Enable. + 23 + 1 + + + ROMON_DIS + Ring Oscillator Disable. + 24 + 3 + + + RO_0 + Ring Oscillator 0. + 1 + + + RO_1 + Ring Oscillator 1. + 2 + + + RO_2 + Ring Oscillator 2. + 4 + + + + + ROMON_DIV2 + Divide ring by 2. + 28 + 3 + + + RO_0 + Ring Oscillator 0. + 0 + + + RO_1 + Ring Oscillator 1. + 1 + + + RO_2 + Ring Oscillator 2. + 2 + + + + + + + STATUS + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + + + RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + OD_HEALTH + On-Demand health test status. + 1 + 1 + + + HEALTH + Health test status. + 2 + 1 + + + SRCFAIL + Entropy source has failed. + 3 + 1 + + + AES_KEYGEN + AESKGD. + 4 + 1 + + + OD_ROMON + On demand ring oscillator test status. + 6 + 1 + + + OD_EE + On demand entropy estimator status. + 7 + 1 + + + PP_ERR + Post process error. + 8 + 1 + + + ROMON_0_ERR + Ring Oscillator 0 Monitor Error. + 9 + 1 + + + ROMON_1_ERR + Ring Oscillator 1 Monitor Error. + 10 + 1 + + + ROMON_2_ERR + Ring Oscillator 2 Monitor Error. + 11 + 1 + + + EE_ERR_THR + Entropy Estimator Threshold Error. + 12 + 1 + + + EE_ERR_OOB + Entropy Estimator Out of Bounds Error.. + 13 + 1 + + + EE_ERR_LOCK + Entropy Estimator Lock Error. + 14 + 1 + + + TERO_CNT_RDY + TERO Count Ready. + 16 + 1 + + + RC_ERR + Repetition Count Error. + 17 + 1 + + + AP_ERR + Adaptive Proportion Error. + 18 + 1 + + + DATA_DONE + Data register has been loaded with at least 32 new entropy bits. + 19 + 1 + + + DATA_NIST_DONE + Data NIST register has been loaded with at least 32 new entropy bits. + 20 + 1 + + + HEALTH_DONE + Health Test Done. + 21 + 1 + + + ROMON_DONE + Ring Oscillator Monitor Test Done. + 22 + 1 + + + EE_DONE + Entropy Estimator Test Done. + 23 + 1 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + DATA_NIST + Data NIST Register. + 0x38 + + + DATA + Ring Oscillator 1 Monitor Last Ring Oscillator Count. + 0 + 32 + + + + + + + + UART + UART Low Power Registers + 0x50042000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control register + 0x0000 + + + RX_THD_VAL + This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) + 0 + 4 + + + PAR_EN + Parity Enable + 4 + 1 + + + PAR_EO + when PAREN=1 selects odd or even parity odd is 1 even is 0 + 5 + 1 + + + PAR_MD + Selects parity based on 1s or 0s count (when PAREN=1) + 6 + 1 + + + CTS_DIS + CTS Sampling Disable + 7 + 1 + + + TX_FLUSH + Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 8 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 9 + 1 + + + CHAR_SIZE + Selects UART character size + 10 + 2 + + + 5bits + 5 bits + 0 + + + 6bits + 6 bits + 1 + + + 7bits + 7 bits + 2 + + + 8bits + 8 bits + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated + 12 + 1 + + + HFC_EN + Enables/disables hardware flow control + 13 + 1 + + + RTS_NEG + The condition to negate RTS in HFC mode. + 14 + 1 + + + CLK_EN + Baud clock enable + 15 + 1 + + + CLK_SEL + To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. + 16 + 2 + + + PERIPHERAL_CLOCK + APB Clock. + 0 + + + CLK1 + IBRO clock. + 1 + + + + + CLK_RDY + Baud clock Ready read only bit + 19 + 1 + + + CLK_GATE + UART Clock Auto Gating mode + 20 + 1 + + + + + STATUS + Status register + 0x0004 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status + 0 + 1 + + + RX_BUSY + Read-only flag indicating the UART receiver status + 1 + 1 + + + RX_EM + Read-only flag indicating the RX FIFO state + 4 + 1 + + + RX_FULL + Read-only flag indicating the RX FIFO state + 5 + 1 + + + TX_EM + Read-only flag indicating the TX FIFO state + 6 + 1 + + + TX_FULL + Read-only flag indicating the TX FIFO state + 7 + 1 + + + RX_LVL + Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) + 8 + 4 + + + TX_LVL + Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) + 12 + 4 + + + + + INTEN + Interrupt Enable control register + 0x0008 + + + RX_FERR + Enable Interrupt For RX Frame Error + 0 + 1 + + + RX_PAR + Enable Interrupt For RX Parity Error + 1 + 1 + + + CTS_EV + Enable Interrupt For CTS signal change Error + 2 + 1 + + + RX_OV + Enable Interrupt For RX FIFO Overrun Error + 3 + 1 + + + RX_THD + Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD + 4 + 1 + + + TX_OB + Enable Interrupt For TX FIFO when only one byte is remaining. + 5 + 1 + + + TX_THD + Enable Interrupt for when TX FIFO meets or passes the threshold level. + 6 + 1 + + + RX_FULL + Enable for RX FIFO Full interrupt. + 7 + 1 + + + + + INTFL + Interrupt status flags Control register + 0x000C + + + RX_FERR + Flag for RX Frame Error Interrupt. + 0 + 1 + + + RX_PAR + Flag for RX Parity Error interrupt + 1 + 1 + + + CTS_EV + Flag for CTS signal change interrupt (hardware flow control disabled) + 2 + 1 + + + RX_OV + Flag for RX FIFO Overrun interrupt + 3 + 1 + + + RX_THD + Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field + 4 + 1 + + + TX_OB + Flag for interrupt when TX FIFO has only one byte is remaining. + 5 + 1 + + + TX_THD + Flag for interrupt when TX FIFO meets or passes the threshold level. + 6 + 1 + + + RX_FULL + Flag for full RX FIFO. + 7 + 1 + + + + + CLKDIV + Clock Divider register + 0x0010 + + + CLKDIV + Baud rate divisor value + 0 + 20 + + + + + OSR + Over Sampling Rate register + 0x0014 + + + OSR + OSR + 0 + 3 + + + + + TXPEEK + TX FIFO Output Peek register + 0x0018 + + + DATA + Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. + 0 + 8 + + + + + PIN + Pin register + 0x001C + + + CTS + Current sampled value of CTS IO + 0 + 1 + read-only + + + RTS + This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. + 1 + 1 + + + + + FIFO + FIFO Read/Write register + 0x0020 + + + DATA + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + RX_PAR + Parity error flag for next byte to be read from FIFO. + 8 + 1 + + + + + DMA + DMA Configuration register + 0x0030 + + + TX_THD_VAL + TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. + 0 + 4 + + + TX_EN + TX DMA channel enable + 4 + 1 + + + RX_THD_VAL + Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. + 5 + 4 + + + RX_EN + RX DMA channel enable + 9 + 1 + + + + + WKEN + Wake up enable Control register + 0x0034 + + + RX_NE + Wake-Up Enable for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Enable for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Enable for RX FIFO Threshold Met + 2 + 1 + + + + + WKFL + Wake up Flags register + 0x0038 + + + RX_NE + Wake-Up Flag for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Flag for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Flag for RX FIFO Threshold Met + 2 + 1 + + + + + + + + WDT + Windowed Watchdog Timer + 0x50003000 + + 0x00 + 0x0400 + registers + + + WWDT + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + read-write + + + INT_LATE_VAL + Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_LATE_VAL + Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + EN + Windowed Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_LATE + Windowed Watchdog Timer Interrupt Flag Too Late. + 9 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + WDT_INT_EN + Windowed Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + WDT_RST_EN + Windowed Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_EARLY + Windowed Watchdog Timer Interrupt Flag Too Soon. + 12 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EARLY_VAL + Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 16 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_EARLY_VAL + Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 20 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + CLKRDY_IE + Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. + 27 + 1 + + + CLKRDY + Clock Status. + 28 + 1 + + + WIN_EN + Enables the Windowed Watchdog Function. + 29 + 1 + + + dis + Windowed Mode Disabled (i.e. Compatibility Mode). + 0 + + + en + Windowed Mode Enabled. + 1 + + + + + RST_EARLY + Windowed Watchdog Timer Reset Flag Too Soon. + 30 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + RST_LATE + Windowed Watchdog Timer Reset Flag Too Late. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Windowed Watchdog Timer Reset Register. + 0x04 + write-only + + + RESET + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + CLKSEL + Windowed Watchdog Timer Clock Select Register. + 0x08 + read-write + + + SOURCE + WWDT Clock Selection Register. + 0 + 3 + + + + + CNT + Windowed Watchdog Timer Count Register. + 0x0C + read-only + + + COUNT + Current Value of the Windowed Watchdog Timer Counter. + 0 + 32 + + + + + + + + WUT + 32-bit reloadable timer that can be used for timing and wakeup. + 0x50006400 + + 0x00 + 0x400 + registers + + + WUT + WUT IRQ + 53 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Timer Count Value. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Timer Compare Value. + 0 + 32 + + + + + INTFL + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + CLR + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOL_LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOL_HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + PRESET + Preset register. + 0x18 + + + PRESET + Preset Value. + 0 + 32 + + + + + RELOAD + Reload register. + 0x1C + + + RELOAD + Rerload Value. + 0 + 32 + + + + + SNAPSHOT + Snapshot register. + 0x20 + + + SNAPSHOT + Snapshot Value. + 0 + 32 + + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h new file mode 100644 index 00000000..039c7940 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -0,0 +1,153 @@ +/** + * @file mcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. + * @note This file is @generated. + * @ingroup mcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup mcr + * @defgroup mcr_registers MCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. + * @details Misc Control. + */ + +/** + * @ingroup mcr_registers + * Structure type to access the MCR Registers. + */ +typedef struct { + __R uint32_t rsv_0x0; + __IO uint32_t rst; /**< \b 0x04: MCR RST Register */ + __IO uint32_t outen; /**< \b 0x08: MCR OUTEN Register */ + __R uint32_t rsv_0xc; + __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ + __R uint32_t rsv_0x14_0x2f[7]; + __IO uint32_t bypass0; /**< \b 0x30: MCR BYPASS0 Register */ + __IO uint32_t bypass1; /**< \b 0x34: MCR BYPASS1 Register */ + __R uint32_t rsv_0x38_0x3f[2]; + __IO uint32_t data0; /**< \b 0x40: MCR DATA0 Register */ + __IO uint32_t data1; /**< \b 0x44: MCR DATA1 Register */ +} mxc_mcr_regs_t; + +/* Register offsets for module MCR */ +/** + * @ingroup mcr_registers + * @defgroup MCR_Register_Offsets Register Offsets + * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. + * @{ + */ +#define MXC_R_MCR_RST ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ +#define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ +#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ +#define MXC_R_MCR_BYPASS0 ((uint32_t)0x00000030UL) /**< Offset from MCR Base Address: 0x0030 */ +#define MXC_R_MCR_BYPASS1 ((uint32_t)0x00000034UL) /**< Offset from MCR Base Address: 0x0034 */ +#define MXC_R_MCR_DATA0 ((uint32_t)0x00000040UL) /**< Offset from MCR Base Address: 0x0040 */ +#define MXC_R_MCR_DATA1 ((uint32_t)0x00000044UL) /**< Offset from MCR Base Address: 0x0044 */ +/**@} end of group mcr_registers */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_RST MCR_RST + * @brief Reset Register. + * @{ + */ +#define MXC_F_MCR_RST_BOOST_POS 0 /**< RST_BOOST Position */ +#define MXC_F_MCR_RST_BOOST ((uint32_t)(0x1UL << MXC_F_MCR_RST_BOOST_POS)) /**< RST_BOOST Mask */ + +/**@} end of group MCR_RST_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_OUTEN MCR_OUTEN + * @brief Output Enable Register. + * @{ + */ +#define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0 /**< OUTEN_SQWOUT_EN Position */ +#define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) /**< OUTEN_SQWOUT_EN Mask */ + +/**@} end of group MCR_OUTEN_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_CTRL MCR_CTRL + * @brief Control Register + * @{ + */ +#define MXC_F_MCR_CTRL_CLKSEL_POS 0 /**< CTRL_CLKSEL Position */ +#define MXC_F_MCR_CTRL_CLKSEL ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CLKSEL_POS)) /**< CTRL_CLKSEL Mask */ +#define MXC_V_MCR_CTRL_CLKSEL_ERTCO ((uint32_t)0x0UL) /**< CTRL_CLKSEL_ERTCO Value */ +#define MXC_S_MCR_CTRL_CLKSEL_ERTCO (MXC_V_MCR_CTRL_CLKSEL_ERTCO << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_ERTCO Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 ((uint32_t)0x1UL) /**< CTRL_CLKSEL_INRO_DIV4 Value */ +#define MXC_S_MCR_CTRL_CLKSEL_INRO_DIV4 (MXC_V_MCR_CTRL_CLKSEL_INRO_DIV4 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_INRO_DIV4 Setting */ +#define MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 ((uint32_t)0x2UL) /**< CTRL_CLKSEL_RTC_IN_DIV8 Value */ +#define MXC_S_MCR_CTRL_CLKSEL_RTC_IN_DIV8 (MXC_V_MCR_CTRL_CLKSEL_RTC_IN_DIV8 << MXC_F_MCR_CTRL_CLKSEL_POS) /**< CTRL_CLKSEL_RTC_IN_DIV8 Setting */ + +#define MXC_F_MCR_CTRL_ERTCO32K_EN_POS 3 /**< CTRL_ERTCO32K_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO32K_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO32K_EN_POS)) /**< CTRL_ERTCO32K_EN Mask */ + +#define MXC_F_MCR_CTRL_ERTCO_EN_POS 5 /**< CTRL_ERTCO_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ + +/**@} end of group MCR_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h new file mode 100644 index 00000000..5944ce49 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h @@ -0,0 +1,280 @@ +/** + * @file mpc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @note This file is @generated. + * @ingroup mpc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup mpc + * @defgroup mpc_registers MPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @details Memory Protection Controller. + */ + +/** + * @ingroup mpc_registers + * Structure type to access the MPC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: MPC CTRL Register */ + __R uint32_t rsv_0x4_0xf[3]; + __I uint32_t blk_max; /**< \b 0x0010: MPC BLK_MAX Register */ + __I uint32_t blk_cfg; /**< \b 0x0014: MPC BLK_CFG Register */ + __IO uint32_t blk_idx; /**< \b 0x0018: MPC BLK_IDX Register */ + __IO uint32_t blk_lut; /**< \b 0x001C: MPC BLK_LUT Register */ + __I uint32_t int_stat; /**< \b 0x0020: MPC INT_STAT Register */ + __O uint32_t int_clear; /**< \b 0x0024: MPC INT_CLEAR Register */ + __IO uint32_t int_en; /**< \b 0x0028: MPC INT_EN Register */ + __I uint32_t int_info1; /**< \b 0x002C: MPC INT_INFO1 Register */ + __I uint32_t int_info2; /**< \b 0x0030: MPC INT_INFO2 Register */ + __O uint32_t int_set; /**< \b 0x0034: MPC INT_SET Register */ + __R uint32_t rsv_0x38_0xfcf[998]; + __I uint32_t pidr4; /**< \b 0x0FD0: MPC PIDR4 Register */ + __I uint32_t pidr5; /**< \b 0x0FD4: MPC PIDR5 Register */ + __I uint32_t pidr6; /**< \b 0x0FD8: MPC PIDR6 Register */ + __I uint32_t pidr7; /**< \b 0x0FDC: MPC PIDR7 Register */ + __I uint32_t pidr0; /**< \b 0x0FE0: MPC PIDR0 Register */ + __I uint32_t pidr1; /**< \b 0x0FE4: MPC PIDR1 Register */ + __I uint32_t pidr2; /**< \b 0x0FE8: MPC PIDR2 Register */ + __I uint32_t pidr3; /**< \b 0x0FEC: MPC PIDR3 Register */ + __I uint32_t cidr0; /**< \b 0x0FF0: MPC CIDR0 Register */ + __I uint32_t cidr1; /**< \b 0x0FF4: MPC CIDR1 Register */ + __I uint32_t cidr2; /**< \b 0x0FF8: MPC CIDR2 Register */ + __I uint32_t cidr3; /**< \b 0x0FFC: MPC CIDR3 Register */ +} mxc_mpc_regs_t; + +/* Register offsets for module MPC */ +/** + * @ingroup mpc_registers + * @defgroup MPC_Register_Offsets Register Offsets + * @brief MPC Peripheral Register Offsets from the MPC Base Peripheral Address. + * @{ + */ +#define MXC_R_MPC_CTRL ((uint32_t)0x00000000UL) /**< Offset from MPC Base Address: 0x0000 */ +#define MXC_R_MPC_BLK_MAX ((uint32_t)0x00000010UL) /**< Offset from MPC Base Address: 0x0010 */ +#define MXC_R_MPC_BLK_CFG ((uint32_t)0x00000014UL) /**< Offset from MPC Base Address: 0x0014 */ +#define MXC_R_MPC_BLK_IDX ((uint32_t)0x00000018UL) /**< Offset from MPC Base Address: 0x0018 */ +#define MXC_R_MPC_BLK_LUT ((uint32_t)0x0000001CUL) /**< Offset from MPC Base Address: 0x001C */ +#define MXC_R_MPC_INT_STAT ((uint32_t)0x00000020UL) /**< Offset from MPC Base Address: 0x0020 */ +#define MXC_R_MPC_INT_CLEAR ((uint32_t)0x00000024UL) /**< Offset from MPC Base Address: 0x0024 */ +#define MXC_R_MPC_INT_EN ((uint32_t)0x00000028UL) /**< Offset from MPC Base Address: 0x0028 */ +#define MXC_R_MPC_INT_INFO1 ((uint32_t)0x0000002CUL) /**< Offset from MPC Base Address: 0x002C */ +#define MXC_R_MPC_INT_INFO2 ((uint32_t)0x00000030UL) /**< Offset from MPC Base Address: 0x0030 */ +#define MXC_R_MPC_INT_SET ((uint32_t)0x00000034UL) /**< Offset from MPC Base Address: 0x0034 */ +#define MXC_R_MPC_PIDR4 ((uint32_t)0x00000FD0UL) /**< Offset from MPC Base Address: 0x0FD0 */ +#define MXC_R_MPC_PIDR5 ((uint32_t)0x00000FD4UL) /**< Offset from MPC Base Address: 0x0FD4 */ +#define MXC_R_MPC_PIDR6 ((uint32_t)0x00000FD8UL) /**< Offset from MPC Base Address: 0x0FD8 */ +#define MXC_R_MPC_PIDR7 ((uint32_t)0x00000FDCUL) /**< Offset from MPC Base Address: 0x0FDC */ +#define MXC_R_MPC_PIDR0 ((uint32_t)0x00000FE0UL) /**< Offset from MPC Base Address: 0x0FE0 */ +#define MXC_R_MPC_PIDR1 ((uint32_t)0x00000FE4UL) /**< Offset from MPC Base Address: 0x0FE4 */ +#define MXC_R_MPC_PIDR2 ((uint32_t)0x00000FE8UL) /**< Offset from MPC Base Address: 0x0FE8 */ +#define MXC_R_MPC_PIDR3 ((uint32_t)0x00000FECUL) /**< Offset from MPC Base Address: 0x0FEC */ +#define MXC_R_MPC_CIDR0 ((uint32_t)0x00000FF0UL) /**< Offset from MPC Base Address: 0x0FF0 */ +#define MXC_R_MPC_CIDR1 ((uint32_t)0x00000FF4UL) /**< Offset from MPC Base Address: 0x0FF4 */ +#define MXC_R_MPC_CIDR2 ((uint32_t)0x00000FF8UL) /**< Offset from MPC Base Address: 0x0FF8 */ +#define MXC_R_MPC_CIDR3 ((uint32_t)0x00000FFCUL) /**< Offset from MPC Base Address: 0x0FFC */ +/**@} end of group mpc_registers */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_CTRL MPC_CTRL + * @brief Control Register. + * @{ + */ +#define MXC_F_MPC_CTRL_SEC_ERR_POS 4 /**< CTRL_SEC_ERR Position */ +#define MXC_F_MPC_CTRL_SEC_ERR ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_ERR_POS)) /**< CTRL_SEC_ERR Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_REQ_POS 6 /**< CTRL_DATAIF_REQ Position */ +#define MXC_F_MPC_CTRL_DATAIF_REQ ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_REQ_POS)) /**< CTRL_DATAIF_REQ Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_ACK_POS 7 /**< CTRL_DATAIF_ACK Position */ +#define MXC_F_MPC_CTRL_DATAIF_ACK ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_ACK_POS)) /**< CTRL_DATAIF_ACK Mask */ + +#define MXC_F_MPC_CTRL_AUTO_INC_POS 8 /**< CTRL_AUTO_INC Position */ +#define MXC_F_MPC_CTRL_AUTO_INC ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_AUTO_INC_POS)) /**< CTRL_AUTO_INC Mask */ + +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS 31 /**< CTRL_SEC_LOCKDOWN Position */ +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS)) /**< CTRL_SEC_LOCKDOWN Mask */ + +/**@} end of group MPC_CTRL_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_MAX MPC_BLK_MAX + * @brief Maximum value of block-based index register. + * @{ + */ +#define MXC_F_MPC_BLK_MAX_VAL_POS 0 /**< BLK_MAX_VAL Position */ +#define MXC_F_MPC_BLK_MAX_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_MAX_VAL_POS)) /**< BLK_MAX_VAL Mask */ + +/**@} end of group MPC_BLK_MAX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_CFG MPC_BLK_CFG + * @brief Block Control Register. + * @{ + */ +#define MXC_F_MPC_BLK_CFG_SIZE_POS 0 /**< BLK_CFG_SIZE Position */ +#define MXC_F_MPC_BLK_CFG_SIZE ((uint32_t)(0xFUL << MXC_F_MPC_BLK_CFG_SIZE_POS)) /**< BLK_CFG_SIZE Mask */ + +#define MXC_F_MPC_BLK_CFG_INIT_ST_POS 31 /**< BLK_CFG_INIT_ST Position */ +#define MXC_F_MPC_BLK_CFG_INIT_ST ((uint32_t)(0x1UL << MXC_F_MPC_BLK_CFG_INIT_ST_POS)) /**< BLK_CFG_INIT_ST Mask */ + +/**@} end of group MPC_BLK_CFG_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_IDX MPC_BLK_IDX + * @brief Block Index Register. + * @{ + */ +#define MXC_F_MPC_BLK_IDX_IDX_POS 0 /**< BLK_IDX_IDX Position */ +#define MXC_F_MPC_BLK_IDX_IDX ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_IDX_IDX_POS)) /**< BLK_IDX_IDX Mask */ + +/**@} end of group MPC_BLK_IDX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_LUT MPC_BLK_LUT + * @brief Block-based gating Look Up Table Register. + * @{ + */ +#define MXC_F_MPC_BLK_LUT_ACCESS_POS 0 /**< BLK_LUT_ACCESS Position */ +#define MXC_F_MPC_BLK_LUT_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_LUT_ACCESS_POS)) /**< BLK_LUT_ACCESS Mask */ + +/**@} end of group MPC_BLK_LUT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_STAT MPC_INT_STAT + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ_POS 0 /**< INT_STAT_MPC_IRQ Position */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_STAT_MPC_IRQ_POS)) /**< INT_STAT_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_STAT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_CLEAR MPC_INT_CLEAR + * @brief Interrupt Clear Register. + * @{ + */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS 0 /**< INT_CLEAR_MPC_IRQ Position */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS)) /**< INT_CLEAR_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_CLEAR_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_EN MPC_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_MPC_INT_EN_MPC_IRQ_POS 0 /**< INT_EN_MPC_IRQ Position */ +#define MXC_F_MPC_INT_EN_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_EN_MPC_IRQ_POS)) /**< INT_EN_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_EN_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO1 MPC_INT_INFO1 + * @brief Interrupt Info 1 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO1_HADDR_POS 0 /**< INT_INFO1_HADDR Position */ +#define MXC_F_MPC_INT_INFO1_HADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_INT_INFO1_HADDR_POS)) /**< INT_INFO1_HADDR Mask */ + +/**@} end of group MPC_INT_INFO1_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO2 MPC_INT_INFO2 + * @brief Interrupt Info 2 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO2_HMASTER_POS 0 /**< INT_INFO2_HMASTER Position */ +#define MXC_F_MPC_INT_INFO2_HMASTER ((uint32_t)(0xFFFFUL << MXC_F_MPC_INT_INFO2_HMASTER_POS)) /**< INT_INFO2_HMASTER Mask */ + +#define MXC_F_MPC_INT_INFO2_HNONSEC_POS 16 /**< INT_INFO2_HNONSEC Position */ +#define MXC_F_MPC_INT_INFO2_HNONSEC ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_HNONSEC_POS)) /**< INT_INFO2_HNONSEC Mask */ + +#define MXC_F_MPC_INT_INFO2_CFG_NS_POS 17 /**< INT_INFO2_CFG_NS Position */ +#define MXC_F_MPC_INT_INFO2_CFG_NS ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_CFG_NS_POS)) /**< INT_INFO2_CFG_NS Mask */ + +/**@} end of group MPC_INT_INFO2_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_SET MPC_INT_SET + * @brief Interrupt Set Debug Register. + * @{ + */ +#define MXC_F_MPC_INT_SET_MPC_IRQ_POS 0 /**< INT_SET_MPC_IRQ Position */ +#define MXC_F_MPC_INT_SET_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_SET_MPC_IRQ_POS)) /**< INT_SET_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_SET_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h new file mode 100644 index 00000000..fd2b7bb1 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h @@ -0,0 +1,176 @@ +/** + * @file nspc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the NSPC Peripheral Module. + * @note This file is @generated. + * @ingroup nspc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup nspc + * @defgroup nspc_registers NSPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the NSPC Peripheral Module. + * @details Non-Secure Privilege Controller. + */ + +/** + * @ingroup nspc_registers + * Structure type to access the NSPC Registers. + */ +typedef struct { + __R uint32_t rsv_0x0_0x15f[88]; + __IO uint32_t apbpriv; /**< \b 0x0160: NSPC APBPRIV Register */ + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: NSPC AHBMPRIV Register */ +} mxc_nspc_regs_t; + +/* Register offsets for module NSPC */ +/** + * @ingroup nspc_registers + * @defgroup NSPC_Register_Offsets Register Offsets + * @brief NSPC Peripheral Register Offsets from the NSPC Base Peripheral Address. + * @{ + */ +#define MXC_R_NSPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from NSPC Base Address: 0x0160 */ +#define MXC_R_NSPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from NSPC Base Address: 0x0170 */ +/**@} end of group nspc_registers */ + +/** + * @ingroup nspc_registers + * @defgroup NSPC_APBPRIV NSPC_APBPRIV + * @brief APB Tartet Privileged/Non-privileged PPC Access Register. + * @{ + */ +#define MXC_F_NSPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ +#define MXC_F_NSPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_NSPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ +#define MXC_V_NSPC_APBPRIV_PERIPH_GCR ((uint32_t)0x1UL) /**< APBPRIV_PERIPH_GCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_GCR (MXC_V_NSPC_APBPRIV_PERIPH_GCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_SIR ((uint32_t)0x2UL) /**< APBPRIV_PERIPH_SIR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_SIR (MXC_V_NSPC_APBPRIV_PERIPH_SIR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SIR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_FCR ((uint32_t)0x4UL) /**< APBPRIV_PERIPH_FCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_FCR (MXC_V_NSPC_APBPRIV_PERIPH_FCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_FCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WDT ((uint32_t)0x8UL) /**< APBPRIV_PERIPH_WDT Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WDT (MXC_V_NSPC_APBPRIV_PERIPH_WDT << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WDT Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_AES ((uint32_t)0x10UL) /**< APBPRIV_PERIPH_AES Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_AES (MXC_V_NSPC_APBPRIV_PERIPH_AES << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AES Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBPRIV_PERIPH_AESKEYS Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_AESKEYS (MXC_V_NSPC_APBPRIV_PERIPH_AESKEYS << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AESKEYS Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_CRC ((uint32_t)0x40UL) /**< APBPRIV_PERIPH_CRC Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_CRC (MXC_V_NSPC_APBPRIV_PERIPH_CRC << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_CRC Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBPRIV_PERIPH_GPIO0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_GPIO0 (MXC_V_NSPC_APBPRIV_PERIPH_GPIO0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GPIO0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBPRIV_PERIPH_TMR0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR0 (MXC_V_NSPC_APBPRIV_PERIPH_TMR0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBPRIV_PERIPH_TMR1 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR1 (MXC_V_NSPC_APBPRIV_PERIPH_TMR1 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR1 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBPRIV_PERIPH_TMR2 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR2 (MXC_V_NSPC_APBPRIV_PERIPH_TMR2 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR2 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBPRIV_PERIPH_TMR3 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR3 (MXC_V_NSPC_APBPRIV_PERIPH_TMR3 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR3 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBPRIV_PERIPH_TMR4 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR4 (MXC_V_NSPC_APBPRIV_PERIPH_TMR4 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR4 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBPRIV_PERIPH_TMR5 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TMR5 (MXC_V_NSPC_APBPRIV_PERIPH_TMR5 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR5 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBPRIV_PERIPH_I3C Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_I3C (MXC_V_NSPC_APBPRIV_PERIPH_I3C << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_I3C Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_UART ((uint32_t)0x8000UL) /**< APBPRIV_PERIPH_UART Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_UART (MXC_V_NSPC_APBPRIV_PERIPH_UART << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_UART Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBPRIV_PERIPH_SPI Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_SPI (MXC_V_NSPC_APBPRIV_PERIPH_SPI << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SPI Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBPRIV_PERIPH_TRNG Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TRNG (MXC_V_NSPC_APBPRIV_PERIPH_TRNG << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRNG Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBPRIV_PERIPH_BTLE_DBB Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BTLE_DBB (MXC_V_NSPC_APBPRIV_PERIPH_BTLE_DBB << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_DBB Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBPRIV_PERIPH_BTLE_RFFE Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BTLE_RFFE (MXC_V_NSPC_APBPRIV_PERIPH_BTLE_RFFE << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBPRIV_PERIPH_RSTZ Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_RSTZ (MXC_V_NSPC_APBPRIV_PERIPH_RSTZ << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RSTZ Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBPRIV_PERIPH_BOOST Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_BOOST (MXC_V_NSPC_APBPRIV_PERIPH_BOOST << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BOOST Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBPRIV_PERIPH_TRIMSIR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_TRIMSIR (MXC_V_NSPC_APBPRIV_PERIPH_TRIMSIR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRIMSIR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBPRIV_PERIPH_RTC Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_RTC (MXC_V_NSPC_APBPRIV_PERIPH_RTC << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RTC Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBPRIV_PERIPH_WUT0 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WUT0 (MXC_V_NSPC_APBPRIV_PERIPH_WUT0 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT0 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBPRIV_PERIPH_WUT1 Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_WUT1 (MXC_V_NSPC_APBPRIV_PERIPH_WUT1 << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT1 Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBPRIV_PERIPH_PWRSEQ Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_PWRSEQ (MXC_V_NSPC_APBPRIV_PERIPH_PWRSEQ << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_PWRSEQ Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBPRIV_PERIPH_MCR Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_MCR (MXC_V_NSPC_APBPRIV_PERIPH_MCR << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_MCR Setting */ +#define MXC_V_NSPC_APBPRIV_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBPRIV_PERIPH_ALL Value */ +#define MXC_S_NSPC_APBPRIV_PERIPH_ALL (MXC_V_NSPC_APBPRIV_PERIPH_ALL << MXC_F_NSPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_ALL Setting */ + +/**@} end of group NSPC_APBPRIV_Register */ + +/** + * @ingroup nspc_registers + * @defgroup NSPC_AHBMPRIV NSPC_AHBMPRIV + * @brief AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + * @{ + */ +#define MXC_F_NSPC_AHBMPRIV_DMA_POS 1 /**< AHBMPRIV_DMA Position */ +#define MXC_F_NSPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_NSPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ + +/**@} end of group NSPC_AHBMPRIV_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h new file mode 100644 index 00000000..216ede9b --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -0,0 +1,165 @@ +/** + * @file pwrseq_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @note This file is @generated. + * @ingroup pwrseq_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pwrseq + * @defgroup pwrseq_registers PWRSEQ_Registers + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @details Power Sequencer / Low Power Control Register. + */ + +/** + * @ingroup pwrseq_registers + * Structure type to access the PWRSEQ Registers. + */ +typedef struct { + __IO uint32_t lpctrl; /**< \b 0x00: PWRSEQ LPCTRL Register */ + __IO uint32_t lpwkfl0; /**< \b 0x04: PWRSEQ LPWKFL0 Register */ + __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ + __R uint32_t rsv_0xc_0x2f[9]; + __IO uint32_t lppwst; /**< \b 0x30: PWRSEQ LPPWST Register */ + __R uint32_t rsv_0x34_0x47[5]; + __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ + __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ +} mxc_pwrseq_regs_t; + +/* Register offsets for module PWRSEQ */ +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_Register_Offsets Register Offsets + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @{ + */ +#define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ +#define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ +#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ +#define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ +#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ +#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ +/**@} end of group pwrseq_registers */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPCTRL PWRSEQ_LPCTRL + * @brief Low Power Control Register. + * @{ + */ +#define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS 0 /**< LPCTRL_SRAMRET_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN ((uint32_t)(0x1FUL << MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS)) /**< LPCTRL_SRAMRET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS 11 /**< LPCTRL_BG_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS)) /**< LPCTRL_BG_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_RETLDO_EN_POS 12 /**< LPCTRL_RETLDO_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_RETLDO_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETLDO_EN_POS)) /**< LPCTRL_RETLDO_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY_POS 13 /**< LPCTRL_LDO_EN_DLY Position */ +#define MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LDO_EN_DLY_POS)) /**< LPCTRL_LDO_EN_DLY Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS 31 /**< LPCTRL_LPWKFL_CLR Position */ +#define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS)) /**< LPCTRL_LPWKFL_CLR Mask */ + +/**@} end of group PWRSEQ_LPCTRL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKFL0 PWRSEQ_LPWKFL0 + * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power + * wakeup status for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKFL0_PINS_POS 0 /**< LPWKFL0_PINS Position */ +#define MXC_F_PWRSEQ_LPWKFL0_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKFL0_PINS_POS)) /**< LPWKFL0_PINS Mask */ + +/**@} end of group PWRSEQ_LPWKFL0_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 + * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup + * functionality for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKEN0_PINS_POS 0 /**< LPWKEN0_PINS Position */ +#define MXC_F_PWRSEQ_LPWKEN0_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKEN0_PINS_POS)) /**< LPWKEN0_PINS Mask */ + +/**@} end of group PWRSEQ_LPWKEN0_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST + * @brief Low Power Peripheral Wakeup Status Register. + * @{ + */ +#define MXC_F_PWRSEQ_LPPWST_BACKUP_POS 16 /**< LPPWST_BACKUP Position */ +#define MXC_F_PWRSEQ_LPPWST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) /**< LPPWST_BACKUP Mask */ + +#define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 /**< LPPWST_RESET Position */ +#define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) /**< LPPWST_RESET Mask */ + +/**@} end of group PWRSEQ_LPPWST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h new file mode 100644 index 00000000..5920d77a --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rstz_regs.h @@ -0,0 +1,169 @@ +/** + * @file rstz_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RSTZ Peripheral Module. + * @note This file is @generated. + * @ingroup rstz_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rstz + * @defgroup rstz_registers RSTZ_Registers + * @brief Registers, Bit Masks and Bit Positions for the RSTZ Peripheral Module. + * @details RSTZ Controller + */ + +/** + * @ingroup rstz_registers + * Structure type to access the RSTZ Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: RSTZ CTRL Register */ + __IO uint32_t boost_clkctrl; /**< \b 0x004: RSTZ BOOST_CLKCTRL Register */ + __R uint32_t rsv_0x8_0x27[8]; + __IO uint32_t status_ch[8]; /**< \b 0x028: RSTZ STATUS_CH Register */ +} mxc_rstz_regs_t; + +/* Register offsets for module RSTZ */ +/** + * @ingroup rstz_registers + * @defgroup RSTZ_Register_Offsets Register Offsets + * @brief RSTZ Peripheral Register Offsets from the RSTZ Base Peripheral Address. + * @{ + */ +#define MXC_R_RSTZ_CTRL ((uint32_t)0x00000000UL) /**< Offset from RSTZ Base Address: 0x0000 */ +#define MXC_R_RSTZ_BOOST_CLKCTRL ((uint32_t)0x00000004UL) /**< Offset from RSTZ Base Address: 0x0004 */ +#define MXC_R_RSTZ_STATUS_CH ((uint32_t)0x00000028UL) /**< Offset from RSTZ Base Address: 0x0028 */ +/**@} end of group rstz_registers */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_CTRL RSTZ_CTRL + * @brief RSTZ Control Register. + * @{ + */ +#define MXC_F_RSTZ_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_RSTZ_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_RSTZ_CTRL_SVC_EN_POS 1 /**< CTRL_SVC_EN Position */ +#define MXC_F_RSTZ_CTRL_SVC_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_SVC_EN_POS)) /**< CTRL_SVC_EN Mask */ + +#define MXC_F_RSTZ_CTRL_CH_SEL_POS 2 /**< CTRL_CH_SEL Position */ +#define MXC_F_RSTZ_CTRL_CH_SEL ((uint32_t)(0x7UL << MXC_F_RSTZ_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ + +#define MXC_F_RSTZ_CTRL_CAL_EN_POS 5 /**< CTRL_CAL_EN Position */ +#define MXC_F_RSTZ_CTRL_CAL_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_CAL_EN_POS)) /**< CTRL_CAL_EN Mask */ + +#define MXC_F_RSTZ_CTRL_DMEASURE_EN_POS 6 /**< CTRL_DMEASURE_EN Position */ +#define MXC_F_RSTZ_CTRL_DMEASURE_EN ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_DMEASURE_EN_POS)) /**< CTRL_DMEASURE_EN Mask */ + +#define MXC_F_RSTZ_CTRL_OFFTR_P_POS 7 /**< CTRL_OFFTR_P Position */ +#define MXC_F_RSTZ_CTRL_OFFTR_P ((uint32_t)(0x1FUL << MXC_F_RSTZ_CTRL_OFFTR_P_POS)) /**< CTRL_OFFTR_P Mask */ + +#define MXC_F_RSTZ_CTRL_OFFTR_N_POS 12 /**< CTRL_OFFTR_N Position */ +#define MXC_F_RSTZ_CTRL_OFFTR_N ((uint32_t)(0x1FUL << MXC_F_RSTZ_CTRL_OFFTR_N_POS)) /**< CTRL_OFFTR_N Mask */ + +#define MXC_F_RSTZ_CTRL_DOUT_POS 17 /**< CTRL_DOUT Position */ +#define MXC_F_RSTZ_CTRL_DOUT ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_DOUT_POS)) /**< CTRL_DOUT Mask */ + +#define MXC_F_RSTZ_CTRL_CAL_DOUT_POL_POS 18 /**< CTRL_CAL_DOUT_POL Position */ +#define MXC_F_RSTZ_CTRL_CAL_DOUT_POL ((uint32_t)(0x1UL << MXC_F_RSTZ_CTRL_CAL_DOUT_POL_POS)) /**< CTRL_CAL_DOUT_POL Mask */ + +#define MXC_F_RSTZ_CTRL_NUM_SAMP_POS 24 /**< CTRL_NUM_SAMP Position */ +#define MXC_F_RSTZ_CTRL_NUM_SAMP ((uint32_t)(0xFUL << MXC_F_RSTZ_CTRL_NUM_SAMP_POS)) /**< CTRL_NUM_SAMP Mask */ + +#define MXC_F_RSTZ_CTRL_TRIP_TOL_POS 28 /**< CTRL_TRIP_TOL Position */ +#define MXC_F_RSTZ_CTRL_TRIP_TOL ((uint32_t)(0xFUL << MXC_F_RSTZ_CTRL_TRIP_TOL_POS)) /**< CTRL_TRIP_TOL Mask */ + +/**@} end of group RSTZ_CTRL_Register */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_BOOST_CLKCTRL RSTZ_BOOST_CLKCTRL + * @brief Boost Clock Control Register. + * @{ + */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP_POS 0 /**< BOOST_CLKCTRL_EXIT_NUM_SAMP Position */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP ((uint32_t)(0x3UL << MXC_F_RSTZ_BOOST_CLKCTRL_EXIT_NUM_SAMP_POS)) /**< BOOST_CLKCTRL_EXIT_NUM_SAMP Mask */ + +#define MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL_POS 2 /**< BOOST_CLKCTRL_CH_SEL Position */ +#define MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL ((uint32_t)(0x7UL << MXC_F_RSTZ_BOOST_CLKCTRL_CH_SEL_POS)) /**< BOOST_CLKCTRL_CH_SEL Mask */ + +/**@} end of group RSTZ_BOOST_CLKCTRL_Register */ + +/** + * @ingroup rstz_registers + * @defgroup RSTZ_STATUS_CH RSTZ_STATUS_CH + * @brief Channel X Status Register. + * @{ + */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ_POS 0 /**< STATUS_CH_RSTZ Position */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_RSTZ_POS)) /**< STATUS_CH_RSTZ Mask */ + +#define MXC_F_RSTZ_STATUS_CH_DOUT_POS 1 /**< STATUS_CH_DOUT Position */ +#define MXC_F_RSTZ_STATUS_CH_DOUT ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_DOUT_POS)) /**< STATUS_CH_DOUT Mask */ + +#define MXC_F_RSTZ_STATUS_CH_RSTZ_FL_POS 31 /**< STATUS_CH_RSTZ_FL Position */ +#define MXC_F_RSTZ_STATUS_CH_RSTZ_FL ((uint32_t)(0x1UL << MXC_F_RSTZ_STATUS_CH_RSTZ_FL_POS)) /**< STATUS_CH_RSTZ_FL Mask */ + +/**@} end of group RSTZ_STATUS_CH_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RSTZ_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h new file mode 100644 index 00000000..f54cf7b4 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h @@ -0,0 +1,240 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @note This file is @generated. + * @ingroup rtc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t toda; /**< \b 0x08: RTC TODA Register */ + __IO uint32_t sseca; /**< \b 0x0C: RTC SSECA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ +#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ +#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ +#define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ +#define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ +#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ +#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ +#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SEC RTC_SEC + * @brief RTC Second Counter. This register contains the 32-bit second counter. + * @{ + */ +#define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ +#define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ + +/**@} end of group RTC_SEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ +#define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ +#define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TODA RTC_TODA + * @brief Time-of-day Alarm. + * @{ + */ +#define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ +#define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ + +/**@} end of group RTC_TODA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSECA RTC_SSECA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ +#define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ +#define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ + +/**@} end of group RTC_SSECA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ +#define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ + +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ + +#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ +#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + +#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ +#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +#define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ +#define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ + +#define MXC_F_RTC_CTRL_TOD_ALARM_IF_POS 6 /**< CTRL_TOD_ALARM_IF Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IF_POS)) /**< CTRL_TOD_ALARM_IF Mask */ + +#define MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS 7 /**< CTRL_SSEC_ALARM_IF Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS)) /**< CTRL_SSEC_ALARM_IF Mask */ + +#define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ +#define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ + +#define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ +#define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ + +#define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ +#define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ + +#define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ +#define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ +#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ +#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + +#define MXC_F_RTC_TRIM_VBAT_TMR_POS 8 /**< TRIM_VBAT_TMR Position */ +#define MXC_F_RTC_TRIM_VBAT_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBAT_TMR_POS)) /**< TRIM_VBAT_TMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ +#define MXC_F_RTC_OSCCTRL_FILTER_EN_POS 0 /**< OSCCTRL_FILTER_EN Position */ +#define MXC_F_RTC_OSCCTRL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FILTER_EN_POS)) /**< OSCCTRL_FILTER_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ + +#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ +#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ +#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + +#define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ +#define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h new file mode 100644 index 00000000..8be7861a --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -0,0 +1,166 @@ +/** + * @file sir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @note This file is @generated. + * @ingroup sir_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sir + * @defgroup sir_registers SIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @details System Initialization Registers. + */ + +/** + * @ingroup sir_registers + * Structure type to access the SIR Registers. + */ +typedef struct { + __I uint32_t sistat; /**< \b 0x000: SIR SISTAT Register */ + __I uint32_t addr; /**< \b 0x004: SIR ADDR Register */ + __R uint32_t rsv_0x8_0x1b[5]; + __IO uint32_t btleldo_bb; /**< \b 0x01C: SIR BTLELDO_BB Register */ + __R uint32_t rsv_0x20_0x2b[3]; + __IO uint32_t btleldo_rf; /**< \b 0x002C: SIR BTLELDO_RF Register */ + __R uint32_t rsv_0x30_0x103[53]; + __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ +} mxc_sir_regs_t; + +/* Register offsets for module SIR */ +/** + * @ingroup sir_registers + * @defgroup SIR_Register_Offsets Register Offsets + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @{ + */ +#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ +#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_BTLELDO_BB ((uint32_t)0x0000001CUL) /**< Offset from SIR Base Address: 0x001C */ +#define MXC_R_SIR_BTLELDO_RF ((uint32_t)0x0000002CUL) /**< Offset from SIR Base Address: 0x002C */ +#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ +/**@} end of group sir_registers */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SISTAT SIR_SISTAT + * @brief System Initialization Status Register. + * @{ + */ +#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ +#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ + +#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ +#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ + +/**@} end of group SIR_SISTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_ADDR SIR_ADDR + * @brief Read-only field set by the SIB block if a CRC error occurs during the read of + * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals + * 1). + * @{ + */ +#define MXC_F_SIR_ADDR_ERRADDR_POS 0 /**< ADDR_ERRADDR Position */ +#define MXC_F_SIR_ADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ERRADDR_POS)) /**< ADDR_ERRADDR Mask */ + +/**@} end of group SIR_ADDR_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_BB SIR_BTLELDO_BB + * @brief BTLE LDO TRIM BB Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_BB_TRIM_POS 0 /**< BTLELDO_BB_TRIM Position */ +#define MXC_F_SIR_BTLELDO_BB_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_BB_TRIM_POS)) /**< BTLELDO_BB_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_BB_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_RF SIR_BTLELDO_RF + * @brief BTLE LDO TRIM RF Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_RF_TRIM_POS 0 /**< BTLELDO_RF_TRIM Position */ +#define MXC_F_SIR_BTLELDO_RF_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_RF_TRIM_POS)) /**< BTLELDO_RF_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_RF_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SFSTAT SIR_SFSTAT + * @brief Security function status register. + * @{ + */ +#define MXC_F_SIR_SFSTAT_SECBOOT_EN_POS 0 /**< SFSTAT_SECBOOT_EN Position */ +#define MXC_F_SIR_SFSTAT_SECBOOT_EN ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_EN_POS)) /**< SFSTAT_SECBOOT_EN Mask */ + +#define MXC_F_SIR_SFSTAT_SECEXT_EN_POS 1 /**< SFSTAT_SECEXT_EN Position */ +#define MXC_F_SIR_SFSTAT_SECEXT_EN ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECEXT_EN_POS)) /**< SFSTAT_SECEXT_EN Mask */ + +/**@} end of group SIR_SFSTAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h new file mode 100644 index 00000000..69408b70 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h @@ -0,0 +1,430 @@ +/** + * @file spc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPC Peripheral Module. + * @note This file is @generated. + * @ingroup spc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spc + * @defgroup spc_registers SPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPC Peripheral Module. + * @details Secure Privilege Controller. + */ + +/** + * @ingroup spc_registers + * Structure type to access the SPC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: SPC CTRL Register */ + __R uint32_t rsv_0x4; + __IO uint32_t resp; /**< \b 0x0008: SPC RESP Register */ + __R uint32_t rsv_0xc_0x1f[5]; + __I uint8_t mpc_status; /**< \b 0x0020: SPC MPC_STATUS Register */ + __R uint8_t rsv_0x21_0x23[3]; + __IO uint32_t mpc_inten; /**< \b 0x0024: SPC MPC_INTEN Register */ + __R uint32_t rsv_0x28_0x2f[2]; + __I uint32_t ppc_status; /**< \b 0x0030: SPC PPC_STATUS Register */ + __O uint32_t ppc_intclr; /**< \b 0x0034: SPC PPC_INTCLR Register */ + __IO uint32_t ppc_inten; /**< \b 0x0038: SPC PPC_INTEN Register */ + __R uint32_t rsv_0x3c_0x7f[17]; + __IO uint32_t nscidau; /**< \b 0x0080: SPC NSCIDAU Register */ + __R uint32_t rsv_0x84_0x8f[3]; + __IO uint32_t m33lock; /**< \b 0x0090: SPC M33LOCK Register */ + __R uint32_t rsv_0x94_0x11f[35]; + __IO uint32_t apbsec; /**< \b 0x0120: SPC APBSEC Register */ + __R uint32_t rsv_0x124_0x15f[15]; + __IO uint32_t apbpriv; /**< \b 0x0160: SPC APBPRIV Register */ + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: SPC AHBMPRIV Register */ + __R uint32_t rsv_0x174_0x17f[3]; + __IO uint32_t gpio0; /**< \b 0x0180: SPC GPIO0 Register */ +} mxc_spc_regs_t; + +/* Register offsets for module SPC */ +/** + * @ingroup spc_registers + * @defgroup SPC_Register_Offsets Register Offsets + * @brief SPC Peripheral Register Offsets from the SPC Base Peripheral Address. + * @{ + */ +#define MXC_R_SPC_CTRL ((uint32_t)0x00000000UL) /**< Offset from SPC Base Address: 0x0000 */ +#define MXC_R_SPC_RESP ((uint32_t)0x00000008UL) /**< Offset from SPC Base Address: 0x0008 */ +#define MXC_R_SPC_MPC_STATUS ((uint32_t)0x00000020UL) /**< Offset from SPC Base Address: 0x0020 */ +#define MXC_R_SPC_MPC_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPC Base Address: 0x0024 */ +#define MXC_R_SPC_PPC_STATUS ((uint32_t)0x00000030UL) /**< Offset from SPC Base Address: 0x0030 */ +#define MXC_R_SPC_PPC_INTCLR ((uint32_t)0x00000034UL) /**< Offset from SPC Base Address: 0x0034 */ +#define MXC_R_SPC_PPC_INTEN ((uint32_t)0x00000038UL) /**< Offset from SPC Base Address: 0x0038 */ +#define MXC_R_SPC_NSCIDAU ((uint32_t)0x00000080UL) /**< Offset from SPC Base Address: 0x0080 */ +#define MXC_R_SPC_M33LOCK ((uint32_t)0x00000090UL) /**< Offset from SPC Base Address: 0x0090 */ +#define MXC_R_SPC_APBSEC ((uint32_t)0x00000120UL) /**< Offset from SPC Base Address: 0x0120 */ +#define MXC_R_SPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from SPC Base Address: 0x0160 */ +#define MXC_R_SPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from SPC Base Address: 0x0170 */ +#define MXC_R_SPC_GPIO0 ((uint32_t)0x00000180UL) /**< Offset from SPC Base Address: 0x0180 */ +/**@} end of group spc_registers */ + +/** + * @ingroup spc_registers + * @defgroup SPC_CTRL SPC_CTRL + * @brief SPC Secure Configuration Control Register. + * @{ + */ +#define MXC_F_SPC_CTRL_LOCK_POS 0 /**< CTRL_LOCK Position */ +#define MXC_F_SPC_CTRL_LOCK ((uint32_t)(0x1UL << MXC_F_SPC_CTRL_LOCK_POS)) /**< CTRL_LOCK Mask */ + +/**@} end of group SPC_CTRL_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_RESP SPC_RESP + * @brief Security Violation Response Configuration Register. + * @{ + */ +#define MXC_F_SPC_RESP_VIOLCFG_POS 0 /**< RESP_VIOLCFG Position */ +#define MXC_F_SPC_RESP_VIOLCFG ((uint32_t)(0x1UL << MXC_F_SPC_RESP_VIOLCFG_POS)) /**< RESP_VIOLCFG Mask */ + +/**@} end of group SPC_RESP_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_MPC_STATUS SPC_MPC_STATUS + * @brief Secure MPC Status Register. + * @{ + */ +#define MXC_F_SPC_MPC_STATUS_SRAM0_POS 0 /**< MPC_STATUS_SRAM0 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM0 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM0_POS)) /**< MPC_STATUS_SRAM0 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM1_POS 1 /**< MPC_STATUS_SRAM1 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM1 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM1_POS)) /**< MPC_STATUS_SRAM1 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM2_POS 2 /**< MPC_STATUS_SRAM2 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM2 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM2_POS)) /**< MPC_STATUS_SRAM2 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM3_POS 3 /**< MPC_STATUS_SRAM3 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM3 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM3_POS)) /**< MPC_STATUS_SRAM3 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM4_POS 4 /**< MPC_STATUS_SRAM4 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM4 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM4_POS)) /**< MPC_STATUS_SRAM4 Mask */ + +#define MXC_F_SPC_MPC_STATUS_FLASH_POS 5 /**< MPC_STATUS_FLASH Position */ +#define MXC_F_SPC_MPC_STATUS_FLASH ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_FLASH_POS)) /**< MPC_STATUS_FLASH Mask */ + +/**@} end of group SPC_MPC_STATUS_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_MPC_INTEN SPC_MPC_INTEN + * @brief Secure MPC Interrupt Enable Register. + * @{ + */ +#define MXC_F_SPC_MPC_INTEN_SRAM0_POS 0 /**< MPC_INTEN_SRAM0 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM0 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM0_POS)) /**< MPC_INTEN_SRAM0 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM1_POS 1 /**< MPC_INTEN_SRAM1 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM1 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM1_POS)) /**< MPC_INTEN_SRAM1 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM2_POS 2 /**< MPC_INTEN_SRAM2 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM2 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM2_POS)) /**< MPC_INTEN_SRAM2 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM3_POS 3 /**< MPC_INTEN_SRAM3 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM3 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM3_POS)) /**< MPC_INTEN_SRAM3 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM4_POS 4 /**< MPC_INTEN_SRAM4 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM4 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM4_POS)) /**< MPC_INTEN_SRAM4 Mask */ + +#define MXC_F_SPC_MPC_INTEN_FLASH_POS 5 /**< MPC_INTEN_FLASH Position */ +#define MXC_F_SPC_MPC_INTEN_FLASH ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_FLASH_POS)) /**< MPC_INTEN_FLASH Mask */ + +/**@} end of group SPC_MPC_INTEN_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_STATUS SPC_PPC_STATUS + * @brief Secure PPC Interrupt Status Register. + * @{ + */ +#define MXC_F_SPC_PPC_STATUS_APBPPC_POS 0 /**< PPC_STATUS_APBPPC Position */ +#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ + +/**@} end of group SPC_PPC_STATUS_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_INTCLR SPC_PPC_INTCLR + * @brief Secure PPC Interrupt Clear Register. + * @{ + */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC_POS 0 /**< PPC_INTCLR_APBPPC Position */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ + +/**@} end of group SPC_PPC_INTCLR_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_INTEN SPC_PPC_INTEN + * @brief Secure PPC Interrupt Enable Register. + * @{ + */ +#define MXC_F_SPC_PPC_INTEN_APBPPC_POS 0 /**< PPC_INTEN_APBPPC Position */ +#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ + +/**@} end of group SPC_PPC_INTEN_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_NSCIDAU SPC_NSCIDAU + * @brief Non-Secure Callabale IDAU Configuration Register. + * @{ + */ +#define MXC_F_SPC_NSCIDAU_CODE_POS 0 /**< NSCIDAU_CODE Position */ +#define MXC_F_SPC_NSCIDAU_CODE ((uint32_t)(0x1UL << MXC_F_SPC_NSCIDAU_CODE_POS)) /**< NSCIDAU_CODE Mask */ + +#define MXC_F_SPC_NSCIDAU_SRAM_POS 1 /**< NSCIDAU_SRAM Position */ +#define MXC_F_SPC_NSCIDAU_SRAM ((uint32_t)(0x1UL << MXC_F_SPC_NSCIDAU_SRAM_POS)) /**< NSCIDAU_SRAM Mask */ + +/**@} end of group SPC_NSCIDAU_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_M33LOCK SPC_M33LOCK + * @brief M33 Core Register Lock Configuratrion Register. + * @{ + */ +#define MXC_F_SPC_M33LOCK_AIRCR_VTOR_S_POS 0 /**< M33LOCK_AIRCR_VTOR_S Position */ +#define MXC_F_SPC_M33LOCK_AIRCR_VTOR_S ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_AIRCR_VTOR_S_POS)) /**< M33LOCK_AIRCR_VTOR_S Mask */ + +#define MXC_F_SPC_M33LOCK_VTOR_NS_POS 1 /**< M33LOCK_VTOR_NS Position */ +#define MXC_F_SPC_M33LOCK_VTOR_NS ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_VTOR_NS_POS)) /**< M33LOCK_VTOR_NS Mask */ + +#define MXC_F_SPC_M33LOCK_MPU_S_POS 2 /**< M33LOCK_MPU_S Position */ +#define MXC_F_SPC_M33LOCK_MPU_S ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_MPU_S_POS)) /**< M33LOCK_MPU_S Mask */ + +#define MXC_F_SPC_M33LOCK_MPU_NS_POS 3 /**< M33LOCK_MPU_NS Position */ +#define MXC_F_SPC_M33LOCK_MPU_NS ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_MPU_NS_POS)) /**< M33LOCK_MPU_NS Mask */ + +#define MXC_F_SPC_M33LOCK_SAU_POS 4 /**< M33LOCK_SAU Position */ +#define MXC_F_SPC_M33LOCK_SAU ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_SAU_POS)) /**< M33LOCK_SAU Mask */ + +/**@} end of group SPC_M33LOCK_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_APBSEC SPC_APBSEC + * @brief APB Target Secure/Non-secure PPC Access Register. + * @{ + */ +#define MXC_F_SPC_APBSEC_PERIPH_POS 0 /**< APBSEC_PERIPH Position */ +#define MXC_F_SPC_APBSEC_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBSEC_PERIPH_POS)) /**< APBSEC_PERIPH Mask */ +#define MXC_V_SPC_APBSEC_PERIPH_GCR ((uint32_t)0x1UL) /**< APBSEC_PERIPH_GCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_GCR (MXC_V_SPC_APBSEC_PERIPH_GCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_GCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_SIR ((uint32_t)0x2UL) /**< APBSEC_PERIPH_SIR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_SIR (MXC_V_SPC_APBSEC_PERIPH_SIR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_SIR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_FCR ((uint32_t)0x4UL) /**< APBSEC_PERIPH_FCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_FCR (MXC_V_SPC_APBSEC_PERIPH_FCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_FCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WDT ((uint32_t)0x8UL) /**< APBSEC_PERIPH_WDT Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WDT (MXC_V_SPC_APBSEC_PERIPH_WDT << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WDT Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_AES ((uint32_t)0x10UL) /**< APBSEC_PERIPH_AES Value */ +#define MXC_S_SPC_APBSEC_PERIPH_AES (MXC_V_SPC_APBSEC_PERIPH_AES << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_AES Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBSEC_PERIPH_AESKEYS Value */ +#define MXC_S_SPC_APBSEC_PERIPH_AESKEYS (MXC_V_SPC_APBSEC_PERIPH_AESKEYS << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_AESKEYS Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_CRC ((uint32_t)0x40UL) /**< APBSEC_PERIPH_CRC Value */ +#define MXC_S_SPC_APBSEC_PERIPH_CRC (MXC_V_SPC_APBSEC_PERIPH_CRC << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_CRC Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBSEC_PERIPH_GPIO0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_GPIO0 (MXC_V_SPC_APBSEC_PERIPH_GPIO0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_GPIO0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBSEC_PERIPH_TMR0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR0 (MXC_V_SPC_APBSEC_PERIPH_TMR0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBSEC_PERIPH_TMR1 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR1 (MXC_V_SPC_APBSEC_PERIPH_TMR1 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR1 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBSEC_PERIPH_TMR2 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR2 (MXC_V_SPC_APBSEC_PERIPH_TMR2 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR2 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBSEC_PERIPH_TMR3 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR3 (MXC_V_SPC_APBSEC_PERIPH_TMR3 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR3 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBSEC_PERIPH_TMR4 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR4 (MXC_V_SPC_APBSEC_PERIPH_TMR4 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR4 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBSEC_PERIPH_TMR5 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TMR5 (MXC_V_SPC_APBSEC_PERIPH_TMR5 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TMR5 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBSEC_PERIPH_I3C Value */ +#define MXC_S_SPC_APBSEC_PERIPH_I3C (MXC_V_SPC_APBSEC_PERIPH_I3C << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_I3C Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_UART ((uint32_t)0x8000UL) /**< APBSEC_PERIPH_UART Value */ +#define MXC_S_SPC_APBSEC_PERIPH_UART (MXC_V_SPC_APBSEC_PERIPH_UART << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_UART Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBSEC_PERIPH_SPI Value */ +#define MXC_S_SPC_APBSEC_PERIPH_SPI (MXC_V_SPC_APBSEC_PERIPH_SPI << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_SPI Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBSEC_PERIPH_TRNG Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TRNG (MXC_V_SPC_APBSEC_PERIPH_TRNG << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TRNG Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBSEC_PERIPH_BTLE_DBB Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BTLE_DBB (MXC_V_SPC_APBSEC_PERIPH_BTLE_DBB << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BTLE_DBB Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBSEC_PERIPH_BTLE_RFFE Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BTLE_RFFE (MXC_V_SPC_APBSEC_PERIPH_BTLE_RFFE << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBSEC_PERIPH_RSTZ Value */ +#define MXC_S_SPC_APBSEC_PERIPH_RSTZ (MXC_V_SPC_APBSEC_PERIPH_RSTZ << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_RSTZ Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBSEC_PERIPH_BOOST Value */ +#define MXC_S_SPC_APBSEC_PERIPH_BOOST (MXC_V_SPC_APBSEC_PERIPH_BOOST << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_BOOST Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBSEC_PERIPH_TRIMSIR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_TRIMSIR (MXC_V_SPC_APBSEC_PERIPH_TRIMSIR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_TRIMSIR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBSEC_PERIPH_RTC Value */ +#define MXC_S_SPC_APBSEC_PERIPH_RTC (MXC_V_SPC_APBSEC_PERIPH_RTC << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_RTC Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBSEC_PERIPH_WUT0 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WUT0 (MXC_V_SPC_APBSEC_PERIPH_WUT0 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WUT0 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBSEC_PERIPH_WUT1 Value */ +#define MXC_S_SPC_APBSEC_PERIPH_WUT1 (MXC_V_SPC_APBSEC_PERIPH_WUT1 << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_WUT1 Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBSEC_PERIPH_PWRSEQ Value */ +#define MXC_S_SPC_APBSEC_PERIPH_PWRSEQ (MXC_V_SPC_APBSEC_PERIPH_PWRSEQ << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_PWRSEQ Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBSEC_PERIPH_MCR Value */ +#define MXC_S_SPC_APBSEC_PERIPH_MCR (MXC_V_SPC_APBSEC_PERIPH_MCR << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_MCR Setting */ +#define MXC_V_SPC_APBSEC_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBSEC_PERIPH_ALL Value */ +#define MXC_S_SPC_APBSEC_PERIPH_ALL (MXC_V_SPC_APBSEC_PERIPH_ALL << MXC_F_SPC_APBSEC_PERIPH_POS) /**< APBSEC_PERIPH_ALL Setting */ + +/**@} end of group SPC_APBSEC_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_APBPRIV SPC_APBPRIV + * @brief APB Tartet Privileged/Non-privileged PPC Access Register. + * @{ + */ +#define MXC_F_SPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ +#define MXC_F_SPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ +#define MXC_V_SPC_APBPRIV_PERIPH_GCR ((uint32_t)0x1UL) /**< APBPRIV_PERIPH_GCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_GCR (MXC_V_SPC_APBPRIV_PERIPH_GCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_SIR ((uint32_t)0x2UL) /**< APBPRIV_PERIPH_SIR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_SIR (MXC_V_SPC_APBPRIV_PERIPH_SIR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SIR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_FCR ((uint32_t)0x4UL) /**< APBPRIV_PERIPH_FCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_FCR (MXC_V_SPC_APBPRIV_PERIPH_FCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_FCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WDT ((uint32_t)0x8UL) /**< APBPRIV_PERIPH_WDT Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WDT (MXC_V_SPC_APBPRIV_PERIPH_WDT << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WDT Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_AES ((uint32_t)0x10UL) /**< APBPRIV_PERIPH_AES Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_AES (MXC_V_SPC_APBPRIV_PERIPH_AES << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AES Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_AESKEYS ((uint32_t)0x20UL) /**< APBPRIV_PERIPH_AESKEYS Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_AESKEYS (MXC_V_SPC_APBPRIV_PERIPH_AESKEYS << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_AESKEYS Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_CRC ((uint32_t)0x40UL) /**< APBPRIV_PERIPH_CRC Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_CRC (MXC_V_SPC_APBPRIV_PERIPH_CRC << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_CRC Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_GPIO0 ((uint32_t)0x80UL) /**< APBPRIV_PERIPH_GPIO0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_GPIO0 (MXC_V_SPC_APBPRIV_PERIPH_GPIO0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_GPIO0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR0 ((uint32_t)0x100UL) /**< APBPRIV_PERIPH_TMR0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR0 (MXC_V_SPC_APBPRIV_PERIPH_TMR0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR1 ((uint32_t)0x200UL) /**< APBPRIV_PERIPH_TMR1 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR1 (MXC_V_SPC_APBPRIV_PERIPH_TMR1 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR1 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR2 ((uint32_t)0x400UL) /**< APBPRIV_PERIPH_TMR2 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR2 (MXC_V_SPC_APBPRIV_PERIPH_TMR2 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR2 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR3 ((uint32_t)0x800UL) /**< APBPRIV_PERIPH_TMR3 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR3 (MXC_V_SPC_APBPRIV_PERIPH_TMR3 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR3 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR4 ((uint32_t)0x1000UL) /**< APBPRIV_PERIPH_TMR4 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR4 (MXC_V_SPC_APBPRIV_PERIPH_TMR4 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR4 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TMR5 ((uint32_t)0x2000UL) /**< APBPRIV_PERIPH_TMR5 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TMR5 (MXC_V_SPC_APBPRIV_PERIPH_TMR5 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TMR5 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_I3C ((uint32_t)0x4000UL) /**< APBPRIV_PERIPH_I3C Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_I3C (MXC_V_SPC_APBPRIV_PERIPH_I3C << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_I3C Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_UART ((uint32_t)0x8000UL) /**< APBPRIV_PERIPH_UART Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_UART (MXC_V_SPC_APBPRIV_PERIPH_UART << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_UART Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_SPI ((uint32_t)0x10000UL) /**< APBPRIV_PERIPH_SPI Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_SPI (MXC_V_SPC_APBPRIV_PERIPH_SPI << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_SPI Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TRNG ((uint32_t)0x20000UL) /**< APBPRIV_PERIPH_TRNG Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TRNG (MXC_V_SPC_APBPRIV_PERIPH_TRNG << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRNG Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BTLE_DBB ((uint32_t)0x40000UL) /**< APBPRIV_PERIPH_BTLE_DBB Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BTLE_DBB (MXC_V_SPC_APBPRIV_PERIPH_BTLE_DBB << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_DBB Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BTLE_RFFE ((uint32_t)0x80000UL) /**< APBPRIV_PERIPH_BTLE_RFFE Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BTLE_RFFE (MXC_V_SPC_APBPRIV_PERIPH_BTLE_RFFE << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BTLE_RFFE Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_RSTZ ((uint32_t)0x100000UL) /**< APBPRIV_PERIPH_RSTZ Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_RSTZ (MXC_V_SPC_APBPRIV_PERIPH_RSTZ << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RSTZ Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_BOOST ((uint32_t)0x200000UL) /**< APBPRIV_PERIPH_BOOST Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_BOOST (MXC_V_SPC_APBPRIV_PERIPH_BOOST << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_BOOST Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_TRIMSIR ((uint32_t)0x400000UL) /**< APBPRIV_PERIPH_TRIMSIR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_TRIMSIR (MXC_V_SPC_APBPRIV_PERIPH_TRIMSIR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_TRIMSIR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_RTC ((uint32_t)0x1000000UL) /**< APBPRIV_PERIPH_RTC Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_RTC (MXC_V_SPC_APBPRIV_PERIPH_RTC << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_RTC Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WUT0 ((uint32_t)0x2000000UL) /**< APBPRIV_PERIPH_WUT0 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WUT0 (MXC_V_SPC_APBPRIV_PERIPH_WUT0 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT0 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_WUT1 ((uint32_t)0x4000000UL) /**< APBPRIV_PERIPH_WUT1 Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_WUT1 (MXC_V_SPC_APBPRIV_PERIPH_WUT1 << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_WUT1 Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_PWRSEQ ((uint32_t)0x8000000UL) /**< APBPRIV_PERIPH_PWRSEQ Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_PWRSEQ (MXC_V_SPC_APBPRIV_PERIPH_PWRSEQ << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_PWRSEQ Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_MCR ((uint32_t)0x10000000UL) /**< APBPRIV_PERIPH_MCR Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_MCR (MXC_V_SPC_APBPRIV_PERIPH_MCR << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_MCR Setting */ +#define MXC_V_SPC_APBPRIV_PERIPH_ALL ((uint32_t)0x1F7FFFFFUL) /**< APBPRIV_PERIPH_ALL Value */ +#define MXC_S_SPC_APBPRIV_PERIPH_ALL (MXC_V_SPC_APBPRIV_PERIPH_ALL << MXC_F_SPC_APBPRIV_PERIPH_POS) /**< APBPRIV_PERIPH_ALL Setting */ + +/**@} end of group SPC_APBPRIV_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_AHBMPRIV SPC_AHBMPRIV + * @brief AHB Privileged/Non-privileged Secure DMA Access. + * @{ + */ +#define MXC_F_SPC_AHBMPRIV_DMA_POS 0 /**< AHBMPRIV_DMA Position */ +#define MXC_F_SPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_SPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ + +/**@} end of group SPC_AHBMPRIV_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_GPIO0 SPC_GPIO0 + * @brief Secure GPIO0 Configuration Register. + * @{ + */ +#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ +#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0x3FFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ + +/**@} end of group SPC_GPIO0_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h new file mode 100644 index 00000000..75860a7e --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -0,0 +1,501 @@ +/** + * @file spi_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @note This file is @generated. + * @ingroup spi_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi + * @defgroup spi_registers SPI_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi_registers + * Structure type to access the SPI Registers. + */ +typedef struct { + union { + __IO uint32_t fifo32; /**< \b 0x00: SPI FIFO32 Register */ + __IO uint16_t fifo16[2]; /**< \b 0x00: SPI FIFO16 Register */ + __IO uint8_t fifo8[4]; /**< \b 0x00: SPI FIFO8 Register */ + }; + __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ + __IO uint32_t tstime; /**< \b 0x10: SPI TSTIME Register */ + __IO uint32_t clkctrl; /**< \b 0x14: SPI CLKCTRL Register */ + __R uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ + __IO uint32_t intfl; /**< \b 0x20: SPI INTFL Register */ + __IO uint32_t inten; /**< \b 0x24: SPI INTEN Register */ + __IO uint32_t wkfl; /**< \b 0x28: SPI WKFL Register */ + __IO uint32_t wken; /**< \b 0x2C: SPI WKEN Register */ + __I uint32_t status; /**< \b 0x30: SPI STATUS Register */ +} mxc_spi_regs_t; + +/* Register offsets for module SPI */ +/** + * @ingroup spi_registers + * @defgroup SPI_Register_Offsets Register Offsets + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @{ + */ +#define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ +#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ +#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ +#define MXC_R_SPI_TSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ +#define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ +#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ +#define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ +#define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ +#define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ +#define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ +#define MXC_R_SPI_STATUS ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +/**@} end of group spi_registers */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO32 SPI_FIFO32 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ +#define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ + +/**@} end of group SPI_FIFO32_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO16 SPI_FIFO16 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ +#define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ + +/**@} end of group SPI_FIFO16_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO8 SPI_FIFO8 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ +#define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ + +/**@} end of group SPI_FIFO8_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL0 SPI_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ +#define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ + +#define MXC_F_SPI_CTRL0_CONT_MODE_POS 1 /**< CTRL0_CONT_MODE Position */ +#define MXC_F_SPI_CTRL0_CONT_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CONT_MODE_POS)) /**< CTRL0_CONT_MODE Mask */ + +#define MXC_F_SPI_CTRL0_TS_IO_POS 4 /**< CTRL0_TS_IO Position */ +#define MXC_F_SPI_CTRL0_TS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_IO_POS)) /**< CTRL0_TS_IO Mask */ + +#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ +#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ + +#define MXC_F_SPI_CTRL0_TS_CTRL_POS 8 /**< CTRL0_TS_CTRL Position */ +#define MXC_F_SPI_CTRL0_TS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_CTRL_POS)) /**< CTRL0_TS_CTRL Mask */ + +#define MXC_F_SPI_CTRL0_TS_ACTIVE_POS 16 /**< CTRL0_TS_ACTIVE Position */ +#define MXC_F_SPI_CTRL0_TS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_TS_ACTIVE_POS)) /**< CTRL0_TS_ACTIVE Mask */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS0 ((uint32_t)0x1UL) /**< CTRL0_TS_ACTIVE_TS0 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS0 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS0 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS0 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 ((uint32_t)0x2UL) /**< CTRL0_TS_ACTIVE_TS1 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS1 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_TS2 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS2 Setting */ + +/**@} end of group SPI_CTRL0_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL1 SPI_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI_CTRL1_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL2 SPI_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ +#define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ + +#define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ +#define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ + +#define MXC_F_SPI_CTRL2_SCLK_FB_INV_POS 4 /**< CTRL2_SCLK_FB_INV Position */ +#define MXC_F_SPI_CTRL2_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SCLK_FB_INV_POS)) /**< CTRL2_SCLK_FB_INV Mask */ + +#define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ +#define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ +#define MXC_V_SPI_CTRL2_NUMBITS_16 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_16 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_16 (MXC_V_SPI_CTRL2_NUMBITS_16 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_16 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_1 ((uint32_t)0x1UL) /**< CTRL2_NUMBITS_1 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_1 (MXC_V_SPI_CTRL2_NUMBITS_1 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_1 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_2 ((uint32_t)0x2UL) /**< CTRL2_NUMBITS_2 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_2 (MXC_V_SPI_CTRL2_NUMBITS_2 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_2 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_3 ((uint32_t)0x3UL) /**< CTRL2_NUMBITS_3 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_3 (MXC_V_SPI_CTRL2_NUMBITS_3 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_3 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_4 ((uint32_t)0x4UL) /**< CTRL2_NUMBITS_4 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_4 (MXC_V_SPI_CTRL2_NUMBITS_4 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_4 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_5 ((uint32_t)0x5UL) /**< CTRL2_NUMBITS_5 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_5 (MXC_V_SPI_CTRL2_NUMBITS_5 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_5 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_6 ((uint32_t)0x6UL) /**< CTRL2_NUMBITS_6 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_6 (MXC_V_SPI_CTRL2_NUMBITS_6 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_6 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_7 ((uint32_t)0x7UL) /**< CTRL2_NUMBITS_7 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_7 (MXC_V_SPI_CTRL2_NUMBITS_7 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_7 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_8 ((uint32_t)0x8UL) /**< CTRL2_NUMBITS_8 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_8 (MXC_V_SPI_CTRL2_NUMBITS_8 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_8 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_9 ((uint32_t)0x9UL) /**< CTRL2_NUMBITS_9 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_9 (MXC_V_SPI_CTRL2_NUMBITS_9 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_9 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_10 ((uint32_t)0xAUL) /**< CTRL2_NUMBITS_10 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_10 (MXC_V_SPI_CTRL2_NUMBITS_10 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_10 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_11 ((uint32_t)0xBUL) /**< CTRL2_NUMBITS_11 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_11 (MXC_V_SPI_CTRL2_NUMBITS_11 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_11 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_12 ((uint32_t)0xCUL) /**< CTRL2_NUMBITS_12 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_12 (MXC_V_SPI_CTRL2_NUMBITS_12 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_12 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_13 ((uint32_t)0xDUL) /**< CTRL2_NUMBITS_13 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_13 (MXC_V_SPI_CTRL2_NUMBITS_13 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_13 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_14 ((uint32_t)0xEUL) /**< CTRL2_NUMBITS_14 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_14 (MXC_V_SPI_CTRL2_NUMBITS_14 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_14 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_15 ((uint32_t)0xFUL) /**< CTRL2_NUMBITS_15 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_15 (MXC_V_SPI_CTRL2_NUMBITS_15 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_15 Setting */ + +#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + +#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ +#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + +#define MXC_F_SPI_CTRL2_TSPOL_POS 16 /**< CTRL2_TSPOL Position */ +#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0x7UL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */ +#define MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_TS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_TS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_TS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS2_HIGH Setting */ + +/**@} end of group SPI_CTRL2_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_TSTIME SPI_TSTIME + * @brief Register for controlling SPI peripheral/Target Select Timing. + * @{ + */ +#define MXC_F_SPI_TSTIME_PRE_POS 0 /**< TSTIME_PRE Position */ +#define MXC_F_SPI_TSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_PRE_POS)) /**< TSTIME_PRE Mask */ +#define MXC_V_SPI_TSTIME_PRE_256 ((uint32_t)0x0UL) /**< TSTIME_PRE_256 Value */ +#define MXC_S_SPI_TSTIME_PRE_256 (MXC_V_SPI_TSTIME_PRE_256 << MXC_F_SPI_TSTIME_PRE_POS) /**< TSTIME_PRE_256 Setting */ + +#define MXC_F_SPI_TSTIME_POST_POS 8 /**< TSTIME_POST Position */ +#define MXC_F_SPI_TSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_POST_POS)) /**< TSTIME_POST Mask */ +#define MXC_V_SPI_TSTIME_POST_256 ((uint32_t)0x0UL) /**< TSTIME_POST_256 Value */ +#define MXC_S_SPI_TSTIME_POST_256 (MXC_V_SPI_TSTIME_POST_256 << MXC_F_SPI_TSTIME_POST_POS) /**< TSTIME_POST_256 Setting */ + +#define MXC_F_SPI_TSTIME_INACT_POS 16 /**< TSTIME_INACT Position */ +#define MXC_F_SPI_TSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_INACT_POS)) /**< TSTIME_INACT Mask */ +#define MXC_V_SPI_TSTIME_INACT_256 ((uint32_t)0x0UL) /**< TSTIME_INACT_256 Value */ +#define MXC_S_SPI_TSTIME_INACT_256 (MXC_V_SPI_TSTIME_INACT_256 << MXC_F_SPI_TSTIME_INACT_POS) /**< TSTIME_INACT_256 Setting */ + +/**@} end of group SPI_TSTIME_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CLKCTRL SPI_CLKCTRL + * @brief Register for controlling SPI clock rate. + * @{ + */ +#define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ +#define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ +#define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ +#define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ + +#define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ +#define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ +#define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ +#define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ + +#define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ +#define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ + +/**@} end of group SPI_CLKCTRL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_DMA SPI_DMA + * @brief Register for controlling DMA. + * @{ + */ +#define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ + +#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + +#define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ +#define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ + +#define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ +#define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ + +#define MXC_F_SPI_DMA_TX_EN_POS 15 /**< DMA_TX_EN Position */ +#define MXC_F_SPI_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + +#define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ + +#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + +#define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ +#define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ + +#define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ +#define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ + +#define MXC_F_SPI_DMA_RX_EN_POS 31 /**< DMA_RX_EN Position */ +#define MXC_F_SPI_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group SPI_DMA_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTFL SPI_INTFL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ +#define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ +#define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ + +#define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ +#define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ + +#define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ +#define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ + +#define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ +#define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ + +#define MXC_F_SPI_INTFL_TSA_POS 4 /**< INTFL_TSA Position */ +#define MXC_F_SPI_INTFL_TSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TSA_POS)) /**< INTFL_TSA Mask */ + +#define MXC_F_SPI_INTFL_TSD_POS 5 /**< INTFL_TSD Position */ +#define MXC_F_SPI_INTFL_TSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TSD_POS)) /**< INTFL_TSD Mask */ + +#define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ +#define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ + +#define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ +#define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ + +#define MXC_F_SPI_INTFL_CONT_DONE_POS 11 /**< INTFL_CONT_DONE Position */ +#define MXC_F_SPI_INTFL_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CONT_DONE_POS)) /**< INTFL_CONT_DONE Mask */ + +#define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ +#define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ + +#define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ +#define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ + +#define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ +#define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ + +#define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ +#define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ + +/**@} end of group SPI_INTFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTEN SPI_INTEN + * @brief Register for enabling interrupts. + * @{ + */ +#define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ +#define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ + +#define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ +#define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ + +#define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ +#define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ + +#define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ +#define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ + +#define MXC_F_SPI_INTEN_TSA_POS 4 /**< INTEN_TSA Position */ +#define MXC_F_SPI_INTEN_TSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TSA_POS)) /**< INTEN_TSA Mask */ + +#define MXC_F_SPI_INTEN_TSD_POS 5 /**< INTEN_TSD Position */ +#define MXC_F_SPI_INTEN_TSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TSD_POS)) /**< INTEN_TSD Mask */ + +#define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ +#define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ + +#define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ +#define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ + +#define MXC_F_SPI_INTEN_CONT_DONE_POS 11 /**< INTEN_CONT_DONE Position */ +#define MXC_F_SPI_INTEN_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CONT_DONE_POS)) /**< INTEN_CONT_DONE Mask */ + +#define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ +#define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ + +#define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ +#define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ + +#define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ +#define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ + +#define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ +#define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ + +/**@} end of group SPI_INTEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKFL SPI_WKFL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ +#define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ +#define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ + +#define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ +#define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ + +#define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ + +#define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ +#define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ + +/**@} end of group SPI_WKFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKEN SPI_WKEN + * @brief Register for wake up enable. + * @{ + */ +#define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ +#define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ + +#define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ +#define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ + +#define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ + +#define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ +#define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ + +/**@} end of group SPI_WKEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_STATUS SPI_STATUS + * @brief SPI Status register. + * @{ + */ +#define MXC_F_SPI_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_SPI_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +/**@} end of group SPI_STATUS_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h new file mode 100644 index 00000000..0a086a13 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -0,0 +1,109 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ +#ifndef EXTCLK_FREQ +#define EXTCLK_FREQ 75000000 +#endif + +/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. + Update if use of this oscillator requires precise timing.*/ +/* NOTE: INRO was previously named NANORING */ +#ifndef INRO_FREQ +#define INRO_FREQ 100000 +#endif + +#ifndef IPO_FREQ +#define IPO_FREQ 50000000 +#endif + +#ifndef ERFO_FREQ +#define ERFO_FREQ 32000000 +#endif + +#ifndef IBRO_FREQ +#define IBRO_FREQ 7372800 +#endif + +#ifndef ERTCO_FREQ +#define ERTCO_FREQ 32768 +#endif + +#ifndef HIRC_FREQ +#define HIRC_FREQ IPO_FREQ +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifdef PeripheralClock +#warning PeripheralClock define is being overidden. +#else +#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ +#endif + +/* + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/* + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * @brief This function is called in Secure code just before control + * is transferred to non-secure world. Only available when + * trustzone feature is used. + * + * You may over-ride this function in your program by defining a custom + * NonSecure_Init(), but care should be taken to reproduce the initialization + * steps to non-secure code. + * + * Caller must be aware of configuring MPC, SPC, and NSPC before this + * function is called. + * + * @return Should not return if successful. If Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int NonSecure_Init(void); +#endif + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h new file mode 100644 index 00000000..61b8e57c --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -0,0 +1,430 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @note This file is @generated. + * @ingroup tmr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details Low-Power Configurable Timer + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intfl; /**< \b 0x0C: TMR INTFL Register */ + __IO uint32_t ctrl0; /**< \b 0x10: TMR CTRL0 Register */ + __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ + __IO uint32_t ctrl1; /**< \b 0x18: TMR CTRL1 Register */ + __IO uint32_t wkfl; /**< \b 0x1C: TMR WKFL Register */ +} mxc_tmr_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ +#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ +#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ +#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ +#define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ +#define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +#define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: 0x0018 */ +#define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: 0x001C */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CNT TMR_CNT + * @brief Timer Counter Register. + * @{ + */ +#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group TMR_CNT_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CMP TMR_CMP + * @brief Timer Compare Register. + * @{ + */ +#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ + +/**@} end of group TMR_CMP_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_PWM TMR_PWM + * @brief Timer PWM Register. + * @{ + */ +#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ +#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ + +/**@} end of group TMR_PWM_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTFL TMR_INTFL + * @brief Timer Interrupt Status Register. + * @{ + */ +#define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ +#define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ +#define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ +#define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ + +#define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ +#define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ +#define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ +#define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ + +/**@} end of group TMR_INTFL_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL0 TMR_CTRL0 + * @brief Timer Control Register. + * @{ + */ +#define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ +#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ +#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ +#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ + +#define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ +#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ +#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ +#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ + +#define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ +#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ +#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ +#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ + +#define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ +#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ +#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ +#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ + +/**@} end of group TMR_CTRL0_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_NOLCMP TMR_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ +#define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ +#define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ + +#define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ +#define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ + +#define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ +#define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ + +#define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ +#define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ + +/**@} end of group TMR_NOLCMP_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL1 TMR_CTRL1 + * @brief Timer Configuration Register. + * @{ + */ +#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ +#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ + +#define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ +#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ + +#define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ +#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ +#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ + +#define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ +#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ + +#define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ +#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ + +#define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ +#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ + +/**@} end of group TMR_CTRL1_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_WKFL TMR_WKFL + * @brief Timer Wakeup Status Register. + * @{ + */ +#define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ +#define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ + +#define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ +#define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ + +/**@} end of group TMR_WKFL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h new file mode 100644 index 00000000..63a2682e --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -0,0 +1,118 @@ +/** + * @file trimsir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. + * @note This file is @generated. + * @ingroup trimsir_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup trimsir + * @defgroup trimsir_registers TRIMSIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. + * @details Trim System Initilazation Registers. + */ + +/** + * @ingroup trimsir_registers + * Structure type to access the TRIMSIR Registers. + */ +typedef struct { + __R uint32_t rsv_0x0_0x3b[15]; + __IO uint32_t rtcx1; /**< \b 0x3C: TRIMSIR RTCX1 Register */ + __R uint32_t rsv_0x40; + __IO uint32_t rtcx2; /**< \b 0x44: TRIMSIR RTCX2 Register */ +} mxc_trimsir_regs_t; + +/* Register offsets for module TRIMSIR */ +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_Register_Offsets Register Offsets + * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. + * @{ + */ +#define MXC_R_TRIMSIR_RTCX1 ((uint32_t)0x0000003CUL) /**< Offset from TRIMSIR Base Address: 0x003C */ +#define MXC_R_TRIMSIR_RTCX2 ((uint32_t)0x00000044UL) /**< Offset from TRIMSIR Base Address: 0x0044 */ +/**@} end of group trimsir_registers */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_RTCX1 TRIMSIR_RTCX1 + * @brief RTC X1 Capacitor Setting. + * @{ + */ +#define MXC_F_TRIMSIR_RTCX1_CAP_POS 0 /**< RTCX1_CAP Position */ +#define MXC_F_TRIMSIR_RTCX1_CAP ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTCX1_CAP_POS)) /**< RTCX1_CAP Mask */ + +/**@} end of group TRIMSIR_RTCX1_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_RTCX2 TRIMSIR_RTCX2 + * @brief RTC X2 Capacitor Setting. + * @{ + */ +#define MXC_F_TRIMSIR_RTCX2_CAP_POS 0 /**< RTCX2_CAP Position */ +#define MXC_F_TRIMSIR_RTCX2_CAP ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTCX2_CAP_POS)) /**< RTCX2_CAP Mask */ + +/**@} end of group TRIMSIR_RTCX2_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h new file mode 100644 index 00000000..362dd355 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h @@ -0,0 +1,265 @@ +/** + * @file trng_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. + * @note This file is @generated. + * @ingroup trng_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup trng + * @defgroup trng_registers TRNG_Registers + * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. + * @details Random Number Generator. + */ + +/** + * @ingroup trng_registers + * Structure type to access the TRNG Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: TRNG CTRL Register */ + __IO uint32_t status; /**< \b 0x04: TRNG STATUS Register */ + __I uint32_t data; /**< \b 0x08: TRNG DATA Register */ + __R uint32_t rsv_0xc_0x37[11]; + __IO uint32_t data_nist; /**< \b 0x38: TRNG DATA_NIST Register */ +} mxc_trng_regs_t; + +/* Register offsets for module TRNG */ +/** + * @ingroup trng_registers + * @defgroup TRNG_Register_Offsets Register Offsets + * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. + * @{ + */ +#define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ +#define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ +#define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ +#define MXC_R_TRNG_DATA_NIST ((uint32_t)0x00000038UL) /**< Offset from TRNG Base Address: 0x0038 */ +/**@} end of group trng_registers */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_CTRL TRNG_CTRL + * @brief TRNG Control Register. + * @{ + */ +#define MXC_F_TRNG_CTRL_OD_HEALTH_POS 0 /**< CTRL_OD_HEALTH Position */ +#define MXC_F_TRNG_CTRL_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_HEALTH_POS)) /**< CTRL_OD_HEALTH Mask */ + +#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ +#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ + +#define MXC_F_TRNG_CTRL_HEALTH_IE_POS 2 /**< CTRL_HEALTH_IE Position */ +#define MXC_F_TRNG_CTRL_HEALTH_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_IE_POS)) /**< CTRL_HEALTH_IE Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEU_POS 3 /**< CTRL_AESKG_MEU Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEU ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEU_POS)) /**< CTRL_AESKG_MEU Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP_POS 4 /**< CTRL_AESKG_MEMPROT_XIP Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP_POS)) /**< CTRL_AESKG_MEMPROT_XIP Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP_POS 5 /**< CTRL_AESKG_MEMPROT_DIP Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP_POS)) /**< CTRL_AESKG_MEMPROT_DIP Mask */ + +#define MXC_F_TRNG_CTRL_OD_ROMON_POS 6 /**< CTRL_OD_ROMON Position */ +#define MXC_F_TRNG_CTRL_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_ROMON_POS)) /**< CTRL_OD_ROMON Mask */ + +#define MXC_F_TRNG_CTRL_OD_EE_POS 7 /**< CTRL_OD_EE Position */ +#define MXC_F_TRNG_CTRL_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_EE_POS)) /**< CTRL_OD_EE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS 8 /**< CTRL_ROMON_EE_FOE Position */ +#define MXC_F_TRNG_CTRL_ROMON_EE_FOE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS)) /**< CTRL_ROMON_EE_FOE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS 9 /**< CTRL_ROMON_EE_FOD Position */ +#define MXC_F_TRNG_CTRL_ROMON_EE_FOD ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS)) /**< CTRL_ROMON_EE_FOD Mask */ + +#define MXC_F_TRNG_CTRL_EBLS_POS 10 /**< CTRL_EBLS Position */ +#define MXC_F_TRNG_CTRL_EBLS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EBLS_POS)) /**< CTRL_EBLS Mask */ + +#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ +#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ + +#define MXC_F_TRNG_CTRL_GET_TERO_CNT_POS 16 /**< CTRL_GET_TERO_CNT Position */ +#define MXC_F_TRNG_CTRL_GET_TERO_CNT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_GET_TERO_CNT_POS)) /**< CTRL_GET_TERO_CNT Mask */ + +#define MXC_F_TRNG_CTRL_EE_DONE_IE_POS 23 /**< CTRL_EE_DONE_IE Position */ +#define MXC_F_TRNG_CTRL_EE_DONE_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EE_DONE_IE_POS)) /**< CTRL_EE_DONE_IE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_DIS_POS 24 /**< CTRL_ROMON_DIS Position */ +#define MXC_F_TRNG_CTRL_ROMON_DIS ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIS_POS)) /**< CTRL_ROMON_DIS Mask */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIS_RO_0 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_0 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIS_RO_1 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_1 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 ((uint32_t)0x4UL) /**< CTRL_ROMON_DIS_RO_2 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_2 Setting */ + +#define MXC_F_TRNG_CTRL_ROMON_DIV2_POS 28 /**< CTRL_ROMON_DIV2 Position */ +#define MXC_F_TRNG_CTRL_ROMON_DIV2 ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIV2_POS)) /**< CTRL_ROMON_DIV2 Mask */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_0 ((uint32_t)0x0UL) /**< CTRL_ROMON_DIV2_RO_0 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_0 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_1 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIV2_RO_1 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_1 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_2 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIV2_RO_2 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_2 Setting */ + +/**@} end of group TRNG_CTRL_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_STATUS TRNG_STATUS + * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is + * disabled, read returns 0x0000 0000. + * @{ + */ +#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ +#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ + +#define MXC_F_TRNG_STATUS_OD_HEALTH_POS 1 /**< STATUS_OD_HEALTH Position */ +#define MXC_F_TRNG_STATUS_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_HEALTH_POS)) /**< STATUS_OD_HEALTH Mask */ + +#define MXC_F_TRNG_STATUS_HEALTH_POS 2 /**< STATUS_HEALTH Position */ +#define MXC_F_TRNG_STATUS_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_POS)) /**< STATUS_HEALTH Mask */ + +#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ +#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ + +#define MXC_F_TRNG_STATUS_AES_KEYGEN_POS 4 /**< STATUS_AES_KEYGEN Position */ +#define MXC_F_TRNG_STATUS_AES_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AES_KEYGEN_POS)) /**< STATUS_AES_KEYGEN Mask */ + +#define MXC_F_TRNG_STATUS_OD_ROMON_POS 6 /**< STATUS_OD_ROMON Position */ +#define MXC_F_TRNG_STATUS_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_ROMON_POS)) /**< STATUS_OD_ROMON Mask */ + +#define MXC_F_TRNG_STATUS_OD_EE_POS 7 /**< STATUS_OD_EE Position */ +#define MXC_F_TRNG_STATUS_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_EE_POS)) /**< STATUS_OD_EE Mask */ + +#define MXC_F_TRNG_STATUS_PP_ERR_POS 8 /**< STATUS_PP_ERR Position */ +#define MXC_F_TRNG_STATUS_PP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_PP_ERR_POS)) /**< STATUS_PP_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_0_ERR_POS 9 /**< STATUS_ROMON_0_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_0_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_0_ERR_POS)) /**< STATUS_ROMON_0_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_1_ERR_POS 10 /**< STATUS_ROMON_1_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_1_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_1_ERR_POS)) /**< STATUS_ROMON_1_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_2_ERR_POS 11 /**< STATUS_ROMON_2_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_2_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_2_ERR_POS)) /**< STATUS_ROMON_2_ERR Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_THR_POS 12 /**< STATUS_EE_ERR_THR Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_THR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_THR_POS)) /**< STATUS_EE_ERR_THR Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_OOB_POS 13 /**< STATUS_EE_ERR_OOB Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_OOB ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_OOB_POS)) /**< STATUS_EE_ERR_OOB Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS 14 /**< STATUS_EE_ERR_LOCK Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_LOCK ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS)) /**< STATUS_EE_ERR_LOCK Mask */ + +#define MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS 16 /**< STATUS_TERO_CNT_RDY Position */ +#define MXC_F_TRNG_STATUS_TERO_CNT_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS)) /**< STATUS_TERO_CNT_RDY Mask */ + +#define MXC_F_TRNG_STATUS_RC_ERR_POS 17 /**< STATUS_RC_ERR Position */ +#define MXC_F_TRNG_STATUS_RC_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RC_ERR_POS)) /**< STATUS_RC_ERR Mask */ + +#define MXC_F_TRNG_STATUS_AP_ERR_POS 18 /**< STATUS_AP_ERR Position */ +#define MXC_F_TRNG_STATUS_AP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AP_ERR_POS)) /**< STATUS_AP_ERR Mask */ + +#define MXC_F_TRNG_STATUS_DATA_DONE_POS 19 /**< STATUS_DATA_DONE Position */ +#define MXC_F_TRNG_STATUS_DATA_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_DONE_POS)) /**< STATUS_DATA_DONE Mask */ + +#define MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS 20 /**< STATUS_DATA_NIST_DONE Position */ +#define MXC_F_TRNG_STATUS_DATA_NIST_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS)) /**< STATUS_DATA_NIST_DONE Mask */ + +#define MXC_F_TRNG_STATUS_HEALTH_DONE_POS 21 /**< STATUS_HEALTH_DONE Position */ +#define MXC_F_TRNG_STATUS_HEALTH_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_DONE_POS)) /**< STATUS_HEALTH_DONE Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_DONE_POS 22 /**< STATUS_ROMON_DONE Position */ +#define MXC_F_TRNG_STATUS_ROMON_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_DONE_POS)) /**< STATUS_ROMON_DONE Mask */ + +#define MXC_F_TRNG_STATUS_EE_DONE_POS 23 /**< STATUS_EE_DONE Position */ +#define MXC_F_TRNG_STATUS_EE_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_DONE_POS)) /**< STATUS_EE_DONE Mask */ + +/**@} end of group TRNG_STATUS_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_DATA TRNG_DATA + * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is + * disabled, read returns 0x0000 0000. + * @{ + */ +#define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group TRNG_DATA_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_DATA_NIST TRNG_DATA_NIST + * @brief Data NIST Register. + * @{ + */ +#define MXC_F_TRNG_DATA_NIST_DATA_POS 0 /**< DATA_NIST_DATA Position */ +#define MXC_F_TRNG_DATA_NIST_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_NIST_DATA_POS)) /**< DATA_NIST_DATA Mask */ + +/**@} end of group TRNG_DATA_NIST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h new file mode 100644 index 00000000..831c2a57 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -0,0 +1,391 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @note This file is @generated. + * @ingroup uart_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART Low Power Registers + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: UART CTRL Register */ + __I uint32_t status; /**< \b 0x0004: UART STATUS Register */ + __IO uint32_t inten; /**< \b 0x0008: UART INTEN Register */ + __IO uint32_t intfl; /**< \b 0x000C: UART INTFL Register */ + __IO uint32_t clkdiv; /**< \b 0x0010: UART CLKDIV Register */ + __IO uint32_t osr; /**< \b 0x0014: UART OSR Register */ + __IO uint32_t txpeek; /**< \b 0x0018: UART TXPEEK Register */ + __IO uint32_t pin; /**< \b 0x001C: UART PIN Register */ + __IO uint32_t fifo; /**< \b 0x0020: UART FIFO Register */ + __R uint32_t rsv_0x24_0x2f[3]; + __IO uint32_t dma; /**< \b 0x0030: UART DMA Register */ + __IO uint32_t wken; /**< \b 0x0034: UART WKEN Register */ + __IO uint32_t wkfl; /**< \b 0x0038: UART WKFL Register */ +} mxc_uart_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ +#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ +#define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ +#define MXC_R_UART_INTEN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ +#define MXC_R_UART_INTFL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ +#define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ +#define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ +#define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ +#define MXC_R_UART_PIN ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ +#define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ +#define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: 0x0030 */ +#define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: 0x0034 */ +#define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: 0x0038 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL UART_CTRL + * @brief Control register + * @{ + */ +#define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ +#define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ + +#define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ +#define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ + +#define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ +#define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ + +#define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ +#define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ + +#define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ +#define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ + +#define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ +#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + +#define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ +#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + +#define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ +#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ +#define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ + +#define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ +#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ + +#define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ +#define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ + +#define MXC_F_UART_CTRL_RTS_NEG_POS 14 /**< CTRL_RTS_NEG Position */ +#define MXC_F_UART_CTRL_RTS_NEG ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTS_NEG_POS)) /**< CTRL_RTS_NEG Mask */ + +#define MXC_F_UART_CTRL_CLK_EN_POS 15 /**< CTRL_CLK_EN Position */ +#define MXC_F_UART_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ + +#define MXC_F_UART_CTRL_CLK_SEL_POS 16 /**< CTRL_CLK_SEL Position */ +#define MXC_F_UART_CTRL_CLK_SEL ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CLK_SEL_POS)) /**< CTRL_CLK_SEL Mask */ +#define MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Value */ +#define MXC_S_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_CLK_SEL_CLK1 ((uint32_t)0x1UL) /**< CTRL_CLK_SEL_CLK1 Value */ +#define MXC_S_UART_CTRL_CLK_SEL_CLK1 (MXC_V_UART_CTRL_CLK_SEL_CLK1 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK1 Setting */ + +#define MXC_F_UART_CTRL_CLK_RDY_POS 19 /**< CTRL_CLK_RDY Position */ +#define MXC_F_UART_CTRL_CLK_RDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_RDY_POS)) /**< CTRL_CLK_RDY Mask */ + +#define MXC_F_UART_CTRL_CLK_GATE_POS 20 /**< CTRL_CLK_GATE Position */ +#define MXC_F_UART_CTRL_CLK_GATE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_GATE_POS)) /**< CTRL_CLK_GATE Mask */ + +/**@} end of group UART_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STATUS UART_STATUS + * @brief Status register + * @{ + */ +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + +#define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ +#define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ + +#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ +#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + +#define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ +#define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ + +#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ +#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + +#define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ +#define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ + +#define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ +#define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ + +/**@} end of group UART_STATUS_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INTEN UART_INTEN + * @brief Interrupt Enable control register + * @{ + */ +#define MXC_F_UART_INTEN_RX_FERR_POS 0 /**< INTEN_RX_FERR Position */ +#define MXC_F_UART_INTEN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FERR_POS)) /**< INTEN_RX_FERR Mask */ + +#define MXC_F_UART_INTEN_RX_PAR_POS 1 /**< INTEN_RX_PAR Position */ +#define MXC_F_UART_INTEN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_PAR_POS)) /**< INTEN_RX_PAR Mask */ + +#define MXC_F_UART_INTEN_CTS_EV_POS 2 /**< INTEN_CTS_EV Position */ +#define MXC_F_UART_INTEN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_CTS_EV_POS)) /**< INTEN_CTS_EV Mask */ + +#define MXC_F_UART_INTEN_RX_OV_POS 3 /**< INTEN_RX_OV Position */ +#define MXC_F_UART_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ + +#define MXC_F_UART_INTEN_RX_THD_POS 4 /**< INTEN_RX_THD Position */ +#define MXC_F_UART_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ + +#define MXC_F_UART_INTEN_TX_OB_POS 5 /**< INTEN_TX_OB Position */ +#define MXC_F_UART_INTEN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_OB_POS)) /**< INTEN_TX_OB Mask */ + +#define MXC_F_UART_INTEN_TX_THD_POS 6 /**< INTEN_TX_THD Position */ +#define MXC_F_UART_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ + +#define MXC_F_UART_INTEN_RX_FULL_POS 7 /**< INTEN_RX_FULL Position */ +#define MXC_F_UART_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ + +/**@} end of group UART_INTEN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INTFL UART_INTFL + * @brief Interrupt status flags Control register + * @{ + */ +#define MXC_F_UART_INTFL_RX_FERR_POS 0 /**< INTFL_RX_FERR Position */ +#define MXC_F_UART_INTFL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FERR_POS)) /**< INTFL_RX_FERR Mask */ + +#define MXC_F_UART_INTFL_RX_PAR_POS 1 /**< INTFL_RX_PAR Position */ +#define MXC_F_UART_INTFL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_PAR_POS)) /**< INTFL_RX_PAR Mask */ + +#define MXC_F_UART_INTFL_CTS_EV_POS 2 /**< INTFL_CTS_EV Position */ +#define MXC_F_UART_INTFL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_CTS_EV_POS)) /**< INTFL_CTS_EV Mask */ + +#define MXC_F_UART_INTFL_RX_OV_POS 3 /**< INTFL_RX_OV Position */ +#define MXC_F_UART_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ + +#define MXC_F_UART_INTFL_RX_THD_POS 4 /**< INTFL_RX_THD Position */ +#define MXC_F_UART_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ + +#define MXC_F_UART_INTFL_TX_OB_POS 5 /**< INTFL_TX_OB Position */ +#define MXC_F_UART_INTFL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_OB_POS)) /**< INTFL_TX_OB Mask */ + +#define MXC_F_UART_INTFL_TX_THD_POS 6 /**< INTFL_TX_THD Position */ +#define MXC_F_UART_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ + +#define MXC_F_UART_INTFL_RX_FULL_POS 7 /**< INTFL_RX_FULL Position */ +#define MXC_F_UART_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ + +/**@} end of group UART_INTFL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_CLKDIV UART_CLKDIV + * @brief Clock Divider register + * @{ + */ +#define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group UART_CLKDIV_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_OSR UART_OSR + * @brief Over Sampling Rate register + * @{ + */ +#define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ +#define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ + +/**@} end of group UART_OSR_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TXPEEK UART_TXPEEK + * @brief TX FIFO Output Peek register + * @{ + */ +#define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ +#define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ + +/**@} end of group UART_TXPEEK_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_PIN UART_PIN + * @brief Pin register + * @{ + */ +#define MXC_F_UART_PIN_CTS_POS 0 /**< PIN_CTS Position */ +#define MXC_F_UART_PIN_CTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_CTS_POS)) /**< PIN_CTS Mask */ + +#define MXC_F_UART_PIN_RTS_POS 1 /**< PIN_RTS Position */ +#define MXC_F_UART_PIN_RTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_RTS_POS)) /**< PIN_RTS Mask */ + +/**@} end of group UART_PIN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Read/Write register + * @{ + */ +#define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +#define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ +#define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration register + * @{ + */ +#define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ + +#define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ +#define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + +#define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ + +#define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ +#define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_WKEN UART_WKEN + * @brief Wake up enable Control register + * @{ + */ +#define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ +#define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ + +#define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ +#define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ + +#define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ + +/**@} end of group UART_WKEN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_WKFL UART_WKFL + * @brief Wake up Flags register + * @{ + */ +#define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ +#define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ + +#define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ +#define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ + +#define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ + +/**@} end of group UART_WKFL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h new file mode 100644 index 00000000..1e629961 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h @@ -0,0 +1,313 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @note This file is @generated. + * @ingroup wdt_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Windowed Watchdog Timer + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ + __IO uint32_t clksel; /**< \b 0x08: WDT CLKSEL Register */ + __I uint32_t cnt; /**< \b 0x0C: WDT CNT Register */ +} mxc_wdt_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ +#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ +#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +#define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: 0x0008 */ +#define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: 0x000C */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */ +#define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */ +#define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */ + +#define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */ +#define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */ + +#define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */ +#define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */ + +#define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */ +#define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */ + +#define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */ +#define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */ + +#define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */ +#define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */ + +#define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */ +#define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */ + +#define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */ +#define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */ + +#define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */ +#define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Windowed Watchdog Timer Reset Register. + * @{ + */ +#define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */ +#define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */ +#define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */ +#define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */ +#define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */ +#define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CLKSEL WDT_CLKSEL + * @brief Windowed Watchdog Timer Clock Select Register. + * @{ + */ +#define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */ +#define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */ + +/**@} end of group WDT_CLKSEL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CNT WDT_CNT + * @brief Windowed Watchdog Timer Count Register. + * @{ + */ +#define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group WDT_CNT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h new file mode 100644 index 00000000..37f3861f --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -0,0 +1,242 @@ +/** + * @file wut_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WUT Peripheral Module. + * @note This file is @generated. + * @ingroup wut_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wut + * @defgroup wut_registers WUT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WUT Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and wakeup. + */ + +/** + * @ingroup wut_registers + * Structure type to access the WUT Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: WUT CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: WUT CMP Register */ + __R uint32_t rsv_0x8; + __IO uint32_t intfl; /**< \b 0x0C: WUT INTFL Register */ + __IO uint32_t ctrl; /**< \b 0x10: WUT CTRL Register */ + __IO uint32_t nolcmp; /**< \b 0x14: WUT NOLCMP Register */ + __IO uint32_t preset; /**< \b 0x18: WUT PRESET Register */ + __IO uint32_t reload; /**< \b 0x1C: WUT RELOAD Register */ + __IO uint32_t snapshot; /**< \b 0x20: WUT SNAPSHOT Register */ +} mxc_wut_regs_t; + +/* Register offsets for module WUT */ +/** + * @ingroup wut_registers + * @defgroup WUT_Register_Offsets Register Offsets + * @brief WUT Peripheral Register Offsets from the WUT Base Peripheral Address. + * @{ + */ +#define MXC_R_WUT_CNT ((uint32_t)0x00000000UL) /**< Offset from WUT Base Address: 0x0000 */ +#define MXC_R_WUT_CMP ((uint32_t)0x00000004UL) /**< Offset from WUT Base Address: 0x0004 */ +#define MXC_R_WUT_INTFL ((uint32_t)0x0000000CUL) /**< Offset from WUT Base Address: 0x000C */ +#define MXC_R_WUT_CTRL ((uint32_t)0x00000010UL) /**< Offset from WUT Base Address: 0x0010 */ +#define MXC_R_WUT_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from WUT Base Address: 0x0014 */ +#define MXC_R_WUT_PRESET ((uint32_t)0x00000018UL) /**< Offset from WUT Base Address: 0x0018 */ +#define MXC_R_WUT_RELOAD ((uint32_t)0x0000001CUL) /**< Offset from WUT Base Address: 0x001C */ +#define MXC_R_WUT_SNAPSHOT ((uint32_t)0x00000020UL) /**< Offset from WUT Base Address: 0x0020 */ +/**@} end of group wut_registers */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CNT WUT_CNT + * @brief Count. This register stores the current timer count. + * @{ + */ +#define MXC_F_WUT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_WUT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group WUT_CNT_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CMP WUT_CMP + * @brief Compare. This register stores the compare value, which is used to set the + * maximum count value to initiate a reload of the timer to 0x0001. + * @{ + */ +#define MXC_F_WUT_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_WUT_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ + +/**@} end of group WUT_CMP_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_INTFL WUT_INTFL + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ +#define MXC_F_WUT_INTFL_CLR_POS 0 /**< INTFL_CLR Position */ +#define MXC_F_WUT_INTFL_CLR ((uint32_t)(0x1UL << MXC_F_WUT_INTFL_CLR_POS)) /**< INTFL_CLR Mask */ + +/**@} end of group WUT_INTFL_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CTRL WUT_CTRL + * @brief Timer Control Register. + * @{ + */ +#define MXC_F_WUT_CTRL_TMODE_POS 0 /**< CTRL_TMODE Position */ +#define MXC_F_WUT_CTRL_TMODE ((uint32_t)(0x7UL << MXC_F_WUT_CTRL_TMODE_POS)) /**< CTRL_TMODE Mask */ +#define MXC_V_WUT_CTRL_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_TMODE_ONESHOT Value */ +#define MXC_S_WUT_CTRL_TMODE_ONESHOT (MXC_V_WUT_CTRL_TMODE_ONESHOT << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_ONESHOT Setting */ +#define MXC_V_WUT_CTRL_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_TMODE_CONTINUOUS Value */ +#define MXC_S_WUT_CTRL_TMODE_CONTINUOUS (MXC_V_WUT_CTRL_TMODE_CONTINUOUS << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CONTINUOUS Setting */ +#define MXC_V_WUT_CTRL_TMODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_TMODE_COUNTER Value */ +#define MXC_S_WUT_CTRL_TMODE_COUNTER (MXC_V_WUT_CTRL_TMODE_COUNTER << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_COUNTER Setting */ +#define MXC_V_WUT_CTRL_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_TMODE_CAPTURE Value */ +#define MXC_S_WUT_CTRL_TMODE_CAPTURE (MXC_V_WUT_CTRL_TMODE_CAPTURE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CAPTURE Setting */ +#define MXC_V_WUT_CTRL_TMODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_TMODE_COMPARE Value */ +#define MXC_S_WUT_CTRL_TMODE_COMPARE (MXC_V_WUT_CTRL_TMODE_COMPARE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_COMPARE Setting */ +#define MXC_V_WUT_CTRL_TMODE_GATED ((uint32_t)0x6UL) /**< CTRL_TMODE_GATED Value */ +#define MXC_S_WUT_CTRL_TMODE_GATED (MXC_V_WUT_CTRL_TMODE_GATED << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_GATED Setting */ +#define MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_TMODE_CAPTURECOMPARE Value */ +#define MXC_S_WUT_CTRL_TMODE_CAPTURECOMPARE (MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CAPTURECOMPARE Setting */ + +#define MXC_F_WUT_CTRL_PRES_POS 3 /**< CTRL_PRES Position */ +#define MXC_F_WUT_CTRL_PRES ((uint32_t)(0x7UL << MXC_F_WUT_CTRL_PRES_POS)) /**< CTRL_PRES Mask */ +#define MXC_V_WUT_CTRL_PRES_DIV1 ((uint32_t)0x0UL) /**< CTRL_PRES_DIV1 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV1 (MXC_V_WUT_CTRL_PRES_DIV1 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV1 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV2 ((uint32_t)0x1UL) /**< CTRL_PRES_DIV2 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV2 (MXC_V_WUT_CTRL_PRES_DIV2 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV2 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV4 ((uint32_t)0x2UL) /**< CTRL_PRES_DIV4 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV4 (MXC_V_WUT_CTRL_PRES_DIV4 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV4 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV8 ((uint32_t)0x3UL) /**< CTRL_PRES_DIV8 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV8 (MXC_V_WUT_CTRL_PRES_DIV8 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV8 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV16 ((uint32_t)0x4UL) /**< CTRL_PRES_DIV16 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV16 (MXC_V_WUT_CTRL_PRES_DIV16 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV16 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV32 ((uint32_t)0x5UL) /**< CTRL_PRES_DIV32 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV32 (MXC_V_WUT_CTRL_PRES_DIV32 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV32 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV64 ((uint32_t)0x6UL) /**< CTRL_PRES_DIV64 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV64 (MXC_V_WUT_CTRL_PRES_DIV64 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV64 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV128 ((uint32_t)0x7UL) /**< CTRL_PRES_DIV128 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV128 (MXC_V_WUT_CTRL_PRES_DIV128 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV128 Setting */ + +#define MXC_F_WUT_CTRL_TPOL_POS 6 /**< CTRL_TPOL Position */ +#define MXC_F_WUT_CTRL_TPOL ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_TPOL_POS)) /**< CTRL_TPOL Mask */ + +#define MXC_F_WUT_CTRL_TEN_POS 7 /**< CTRL_TEN Position */ +#define MXC_F_WUT_CTRL_TEN ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_TEN_POS)) /**< CTRL_TEN Mask */ + +#define MXC_F_WUT_CTRL_PRES3_POS 8 /**< CTRL_PRES3 Position */ +#define MXC_F_WUT_CTRL_PRES3 ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_PRES3_POS)) /**< CTRL_PRES3 Mask */ + +/**@} end of group WUT_CTRL_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_NOLCMP WUT_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ +#define MXC_F_WUT_NOLCMP_NOL_LO_POS 0 /**< NOLCMP_NOL_LO Position */ +#define MXC_F_WUT_NOLCMP_NOL_LO ((uint32_t)(0xFFUL << MXC_F_WUT_NOLCMP_NOL_LO_POS)) /**< NOLCMP_NOL_LO Mask */ + +#define MXC_F_WUT_NOLCMP_NOL_HI_POS 8 /**< NOLCMP_NOL_HI Position */ +#define MXC_F_WUT_NOLCMP_NOL_HI ((uint32_t)(0xFFUL << MXC_F_WUT_NOLCMP_NOL_HI_POS)) /**< NOLCMP_NOL_HI Mask */ + +/**@} end of group WUT_NOLCMP_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_PRESET WUT_PRESET + * @brief Preset register. + * @{ + */ +#define MXC_F_WUT_PRESET_PRESET_POS 0 /**< PRESET_PRESET Position */ +#define MXC_F_WUT_PRESET_PRESET ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_PRESET_PRESET_POS)) /**< PRESET_PRESET Mask */ + +/**@} end of group WUT_PRESET_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_RELOAD WUT_RELOAD + * @brief Reload register. + * @{ + */ +#define MXC_F_WUT_RELOAD_RELOAD_POS 0 /**< RELOAD_RELOAD Position */ +#define MXC_F_WUT_RELOAD_RELOAD ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_RELOAD_RELOAD_POS)) /**< RELOAD_RELOAD Mask */ + +/**@} end of group WUT_RELOAD_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_SNAPSHOT WUT_SNAPSHOT + * @brief Snapshot register. + * @{ + */ +#define MXC_F_WUT_SNAPSHOT_SNAPSHOT_POS 0 /**< SNAPSHOT_SNAPSHOT Position */ +#define MXC_F_WUT_SNAPSHOT_SNAPSHOT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_SNAPSHOT_SNAPSHOT_POS)) /**< SNAPSHOT_SNAPSHOT Mask */ + +/**@} end of group WUT_SNAPSHOT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_ns.ld b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_ns.ld new file mode 100644 index 00000000..5df3d4c9 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_ns.ld @@ -0,0 +1,164 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * 1MB Total Physical Flash Size + * 256KB Total Physical SRAM Size + * - SRAM0 (32KB) + * - SRAM1 (32KB) + * - SRAM2 (64KB) + * - SRAM3 (64KB) + * - SRAM4 (64KB) + */ + +ENTRY(Reset_Handler) + +MEMORY { + FLASH (rx) : ORIGIN = $FLASH_ORIGIN_NS$, LENGTH = $FLASH_SIZE_NS$ /* User-selected Non-Secure Flash settings */ + SRAM (rwx) : ORIGIN = $SRAM_ORIGIN_NS$, LENGTH = $SRAM_SIZE_NS$ /* User-selected Non-Secure SRAM settings */ +} + +SECTIONS { + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* Program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + .flash_code : + { + . = ALIGN(16); + _flash_code = .; + *(.flash_code_section) + _eflash_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sram_code = .; + *(.sram_code_section) + _esram_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.flashprog*) /* Flash program */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + _ebss = ALIGN(., 4); + } > SRAM + + /** + * Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section. + */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /** + * .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later. + */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_s.ld b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_s.ld new file mode 100644 index 00000000..9814e0c3 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/max32657_s.ld @@ -0,0 +1,199 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * 1MB Total Physical Flash Size + * 256KB Total Physical SRAM Size + * - SRAM0 (32KB) + * - SRAM1 (32KB) + * - SRAM2 (64KB) + * - SRAM3 (64KB) + * - SRAM4 (64KB) + */ + +MEMORY { + FLASH (rx) : ORIGIN = $FLASH_ORIGIN_S$, LENGTH = $FLASH_SIZE_S$ /* User-selected Secure Flash */ + FLASH_NS (rx) : ORIGIN = $FLASH_ORIGIN_NS$, LENGTH = $FLASH_SIZE_NS$ /* User-selected Non-Secure Flash */ + SRAM (rwx) : ORIGIN = $SRAM_ORIGIN_S$, LENGTH = $SRAM_SIZE_S$ /* User-selected Secure SRAM */ + SRAM_NS (rwx) : ORIGIN = $SRAM_ORIGIN_NS$, LENGTH = $SRAM_SIZE_NS$ /* User-selected Non-Secure SRAM */ + + NSC_REGION $perm$ : ORIGIN = $MEM_ORIGIN_NSC$, LENGTH = $MEM_SIZE_NSC$ /* User-selected Non-Secure Callable Region */ +} + +SECTIONS { + .nonsecure_flash : + { + /* Non-Secure Code must be aligned with this memory's block size. */ + _nonsecure_start = ALIGN(., $MPC_BLOCK_SIZE$); + KEEP(*nonsecure.o) /* Non-Secure program code */ + _nonsecure_end = ALIGN(., $MPC_BLOCK_SIZE$) - 1; /* -1 for last accessible address, not start of next block */ + } > $CODE_MEM_TYPE$_NS + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + *(.text*) /* Program code */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > $CODE_MEM_TYPE$ + + /* + * Secure Gatway (SG) veneers. + * All SG veneers are placed in the special output section .gnu.sgstubs. + * Must be placed in Non-Secure Callable Region. + */ + .gnu.sgstubs : + { + _sg_veneers = .; + *(.gnu.sgstubs*) + _esg_veneers = .; + } > NSC_REGION + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > $CODE_MEM_TYPE$ + + .flash_code : + { + . = ALIGN(16); + _flash_code = .; + *(.flash_code_section) + _eflash_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sram_code = .; + *(.sram_code_section) + _esram_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > $CODE_MEM_TYPE$ + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /* read-write initialized data: initialized global variable */ + *(.flashprog*) /* Flash program */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>$CODE_MEM_TYPE$ + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /* read-write zero initialized data: uninitialzed global variable */ + _ebss = ALIGN(., 4); + } > SRAM + + /** + * Stack Seal section is required for secure builds. Stack sealing protects + * secure stack from illegal access by non-secure code. + */ + .stackseal (COPY): + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > SRAM + + /** + * Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section. + */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /** + * .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later. + */ + .stack_dummy (COPY): + { + KEEP(*(.stack*)) + KEEP(*(.stackseal*)) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/partition_max32657.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/partition_max32657.h new file mode 100644 index 00000000..09095504 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/Template/partition_max32657.h @@ -0,0 +1,1298 @@ +/***************************************************************************** + * @file partition_max32657.h + * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for + * MAX32657 + * @version V1.0.0 + * @date 20. January 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_TEMPLATE_PARTITION_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_TEMPLATE_PARTITION_MAX32657_H_ + +#include "mxc_device.h" + +// clang-format off +#if CONFIG_TRUSTED_EXECUTION_SECURE + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +/** + * Analog Devices, Inc. + * 4 Memory Spaces in the MAX32657. + * 1. Non-Secure Flash + * 2. Secure Flash + * 3. Non-Secure SRAM + * 4. Secure SRAM + * + * Finer grain control can be achieved depending on the application + * requirements by updating the regions of this file. + * + * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF + * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF + * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF + * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF + * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF + * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF + * + * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF + * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF + * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF + * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF + * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF + * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF + * + * Note: The total physical space for Flash is 1MB, and SRAM is 256KB. + * The total size between the non-secure and secure Flash regions + * should be 1MB. + * The total size between the non-secure and secure SRAM regions + * should be 256KB. + * - By default, this file sets the following regions: + * Secure Flash (504KB): 0x1100.0000 - 0x1107.DFFF + * Non-Secure Callable Flash (8KB): 0x1107.E000 - 0x1107.FFFF + * Non-Secure Flash (512KB): 0x0108.0000 - 0x010F.FFFF + * Secure SRAM (0-2) (128KB): 0x3000.0000 - 0x3001.FFFF + * Non-Secure SRAM (3-4) (128KB): 0x2002.0000 - 0x2003.FFFF + */ +#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 (Secure Flash) +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 $FLASH_ORIGIN_S$ /* start address of SAU region 0 (ROM) */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 $FLASH_END_S$ /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 (Non-Secure Flash) +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 $FLASH_ORIGIN_NS$ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 $FLASH_END_NS$ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 (Secure SRAM (0-2)) +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 $SRAM_ORIGIN_S$ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 $SRAM_END_S$ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 (Non-Secure SRAM (3-4)) +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 $SRAM_ORIGIN_NS$ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 $SRAM_END_NS$ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 (Non-Secure SRAM) +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// ICE Unlock <0=> Secure state <1=> Non-Secure state +// Watchdog Timer <0=> Secure state <1=> Non-Secure state +// Real Time Clock <0=> Secure state <1=> Non-Secure state +// True Random Number Generator <0=> Secure state <1=> Non-Secure state +// Timer 0 <0=> Secure state <1=> Non-Secure state +// Timer 1 <0=> Secure state <1=> Non-Secure state +// Timer 2 <0=> Secure state <1=> Non-Secure state +// Timer 3 <0=> Secure state <1=> Non-Secure state +// Timer 4 <0=> Secure state <1=> Non-Secure state +// Timer 5 <0=> Secure state <1=> Non-Secure state +// I3C <0=> Secure state <1=> Non-Secure state +// UART <0=> Secure state <1=> Non-Secure state +// SPI <0=> Secure state <1=> Non-Secure state +// Flash Controller <0=> Secure state <1=> Non-Secure state +// GPIO0 <0=> Secure state <1=> Non-Secure state +// Reserved (15) <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state +// GPIO Wake <0=> Secure state <1=> Non-Secure state +// CRC <0=> Secure state <1=> Non-Secure state +// AES <0=> Secure state <1=> Non-Secure state +// ERFO Ready <0=> Secure state <1=> Non-Secure state +// Boost Controller <0=> Secure state <1=> Non-Secure state +// ECC <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state +// BTLE XXXXA <0=> Secure state <1=> Non-Secure state +// BTLE XXXXB <0=> Secure state <1=> Non-Secure state +// BTLE XXXXC <0=> Secure state <1=> Non-Secure state +// BTLE XXXXD <0=> Secure state <1=> Non-Secure state +// BTLE XXXXE <0=> Secure state <1=> Non-Secure state +// Reserved (47) <0=> Secure state <1=> Non-Secure state +// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// Reserved (50) <0=> Secure state <1=> Non-Secure state +// Reserved (51) <0=> Secure state <1=> Non-Secure state +// Reserved (52) <0=> Secure state <1=> Non-Secure state +// Reserved (53) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk); + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_TEMPLATE_PARTITION_MAX32657_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c new file mode 100644 index 00000000..80559e95 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include + +/* + sbrk + Increase program data space. + Malloc and related functions depend on this + */ +static char *heap_end = 0; +extern unsigned int __HeapBase; +extern unsigned int __HeapLimit; +caddr_t _sbrk(int incr) +{ + char *prev_heap_end; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + prev_heap_end = heap_end; + + if ((unsigned int)(heap_end + incr) > (unsigned int)&__HeapLimit) { + errno = ENOMEM; + return (caddr_t)-1; + } + + heap_end += incr; + + return (caddr_t)prev_heap_end; +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c new file mode 100644 index 00000000..813cc82b --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/***** Includes *****/ +#include +#include + +extern uint32_t _application_end; + +#define SLA_HEADER_MAGIC0 0xBF1421E4 +#define SLA_HEADER_MAGIC1 0x461A8CF5 +#define SLA_HEADER_VERSION 0x00000001 +#define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001 +#define SLA_HEADER_RESERVED 0x00000000 + +typedef struct { + uint32_t magic0; + uint32_t magic1; + uint32_t version; + uint32_t verifytype; + uint32_t sigaddress; + uint32_t reserved5; + uint32_t reserved6; + uint32_t reserved7; +} flash_app_header_t; + +__attribute__((section(".sla_header"))) __attribute__((__used__)) +const flash_app_header_t sla_header = { .magic0 = SLA_HEADER_MAGIC0, + .magic1 = SLA_HEADER_MAGIC1, + .version = SLA_HEADER_VERSION, + .verifytype = SLA_HEADER_ALGORITHM_ECDSA, + .sigaddress = (uint32_t)&_application_end, + .reserved5 = SLA_HEADER_RESERVED, + .reserved6 = SLA_HEADER_RESERVED, + .reserved7 = SLA_HEADER_RESERVED }; diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c new file mode 100644 index 00000000..5e24e6a3 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -0,0 +1,246 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include +#include "mxc_sys.h" +#include "mxc_errors.h" +#include "max32657.h" +#include "system_max32657.h" +#include "gcr_regs.h" +#include "mpc.h" + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include "partition_max32657.h" + +// From linker script. +extern uint32_t _nonsecure_start, _nonsecure_end; + +#define VECTOR_TABLE_START_ADDR_NS \ + (uint32_t)(&_nonsecure_start) // Now setting the start of the vector table using a linker symbol +#define MXC_Reset_Handler_NS (mxc_ns_call_t) * ((uint32_t *)(VECTOR_TABLE_START_ADDR_NS + 4)) +#define MXC_MSP_NS *((uint32_t *)(VECTOR_TABLE_START_ADDR_NS)) +#endif + +extern void (*const __isr_vector[])(void); + +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +/* + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. +*/ +__weak int _getpid(void) +{ + return E_NOT_SUPPORTED; +} + +__weak int _kill(void) +{ + return E_NOT_SUPPORTED; +} + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + base_freq = IPO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + base_freq = IBRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: + // base_freq = EXTCLK_FREQ; + // break; + // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; + } + + // Get the clock divider + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; + + SystemCoreClock = base_freq >> div; +} + +/** + * This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initialization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + /* Do nothing */ + return 0; +} + +/** + * This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + +/* This function can be implemented by the application to initialize the board */ +__weak int Board_Init(void) +{ + /* Do nothing */ + return 0; +} + +/** + * This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +__weak void SystemInit(void) +{ +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + SCB->VTOR = (uint32_t)__isr_vector; +#endif /* __VTOR_PRESENT check */ + +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + /** + * Enable Unaligned Access Trapping to throw an exception when there is an + * unaligned memory access while unaligned access support is disabled. + * + * Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Security Extension Features */ +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ + /* Set up secure and non-secure regions with SAU. */ + TZ_SAU_Setup(); +#endif /* TrustZone */ + + __DSB(); + __ISB(); + + /* Enable interrupts */ + __enable_irq(); + + // TODO(ICC): Enable the internal cache controller after testing. + // MXC_ICC_Enable(); + + /* Change system clock source to the main high-speed clock */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); + MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); + SystemCoreClockUpdate(); + + PinInit(); + Board_Init(); +} + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + * This function is called in Secure code just before control + * is transferred to non-secure world. Only available when + * trustzone feature is used. + * + * You may over-ride this function in your program by defining a custom + * NonSecure_Init(), but care should be taken to reproduce the initialization + * steps to non-secure code. + * + * Caller must be aware of configuring MPC, SPC, and NSPC before this + * function is called. + * + * Function should never return if successful. + */ +__weak int NonSecure_Init(void) +{ + int error; + mxc_ns_call_t Reset_Handler_NS; + + // Secure world must enable FPU for non-secure world. (Turned off by default). +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB_NS->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ + + // Setup Non-Secure vector table. + // Global symbols defined in Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/nonsecure_load.S + // indicates the beginning of the nonsecure image, which starts at the vector table. + SCB_NS->VTOR = VECTOR_TABLE_START_ADDR_NS; + + // Setup Non-Secure Main Stack Pointer (MSP_NS). + // Start of vector table contains top of stack value. + __TZ_set_MSP_NS(MXC_MSP_NS); + + // Get Non-Secure Reset_Handler. + Reset_Handler_NS = MXC_Reset_Handler_NS; + + // Set MPCs for Non-Secure region. + // (Not setting up Secure regions as, by default, MPC regions are set as secure on startup). + error = MXC_MPC_SetNonSecure((uint32_t)(&_nonsecure_start), (uint32_t)(&_nonsecure_end)); + if (error != E_NO_ERROR) { + return error; + } + + // Lock MPCs. + MXC_MPC_Lock(MXC_MPC_FLASH); + MXC_MPC_Lock(MXC_MPC_SRAM0); + MXC_MPC_Lock(MXC_MPC_SRAM1); + MXC_MPC_Lock(MXC_MPC_SRAM2); + MXC_MPC_Lock(MXC_MPC_SRAM3); + MXC_MPC_Lock(MXC_MPC_SRAM4); + + // Start Non-Secure code. + Reset_Handler_NS(); + + // Should not reach here if switching to non-secure world was successful. + return E_FAIL; +} +#endif diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index d409ce7b..024c30fe 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -142,6 +153,7 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/header_MAX32662.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/sla_header_MAX32662.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/header_MAX32662.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/sla_header_MAX32662.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c index c5587db6..89c35233 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c @@ -120,6 +120,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -160,6 +171,7 @@ __weak void SystemInit(void) MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); SystemCoreClockUpdate(); + PinInit(); Board_Init(); __enable_irq(); diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h index 630c490b..5e11de9b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/dma_regs.h @@ -88,7 +88,7 @@ typedef struct { __IO uint32_t cn; /**< \b 0x000: DMA CN Register */ __I uint32_t intr; /**< \b 0x004: DMA INTR Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[8]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h index 712a0c64..54d1e0cc 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.h @@ -21,6 +21,8 @@ #ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ #define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_MAX32665_H_ +// clang-format off + #ifndef TARGET_NUM #define TARGET_NUM 32665 #endif @@ -178,15 +180,16 @@ typedef enum { /* ================================================================================ */ /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */ -#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ -#define __MPU_PRESENT 1 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ -#include /*!< Cortex-M4 processor and core peripherals */ +#include /*!< Cortex-M4 processor and core peripherals */ -#include "system_max32665.h" /*!< System Header */ +#include "system_max32665.h" /*!< System Header */ +#include "system_core1_max32665.h" /*!< System Header for Core 1 */ /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd index ff0bf637..8f1abdaf 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd @@ -4335,13 +4335,13 @@ - LDORXBYPENENDLY + LDOTXBYPENENDLY LDOTX Bypass Enable Delay 14 1 - LDOTXBYPENENDLY + LDORXBYPENENDLY LDORX Bypass Enable Delay 15 1 diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h new file mode 100644 index 00000000..a206d719 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/system_core1_max32665.h @@ -0,0 +1,59 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * @brief Start Core 1 code. + */ +void Start_Core1(void); + +/** + * @brief Stops Core 1 by disabling CPU1 clock. + */ +void Stop_Core1(void); + +/** + * @brief Main function for Core 1 Code. + * The user should override this function in their application code. + */ +int main_core1(void); + +/** + * @brief Equivalent to PreInit for Core 0, + * Can be used for preliminary initialization. + */ +void PreInit_Core1(void); + +/** + * @brief Initialize the system for Core 1. + */ +void SystemInit_Core1(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32665_INCLUDE_SYSTEM_CORE1_MAX32665_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c index 80559e95..4409f35a 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/header_MAX32665.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/sla_header_MAX32665.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/header_MAX32665.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/sla_header_MAX32665.c diff --git a/MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c similarity index 54% rename from MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c index f1cbd38b..74a277be 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CORE1/system_core1.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_core1_max32665.c @@ -18,64 +18,66 @@ * ******************************************************************************/ -/** - * @file core1startup.c - * @brief Startup Code for MAX32665 Family CPU1 - * @details These functions are called at the startup of the second ARM core (CPU1/Core1) - */ #include #include #include -#include "max32665.h" +#include "mxc_device.h" #include "mxc_sys.h" #include "gcr_regs.h" -#include "icc_regs.h" -#include "pwrseq_regs.h" -extern uint32_t __isr_vector_core1; +extern void (*const __isr_vector_core1[])(void); -void Core1_Start(void) +void Start_Core1(void) { - MXC_GCR->gp0 = (uint32_t)(&__isr_vector_core1); + // Save Core 1 vector table location in GCR. + MXC_GCR->gp0 = (uint32_t)&__isr_vector_core1; MXC_GCR->perckcn1 &= ~MXC_F_GCR_PERCKCN1_CPU1D; } -void Core1_Stop(void) +void Stop_Core1(void) { MXC_GCR->perckcn1 |= MXC_F_GCR_PERCKCN1_CPU1D; } -__weak int Core1_Main(void) +/** + * The user declares this in application code. + */ +__weak int main_core1(void) { - // The user should declare this in application code, so we'll just spin while (1) {} } + +/** + * You may over-ride this function in your program by defining a custom + * PreInit_Core1(). + */ __weak void PreInit_Core1(void) { return; } +/** + * This function is called just before control is transferred to main() + * on Core 1. + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ __weak void SystemInit_Core1(void) { - /* Configure the interrupt controller to use the application vector table in - * the application space */ + /** + * Configure the interrupt controller to use the application vector + * table in flash. Initially, VTOR points to the ROM's table. + */ SCB->VTOR = (uint32_t)&__isr_vector_core1; - /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 - * Grant full access, per "Table B3-24 CPACR bit assignments". - * DDI0403D "ARMv7-M Architecture Reference Manual" */ + /** + * Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 + * Grant full access, per "Table B3-24 CPACR bit assignments". + * DDI0403D "ARMv7-M Architecture Reference Manual" + */ SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); - - // Enable ICache1 Clock - MXC_GCR->perckcn1 &= ~(1 << 22); - - // Invalidate cache and wait until ready - MXC_ICC1->invalidate = 1; - while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} - - // Enable Cache - MXC_ICC1->cache_ctrl |= MXC_F_ICC_CACHE_CTRL_EN; - while (!(MXC_ICC1->cache_ctrl & MXC_F_ICC_CACHE_CTRL_RDY)) {} } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c index 314414cd..2729e992 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c @@ -120,6 +120,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + // This function can be implemented by the application to initialize the board __weak int Board_Init(void) { @@ -191,6 +202,7 @@ __weak void SystemInit(void) /* Disable fast wakeup due to issues with SIMO in wakeup */ MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FWKM; + PinInit(); Board_Init(); PalSysInit(); diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h index b50a0dc9..8d0db135 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Include/max32670.h @@ -197,7 +197,9 @@ typedef enum { #define MXC_FLASH0_MEM_BASE 0x10000000UL #define MXC_FLASH_MEM_BASE MXC_FLASH0_MEM_BASE #define MXC_FLASH_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_MEM_SIZE 0x00060000UL +#define MXC_FLASH_MEM_SIZE (0x00060000UL - MXC_FLASH_PAGE_SIZE) +// ^ Last page of flash is used by the bootloader and cannot be used by app code. +// Furthermore, it appears that using this page will brick the device... #define MXC_INFO0_MEM_BASE 0x10800000UL #define MXC_INFO_MEM_BASE MXC_INFO0_MEM_BASE #define MXC_INFO_MEM_SIZE 0x00004000UL diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c index 3580a656..b7951e51 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c @@ -102,6 +102,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -148,6 +159,7 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h index f4c0d699..604e6d57 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Include/max32672.h @@ -29,13 +29,6 @@ #include -// TODO(ADI): Remove below after grace period. Temporarily added these includes to resolve errors -// for grace period before eventually removing support for deprecated features. 10-24-2022 -//>>> -#include "trimsir_regs.h" -#include "aes_regs.h" -//<<< - #ifndef FALSE #define FALSE (0) #endif @@ -314,10 +307,6 @@ typedef enum { #define MXC_BASE_AES ((uint32_t)0x40207400UL) #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES) -// DEPRECATED(10-24-2022): Scheduled for removal. -typedef __attribute__((deprecated( - "Use MXC_AES (mxc_aes_regs_t), not the deprecated MXC_SYS_AES (mxc_sys_aes_regs_t) instance name and struct. 10-24-2022"))) -mxc_aes_regs_t mxc_sys_aes_regs_t; #define MXC_SYS_AES ((mxc_sys_aes_regs_t *)MXC_BASE_AES) /******************************************************************************/ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/header_MAX32672.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/sla_header_MAX32672.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/header_MAX32672.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/sla_header_MAX32672.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c index f6250d24..67a1c371 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c @@ -115,6 +115,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -154,5 +165,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h index a07dac44..76639b86 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/afe_adc_zero_regs.h @@ -563,7 +563,7 @@ extern "C" { * @{ */ #define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS 0 /**< PART_ID_REV_ID Position */ -#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x7UL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ +#define MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID ((uint32_t)(0x3FUL << MXC_F_AFE_ADC_ZERO_PART_ID_REV_ID_POS)) /**< PART_ID_REV_ID Mask */ /**@} end of group AFE_ADC_ZERO_PART_ID_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.h index 4f9cd5d3..29b9dfa2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Include/max32675.h @@ -121,7 +121,7 @@ typedef enum { RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ - RSV54_IRQn, /* 0x46 0x0118 70: Reserved */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIOWAKE */ RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ RSV56_IRQn, /* 0x48 0x0120 72: Reserved */ WDT1_IRQn, /* 0x49 0x0124 73: Watchdog 1 */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c index d652ade0..ce9f218b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c @@ -117,6 +117,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -153,13 +164,16 @@ __weak void SystemInit(void) __DSB(); __ISB(); - /* Change system clock source to the main high-speed clock */ - MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); - SystemCoreClockUpdate(); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + /* Various revisions of the MAX32675 have different startup frequencies. + Calling SystemCoreClockUpdate will examine the part's registers to + determine the correct initial value for the SystemCoreClock variable. + */ + SystemCoreClockUpdate(); + + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c index 8b325fad..b3395119 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c @@ -101,6 +101,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -143,6 +154,7 @@ __weak void SystemInit(void) MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); + PinInit(); Board_Init(); PalSysInit(); diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c index 80559e95..4409f35a 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/heap.c @@ -21,6 +21,7 @@ #include #include #include +#include /* sbrk @@ -48,3 +49,79 @@ caddr_t _sbrk(int incr) return (caddr_t)prev_heap_end; } + +// struct mallinfo { +// size_t arena; /* total space allocated from system */ +// size_t ordblks; /* number of non-inuse chunks */ +// size_t smblks; /* unused -- always zero */ +// size_t hblks; /* number of mmapped regions */ +// size_t hblkhd; /* total space in mmapped regions */ +// size_t usmblks; /* unused -- always zero */ +// size_t fsmblks; /* unused -- always zero */ +// size_t uordblks; /* total allocated space */ +// size_t fordblks; /* total non-inuse space */ +// size_t keepcost; /* top-most, releasable (via malloc_trim) space */ +// }; + +/* +The structure fields contain the following information: + + arena The total amount of memory allocated by means other than + mmap(2) (i.e., memory allocated on the heap). This figure + includes both in-use blocks and blocks on the free list. + + ordblks + The number of ordinary (i.e., non-fastbin) free blocks. + + smblks The number of fastbin free blocks (see mallopt(3)). + + hblks The number of blocks currently allocated using mmap(2). + (See the discussion of M_MMAP_THRESHOLD in mallopt(3).) + + hblkhd The number of bytes in blocks currently allocated using + mmap(2). + + usmblks + This field is unused, and is always 0. Historically, it + was the "highwater mark" for allocated space—that is, the + maximum amount of space that was ever allocated (in + bytes); this field was maintained only in nonthreading + environments. + + fsmblks + The total number of bytes in fastbin free blocks. + + uordblks + The total number of bytes used by in-use allocations. + + fordblks + The total number of bytes in free blocks. + + keepcost + The total amount of releasable free space at the top of + the heap. This is the maximum number of bytes that could + ideally (i.e., ignoring page alignment restrictions, and + so on) be released by malloc_trim(3). +*/ + +struct mallinfo mallinfo(void) +{ + struct mallinfo temp_mallinfo; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + + temp_mallinfo.arena = ((size_t)&__HeapLimit - (size_t)&__HeapBase); + temp_mallinfo.ordblks = 0; /* Unused */ + temp_mallinfo.smblks = 0; /* Unused */ + temp_mallinfo.hblks = 0; /* Unused */ + temp_mallinfo.hblkhd = 0; /* Unused */ + temp_mallinfo.usmblks = 0; /* Unused */ + temp_mallinfo.fsmblks = 0; /* Unused */ + temp_mallinfo.uordblks = (size_t)heap_end - (size_t)&__HeapBase; + temp_mallinfo.fordblks = (size_t)&__HeapLimit - (size_t)heap_end; + temp_mallinfo.keepcost = 0 /* Unused */; + + return temp_mallinfo; +} diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/header_MAX32690.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/sla_header_MAX32690.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/header_MAX32690.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/sla_header_MAX32690.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c index fe85bf4a..f51599c5 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c @@ -100,6 +100,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -150,6 +161,7 @@ __weak void SystemInit(void) PalSysInit(); + PinInit(); Board_Init(); __enable_irq(); diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c index a11be015..4c5c1dc5 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -131,5 +142,6 @@ __weak void SystemInit(void) SystemCoreClockUpdate(); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c index 8a51789a..d6cbd2fc 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c @@ -102,6 +102,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -133,5 +144,6 @@ __weak void SystemInit(void) SystemCoreClockUpdate(); + PinInit(); Board_Init(); } diff --git a/MAX/Libraries/CMSIS/Include/arm_common_tables.h b/MAX/Libraries/CMSIS/Include/arm_common_tables.h new file mode 100644 index 00000000..21ad6103 --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/arm_common_tables.h @@ -0,0 +1,105 @@ +#warning This file has been deprecated for newer versions of CMSIS-DSP. +/* +This header file is for use with the older CMSIS-DSP pre-compiled libraries +in the Libraries\CMSIS\Lib\GCC folder. That library is CMSIS version 3. +The MaximSDK now contains CMSIS version 5.9.0, which should be used instead. +The newer header files can be found in the Libraries\CMSIS\5.9.0\DSP\Include +folder, and these should be used instead. +*/ +/** + * @file arm_common_tables.h + * @brief External declaration for common tables like Bitreverse, reciprocal etc. + */ + +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.h +* +* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_COMMON_TABLES_H +#define _ARM_COMMON_TABLES_H + +#include "arm_math.h" + +extern const uint16_t armBitRevTable[1024]; +extern const q15_t armRecipTableQ15[64]; +extern const q31_t armRecipTableQ31[64]; +extern const q31_t realCoefAQ31[1024]; +extern const q31_t realCoefBQ31[1024]; +extern const float32_t twiddleCoef_16[32]; +extern const float32_t twiddleCoef_32[64]; +extern const float32_t twiddleCoef_64[128]; +extern const float32_t twiddleCoef_128[256]; +extern const float32_t twiddleCoef_256[512]; +extern const float32_t twiddleCoef_512[1024]; +extern const float32_t twiddleCoef_1024[2048]; +extern const float32_t twiddleCoef_2048[4096]; +extern const float32_t twiddleCoef_4096[8192]; +#define twiddleCoef twiddleCoef_4096 +extern const q31_t twiddleCoefQ31[6144]; +extern const q15_t twiddleCoefQ15[6144]; +extern const float32_t twiddleCoef_rfft_32[32]; +extern const float32_t twiddleCoef_rfft_64[64]; +extern const float32_t twiddleCoef_rfft_128[128]; +extern const float32_t twiddleCoef_rfft_256[256]; +extern const float32_t twiddleCoef_rfft_512[512]; +extern const float32_t twiddleCoef_rfft_1024[1024]; +extern const float32_t twiddleCoef_rfft_2048[2048]; +extern const float32_t twiddleCoef_rfft_4096[4096]; + +#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20) +#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48) +#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56) +#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208) +#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440) +#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448) +#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800) +#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808) +#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032) + +extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH]; +extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH]; + +#endif /* ARM_COMMON_TABLES_H */ diff --git a/MAX/Libraries/CMSIS/Include/arm_const_structs.h b/MAX/Libraries/CMSIS/Include/arm_const_structs.h new file mode 100644 index 00000000..e18be233 --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/arm_const_structs.h @@ -0,0 +1,87 @@ +#warning This file has been deprecated for newer versions of CMSIS-DSP. +/* +This header file is for use with the older CMSIS-DSP pre-compiled libraries +in the Libraries\CMSIS\Lib\GCC folder. That library is CMSIS version 3. +The MaximSDK now contains CMSIS version 5.9.0, which should be used instead. +The newer header files can be found in the Libraries\CMSIS\5.9.0\DSP\Include +folder, and these should be used instead. +*/ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_const_structs.h +* +* Description: This file has constant structs that are initialized for +* user convenience. For example, some can be given as +* arguments to the arm_cfft_f32() function. +* +* Target Processor: Cortex-M4/Cortex-M3 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. +* -------------------------------------------------------------------- */ + +#ifndef _ARM_CONST_STRUCTS_H +#define _ARM_CONST_STRUCTS_H + +#include "arm_math.h" +#include "arm_common_tables.h" + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = { 16, twiddleCoef_16, armBitRevIndexTable16, + ARMBITREVINDEXTABLE__16_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = { 32, twiddleCoef_32, armBitRevIndexTable32, + ARMBITREVINDEXTABLE__32_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = { 64, twiddleCoef_64, armBitRevIndexTable64, + ARMBITREVINDEXTABLE__64_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = { 128, twiddleCoef_128, armBitRevIndexTable128, + ARMBITREVINDEXTABLE_128_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = { 256, twiddleCoef_256, armBitRevIndexTable256, + ARMBITREVINDEXTABLE_256_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = { 512, twiddleCoef_512, armBitRevIndexTable512, + ARMBITREVINDEXTABLE_512_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = { 1024, twiddleCoef_1024, + armBitRevIndexTable1024, + ARMBITREVINDEXTABLE1024_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = { 2048, twiddleCoef_2048, + armBitRevIndexTable2048, + ARMBITREVINDEXTABLE2048_TABLE_LENGTH }; + +const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = { 4096, twiddleCoef_4096, + armBitRevIndexTable4096, + ARMBITREVINDEXTABLE4096_TABLE_LENGTH }; + +#endif diff --git a/MAX/Libraries/CMSIS/Include/arm_math.h b/MAX/Libraries/CMSIS/Include/arm_math.h new file mode 100644 index 00000000..fb8f1a74 --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/arm_math.h @@ -0,0 +1,5953 @@ +#warning This file has been deprecated for newer versions of CMSIS-DSP. +/* +This header file is for use with the older CMSIS-DSP pre-compiled libraries +in the Libraries\CMSIS\Lib\GCC folder. That library is CMSIS version 3. +The MaximSDK now contains CMSIS version 5.9.0, which should be used instead. +The newer header files can be found in the Libraries\CMSIS\5.9.0\DSP\Include +folder, and these should be used instead. +*/ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010-2013 ARM Limited. All rights reserved. +* +* $Date: 17. January 2013 +* $Revision: V1.4.1 +* +* Project: CMSIS DSP Library +* Title: arm_math.h +* +* Description: Public header file for CMSIS DSP Library +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Redistribution and use in source and binary forms, with or without +* modification, are permitted provided that the following conditions +* are met: +* - Redistributions of source code must retain the above copyright +* notice, this list of conditions and the following disclaimer. +* - Redistributions in binary form must reproduce the above copyright +* notice, this list of conditions and the following disclaimer in +* the documentation and/or other materials provided with the +* distribution. +* - Neither the name of ARM LIMITED nor the names of its contributors +* may be used to endorse or promote products derived from this +* software without specific prior written permission. +* +* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +* POSSIBILITY OF SUCH DAMAGE. + * -------------------------------------------------------------------- */ + +/** + \mainpage CMSIS DSP Software Library + * + * Introduction + * + * This user manual describes the CMSIS DSP software library, + * a suite of common signal processing functions for use on Cortex-M processor based devices. + * + * The library is divided into a number of functions each covering a specific category: + * - Basic math functions + * - Fast math functions + * - Complex math functions + * - Filters + * - Matrix functions + * - Transforms + * - Motor control functions + * - Statistical functions + * - Support functions + * - Interpolation functions + * + * The library has separate functions for operating on 8-bit integers, 16-bit integers, + * 32-bit integer and 32-bit floating-point values. + * + * Using the Library + * + * The library installer contains prebuilt versions of the libraries in the Lib folder. + * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4) + * - arm_cortexM4l_math.lib (Little endian on Cortex-M4) + * - arm_cortexM4b_math.lib (Big endian on Cortex-M4) + * - arm_cortexM3l_math.lib (Little endian on Cortex-M3) + * - arm_cortexM3b_math.lib (Big endian on Cortex-M3) + * - arm_cortexM0l_math.lib (Little endian on Cortex-M0) + * - arm_cortexM0b_math.lib (Big endian on Cortex-M3) + * + * The library functions are declared in the public file arm_math.h which is placed in the Include folder. + * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single + * public header file arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. + * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or + * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application. + * + * Examples + * + * The library ships with a number of examples which demonstrate how to use the library functions. + * + * Toolchain Support + * + * The library has been developed and tested with MDK-ARM version 4.60. + * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly. + * + * Building the Library + * + * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\\DSP_Lib\\Source\\ARM folder. + * - arm_cortexM0b_math.uvproj + * - arm_cortexM0l_math.uvproj + * - arm_cortexM3b_math.uvproj + * - arm_cortexM3l_math.uvproj + * - arm_cortexM4b_math.uvproj + * - arm_cortexM4l_math.uvproj + * - arm_cortexM4bf_math.uvproj + * - arm_cortexM4lf_math.uvproj + * + * + * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above. + * + * Pre-processor Macros + * + * Each library project have differant pre-processor macros. + * + * - UNALIGNED_SUPPORT_DISABLE: + * + * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access + * + * - ARM_MATH_BIG_ENDIAN: + * + * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets. + * + * - ARM_MATH_MATRIX_CHECK: + * + * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices + * + * - ARM_MATH_ROUNDING: + * + * Define macro ARM_MATH_ROUNDING for rounding on support functions + * + * - ARM_MATH_CMx: + * + * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target + * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target. + * + * - __FPU_PRESENT: + * + * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries + * + * Copyright Notice + * + * Copyright (C) 2010-2013 ARM Limited. All rights reserved. + */ + +/** + * @defgroup groupMath Basic Math Functions + */ + +/** + * @defgroup groupFastMath Fast Math Functions + * This set of functions provides a fast approximation to sine, cosine, and square root. + * As compared to most of the other functions in the CMSIS math library, the fast math functions + * operate on individual values and not arrays. + * There are separate functions for Q15, Q31, and floating-point data. + * + */ + +/** + * @defgroup groupCmplxMath Complex Math Functions + * This set of functions operates on complex data vectors. + * The data in the complex arrays is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * In the API functions, the number of samples in a complex array refers + * to the number of complex values; the array contains twice this number of + * real values. + */ + +/** + * @defgroup groupFilters Filtering Functions + */ + +/** + * @defgroup groupMatrix Matrix Functions + * + * This set of functions provides basic matrix math operations. + * The functions operate on matrix data structures. For example, + * the type + * definition for the floating-point matrix structure is shown + * below: + * 
+ *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ *
+ * There are similar definitions for Q15 and Q31 data types. + * + * The structure specifies the size of the matrix and then points to + * an array of data. The array is of size numRows X numCols + * and the values are arranged in row order. That is, the + * matrix element (i, j) is stored at: + * 
+ *     pData[i*numCols + j]
+ *
+ * + * \par Init Functions + * There is an associated initialization function for each type of matrix + * data structure. + * The initialization function sets the values of the internal structure fields. + * Refer to the function arm_mat_init_f32(), arm_mat_init_q31() + * and arm_mat_init_q15() for floating-point, Q31 and Q15 types, respectively. + * + * \par + * Use of the initialization function is optional. However, if initialization function is used + * then the instance structure cannot be placed into a const data section. + * To place the instance structure in a const data + * section, manually initialize the data structure. For example: + * 
+ * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ *
+ * where nRows specifies the number of rows, nColumns + * specifies the number of columns, and pData points to the + * data array. + * + * \par Size Checking + * By default all of the matrix functions perform size checking on the input and + * output matrices. For example, the matrix addition function verifies that the + * two input matrices and the output matrix all have the same number of rows and + * columns. If the size check fails the functions return: + * 
+ *     ARM_MATH_SIZE_MISMATCH
+ *
+ * Otherwise the functions return + * 
+ *     ARM_MATH_SUCCESS
+ *
+ * There is some overhead associated with this matrix size checking. + * The matrix size checking is enabled via the \#define + * 
+ *     ARM_MATH_MATRIX_CHECK
+ *
+ * within the library project settings. By default this macro is defined + * and size checking is enabled. By changing the project settings and + * undefining this macro size checking is eliminated and the functions + * run a bit faster. With size checking disabled the functions always + * return ARM_MATH_SUCCESS. + */ + +/** + * @defgroup groupTransforms Transform Functions + */ + +/** + * @defgroup groupController Controller Functions + */ + +/** + * @defgroup groupStats Statistics Functions + */ +/** + * @defgroup groupSupport Support Functions + */ + +/** + * @defgroup groupInterpolation Interpolation Functions + * These functions perform 1- and 2-dimensional interpolation of data. + * Linear interpolation is used for 1-dimensional data and + * bilinear interpolation is used for 2-dimensional data. + */ + +/** + * @defgroup groupExamples Examples + */ +#ifndef _ARM_MATH_H +#define _ARM_MATH_H + +#define __CMSIS_GENERIC /* disable NVIC and Systick functions */ + +#if defined(ARM_MATH_CM4) +#include "core_cm4.h" +#elif defined(ARM_MATH_CM3) +#include "core_cm3.h" +#elif defined(ARM_MATH_CM0) +#include "core_cm0.h" +#define ARM_MATH_CM0_FAMILY +#elif defined(ARM_MATH_CM0PLUS) +#include "core_cm0plus.h" +#define ARM_MATH_CM0_FAMILY +#else +#include "ARMCM4.h" +#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....." +#endif + +#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */ +#include "string.h" +#include "math.h" +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief Macros required for reciprocal calculation in Normalized LMS + */ + +#define DELTA_Q31 (0x100) +#define DELTA_Q15 0x5 +#define INDEX_MASK 0x0000003F +#ifndef PI +#define PI 3.14159265358979f +#endif + +/** + * @brief Macros required for SINE and COSINE Fast math approximations + */ + +#define TABLE_SIZE 256 +#define TABLE_SPACING_Q31 0x800000 +#define TABLE_SPACING_Q15 0x80 + +/** + * @brief Macros required for SINE and COSINE Controller functions + */ +/* 1.31(q31) Fixed value of 2/360 */ +/* -1 to +1 is divided into 360 values so total spacing is (2/360) */ +#define INPUT_SPACING 0xB60B61 + +/** + * @brief Macro for Unaligned Support + */ +#ifndef UNALIGNED_SUPPORT_DISABLE +#define ALIGN4 +#else +#if defined(__GNUC__) +#define ALIGN4 __attribute__((aligned(4))) +#else +#define ALIGN4 __align(4) +#endif +#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */ + +/** + * @brief Error status returned by some functions in the library. + */ + +typedef enum { + ARM_MATH_SUCCESS = 0, /**< No error */ + ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */ + ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */ + ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */ + ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */ + ARM_MATH_SINGULAR = + -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */ + ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */ +} arm_status; + +/** + * @brief 8-bit fractional data type in 1.7 format. + */ +typedef int8_t q7_t; + +/** + * @brief 16-bit fractional data type in 1.15 format. + */ +typedef int16_t q15_t; + +/** + * @brief 32-bit fractional data type in 1.31 format. + */ +typedef int32_t q31_t; + +/** + * @brief 64-bit fractional data type in 1.63 format. + */ +typedef int64_t q63_t; + +/** + * @brief 32-bit floating-point type definition. + */ +typedef float float32_t; + +/** + * @brief 64-bit floating-point type definition. + */ +typedef double float64_t; + +/** + * @brief definition to read/write two 16 bit values. + */ +#if defined __CC_ARM +#define __SIMD32_TYPE int32_t __packed +#define CMSIS_UNUSED __attribute__((unused)) +#elif defined __ICCARM__ +#define CMSIS_UNUSED +#define __SIMD32_TYPE int32_t __packed +#elif defined __GNUC__ +#define __SIMD32_TYPE int32_t +#define CMSIS_UNUSED __attribute__((unused)) +#else +#error Unknown compiler +#endif + +#define __SIMD32(addr) (*(__SIMD32_TYPE **)&(addr)) +#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr)) + +#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *)(addr)) + +#define __SIMD64(addr) (*(int64_t **)&(addr)) + +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) +/** + * @brief definition to pack two 16 bit values. + */ +#define __PKHBT(ARG1, ARG2, ARG3) \ + ((((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \ + (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)) +#define __PKHTB(ARG1, ARG2, ARG3) \ + ((((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \ + (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF)) + +#endif + +/** + * @brief definition to pack four 8 bit values. + */ +#ifndef ARM_MATH_BIG_ENDIAN + +#define __PACKq7(v0, v1, v2, v3) \ + ((((int32_t)(v0) << 0) & (int32_t)0x000000FF) | (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v3) << 24) & (int32_t)0xFF000000)) +#else + +#define __PACKq7(v0, v1, v2, v3) \ + ((((int32_t)(v3) << 0) & (int32_t)0x000000FF) | (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \ + (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \ + (((int32_t)(v0) << 24) & (int32_t)0xFF000000)) + +#endif + +/** + * @brief Clips Q63 to Q31 values. + */ +static __INLINE q31_t clip_q63_to_q31(q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFFFFFF ^ ((q31_t)(x >> 63)))) : (q31_t)x; +} + +/** + * @brief Clips Q63 to Q15 values. + */ +static __INLINE q15_t clip_q63_to_q15(q63_t x) +{ + return ((q31_t)(x >> 32) != ((q31_t)x >> 31)) ? ((0x7FFF ^ ((q15_t)(x >> 63)))) : + (q15_t)(x >> 15); +} + +/** + * @brief Clips Q31 to Q7 values. + */ +static __INLINE q7_t clip_q31_to_q7(q31_t x) +{ + return ((q31_t)(x >> 24) != ((q31_t)x >> 23)) ? ((0x7F ^ ((q7_t)(x >> 31)))) : (q7_t)x; +} + +/** + * @brief Clips Q31 to Q15 values. + */ +static __INLINE q15_t clip_q31_to_q15(q31_t x) +{ + return ((q31_t)(x >> 16) != ((q31_t)x >> 15)) ? ((0x7FFF ^ ((q15_t)(x >> 31)))) : (q15_t)x; +} + +/** + * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format. + */ + +static __INLINE q63_t mult32x64(q63_t x, q31_t y) +{ + return ((((q63_t)(x & 0x00000000FFFFFFFF) * y) >> 32) + (((q63_t)(x >> 32) * y))); +} + +#if defined(ARM_MATH_CM0_FAMILY) && defined(__CC_ARM) +#define __CLZ __clz +#endif + +#if defined(ARM_MATH_CM0_FAMILY) && \ + ((defined(__ICCARM__)) || (defined(__GNUC__)) || defined(__TASKING__)) + +static __INLINE uint32_t __CLZ(q31_t data); + +static __INLINE uint32_t __CLZ(q31_t data) +{ + uint32_t count = 0; + uint32_t mask = 0x80000000; + + while ((data & mask) == 0) { + count += 1u; + mask = mask >> 1u; + } + + return (count); +} + +#endif + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type. + */ + +static __INLINE uint32_t arm_recip_q31(q31_t in, q31_t *dst, q31_t *pRecipTable) +{ + uint32_t out, tempVal; + uint32_t index, i; + uint32_t signBits; + + if (in > 0) { + signBits = __CLZ(in) - 1; + } else { + signBits = __CLZ(-in) - 1; + } + + /* Convert input sample to 1.31 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = (uint32_t)(in >> 24u); + index = (index & INDEX_MASK); + + /* 1.31 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0u; i < 2u; i++) { + tempVal = (q31_t)(((q63_t)in * out) >> 31u); + tempVal = 0x7FFFFFFF - tempVal; + /* 1.31 with exp 1 */ + //out = (q31_t) (((q63_t) out * tempVal) >> 30u); + out = (q31_t)clip_q63_to_q31(((q63_t)out * tempVal) >> 30u); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1u); +} + +/** + * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type. + */ +static __INLINE uint32_t arm_recip_q15(q15_t in, q15_t *dst, q15_t *pRecipTable) +{ + uint32_t out = 0, tempVal = 0; + uint32_t index = 0, i = 0; + uint32_t signBits = 0; + + if (in > 0) { + signBits = __CLZ(in) - 17; + } else { + signBits = __CLZ(-in) - 17; + } + + /* Convert input sample to 1.15 format */ + in = in << signBits; + + /* calculation of index for initial approximated Val */ + index = in >> 8; + index = (index & INDEX_MASK); + + /* 1.15 with exp 1 */ + out = pRecipTable[index]; + + /* calculation of reciprocal value */ + /* running approximation for two iterations */ + for (i = 0; i < 2; i++) { + tempVal = (q15_t)(((q31_t)in * out) >> 15); + tempVal = 0x7FFF - tempVal; + /* 1.15 with exp 1 */ + out = (q15_t)(((q31_t)out * tempVal) >> 14); + } + + /* write output */ + *dst = out; + + /* return num of signbits of out = 1/in value */ + return (signBits + 1); +} + +/* + * @brief C custom defined intrinisic function for only M0 processors + */ +#if defined(ARM_MATH_CM0_FAMILY) + +static __INLINE q31_t __SSAT(q31_t x, uint32_t y) +{ + int32_t posMax, negMin; + uint32_t i; + + posMax = 1; + for (i = 0; i < (y - 1); i++) { + posMax = posMax * 2; + } + + if (x > 0) { + posMax = (posMax - 1); + + if (x > posMax) { + x = posMax; + } + } else { + negMin = -posMax; + + if (x < negMin) { + x = negMin; + } + } + return (x); +} + +#endif /* end of ARM_MATH_CM0_FAMILY */ + +/* + * @brief C custom defined intrinsic function for M3 and M0 processors + */ +#if defined(ARM_MATH_CM3) || defined(ARM_MATH_CM0_FAMILY) + +/* + * @brief C custom defined QADD8 for M3 and M0 processors + */ +static __INLINE q31_t __QADD8(q31_t x, q31_t y) +{ + q31_t sum; + q7_t r, s, t, u; + + r = (q7_t)x; + s = (q7_t)y; + + r = __SSAT((q31_t)(r + s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) + ((y << 16) >> 24))), 8); + t = __SSAT(((q31_t)(((x << 8) >> 24) + ((y << 8) >> 24))), 8); + u = __SSAT(((q31_t)((x >> 24) + (y >> 24))), 8); + + sum = (((q31_t)u << 24) & 0xFF000000) | (((q31_t)t << 16) & 0x00FF0000) | + (((q31_t)s << 8) & 0x0000FF00) | (r & 0x000000FF); + + return sum; +} + +/* + * @brief C custom defined QSUB8 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB8(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s, t, u; + + r = (q7_t)x; + s = (q7_t)y; + + r = __SSAT((r - s), 8); + s = __SSAT(((q31_t)(((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8; + t = __SSAT(((q31_t)(((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16; + u = __SSAT(((q31_t)((x >> 24) - (y >> 24))), 8) << 24; + + sum = (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF); + + return sum; +} + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ + +/* + * @brief C custom defined QADD16 for M3 and M0 processors + */ +static __INLINE q31_t __QADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = __SSAT(r + s, 16); + s = __SSAT(((q31_t)((x >> 16) + (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SHADD16 for M3 and M0 processors + */ +static __INLINE q31_t __SHADD16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = ((r >> 1) + (s >> 1)); + s = ((q31_t)((x >> 17) + (y >> 17))) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined QSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __QSUB16(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = __SSAT(r - s, 16); + s = __SSAT(((q31_t)((x >> 16) - (y >> 16))), 16) << 16; + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SHSUB16 for M3 and M0 processors + */ +static __INLINE q31_t __SHSUB16(q31_t x, q31_t y) +{ + q31_t diff; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = ((r >> 1) - (s >> 1)); + s = (((x >> 17) - (y >> 17)) << 16); + + diff = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return diff; +} + +/* + * @brief C custom defined QASX for M3 and M0 processors + */ +static __INLINE q31_t __QASX(q31_t x, q31_t y) +{ + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t)((short)(x >> 16) + (short)y))) << 16) + + clip_q31_to_q15((q31_t)((short)x - (short)(y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHASX for M3 and M0 processors + */ +static __INLINE q31_t __SHASX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = ((r >> 1) - (y >> 17)); + s = (((x >> 17) + (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined QSAX for M3 and M0 processors + */ +static __INLINE q31_t __QSAX(q31_t x, q31_t y) +{ + q31_t sum = 0; + + sum = ((sum + clip_q31_to_q15((q31_t)((short)(x >> 16) - (short)y))) << 16) + + clip_q31_to_q15((q31_t)((short)x + (short)(y >> 16))); + + return sum; +} + +/* + * @brief C custom defined SHSAX for M3 and M0 processors + */ +static __INLINE q31_t __SHSAX(q31_t x, q31_t y) +{ + q31_t sum; + q31_t r, s; + + r = (short)x; + s = (short)y; + + r = ((r >> 1) + (y >> 17)); + s = (((x >> 17) - (s >> 1)) << 16); + + sum = (s & 0xFFFF0000) | (r & 0x0000FFFF); + + return sum; +} + +/* + * @brief C custom defined SMUSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMUSDX(q31_t x, q31_t y) +{ + return ((q31_t)(((short)x * (short)(y >> 16)) - ((short)(x >> 16) * (short)y))); +} + +/* + * @brief C custom defined SMUADX for M3 and M0 processors + */ +static __INLINE q31_t __SMUADX(q31_t x, q31_t y) +{ + return ((q31_t)(((short)x * (short)(y >> 16)) + ((short)(x >> 16) * (short)y))); +} + +/* + * @brief C custom defined QADD for M3 and M0 processors + */ +static __INLINE q31_t __QADD(q31_t x, q31_t y) +{ + return clip_q63_to_q31((q63_t)x + y); +} + +/* + * @brief C custom defined QSUB for M3 and M0 processors + */ +static __INLINE q31_t __QSUB(q31_t x, q31_t y) +{ + return clip_q63_to_q31((q63_t)x - y); +} + +/* + * @brief C custom defined SMLAD for M3 and M0 processors + */ +static __INLINE q31_t __SMLAD(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((short)(x >> 16) * (short)(y >> 16)) + ((short)x * (short)y)); +} + +/* + * @brief C custom defined SMLADX for M3 and M0 processors + */ +static __INLINE q31_t __SMLADX(q31_t x, q31_t y, q31_t sum) +{ + return (sum + ((short)(x >> 16) * (short)(y)) + ((short)x * (short)(y >> 16))); +} + +/* + * @brief C custom defined SMLSDX for M3 and M0 processors + */ +static __INLINE q31_t __SMLSDX(q31_t x, q31_t y, q31_t sum) +{ + return (sum - ((short)(x >> 16) * (short)(y)) + ((short)x * (short)(y >> 16))); +} + +/* + * @brief C custom defined SMLALD for M3 and M0 processors + */ +static __INLINE q63_t __SMLALD(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((short)(x >> 16) * (short)(y >> 16)) + ((short)x * (short)y)); +} + +/* + * @brief C custom defined SMLALDX for M3 and M0 processors + */ +static __INLINE q63_t __SMLALDX(q31_t x, q31_t y, q63_t sum) +{ + return (sum + ((short)(x >> 16) * (short)y)) + ((short)x * (short)(y >> 16)); +} + +/* + * @brief C custom defined SMUAD for M3 and M0 processors + */ +static __INLINE q31_t __SMUAD(q31_t x, q31_t y) +{ + return (((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +/* + * @brief C custom defined SMUSD for M3 and M0 processors + */ +static __INLINE q31_t __SMUSD(q31_t x, q31_t y) +{ + return (-((x >> 16) * (y >> 16)) + (((x << 16) >> 16) * ((y << 16) >> 16))); +} + +/* + * @brief C custom defined SXTB16 for M3 and M0 processors + */ +static __INLINE q31_t __SXTB16(q31_t x) +{ + return ((((x << 24) >> 24) & 0x0000FFFF) | (((x << 8) >> 8) & 0xFFFF0000)); +} + +#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */ + +/** + * @brief Instance structure for the Q7 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q7; + +/** + * @brief Instance structure for the Q15 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ +} arm_fir_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of filter coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ +} arm_fir_instance_f32; + +/** + * @brief Processing function for the Q7 FIR filter. + * @param[in] *S points to an instance of the Q7 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q7(const arm_fir_instance_q7 *S, q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the Q7 FIR filter. + * @param[in,out] *S points to an instance of the Q7 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed. + * @return none + */ +void arm_fir_init_q7(arm_fir_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, q7_t *pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR filter. + * @param[in] *S points to an instance of the Q15 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q15(const arm_fir_instance_q15 *S, q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR filter. + * @param[in,out] *S points to an instance of the Q15 FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if + * numTaps is not a supported value. + */ + +arm_status arm_fir_init_q15(arm_fir_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, + q15_t *pState, uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR filter. + * @param[in] *S points to an instance of the Q31 FIR filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_fast_q31(const arm_fir_instance_q31 *S, q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR filter. + * @param[in,out] *S points to an instance of the Q31 FIR structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_q31(arm_fir_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point FIR filter. + * @param[in] *S points to an instance of the floating-point FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_f32(const arm_fir_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR filter. + * @param[in,out] *S points to an instance of the floating-point FIR filter structure. + * @param[in] numTaps Number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of samples that are processed at a time. + * @return none. + */ +void arm_fir_init_f32(arm_fir_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 Biquad cascade filter. + */ +typedef struct { + int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q15_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q15; + +/** + * @brief Instance structure for the Q31 Biquad cascade filter. + */ +typedef struct { + uint32_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q31_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */ + +} arm_biquad_casd_df1_inst_q31; + +/** + * @brief Instance structure for the floating-point Biquad cascade filter. + */ +typedef struct { + uint32_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t * + pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */ + float32_t + *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */ + +} arm_biquad_casd_df1_inst_f32; + +/** + * @brief Processing function for the Q15 Biquad cascade filter. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q15(arm_biquad_casd_df1_inst_q15 *S, uint8_t numStages, + q15_t *pCoeffs, q15_t *pState, int8_t postShift); + +/** + * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q15(const arm_biquad_casd_df1_inst_q15 *S, q15_t *pSrc, + q15_t *pDst, uint32_t blockSize); + +/** + * @brief Processing function for the Q31 Biquad cascade filter + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_fast_q31(const arm_biquad_casd_df1_inst_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 Biquad cascade filter. + * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cascade_df1_init_q31(arm_biquad_casd_df1_inst_q31 *S, uint8_t numStages, + q31_t *pCoeffs, q31_t *pState, int8_t postShift); + +/** + * @brief Processing function for the floating-point Biquad cascade filter. + * @param[in] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df1_f32(const arm_biquad_casd_df1_inst_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point Biquad cascade filter. + * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df1_init_f32(arm_biquad_casd_df1_inst_f32 *S, uint8_t numStages, + float32_t *pCoeffs, float32_t *pState); + +/** + * @brief Instance structure for the floating-point matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + float32_t *pData; /**< points to the data of the matrix. */ +} arm_matrix_instance_f32; + +/** + * @brief Instance structure for the Q15 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q15_t *pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q15; + +/** + * @brief Instance structure for the Q31 matrix structure. + */ + +typedef struct { + uint16_t numRows; /**< number of rows of the matrix. */ + uint16_t numCols; /**< number of columns of the matrix. */ + q31_t *pData; /**< points to the data of the matrix. */ + +} arm_matrix_instance_q31; + +/** + * @brief Floating-point matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); + +/** + * @brief Q15 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); + +/** + * @brief Q31 matrix addition. + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_add_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); + +/** + * @brief Floating-point matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_f32(const arm_matrix_instance_f32 *pSrc, arm_matrix_instance_f32 *pDst); + +/** + * @brief Q15 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q15(const arm_matrix_instance_q15 *pSrc, arm_matrix_instance_q15 *pDst); + +/** + * @brief Q31 matrix transpose. + * @param[in] *pSrc points to the input matrix + * @param[out] *pDst points to the output matrix + * @return The function returns either ARM_MATH_SIZE_MISMATCH + * or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_trans_q31(const arm_matrix_instance_q31 *pSrc, arm_matrix_instance_q31 *pDst); + +/** + * @brief Floating-point matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); + +/** + * @brief Q15 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst, + q15_t *pState); + +/** + * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @param[in] *pState points to the array for storing intermediate results + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, + arm_matrix_instance_q15 *pDst, q15_t *pState); + +/** + * @brief Q31 matrix multiplication + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); + +/** + * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_mult_fast_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, + arm_matrix_instance_q31 *pDst); + +/** + * @brief Floating-point matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_f32(const arm_matrix_instance_f32 *pSrcA, + const arm_matrix_instance_f32 *pSrcB, arm_matrix_instance_f32 *pDst); + +/** + * @brief Q15 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q15(const arm_matrix_instance_q15 *pSrcA, + const arm_matrix_instance_q15 *pSrcB, arm_matrix_instance_q15 *pDst); + +/** + * @brief Q31 matrix subtraction + * @param[in] *pSrcA points to the first input matrix structure + * @param[in] *pSrcB points to the second input matrix structure + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_sub_q31(const arm_matrix_instance_q31 *pSrcA, + const arm_matrix_instance_q31 *pSrcB, arm_matrix_instance_q31 *pDst); + +/** + * @brief Floating-point matrix scaling. + * @param[in] *pSrc points to the input matrix + * @param[in] scale scale factor + * @param[out] *pDst points to the output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_f32(const arm_matrix_instance_f32 *pSrc, float32_t scale, + arm_matrix_instance_f32 *pDst); + +/** + * @brief Q15 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q15(const arm_matrix_instance_q15 *pSrc, q15_t scaleFract, int32_t shift, + arm_matrix_instance_q15 *pDst); + +/** + * @brief Q31 matrix scaling. + * @param[in] *pSrc points to input matrix + * @param[in] scaleFract fractional portion of the scale factor + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to output matrix structure + * @return The function returns either + * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking. + */ + +arm_status arm_mat_scale_q31(const arm_matrix_instance_q31 *pSrc, q31_t scaleFract, int32_t shift, + arm_matrix_instance_q31 *pDst); + +/** + * @brief Q31 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q31(arm_matrix_instance_q31 *S, uint16_t nRows, uint16_t nColumns, q31_t *pData); + +/** + * @brief Q15 matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_q15(arm_matrix_instance_q15 *S, uint16_t nRows, uint16_t nColumns, q15_t *pData); + +/** + * @brief Floating-point matrix initialization. + * @param[in,out] *S points to an instance of the floating-point matrix structure. + * @param[in] nRows number of rows in the matrix. + * @param[in] nColumns number of columns in the matrix. + * @param[in] *pData points to the matrix data array. + * @return none + */ + +void arm_mat_init_f32(arm_matrix_instance_f32 *S, uint16_t nRows, uint16_t nColumns, + float32_t *pData); + +/** + * @brief Instance structure for the Q15 PID Control. + */ +typedef struct { + q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ +#ifdef ARM_MATH_CM0_FAMILY + q15_t A1; + q15_t A2; +#else + q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/ +#endif + q15_t state[3]; /**< The state array of length 3. */ + q15_t Kp; /**< The proportional gain. */ + q15_t Ki; /**< The integral gain. */ + q15_t Kd; /**< The derivative gain. */ +} arm_pid_instance_q15; + +/** + * @brief Instance structure for the Q31 PID Control. + */ +typedef struct { + q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + q31_t A2; /**< The derived gain, A2 = Kd . */ + q31_t state[3]; /**< The state array of length 3. */ + q31_t Kp; /**< The proportional gain. */ + q31_t Ki; /**< The integral gain. */ + q31_t Kd; /**< The derivative gain. */ + +} arm_pid_instance_q31; + +/** + * @brief Instance structure for the floating-point PID Control. + */ +typedef struct { + float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */ + float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */ + float32_t A2; /**< The derived gain, A2 = Kd . */ + float32_t state[3]; /**< The state array of length 3. */ + float32_t Kp; /**< The proportional gain. */ + float32_t Ki; /**< The integral gain. */ + float32_t Kd; /**< The derivative gain. */ +} arm_pid_instance_f32; + +/** + * @brief Initialization function for the floating-point PID Control. + * @param[in,out] *S points to an instance of the PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_f32(arm_pid_instance_f32 *S, int32_t resetStateFlag); + +/** + * @brief Reset function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @return none + */ +void arm_pid_reset_f32(arm_pid_instance_f32 *S); + +/** + * @brief Initialization function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q31(arm_pid_instance_q31 *S, int32_t resetStateFlag); + +/** + * @brief Reset function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @return none + */ + +void arm_pid_reset_q31(arm_pid_instance_q31 *S); + +/** + * @brief Initialization function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID structure. + * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state. + * @return none. + */ +void arm_pid_init_q15(arm_pid_instance_q15 *S, int32_t resetStateFlag); + +/** + * @brief Reset function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the q15 PID Control structure + * @return none + */ +void arm_pid_reset_q15(arm_pid_instance_q15 *S); + +/** + * @brief Instance structure for the floating-point Linear Interpolate function. + */ +typedef struct { + uint32_t nValues; /**< nValues */ + float32_t x1; /**< x1 */ + float32_t xSpacing; /**< xSpacing */ + float32_t *pYData; /**< pointer to the table of Y values */ +} arm_linear_interp_instance_f32; + +/** + * @brief Instance structure for the floating-point bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + float32_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_f32; + +/** + * @brief Instance structure for the Q31 bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q31_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q31; + +/** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q15_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q15; + +/** + * @brief Instance structure for the Q15 bilinear interpolation function. + */ + +typedef struct { + uint16_t numRows; /**< number of rows in the data table. */ + uint16_t numCols; /**< number of columns in the data table. */ + q7_t *pData; /**< points to the data table. */ +} arm_bilinear_interp_instance_q7; + +/** + * @brief Q7 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Q15 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q15; + +arm_status arm_cfft_radix2_init_q15(arm_cfft_radix2_instance_q15 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +void arm_cfft_radix2_q15(const arm_cfft_radix2_instance_q15 *S, q15_t *pSrc); + +/** + * @brief Instance structure for the Q15 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q15; + +arm_status arm_cfft_radix4_init_q15(arm_cfft_radix4_instance_q15 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +void arm_cfft_radix4_q15(const arm_cfft_radix4_instance_q15 *S, q15_t *pSrc); + +/** + * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix2_instance_q31; + +arm_status arm_cfft_radix2_init_q31(arm_cfft_radix2_instance_q31 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +void arm_cfft_radix2_q31(const arm_cfft_radix2_instance_q31 *S, q31_t *pSrc); + +/** + * @brief Instance structure for the Q31 CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ +} arm_cfft_radix4_instance_q31; + +void arm_cfft_radix4_q31(const arm_cfft_radix4_instance_q31 *S, q31_t *pSrc); + +arm_status arm_cfft_radix4_init_q31(arm_cfft_radix4_instance_q31 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix2_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix2_init_f32(arm_cfft_radix2_instance_f32 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix2_f32(const arm_cfft_radix2_instance_f32 *S, float32_t *pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + uint8_t + ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */ + uint8_t + bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */ + float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t + twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + uint16_t + bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */ + float32_t onebyfftLen; /**< value of 1/fftLen. */ +} arm_cfft_radix4_instance_f32; + +/* Deprecated */ +arm_status arm_cfft_radix4_init_f32(arm_cfft_radix4_instance_f32 *S, uint16_t fftLen, + uint8_t ifftFlag, uint8_t bitReverseFlag); + +/* Deprecated */ +void arm_cfft_radix4_f32(const arm_cfft_radix4_instance_f32 *S, float32_t *pSrc); + +/** + * @brief Instance structure for the floating-point CFFT/CIFFT function. + */ + +typedef struct { + uint16_t fftLen; /**< length of the FFT. */ + const float32_t *pTwiddle; /**< points to the Twiddle factor table. */ + const uint16_t *pBitRevTable; /**< points to the bit reversal table. */ + uint16_t bitRevLength; /**< bit reversal table length. */ +} arm_cfft_instance_f32; + +void arm_cfft_f32(const arm_cfft_instance_f32 *S, float32_t *p1, uint8_t ifftFlag, + uint8_t bitReverseFlag); + +/** + * @brief Instance structure for the Q15 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q15; + +arm_status arm_rfft_init_q15(arm_rfft_instance_q15 *S, arm_cfft_radix4_instance_q15 *S_CFFT, + uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); + +void arm_rfft_q15(const arm_rfft_instance_q15 *S, q15_t *pSrc, q15_t *pDst); + +/** + * @brief Instance structure for the Q31 RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint32_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_q31; + +arm_status arm_rfft_init_q31(arm_rfft_instance_q31 *S, arm_cfft_radix4_instance_q31 *S_CFFT, + uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); + +void arm_rfft_q31(const arm_rfft_instance_q31 *S, q31_t *pSrc, q31_t *pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + uint32_t fftLenReal; /**< length of the real FFT. */ + uint16_t fftLenBy2; /**< length of the complex FFT. */ + uint8_t + ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */ + uint8_t + bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */ + uint32_t + twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */ + float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */ + float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_rfft_instance_f32; + +arm_status arm_rfft_init_f32(arm_rfft_instance_f32 *S, arm_cfft_radix4_instance_f32 *S_CFFT, + uint32_t fftLenReal, uint32_t ifftFlagR, uint32_t bitReverseFlag); + +void arm_rfft_f32(const arm_rfft_instance_f32 *S, float32_t *pSrc, float32_t *pDst); + +/** + * @brief Instance structure for the floating-point RFFT/RIFFT function. + */ + +typedef struct { + arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */ + uint16_t fftLenRFFT; /**< length of the real sequence */ + float32_t *pTwiddleRFFT; /**< Twiddle factors real stage */ +} arm_rfft_fast_instance_f32; + +arm_status arm_rfft_fast_init_f32(arm_rfft_fast_instance_f32 *S, uint16_t fftLen); + +void arm_rfft_fast_f32(arm_rfft_fast_instance_f32 *S, float32_t *p, float32_t *pOut, + uint8_t ifftFlag); + +/** + * @brief Instance structure for the floating-point DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + float32_t normalize; /**< normalizing factor. */ + float32_t *pTwiddle; /**< points to the twiddle factor table. */ + float32_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_f32; + +/** + * @brief Initialization function for the floating-point DCT4/IDCT4. + * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length. + */ + +arm_status arm_dct4_init_f32(arm_dct4_instance_f32 *S, arm_rfft_instance_f32 *S_RFFT, + arm_cfft_radix4_instance_f32 *S_CFFT, uint16_t N, uint16_t Nby2, + float32_t normalize); + +/** + * @brief Processing function for the floating-point DCT4/IDCT4. + * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_f32(const arm_dct4_instance_f32 *S, float32_t *pState, float32_t *pInlineBuffer); + +/** + * @brief Instance structure for the Q31 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q31_t normalize; /**< normalizing factor. */ + q31_t *pTwiddle; /**< points to the twiddle factor table. */ + q31_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q31; + +/** + * @brief Initialization function for the Q31 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure + * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q31(arm_dct4_instance_q31 *S, arm_rfft_instance_q31 *S_RFFT, + arm_cfft_radix4_instance_q31 *S_CFFT, uint16_t N, uint16_t Nby2, + q31_t normalize); + +/** + * @brief Processing function for the Q31 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q31 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q31(const arm_dct4_instance_q31 *S, q31_t *pState, q31_t *pInlineBuffer); + +/** + * @brief Instance structure for the Q15 DCT4/IDCT4 function. + */ + +typedef struct { + uint16_t N; /**< length of the DCT4. */ + uint16_t Nby2; /**< half of the length of the DCT4. */ + q15_t normalize; /**< normalizing factor. */ + q15_t *pTwiddle; /**< points to the twiddle factor table. */ + q15_t *pCosFactor; /**< points to the cosFactor table. */ + arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */ + arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */ +} arm_dct4_instance_q15; + +/** + * @brief Initialization function for the Q15 DCT4/IDCT4. + * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure. + * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure. + * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure. + * @param[in] N length of the DCT4. + * @param[in] Nby2 half of the length of the DCT4. + * @param[in] normalize normalizing factor. + * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length. + */ + +arm_status arm_dct4_init_q15(arm_dct4_instance_q15 *S, arm_rfft_instance_q15 *S_RFFT, + arm_cfft_radix4_instance_q15 *S_CFFT, uint16_t N, uint16_t Nby2, + q15_t normalize); + +/** + * @brief Processing function for the Q15 DCT4/IDCT4. + * @param[in] *S points to an instance of the Q15 DCT4 structure. + * @param[in] *pState points to state buffer. + * @param[in,out] *pInlineBuffer points to the in-place input and output buffer. + * @return none. + */ + +void arm_dct4_q15(const arm_dct4_instance_q15 *S, q15_t *pState, q15_t *pInlineBuffer); + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q7(q7_t *pSrcA, q7_t *pSrcB, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_f32(float32_t *pSrc, float32_t scale, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q7(q7_t *pSrc, q7_t scaleFract, int8_t shift, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q15(q15_t *pSrc, q15_t scaleFract, int8_t shift, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_scale_q31(q31_t *pSrc, q31_t scaleFract, int8_t shift, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t blockSize, float32_t *result); + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q7(q7_t *pSrcA, q7_t *pSrcB, uint32_t blockSize, q31_t *result); + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t blockSize, q63_t *result); + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + +void arm_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t blockSize, q63_t *result); + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q7(q7_t *pSrc, int8_t shiftBits, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q15(q15_t *pSrc, int8_t shiftBits, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_shift_q31(q31_t *pSrc, int8_t shiftBits, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_f32(float32_t *pSrc, float32_t offset, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q7(q7_t *pSrc, q7_t offset, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q15(q15_t *pSrc, q15_t offset, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_offset_q31(q31_t *pSrc, q31_t offset, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); +/** + * @brief Copies the elements of a floating-point vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_f32(float32_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Copies the elements of a Q7 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q7(q7_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Copies the elements of a Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q15(q15_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Copies the elements of a Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_copy_q31(q31_t *pSrc, q31_t *pDst, uint32_t blockSize); +/** + * @brief Fills a constant value into a floating-point vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q7 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q7(q7_t value, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q15 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q15(q15_t value, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Fills a constant value into a Q31 vector. + * @param[in] value input value to be filled + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_fill_q31(q31_t value, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, + float32_t *pDst); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_conv_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst, + q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); + +/** + * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_conv_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); + +/** + * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); + +/** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_conv_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, + q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1. + * @return none. + */ + +void arm_conv_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst); + +/** + * @brief Partial convolution of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, + uint32_t srcBLen, float32_t *pDst, uint32_t firstIndex, + uint32_t numPoints); + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, uint32_t numPoints, + q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Partial convolution of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, uint32_t numPoints); + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, uint32_t firstIndex, uint32_t numPoints); + +/** + * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, + uint32_t srcBLen, q15_t *pDst, uint32_t firstIndex, + uint32_t numPoints, q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Partial convolution of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst, uint32_t firstIndex, uint32_t numPoints); + +/** + * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst, uint32_t firstIndex, uint32_t numPoints); + +/** + * @brief Partial convolution of Q7 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst, uint32_t firstIndex, uint32_t numPoints, + q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Partial convolution of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data + * @param[in] firstIndex is the first output sample to start with. + * @param[in] numPoints is the number of output points to be computed. + * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2]. + */ + +arm_status arm_conv_partial_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, + q7_t *pDst, uint32_t firstIndex, uint32_t numPoints); + +/** + * @brief Instance structure for the Q15 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ +} arm_fir_decimate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR decimator. + */ + +typedef struct { + uint8_t M; /**< decimation factor. */ + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + +} arm_fir_decimate_instance_f32; + +/** + * @brief Processing function for the floating-point FIR decimator. + * @param[in] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_f32(const arm_fir_decimate_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR decimator. + * @param[in,out] *S points to an instance of the floating-point FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_f32(arm_fir_decimate_instance_f32 *S, uint16_t numTaps, uint8_t M, + float32_t *pCoeffs, float32_t *pState, uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q15(const arm_fir_decimate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR decimator. + * @param[in,out] *S points to an instance of the Q15 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q15(arm_fir_decimate_instance_q15 *S, uint16_t numTaps, uint8_t M, + q15_t *pCoeffs, q15_t *pState, uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_q31(const arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4. + * @param[in] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of input samples to process per call. + * @return none + */ + +void arm_fir_decimate_fast_q31(arm_fir_decimate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR decimator. + * @param[in,out] *S points to an instance of the Q31 FIR decimator structure. + * @param[in] numTaps number of coefficients in the filter. + * @param[in] M decimation factor. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * blockSize is not a multiple of M. + */ + +arm_status arm_fir_decimate_init_q31(arm_fir_decimate_instance_q31 *S, uint16_t numTaps, uint8_t M, + q31_t *pCoeffs, q31_t *pState, uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q15_t * + pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + q31_t * + pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */ +} arm_fir_interpolate_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR interpolator. + */ + +typedef struct { + uint8_t L; /**< upsample factor. */ + uint16_t phaseLength; /**< length of each polyphase filter component. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */ + float32_t * + pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */ +} arm_fir_interpolate_instance_f32; + +/** + * @brief Processing function for the Q15 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q15(const arm_fir_interpolate_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 FIR interpolator. + * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q15(arm_fir_interpolate_instance_q15 *S, uint8_t L, + uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 FIR interpolator. + * @param[in] *S points to an instance of the Q15 FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_q31(const arm_fir_interpolate_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR interpolator. + * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_q31(arm_fir_interpolate_instance_q31 *S, uint8_t L, + uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, + uint32_t blockSize); + +/** + * @brief Processing function for the floating-point FIR interpolator. + * @param[in] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_interpolate_f32(const arm_fir_interpolate_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR interpolator. + * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure. + * @param[in] L upsample factor. + * @param[in] numTaps number of filter coefficients in the filter. + * @param[in] *pCoeffs points to the filter coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] blockSize number of input samples to process per call. + * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if + * the filter length numTaps is not a multiple of the interpolation factor L. + */ + +arm_status arm_fir_interpolate_init_f32(arm_fir_interpolate_instance_f32 *S, uint8_t L, + uint16_t numTaps, float32_t *pCoeffs, float32_t *pState, + uint32_t blockSize); + +/** + * @brief Instance structure for the high precision Q31 Biquad cascade filter. + */ + +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + q63_t * + pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */ + q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ + uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */ + +} arm_biquad_cas_df1_32x64_ins_q31; + +/** + * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cas_df1_32x64_q31(const arm_biquad_cas_df1_32x64_ins_q31 *S, q31_t *pSrc, + q31_t *pDst, uint32_t blockSize); + +/** + * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format + * @return none + */ + +void arm_biquad_cas_df1_32x64_init_q31(arm_biquad_cas_df1_32x64_ins_q31 *S, uint8_t numStages, + q31_t *pCoeffs, q63_t *pState, uint8_t postShift); + +/** + * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter. + */ + +typedef struct { + uint8_t + numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */ + float32_t * + pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */ + float32_t + *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */ +} arm_biquad_cascade_df2T_instance_f32; + +/** + * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in] *S points to an instance of the filter data structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_biquad_cascade_df2T_f32(const arm_biquad_cascade_df2T_instance_f32 *S, float32_t *pSrc, + float32_t *pDst, uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter. + * @param[in,out] *S points to an instance of the filter data structure. + * @param[in] numStages number of 2nd order stages in the filter. + * @param[in] *pCoeffs points to the filter coefficients. + * @param[in] *pState points to the state buffer. + * @return none + */ + +void arm_biquad_cascade_df2T_init_f32(arm_biquad_cascade_df2T_instance_f32 *S, uint8_t numStages, + float32_t *pCoeffs, float32_t *pState); + +/** + * @brief Instance structure for the Q15 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q15_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + q31_t *pState; /**< points to the state variable array. The array is of length numStages. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point FIR lattice filter. + */ + +typedef struct { + uint16_t numStages; /**< number of filter stages. */ + float32_t *pState; /**< points to the state variable array. The array is of length numStages. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */ +} arm_fir_lattice_instance_f32; + +/** + * @brief Initialization function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q15(arm_fir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pCoeffs, + q15_t *pState); + +/** + * @brief Processing function for the Q15 FIR lattice filter. + * @param[in] *S points to an instance of the Q15 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ +void arm_fir_lattice_q15(const arm_fir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_q31(arm_fir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pCoeffs, + q31_t *pState); + +/** + * @brief Processing function for the Q31 FIR lattice filter. + * @param[in] *S points to an instance of the Q31 FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_q31(const arm_fir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] numStages number of filter stages. + * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages. + * @param[in] *pState points to the state buffer. The array is of length numStages. + * @return none. + */ + +void arm_fir_lattice_init_f32(arm_fir_lattice_instance_f32 *S, uint16_t numStages, + float32_t *pCoeffs, float32_t *pState); + +/** + * @brief Processing function for the floating-point FIR lattice filter. + * @param[in] *S points to an instance of the floating-point FIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_fir_lattice_f32(const arm_fir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q15_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q15_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q15; + +/** + * @brief Instance structure for the Q31 IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + q31_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + q31_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_q31; + +/** + * @brief Instance structure for the floating-point IIR lattice filter. + */ +typedef struct { + uint16_t numStages; /**< number of stages in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numStages+blockSize. */ + float32_t * + pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */ + float32_t * + pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */ +} arm_iir_lattice_instance_f32; + +/** + * @brief Processing function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_f32(const arm_iir_lattice_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point IIR lattice filter. + * @param[in] *S points to an instance of the floating-point IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_f32(arm_iir_lattice_instance_f32 *S, uint16_t numStages, + float32_t *pkCoeffs, float32_t *pvCoeffs, float32_t *pState, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q31(const arm_iir_lattice_instance_q31 *S, q31_t *pSrc, q31_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 IIR lattice filter. + * @param[in] *S points to an instance of the Q31 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_init_q31(arm_iir_lattice_instance_q31 *S, uint16_t numStages, q31_t *pkCoeffs, + q31_t *pvCoeffs, q31_t *pState, uint32_t blockSize); + +/** + * @brief Processing function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the Q15 IIR lattice structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_iir_lattice_q15(const arm_iir_lattice_instance_q15 *S, q15_t *pSrc, q15_t *pDst, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 IIR lattice filter. + * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure. + * @param[in] numStages number of stages in the filter. + * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages. + * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1. + * @param[in] *pState points to state buffer. The array is of length numStages+blockSize. + * @param[in] blockSize number of samples to process per call. + * @return none. + */ + +void arm_iir_lattice_init_q15(arm_iir_lattice_instance_q15 *S, uint16_t numStages, q15_t *pkCoeffs, + q15_t *pvCoeffs, q15_t *pState, uint32_t blockSize); + +/** + * @brief Instance structure for the floating-point LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that controls filter coefficient updates. */ +} arm_lms_instance_f32; + +/** + * @brief Processing function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_f32(const arm_lms_instance_f32 *S, float32_t *pSrc, float32_t *pRef, float32_t *pOut, + float32_t *pErr, uint32_t blockSize); + +/** + * @brief Initialization function for floating-point LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_init_f32(arm_lms_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, float32_t mu, uint32_t blockSize); + +/** + * @brief Instance structure for the Q15 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ +} arm_lms_instance_q15; + +/** + * @brief Initialization function for the Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to the coefficient buffer. + * @param[in] *pState points to the state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q15(arm_lms_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, q15_t *pState, + q15_t mu, uint32_t blockSize, uint32_t postShift); + +/** + * @brief Processing function for Q15 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q15(const arm_lms_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, q15_t *pErr, + uint32_t blockSize); + +/** + * @brief Instance structure for the Q31 LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint32_t postShift; /**< bit shift applied to coefficients. */ + +} arm_lms_instance_q31; + +/** + * @brief Processing function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q15 LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_q31(const arm_lms_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, q31_t *pErr, + uint32_t blockSize); + +/** + * @brief Initialization function for Q31 LMS filter. + * @param[in] *S points to an instance of the Q31 LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_init_q31(arm_lms_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, q31_t *pState, + q31_t mu, uint32_t blockSize, uint32_t postShift); + +/** + * @brief Instance structure for the floating-point normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + float32_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + float32_t mu; /**< step size that control filter coefficient updates. */ + float32_t energy; /**< saves previous frame energy. */ + float32_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_f32; + +/** + * @brief Processing function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_f32(arm_lms_norm_instance_f32 *S, float32_t *pSrc, float32_t *pRef, + float32_t *pOut, float32_t *pErr, uint32_t blockSize); + +/** + * @brief Initialization function for floating-point normalized LMS filter. + * @param[in] *S points to an instance of the floating-point LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_init_f32(arm_lms_norm_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, float32_t mu, uint32_t blockSize); + +/** + * @brief Instance structure for the Q31 normalized LMS filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + q31_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q31_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q31_t *recipTable; /**< points to the reciprocal initial value table. */ + q31_t energy; /**< saves previous frame energy. */ + q31_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q31; + +/** + * @brief Processing function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q31(arm_lms_norm_instance_q31 *S, q31_t *pSrc, q31_t *pRef, q31_t *pOut, + q31_t *pErr, uint32_t blockSize); + +/** + * @brief Initialization function for Q31 normalized LMS filter. + * @param[in] *S points to an instance of the Q31 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q31(arm_lms_norm_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, + q31_t *pState, q31_t mu, uint32_t blockSize, uint8_t postShift); + +/** + * @brief Instance structure for the Q15 normalized LMS filter. + */ + +typedef struct { + uint16_t numTaps; /**< Number of coefficients in the filter. */ + q15_t * + pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */ + q15_t mu; /**< step size that controls filter coefficient updates. */ + uint8_t postShift; /**< bit shift applied to coefficients. */ + q15_t *recipTable; /**< Points to the reciprocal initial value table. */ + q15_t energy; /**< saves previous frame energy. */ + q15_t x0; /**< saves previous input sample. */ +} arm_lms_norm_instance_q15; + +/** + * @brief Processing function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] *pSrc points to the block of input data. + * @param[in] *pRef points to the block of reference data. + * @param[out] *pOut points to the block of output data. + * @param[out] *pErr points to the block of error data. + * @param[in] blockSize number of samples to process. + * @return none. + */ + +void arm_lms_norm_q15(arm_lms_norm_instance_q15 *S, q15_t *pSrc, q15_t *pRef, q15_t *pOut, + q15_t *pErr, uint32_t blockSize); + +/** + * @brief Initialization function for Q15 normalized LMS filter. + * @param[in] *S points to an instance of the Q15 normalized LMS filter structure. + * @param[in] numTaps number of filter coefficients. + * @param[in] *pCoeffs points to coefficient buffer. + * @param[in] *pState points to state buffer. + * @param[in] mu step size that controls filter coefficient updates. + * @param[in] blockSize number of samples to process. + * @param[in] postShift bit shift applied to coefficients. + * @return none. + */ + +void arm_lms_norm_init_q15(arm_lms_norm_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, + q15_t *pState, q15_t mu, uint32_t blockSize, uint8_t postShift); + +/** + * @brief Correlation of floating-point sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_f32(float32_t *pSrcA, uint32_t srcALen, float32_t *pSrcB, uint32_t srcBLen, + float32_t *pDst); + +/** + * @brief Correlation of Q15 sequences + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ +void arm_correlate_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, q15_t *pScratch); + +/** + * @brief Correlation of Q15 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, q15_t *pDst); + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst); + +/** + * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @return none. + */ + +void arm_correlate_fast_opt_q15(q15_t *pSrcA, uint32_t srcALen, q15_t *pSrcB, uint32_t srcBLen, + q15_t *pDst, q15_t *pScratch); + +/** + * @brief Correlation of Q31 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, q31_t *pDst); + +/** + * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4 + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_fast_q31(q31_t *pSrcA, uint32_t srcALen, q31_t *pSrcB, uint32_t srcBLen, + q31_t *pDst); + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2. + * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen). + * @return none. + */ + +void arm_correlate_opt_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst, + q15_t *pScratch1, q15_t *pScratch2); + +/** + * @brief Correlation of Q7 sequences. + * @param[in] *pSrcA points to the first input sequence. + * @param[in] srcALen length of the first input sequence. + * @param[in] *pSrcB points to the second input sequence. + * @param[in] srcBLen length of the second input sequence. + * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1. + * @return none. + */ + +void arm_correlate_q7(q7_t *pSrcA, uint32_t srcALen, q7_t *pSrcB, uint32_t srcBLen, q7_t *pDst); + +/** + * @brief Instance structure for the floating-point sparse FIR filter. + */ +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + float32_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_f32; + +/** + * @brief Instance structure for the Q31 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q31_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q31; + +/** + * @brief Instance structure for the Q15 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q15_t * + pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q15; + +/** + * @brief Instance structure for the Q7 sparse FIR filter. + */ + +typedef struct { + uint16_t numTaps; /**< number of coefficients in the filter. */ + uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */ + q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */ + q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/ + uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */ + int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */ +} arm_fir_sparse_instance_q7; + +/** + * @brief Processing function for the floating-point sparse FIR filter. + * @param[in] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_f32(arm_fir_sparse_instance_f32 *S, float32_t *pSrc, float32_t *pDst, + float32_t *pScratchIn, uint32_t blockSize); + +/** + * @brief Initialization function for the floating-point sparse FIR filter. + * @param[in,out] *S points to an instance of the floating-point sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_f32(arm_fir_sparse_instance_f32 *S, uint16_t numTaps, float32_t *pCoeffs, + float32_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q31 sparse FIR filter. + * @param[in] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q31(arm_fir_sparse_instance_q31 *S, q31_t *pSrc, q31_t *pDst, q31_t *pScratchIn, + uint32_t blockSize); + +/** + * @brief Initialization function for the Q31 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q31 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q31(arm_fir_sparse_instance_q31 *S, uint16_t numTaps, q31_t *pCoeffs, + q31_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q15 sparse FIR filter. + * @param[in] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q15(arm_fir_sparse_instance_q15 *S, q15_t *pSrc, q15_t *pDst, q15_t *pScratchIn, + q31_t *pScratchOut, uint32_t blockSize); + +/** + * @brief Initialization function for the Q15 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q15 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q15(arm_fir_sparse_instance_q15 *S, uint16_t numTaps, q15_t *pCoeffs, + q15_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); + +/** + * @brief Processing function for the Q7 sparse FIR filter. + * @param[in] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] *pSrc points to the block of input data. + * @param[out] *pDst points to the block of output data + * @param[in] *pScratchIn points to a temporary buffer of size blockSize. + * @param[in] *pScratchOut points to a temporary buffer of size blockSize. + * @param[in] blockSize number of input samples to process per call. + * @return none. + */ + +void arm_fir_sparse_q7(arm_fir_sparse_instance_q7 *S, q7_t *pSrc, q7_t *pDst, q7_t *pScratchIn, + q31_t *pScratchOut, uint32_t blockSize); + +/** + * @brief Initialization function for the Q7 sparse FIR filter. + * @param[in,out] *S points to an instance of the Q7 sparse FIR structure. + * @param[in] numTaps number of nonzero coefficients in the filter. + * @param[in] *pCoeffs points to the array of filter coefficients. + * @param[in] *pState points to the state buffer. + * @param[in] *pTapDelay points to the array of offset times. + * @param[in] maxDelay maximum offset time supported. + * @param[in] blockSize number of samples that will be processed per block. + * @return none + */ + +void arm_fir_sparse_init_q7(arm_fir_sparse_instance_q7 *S, uint16_t numTaps, q7_t *pCoeffs, + q7_t *pState, int32_t *pTapDelay, uint16_t maxDelay, + uint32_t blockSize); + +/* + * @brief Floating-point sin_cos function. + * @param[in] theta input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cos output. + * @return none. + */ + +void arm_sin_cos_f32(float32_t theta, float32_t *pSinVal, float32_t *pCcosVal); + +/* + * @brief Q31 sin_cos function. + * @param[in] theta scaled input value in degrees + * @param[out] *pSinVal points to the processed sine output. + * @param[out] *pCosVal points to the processed cosine output. + * @return none. + */ + +void arm_sin_cos_q31(q31_t theta, q31_t *pSinVal, q31_t *pCosVal); + +/** + * @brief Floating-point complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); + +/** + * @brief Q31 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +/** + * @brief Q15 complex conjugate. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_conj_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +/** + * @brief Floating-point complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); + +/** + * @brief Q31 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +/** + * @brief Q15 complex magnitude squared + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_squared_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +/** + * @ingroup groupController + */ + +/** + * @defgroup PID PID Motor Control + * + * A Proportional Integral Derivative (PID) controller is a generic feedback control + * loop mechanism widely used in industrial control systems. + * A PID controller is the most commonly used type of feedback controller. + * + * This set of functions implements (PID) controllers + * for Q15, Q31, and floating-point data types. The functions operate on a single sample + * of data and each call to the function returns a single processed value. + * S points to an instance of the PID control data structure. in + * is the input sample value. The functions return the output value. + * + * \par Algorithm: + * 
+   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd
+ * + * \par + * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant + * + * \par + * \image html PID.gif "Proportional Integral Derivative Controller" + * + * \par + * The PID controller calculates an "error" value as the difference between + * the measured output and the reference input. + * The controller attempts to minimize the error by adjusting the process control inputs. + * The proportional value determines the reaction to the current error, + * the integral value determines the reaction based on the sum of recent errors, + * and the derivative value determines the reaction based on the rate at which the error has been changing. + * + * \par Instance Structure + * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. + * A separate instance structure must be defined for each PID Controller. + * There are separate instance structure declarations for each of the 3 supported data types. + * + * \par Reset Functions + * There is also an associated reset function for each data type which clears the state array. + * + * \par Initialization Functions + * There is also an associated initialization function for each data type. + * The initialization function performs the following operations: + * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains. + * - Zeros out the values in the state buffer. + * + * \par + * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. + * + * \par Fixed-Point Behavior + * Care must be taken when using the fixed-point versions of the PID Controller functions. + * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup PID + * @{ + */ + +/** + * @brief Process function for the floating-point PID Control. + * @param[in,out] *S is an instance of the floating-point PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + */ + +static __INLINE float32_t arm_pid_f32(arm_pid_instance_f32 *S, float32_t in) +{ + float32_t out; + + /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */ + out = (S->A0 * in) + (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @brief Process function for the Q31 PID Control. + * @param[in,out] *S points to an instance of the Q31 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 64-bit accumulator. + * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. + * Thus, if the accumulator result overflows it wraps around rather than clip. + * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. + * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. + */ + +static __INLINE q31_t arm_pid_q31(arm_pid_instance_q31 *S, q31_t in) +{ + q63_t acc; + q31_t out; + + /* acc = A0 * x[n] */ + acc = (q63_t)S->A0 * in; + + /* acc += A1 * x[n-1] */ + acc += (q63_t)S->A1 * S->state[0]; + + /* acc += A2 * x[n-2] */ + acc += (q63_t)S->A2 * S->state[1]; + + /* convert output to 1.31 format to add y[n-1] */ + out = (q31_t)(acc >> 31u); + + /* out += y[n-1] */ + out += S->state[2]; + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @brief Process function for the Q15 PID Control. + * @param[in,out] *S points to an instance of the Q15 PID Control structure + * @param[in] in input sample to process + * @return out processed output sample. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using a 64-bit internal accumulator. + * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. + * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. + * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. + * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. + * Lastly, the accumulator is saturated to yield a result in 1.15 format. + */ + +static __INLINE q15_t arm_pid_q15(arm_pid_instance_q15 *S, q15_t in) +{ + q63_t acc; + q15_t out; + +#ifndef ARM_MATH_CM0_FAMILY + __SIMD32_TYPE *vstate; + + /* Implementation of PID controller */ + + /* acc = A0 * x[n] */ + acc = (q31_t)__SMUAD(S->A0, in); + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + vstate = __SIMD32_CONST(S->state); + acc = __SMLALD(S->A1, (q31_t)*vstate, acc); + +#else + /* acc = A0 * x[n] */ + acc = ((q31_t)S->A0) * in; + + /* acc += A1 * x[n-1] + A2 * x[n-2] */ + acc += (q31_t)S->A1 * S->state[0]; + acc += (q31_t)S->A2 * S->state[1]; + +#endif + + /* acc += y[n-1] */ + acc += (q31_t)S->state[2] << 15; + + /* saturate the output */ + out = (q15_t)(__SSAT((acc >> 15), 16)); + + /* Update state */ + S->state[1] = S->state[0]; + S->state[0] = in; + S->state[2] = out; + + /* return to application */ + return (out); +} + +/** + * @} end of PID group + */ + +/** + * @brief Floating-point matrix inverse. + * @param[in] *src points to the instance of the input floating-point matrix structure. + * @param[out] *dst points to the instance of the output floating-point matrix structure. + * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match. + * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR. + */ + +arm_status arm_mat_inverse_f32(const arm_matrix_instance_f32 *src, arm_matrix_instance_f32 *dst); + +/** + * @ingroup groupController + */ + +/** + * @defgroup clarke Vector Clarke Transform + * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector. + * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents + * in the two-phase orthogonal stator axis Ialpha and Ibeta. + * When Ialpha is superposed with Ia as shown in the figure below + * \image html clarke.gif Stator current space vector and its components in (a,b). + * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta + * can be calculated using only Ia and Ib. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeFormula.gif + * where Ia and Ib are the instantaneous stator phases and + * pIalpha and pIbeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup clarke + * @{ + */ + +/** + * + * @brief Floating-point Clarke transform + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + */ + +static __INLINE void arm_clarke_f32(float32_t Ia, float32_t Ib, float32_t *pIalpha, + float32_t *pIbeta) +{ + /* Calculate pIalpha using the equation, pIalpha = Ia */ + *pIalpha = Ia; + + /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */ + *pIbeta = ((float32_t)0.57735026919 * Ia + (float32_t)1.15470053838 * Ib); +} + +/** + * @brief Clarke transform for Q31 version + * @param[in] Ia input three-phase coordinate a + * @param[in] Ib input three-phase coordinate b + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + +static __INLINE void arm_clarke_q31(q31_t Ia, q31_t Ib, q31_t *pIalpha, q31_t *pIbeta) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIalpha from Ia by equation pIalpha = Ia */ + *pIalpha = Ia; + + /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)Ia * 0x24F34E8B) >> 30); + + /* Intermediate product is calculated by (2/sqrt(3) * Ib) */ + product2 = (q31_t)(((q63_t)Ib * 0x49E69D16) >> 30); + + /* pIbeta is calculated by adding the intermediate products */ + *pIbeta = __QADD(product1, product2); +} + +/** + * @} end of clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q31 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q31(q7_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_clarke Vector Inverse Clarke Transform + * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html clarkeInvFormula.gif + * where pIa and pIb are the instantaneous stator phases and + * Ialpha and Ibeta are the two coordinates of time invariant vector. + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Clarke transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_clarke + * @{ + */ + +/** + * @brief Floating-point Inverse Clarke transform + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + */ + +static __INLINE void arm_inv_clarke_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pIa, + float32_t *pIb) +{ + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */ + *pIb = -0.5 * Ialpha + (float32_t)0.8660254039 * Ibeta; +} + +/** + * @brief Inverse Clarke transform for Q31 version + * @param[in] Ialpha input two-phase orthogonal vector axis alpha + * @param[in] Ibeta input two-phase orthogonal vector axis beta + * @param[out] *pIa points to output three-phase coordinate a + * @param[out] *pIb points to output three-phase coordinate b + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the subtraction, hence there is no risk of overflow. + */ + +static __INLINE void arm_inv_clarke_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pIa, q31_t *pIb) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + + /* Calculating pIa from Ialpha by equation pIa = Ialpha */ + *pIa = Ialpha; + + /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (0x40000000)) >> 31); + + /* Intermediate product is calculated by (1/sqrt(3) * pIb) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (0x6ED9EBA1)) >> 31); + + /* pIb is calculated by subtracting the products */ + *pIb = __QSUB(product2, product1); +} + +/** + * @} end of inv_clarke group + */ + +/** + * @brief Converts the elements of the Q7 vector to Q15 vector. + * @param[in] *pSrc input pointer + * @param[out] *pDst output pointer + * @param[in] blockSize number of samples to process + * @return none. + */ +void arm_q7_to_q15(q7_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @ingroup groupController + */ + +/** + * @defgroup park Vector Park Transform + * + * Forward Park transform converts the input two-coordinate vector to flux and torque components. + * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents + * from the stationary to the moving reference frame and control the spatial relationship between + * the stator vector current and rotor flux vector. + * If we consider the d axis aligned with the rotor flux, the diagram below shows the + * current vector and the relationship from the two reference frames: + * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame" + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkFormula.gif + * where Ialpha and Ibeta are the stator vector components, + * pId and pIq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup park + * @{ + */ + +/** + * @brief Floating-point Park transform + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * The function implements the forward Park transform. + * + */ + +static __INLINE void arm_park_f32(float32_t Ialpha, float32_t Ibeta, float32_t *pId, float32_t *pIq, + float32_t sinVal, float32_t cosVal) +{ + /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */ + *pId = Ialpha * cosVal + Ibeta * sinVal; + + /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */ + *pIq = -Ialpha * sinVal + Ibeta * cosVal; +} + +/** + * @brief Park transform for Q31 version + * @param[in] Ialpha input two-phase vector coordinate alpha + * @param[in] Ibeta input two-phase vector coordinate beta + * @param[out] *pId points to output rotor reference frame d + * @param[out] *pIq points to output rotor reference frame q + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition and subtraction, hence there is no risk of overflow. + */ + +static __INLINE void arm_park_q31(q31_t Ialpha, q31_t Ibeta, q31_t *pId, q31_t *pIq, q31_t sinVal, + q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Ialpha * cosVal) */ + product1 = (q31_t)(((q63_t)(Ialpha) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * sinVal) */ + product2 = (q31_t)(((q63_t)(Ibeta) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ialpha * sinVal) */ + product3 = (q31_t)(((q63_t)(Ialpha) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Ibeta * cosVal) */ + product4 = (q31_t)(((q63_t)(Ibeta) * (cosVal)) >> 31); + + /* Calculate pId by adding the two intermediate products 1 and 2 */ + *pId = __QADD(product1, product2); + + /* Calculate pIq by subtracting the two intermediate products 3 from 4 */ + *pIq = __QSUB(product4, product3); +} + +/** + * @} end of park group + */ + +/** + * @brief Converts the elements of the Q7 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q7_to_float(q7_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @ingroup groupController + */ + +/** + * @defgroup inv_park Vector Inverse Park transform + * Inverse Park transform converts the input flux and torque components to two-coordinate vector. + * + * The function operates on a single sample of data and each call to the function returns the processed output. + * The library provides separate functions for Q31 and floating-point data types. + * \par Algorithm + * \image html parkInvFormula.gif + * where pIalpha and pIbeta are the stator vector components, + * Id and Iq are rotor vector components and cosVal and sinVal are the + * cosine and sine values of theta (rotor flux position). + * \par Fixed-Point Behavior + * Care must be taken when using the Q31 version of the Park transform. + * In particular, the overflow and saturation behavior of the accumulator used must be considered. + * Refer to the function specific documentation below for usage guidelines. + */ + +/** + * @addtogroup inv_park + * @{ + */ + +/** + * @brief Floating-point Inverse Park transform + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + */ + +static __INLINE void arm_inv_park_f32(float32_t Id, float32_t Iq, float32_t *pIalpha, + float32_t *pIbeta, float32_t sinVal, float32_t cosVal) +{ + /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */ + *pIalpha = Id * cosVal - Iq * sinVal; + + /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */ + *pIbeta = Id * sinVal + Iq * cosVal; +} + +/** + * @brief Inverse Park transform for Q31 version + * @param[in] Id input coordinate of rotor reference frame d + * @param[in] Iq input coordinate of rotor reference frame q + * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha + * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta + * @param[in] sinVal sine value of rotation angle theta + * @param[in] cosVal cosine value of rotation angle theta + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function is implemented using an internal 32-bit accumulator. + * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format. + * There is saturation on the addition, hence there is no risk of overflow. + */ + +static __INLINE void arm_inv_park_q31(q31_t Id, q31_t Iq, q31_t *pIalpha, q31_t *pIbeta, + q31_t sinVal, q31_t cosVal) +{ + q31_t product1, product2; /* Temporary variables used to store intermediate results */ + q31_t product3, product4; /* Temporary variables used to store intermediate results */ + + /* Intermediate product is calculated by (Id * cosVal) */ + product1 = (q31_t)(((q63_t)(Id) * (cosVal)) >> 31); + + /* Intermediate product is calculated by (Iq * sinVal) */ + product2 = (q31_t)(((q63_t)(Iq) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Id * sinVal) */ + product3 = (q31_t)(((q63_t)(Id) * (sinVal)) >> 31); + + /* Intermediate product is calculated by (Iq * cosVal) */ + product4 = (q31_t)(((q63_t)(Iq) * (cosVal)) >> 31); + + /* Calculate pIalpha by using the two intermediate products 1 and 2 */ + *pIalpha = __QSUB(product1, product2); + + /* Calculate pIbeta by using the two intermediate products 3 and 4 */ + *pIbeta = __QADD(product4, product3); +} + +/** + * @} end of Inverse park group + */ + +/** + * @brief Converts the elements of the Q31 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_float(q31_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup LinearInterpolate Linear Interpolation + * + * Linear interpolation is a method of curve fitting using linear polynomials. + * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line + * + * \par + * \image html LinearInterp.gif "Linear interpolation" + * + * \par + * A Linear Interpolate function calculates an output value(y), for the input(x) + * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values) + * + * \par Algorithm: + * 
+   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   *
+ * + * \par + * This set of functions implements Linear interpolation process + * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single + * sample of data and each call to the function returns a single processed value. + * S points to an instance of the Linear Interpolate function data structure. + * x is the input sample value. The functions returns the output value. + * + * \par + * if x is outside of the table boundary, Linear interpolation returns first value of the table + * if x is below input range and returns last value of table if x is above range. + */ + +/** + * @addtogroup LinearInterpolate + * @{ + */ + +/** + * @brief Process function for the floating-point Linear Interpolation Function. + * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure + * @param[in] x input sample to process + * @return y processed output sample. + * + */ + +static __INLINE float32_t arm_linear_interp_f32(arm_linear_interp_instance_f32 *S, float32_t x) +{ + float32_t y; + float32_t x0, x1; /* Nearest input values */ + float32_t y0, y1; /* Nearest output values */ + float32_t xSpacing = S->xSpacing; /* spacing between input values */ + int32_t i; /* Index variable */ + float32_t *pYData = S->pYData; /* pointer to output table */ + + /* Calculation of index */ + i = (int32_t)((x - S->x1) / xSpacing); + + if (i < 0) { + /* Iniatilize output for below specified range as least output value of table */ + y = pYData[0]; + } else if ((uint32_t)i >= S->nValues) { + /* Iniatilize output for above specified range as last output value of table */ + y = pYData[S->nValues - 1]; + } else { + /* Calculation of nearest input values */ + x0 = S->x1 + i * xSpacing; + x1 = S->x1 + (i + 1) * xSpacing; + + /* Read of nearest output values */ + y0 = pYData[i]; + y1 = pYData[i + 1]; + + /* Calculation of output */ + y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0)); + } + + /* returns output value */ + return (y); +} + +/** + * + * @brief Process function for the Q31 Linear Interpolation Function. + * @param[in] *pYData pointer to Q31 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + +static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData, q31_t x, uint32_t nValues) +{ + q31_t y; /* output */ + q31_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } else if (index < 0) { + return (pYData[0]); + } else { + /* 20 bits for the fractional part */ + /* shift left by 11 to keep fract in 1.31 format */ + fract = (x & 0x000FFFFF) << 11; + + /* Read two nearest output values from the index in 1.31(q31) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 2.30 format */ + y = ((q31_t)((q63_t)y0 * (0x7FFFFFFF - fract) >> 32)); + + /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */ + y += ((q31_t)(((q63_t)y1 * fract) >> 32)); + + /* Convert y to 1.31 format */ + return (y << 1u); + } +} + +/** + * + * @brief Process function for the Q15 Linear Interpolation Function. + * @param[in] *pYData pointer to Q15 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + * + */ + +static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues) +{ + q63_t y; /* output */ + q15_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + int32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + index = ((x & 0xFFF00000) >> 20u); + + if (index >= (int32_t)(nValues - 1)) { + return (pYData[nValues - 1]); + } else if (index < 0) { + return (pYData[0]); + } else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract) and y is in 13.35 format */ + y = ((q63_t)y0 * (0xFFFFF - fract)); + + /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */ + y += ((q63_t)y1 * (fract)); + + /* convert y to 1.15 format */ + return (y >> 20); + } +} + +/** + * + * @brief Process function for the Q7 Linear Interpolation Function. + * @param[in] *pYData pointer to Q7 Linear Interpolation table + * @param[in] x input sample to process + * @param[in] nValues number of table values + * @return y processed output sample. + * + * \par + * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part. + * This function can support maximum of table size 2^12. + */ + +static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x, uint32_t nValues) +{ + q31_t y; /* output */ + q7_t y0, y1; /* Nearest output values */ + q31_t fract; /* fractional part */ + uint32_t index; /* Index to read nearest output values */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + if (x < 0) { + return (pYData[0]); + } + index = (x >> 20) & 0xfff; + + if (index >= (nValues - 1)) { + return (pYData[nValues - 1]); + } else { + /* 20 bits for the fractional part */ + /* fract is in 12.20 format */ + fract = (x & 0x000FFFFF); + + /* Read two nearest output values from the index and are in 1.7(q7) format */ + y0 = pYData[index]; + y1 = pYData[index + 1u]; + + /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */ + y = ((y0 * (0xFFFFF - fract))); + + /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */ + y += (y1 * fract); + + /* convert y to 1.7(q7) format */ + return (y >> 20u); + } +} +/** + * @} end of LinearInterpolate group + */ + +/** + * @brief Fast approximation to the trigonometric sine function for floating-point data. + * @param[in] x input value in radians. + * @return sin(x). + */ + +float32_t arm_sin_f32(float32_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q31_t arm_sin_q31(q31_t x); + +/** + * @brief Fast approximation to the trigonometric sine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return sin(x). + */ + +q15_t arm_sin_q15(q15_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for floating-point data. + * @param[in] x input value in radians. + * @return cos(x). + */ + +float32_t arm_cos_f32(float32_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q31 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q31_t arm_cos_q31(q31_t x); + +/** + * @brief Fast approximation to the trigonometric cosine function for Q15 data. + * @param[in] x Scaled input value in radians. + * @return cos(x). + */ + +q15_t arm_cos_q15(q15_t x); + +/** + * @ingroup groupFastMath + */ + +/** + * @defgroup SQRT Square Root + * + * Computes the square root of a number. + * There are separate functions for Q15, Q31, and floating-point data types. + * The square root function is computed using the Newton-Raphson algorithm. + * This is an iterative algorithm of the form: + * 
+   *      x1 = x0 - f(x0)/f'(x0)
+   *
+ * where x1 is the current estimate, + * x0 is the previous estimate, and + * f'(x0) is the derivative of f() evaluated at x0. + * For the square root function, the algorithm reduces to: + * 
+   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   *
+ */ + +/** + * @addtogroup SQRT + * @{ + */ + +/** + * @brief Floating-point square root function. + * @param[in] in input value. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ + +static __INLINE arm_status arm_sqrt_f32(float32_t in, float32_t *pOut) +{ + if (in > 0) { +// #if __FPU_USED +#if (__FPU_USED == 1) && defined(__CC_ARM) + *pOut = __sqrtf(in); +#else + *pOut = sqrtf(in); +#endif + + return (ARM_MATH_SUCCESS); + } else { + *pOut = 0.0f; + return (ARM_MATH_ARGUMENT_ERROR); + } +} + +/** + * @brief Q31 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q31(q31_t in, q31_t *pOut); + +/** + * @brief Q15 square root function. + * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. + * @param[out] *pOut square root of input value. + * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if + * in is negative value and returns zero output for negative values. + */ +arm_status arm_sqrt_q15(q15_t in, q15_t *pOut); + +/** + * @} end of SQRT group + */ + +/** + * @brief floating-point Circular write function. + */ + +static __INLINE void arm_circularWrite_f32(int32_t *circBuffer, int32_t L, uint16_t *writeOffset, + int32_t bufferInc, const int32_t *src, int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + +/** + * @brief floating-point Circular Read function. + */ +static __INLINE void arm_circularRead_f32(int32_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, int32_t *dst, int32_t *dst_base, + int32_t dst_length, int32_t dstInc, uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (int32_t *)dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + * @brief Q15 Circular write function. + */ + +static __INLINE void arm_circularWrite_q15(q15_t *circBuffer, int32_t L, uint16_t *writeOffset, + int32_t bufferInc, const q15_t *src, int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + +/** + * @brief Q15 Circular Read function. + */ +static __INLINE void arm_circularRead_q15(q15_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, q15_t *dst, q15_t *dst_base, + int32_t dst_length, int32_t dstInc, uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q15_t *)dst_end) { + dst = dst_base; + } + + /* Circularly update wOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + * @brief Q7 Circular write function. + */ + +static __INLINE void arm_circularWrite_q7(q7_t *circBuffer, int32_t L, uint16_t *writeOffset, + int32_t bufferInc, const q7_t *src, int32_t srcInc, + uint32_t blockSize) +{ + uint32_t i = 0u; + int32_t wOffset; + + /* Copy the value of Index pointer that points + * to the current location where the input samples to be copied */ + wOffset = *writeOffset; + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the input sample to the circular buffer */ + circBuffer[wOffset] = *src; + + /* Update the input pointer */ + src += srcInc; + + /* Circularly update wOffset. Watch out for positive and negative value */ + wOffset += bufferInc; + if (wOffset >= L) + wOffset -= L; + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *writeOffset = wOffset; +} + +/** + * @brief Q7 Circular Read function. + */ +static __INLINE void arm_circularRead_q7(q7_t *circBuffer, int32_t L, int32_t *readOffset, + int32_t bufferInc, q7_t *dst, q7_t *dst_base, + int32_t dst_length, int32_t dstInc, uint32_t blockSize) +{ + uint32_t i = 0; + int32_t rOffset, dst_end; + + /* Copy the value of Index pointer that points + * to the current location from where the input samples to be read */ + rOffset = *readOffset; + + dst_end = (int32_t)(dst_base + dst_length); + + /* Loop over the blockSize */ + i = blockSize; + + while (i > 0u) { + /* copy the sample from the circular buffer to the destination buffer */ + *dst = circBuffer[rOffset]; + + /* Update the input pointer */ + dst += dstInc; + + if (dst == (q7_t *)dst_end) { + dst = dst_base; + } + + /* Circularly update rOffset. Watch out for positive and negative value */ + rOffset += bufferInc; + + if (rOffset >= L) { + rOffset -= L; + } + + /* Decrement the loop counter */ + i--; + } + + /* Update the index pointer */ + *readOffset = rOffset; +} + +/** + * @brief Sum of the squares of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult); + +/** + * @brief Sum of the squares of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +/** + * @brief Sum of the squares of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q15(q15_t *pSrc, uint32_t blockSize, q63_t *pResult); + +/** + * @brief Sum of the squares of the elements of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_power_q7(q7_t *pSrc, uint32_t blockSize, q31_t *pResult); + +/** + * @brief Mean value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_mean_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult); + +/** + * @brief Mean value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +/** + * @brief Mean value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +/** + * @brief Mean value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ +void arm_mean_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +/** + * @brief Variance of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +/** + * @brief Variance of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q31(q31_t *pSrc, uint32_t blockSize, q63_t *pResult); + +/** + * @brief Variance of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_var_q15(q15_t *pSrc, uint32_t blockSize, q31_t *pResult); + +/** + * @brief Root Mean Square of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +/** + * @brief Root Mean Square of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +/** + * @brief Root Mean Square of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_rms_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +/** + * @brief Standard deviation of the elements of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult); + +/** + * @brief Standard deviation of the elements of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult); + +/** + * @brief Standard deviation of the elements of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output value. + * @return none. + */ + +void arm_std_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult); + +/** + * @brief Floating-point complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_f32(float32_t *pSrc, float32_t *pDst, uint32_t numSamples); + +/** + * @brief Q31 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q31(q31_t *pSrc, q31_t *pDst, uint32_t numSamples); + +/** + * @brief Q15 complex magnitude + * @param[in] *pSrc points to the complex input vector + * @param[out] *pDst points to the real output vector + * @param[in] numSamples number of complex samples in the input vector + * @return none. + */ + +void arm_cmplx_mag_q15(q15_t *pSrc, q15_t *pDst, uint32_t numSamples); + +/** + * @brief Q15 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q15(q15_t *pSrcA, q15_t *pSrcB, uint32_t numSamples, q31_t *realResult, + q31_t *imagResult); + +/** + * @brief Q31 complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_q31(q31_t *pSrcA, q31_t *pSrcB, uint32_t numSamples, q63_t *realResult, + q63_t *imagResult); + +/** + * @brief Floating-point complex dot product + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] numSamples number of complex samples in each vector + * @param[out] *realResult real part of the result returned here + * @param[out] *imagResult imaginary part of the result returned here + * @return none. + */ + +void arm_cmplx_dot_prod_f32(float32_t *pSrcA, float32_t *pSrcB, uint32_t numSamples, + float32_t *realResult, float32_t *imagResult); + +/** + * @brief Q15 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q15(q15_t *pSrcCmplx, q15_t *pSrcReal, q15_t *pCmplxDst, + uint32_t numSamples); + +/** + * @brief Q31 complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_q31(q31_t *pSrcCmplx, q31_t *pSrcReal, q31_t *pCmplxDst, + uint32_t numSamples); + +/** + * @brief Floating-point complex-by-real multiplication + * @param[in] *pSrcCmplx points to the complex input vector + * @param[in] *pSrcReal points to the real input vector + * @param[out] *pCmplxDst points to the complex output vector + * @param[in] numSamples number of samples in each vector + * @return none. + */ + +void arm_cmplx_mult_real_f32(float32_t *pSrcCmplx, float32_t *pSrcReal, float32_t *pCmplxDst, + uint32_t numSamples); + +/** + * @brief Minimum value of a Q7 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *result is output pointer + * @param[in] index is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q7(q7_t *pSrc, uint32_t blockSize, q7_t *result, uint32_t *index); + +/** + * @brief Minimum value of a Q15 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[in] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); + +/** + * @brief Minimum value of a Q31 vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ +void arm_min_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); + +/** + * @brief Minimum value of a floating-point vector. + * @param[in] *pSrc is input pointer + * @param[in] blockSize is the number of samples to process + * @param[out] *pResult is output pointer + * @param[out] *pIndex is the array index of the minimum value in the input buffer. + * @return none. + */ + +void arm_min_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); + +/** + * @brief Maximum value of a Q7 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q7(q7_t *pSrc, uint32_t blockSize, q7_t *pResult, uint32_t *pIndex); + +/** + * @brief Maximum value of a Q15 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q15(q15_t *pSrc, uint32_t blockSize, q15_t *pResult, uint32_t *pIndex); + +/** + * @brief Maximum value of a Q31 vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_q31(q31_t *pSrc, uint32_t blockSize, q31_t *pResult, uint32_t *pIndex); + +/** + * @brief Maximum value of a floating-point vector. + * @param[in] *pSrc points to the input buffer + * @param[in] blockSize length of the input vector + * @param[out] *pResult maximum value returned here + * @param[out] *pIndex index of maximum value returned here + * @return none. + */ + +void arm_max_f32(float32_t *pSrc, uint32_t blockSize, float32_t *pResult, uint32_t *pIndex); + +/** + * @brief Q15 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q15(q15_t *pSrcA, q15_t *pSrcB, q15_t *pDst, uint32_t numSamples); + +/** + * @brief Q31 complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_q31(q31_t *pSrcA, q31_t *pSrcB, q31_t *pDst, uint32_t numSamples); + +/** + * @brief Floating-point complex-by-complex multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] numSamples number of complex samples in each vector + * @return none. + */ + +void arm_cmplx_mult_cmplx_f32(float32_t *pSrcA, float32_t *pSrcB, float32_t *pDst, + uint32_t numSamples); + +/** + * @brief Converts the elements of the floating-point vector to Q31 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q31 output vector + * @param[in] blockSize length of the input vector + * @return none. + */ +void arm_float_to_q31(float32_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q15 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q15 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q15(float32_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the floating-point vector to Q7 vector. + * @param[in] *pSrc points to the floating-point input vector + * @param[out] *pDst points to the Q7 output vector + * @param[in] blockSize length of the input vector + * @return none + */ +void arm_float_to_q7(float32_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q31 vector to Q15 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q15(q31_t *pSrc, q15_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q31 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q31_to_q7(q31_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q15 vector to floating-point vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_float(q15_t *pSrc, float32_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q15 vector to Q31 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q31(q15_t *pSrc, q31_t *pDst, uint32_t blockSize); + +/** + * @brief Converts the elements of the Q15 vector to Q7 vector. + * @param[in] *pSrc is input pointer + * @param[out] *pDst is output pointer + * @param[in] blockSize is the number of samples to process + * @return none. + */ +void arm_q15_to_q7(q15_t *pSrc, q7_t *pDst, uint32_t blockSize); + +/** + * @ingroup groupInterpolation + */ + +/** + * @defgroup BilinearInterpolate Bilinear Interpolation + * + * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid. + * The underlying function f(x, y) is sampled on a regular grid and the interpolation process + * determines values between the grid points. + * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension. + * Bilinear interpolation is often used in image processing to rescale images. + * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types. + * + * Algorithm + * \par + * The instance structure used by the bilinear interpolation functions describes a two dimensional data table. + * For floating-point, the instance structure is defined as: + * 
+   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   *
+ * + * \par + * where numRows specifies the number of rows in the table; + * numCols specifies the number of columns in the table; + * and pData points to an array of size numRows*numCols values. + * The data table pTable is organized in row order and the supplied data values fall on integer indexes. + * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers. + * + * \par + * Let (x, y) specify the desired interpolation point. Then define: + * 
+   *     XF = floor(x)
+   *     YF = floor(y)
+   *
+ * \par + * The interpolated output point is computed as: + * 
+   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   *
+ * Note that the coordinates (x, y) contain integer and fractional components. + * The integer components specify which portion of the table to use while the + * fractional components control the interpolation processor. + * + * \par + * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. + */ + +/** + * @addtogroup BilinearInterpolate + * @{ + */ + +/** + * + * @brief Floating-point bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate. + * @param[in] Y interpolation coordinate. + * @return out interpolated value. + */ + +static __INLINE float32_t arm_bilinear_interp_f32(const arm_bilinear_interp_instance_f32 *S, + float32_t X, float32_t Y) +{ + float32_t out; + float32_t f00, f01, f10, f11; + float32_t *pData = S->pData; + int32_t xIndex, yIndex, index; + float32_t xdiff, ydiff; + float32_t b1, b2, b3, b4; + + xIndex = (int32_t)X; + yIndex = (int32_t)Y; + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0 || yIndex > (S->numCols - 1)) { + return (0); + } + + /* Calculation of index for two nearest points in X-direction */ + index = (xIndex - 1) + (yIndex - 1) * S->numCols; + + /* Read two nearest points in X-direction */ + f00 = pData[index]; + f01 = pData[index + 1]; + + /* Calculation of index for two nearest points in Y-direction */ + index = (xIndex - 1) + (yIndex)*S->numCols; + + /* Read two nearest points in Y-direction */ + f10 = pData[index]; + f11 = pData[index + 1]; + + /* Calculation of intermediate values */ + b1 = f00; + b2 = f01 - f00; + b3 = f10 - f00; + b4 = f00 - f01 - f10 + f11; + + /* Calculation of fractional part in X */ + xdiff = X - xIndex; + + /* Calculation of fractional part in Y */ + ydiff = Y - yIndex; + + /* Calculation of bi-linear interpolated output */ + out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff; + + /* return to application */ + return (out); +} + +/** + * + * @brief Q31 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + +static __INLINE q31_t arm_bilinear_interp_q31(arm_bilinear_interp_instance_q31 *S, q31_t X, q31_t Y) +{ + q31_t out; /* Temporary output */ + q31_t acc = 0; /* output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q31_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q31_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20u); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20u); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* shift left xfract by 11 to keep 1.31 format */ + xfract = (X & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* shift left yfract by 11 to keep 1.31 format */ + yfract = (Y & 0x000FFFFF) << 11u; + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */ + out = ((q31_t)(((q63_t)x1 * (0x7FFFFFFF - xfract)) >> 32)); + acc = ((q31_t)(((q63_t)out * (0x7FFFFFFF - yfract)) >> 32)); + + /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)x2 * (0x7FFFFFFF - yfract) >> 32)); + acc += ((q31_t)((q63_t)out * (xfract) >> 32)); + + /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y1 * (0x7FFFFFFF - xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); + + /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */ + out = ((q31_t)((q63_t)y2 * (xfract) >> 32)); + acc += ((q31_t)((q63_t)out * (yfract) >> 32)); + + /* Convert acc to 1.31(q31) format */ + return (acc << 2u); +} + +/** + * @brief Q15 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + +static __INLINE q15_t arm_bilinear_interp_q15(arm_bilinear_interp_instance_q15 *S, q31_t X, q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q15_t x1, x2, y1, y2; /* Nearest output values */ + q31_t xfract, yfract; /* X, Y fractional parts */ + int32_t rI, cI; /* Row and column indices */ + q15_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */ + + /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */ + /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */ + out = (q31_t)(((q63_t)x1 * (0xFFFFF - xfract)) >> 4u); + acc = ((q63_t)out * (0xFFFFF - yfract)); + + /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)x2 * (0xFFFFF - yfract)) >> 4u); + acc += ((q63_t)out * (xfract)); + + /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y1 * (0xFFFFF - xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); + + /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */ + out = (q31_t)(((q63_t)y2 * (xfract)) >> 4u); + acc += ((q63_t)out * (yfract)); + + /* acc is in 13.51 format and down shift acc by 36 times */ + /* Convert out to 1.15 format */ + return (acc >> 36); +} + +/** + * @brief Q7 bilinear interpolation. + * @param[in,out] *S points to an instance of the interpolation structure. + * @param[in] X interpolation coordinate in 12.20 format. + * @param[in] Y interpolation coordinate in 12.20 format. + * @return out interpolated value. + */ + +static __INLINE q7_t arm_bilinear_interp_q7(arm_bilinear_interp_instance_q7 *S, q31_t X, q31_t Y) +{ + q63_t acc = 0; /* output */ + q31_t out; /* Temporary output */ + q31_t xfract, yfract; /* X, Y fractional parts */ + q7_t x1, x2, y1, y2; /* Nearest output values */ + int32_t rI, cI; /* Row and column indices */ + q7_t *pYData = S->pData; /* pointer to output table values */ + uint32_t nCols = S->numCols; /* num of rows */ + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + rI = ((X & 0xFFF00000) >> 20); + + /* Input is in 12.20 format */ + /* 12 bits for the table index */ + /* Index value calculation */ + cI = ((Y & 0xFFF00000) >> 20); + + /* Care taken for table outside boundary */ + /* Returns zero output when values are outside table boundary */ + if (rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1)) { + return (0); + } + + /* 20 bits for the fractional part */ + /* xfract should be in 12.20 format */ + xfract = (X & 0x000FFFFF); + + /* Read two nearest output values from the index */ + x1 = pYData[(rI) + nCols * (cI)]; + x2 = pYData[(rI) + nCols * (cI) + 1u]; + + /* 20 bits for the fractional part */ + /* yfract should be in 12.20 format */ + yfract = (Y & 0x000FFFFF); + + /* Read two nearest output values from the index */ + y1 = pYData[(rI) + nCols * (cI + 1)]; + y2 = pYData[(rI) + nCols * (cI + 1) + 1u]; + + /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */ + out = ((x1 * (0xFFFFF - xfract))); + acc = (((q63_t)out * (0xFFFFF - yfract))); + + /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */ + out = ((x2 * (0xFFFFF - yfract))); + acc += (((q63_t)out * (xfract))); + + /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y1 * (0xFFFFF - xfract))); + acc += (((q63_t)out * (yfract))); + + /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */ + out = ((y2 * (yfract))); + acc += (((q63_t)out * (xfract))); + + /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */ + return (acc >> 40); +} + +/** + * @} end of BilinearInterpolate group + */ + +#if defined(__CC_ARM) //Keil \ + //SMMLAR +#define multAcc_32x32_keep32_R(a, x, y) \ + a = (q31_t)(((((q63_t)a) << 32) + ((q63_t)x * y) + 0x80000000LL) >> 32) + +//SMMLSR +#define multSub_32x32_keep32_R(a, x, y) \ + a = (q31_t)(((((q63_t)a) << 32) - ((q63_t)x * y) + 0x80000000LL) >> 32) + +//SMMULR +#define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y + 0x80000000LL) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER _Pragma("push") _Pragma("O1") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT _Pragma("pop") + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__ICCARM__) //IAR +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) a += (q31_t)(((q63_t)x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) a -= (q31_t)(((q63_t)x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y) >> 32) + +//Enter low optimization region - place directly above function definition +#define LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define LOW_OPTIMIZATION_EXIT + +//Enter low optimization region - place directly above function definition +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER _Pragma("optimize=low") + +//Exit low optimization region - place directly after end of function definition +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#elif defined(__GNUC__) +//SMMLA +#define multAcc_32x32_keep32_R(a, x, y) a += (q31_t)(((q63_t)x * y) >> 32) + +//SMMLS +#define multSub_32x32_keep32_R(a, x, y) a -= (q31_t)(((q63_t)x * y) >> 32) + +//SMMUL +#define mult_32x32_keep32_R(a, x, y) a = (q31_t)(((q63_t)x * y) >> 32) + +#define LOW_OPTIMIZATION_ENTER __attribute__((optimize("-O1"))) + +#define LOW_OPTIMIZATION_EXIT + +#define IAR_ONLY_LOW_OPTIMIZATION_ENTER + +#define IAR_ONLY_LOW_OPTIMIZATION_EXIT + +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* _ARM_MATH_H */ + +/** + * + * End of file. + */ diff --git a/MAX/Libraries/CMSIS/Include/core_cm3.h b/MAX/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 00000000..63b8098e --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1704 @@ +/**************************************************************************/ /** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M3 + @{ + */ + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION \ + ((__CM3_CMSIS_VERSION_MAIN << 16) | \ + __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x03) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE \ + inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all +*/ +#define __FPU_USED 0 + +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__TMS470__) +#if defined __TI__VFP_SUPPORT____ +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif + +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM3_REV +#define __CM3_REV 0x0200 +#warning "__CM3_REV not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M3 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t + CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t + ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t + VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t + AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t + SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t + CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t + SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t + SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t + CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t + HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t + DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t + MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t + BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t + AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t + PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t + DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t + ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t + MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t + ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t + CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk \ + (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk \ + (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk \ + (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk \ + (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if (__CM3_REV < 0x0201) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk \ + (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk \ + (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk \ + (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk \ + (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk \ + (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk \ + (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk \ + (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk \ + (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk \ + (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk \ + (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk \ + (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk \ + (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk \ + (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk \ + (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk \ + (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk \ + (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk \ + (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk \ + (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk \ + (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk \ + (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk \ + (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk \ + (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk \ + (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk \ + (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk \ + (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk \ + (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk \ + (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk \ + (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk \ + (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk \ + (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk \ + (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk \ + (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk \ + (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk \ + (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk \ + (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk \ + (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk \ + (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk \ + (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk \ + (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk \ + (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk \ + (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk \ + (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk \ + (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk \ + (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk \ + (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk \ + (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk \ + (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk \ + (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk \ + (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk \ + (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk \ + (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk \ + (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t + RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t + RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t + RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t + RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t + RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t + RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk \ + (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk \ + (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk \ + (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk \ + (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk \ + (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk \ + (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk \ + (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk \ + (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk \ + (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk \ + (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk \ + (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk \ + (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk \ + (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk \ + (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk \ + (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk \ + (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk \ + (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk \ + (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk \ + (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk \ + (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk \ + (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk \ + (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M3 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ +#endif + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = + (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= + ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> + SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* enable interrupt */ +} + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ +} + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? + 1 : + 0)); /* Return 1 if pending else 0 */ +} + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = + (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ +} + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = + (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ +} + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? + 1 : + 0)); /* Return 1 if active else 0 */ +} + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if (IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + if (IRQn < 0) { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, + uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : + 7 - PriorityGroupTmp; + SubPriorityBits = + ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return (((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); +} + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, + uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : + 7 - PriorityGroupTmp; + SubPriorityBits = + ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); +} + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, + (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t + ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY \ + 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/MAX/Libraries/CMSIS/Include/core_cm4.h b/MAX/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 00000000..9d406f11 --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,1865 @@ +/**************************************************************************/ /** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V3.20 + * @date 25. February 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#if defined(__ICCARM__) +#pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \ingroup Cortex_M4 + @{ + */ + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION \ + ((__CM4_CMSIS_VERSION_MAIN << 16) | \ + __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x04) /*!< Cortex-M Core */ + +#if defined(__CC_ARM) +#define __ASM __asm /*!< asm keyword for ARM Compiler */ +#define __INLINE __inline /*!< inline keyword for ARM Compiler */ +#define __STATIC_INLINE static __inline + +#elif defined(__ICCARM__) +#define __ASM __asm /*!< asm keyword for IAR Compiler */ +#define __INLINE \ + inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ +#define __STATIC_INLINE static inline + +#elif defined(__TMS470__) +#define __ASM __asm /*!< asm keyword for TI CCS Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__GNUC__) +#define __ASM __asm /*!< asm keyword for GNU Compiler */ +#define __INLINE inline /*!< inline keyword for GNU Compiler */ +#define __STATIC_INLINE static inline + +#elif defined(__TASKING__) +#define __ASM __asm /*!< asm keyword for TASKING Compiler */ +#define __INLINE inline /*!< inline keyword for TASKING Compiler */ +#define __STATIC_INLINE static inline + +#endif + +/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined(__CC_ARM) +#if defined __TARGET_FPU_VFP +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined(__ICCARM__) +#if defined __ARMVFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined(__TMS470__) +#if defined __TI_VFP_SUPPORT__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined(__GNUC__) +#if defined(__VFP_FP__) && !defined(__SOFTFP__) +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif + +#elif defined(__TASKING__) +#if defined __FPU_VFP__ +#if (__FPU_PRESENT == 1) +#define __FPU_USED 1 +#else +#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" +#define __FPU_USED 0 +#endif +#else +#define __FPU_USED 0 +#endif +#endif + +#include /* standard types definitions */ +#include /* Core Instruction Access */ +#include /* Core Function Access */ +#include /* Compiler specific SIMD Intrinsics */ + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES +#ifndef __CM4_REV +#define __CM4_REV 0x0000 +#warning "__CM4_REV not defined in device header file; using default!" +#endif + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 +#warning "__FPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __MPU_PRESENT +#define __MPU_PRESENT 0 +#warning "__MPU_PRESENT not defined in device header file; using default!" +#endif + +#ifndef __NVIC_PRIO_BITS +#define __NVIC_PRIO_BITS 4 +#warning "__NVIC_PRIO_BITS not defined in device header file; using default!" +#endif + +#ifndef __Vendor_SysTickConfig +#define __Vendor_SysTickConfig 0 +#warning "__Vendor_SysTickConfig not defined in device header file; using default!" +#endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus +#define __I volatile /*!< Defines 'read only' permissions */ +#else +#define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/*@} end of group Cortex_M4 */ + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union { + struct { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0 : 27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0 : 16; /*!< bit: 0..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union { + struct { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0 : 23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union { + struct { + uint32_t ISR : 9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0 : 15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0 : 7; /*!< bit: 9..15 Reserved */ + uint32_t GE : 4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1 : 4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T : 1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT : 2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q : 1; /*!< bit: 27 Saturation condition flag */ + uint32_t V : 1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C : 1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z : 1; /*!< bit: 30 Zero condition code flag */ + uint32_t N : 1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union { + struct { + uint32_t nPRIV : 1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL : 1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA : 1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0 : 29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct { + __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24]; + __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[24]; + __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24]; + __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24]; + __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56]; + __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644]; + __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct { + __I uint32_t + CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t + ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IO uint32_t + VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IO uint32_t + AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t + SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t + CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IO uint8_t + SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IO uint32_t + SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IO uint32_t + CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IO uint32_t + HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IO uint32_t + DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IO uint32_t + MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IO uint32_t + BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IO uint32_t + AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __I uint32_t + PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __I uint32_t + DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __I uint32_t + ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __I uint32_t + MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __I uint32_t + ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5]; + __IO uint32_t + CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk \ + (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk \ + (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk \ + (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk \ + (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk \ + (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk \ + (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk \ + (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk \ + (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk \ + (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk \ + (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk \ + (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk \ + (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk \ + (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk \ + (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk \ + (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk \ + (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk \ + (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk \ + (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk \ + (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Registers Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk \ + (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk \ + (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk \ + (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* SCB Hard Fault Status Registers Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct { + uint32_t RESERVED0[1]; + __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk \ + (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk \ + (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk \ + (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk \ + (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk \ + (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk \ + (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk \ + (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk \ + (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk \ + (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct { + __O union { + __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT[32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864]; + __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15]; + __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15]; + __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29]; + __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43]; + __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6]; + __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk \ + (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk \ + (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct { + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1]; + __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1]; + __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1]; + __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk \ + (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk \ + (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk \ + (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk \ + (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk \ + (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk \ + (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk \ + (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk \ + (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk \ + (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk \ + (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk \ + (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk \ + (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct { + __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2]; + __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55]; + __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131]; + __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759]; + __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1]; + __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39]; + __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8]; + __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk \ + (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk \ + (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk \ + (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk \ + (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk \ + (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk \ + (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk \ + (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk \ + (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk \ + (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk \ + (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk \ + (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk \ + (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + +#if (__MPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct { + __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IO uint32_t + RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IO uint32_t + RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IO uint32_t + RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IO uint32_t + RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IO uint32_t + RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IO uint32_t + RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register */ +#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register */ +#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register */ +#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register */ +#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register */ +#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk \ + (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk \ + (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + +#if (__FPU_PRESENT == 1) +/** \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct { + uint32_t RESERVED0[1]; + __IO uint32_t + FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IO uint32_t + FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IO uint32_t + FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __I uint32_t + MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __I uint32_t + MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register */ +#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk \ + (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk \ + (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register */ +#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk \ + (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register */ +#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk \ + (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk \ + (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk \ + (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk \ + (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk \ + (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk \ + (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk \ + (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk \ + (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk \ + (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ +#endif + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct { + __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk \ + (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk \ + (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk \ + (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk \ + (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk \ + (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk \ + (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk \ + (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk \ + (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk \ + (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk \ + (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk \ + (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk \ + (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register */ +#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk \ + (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk \ + (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk \ + (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk \ + (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk \ + (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk \ + (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk \ + (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk \ + (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk \ + (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Cortex-M4 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *)SCS_BASE) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *)SCB_BASE) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *)SysTick_BASE) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *)NVIC_BASE) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *)ITM_BASE) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *)DWT_BASE) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *)TPI_BASE) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *)CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if (__MPU_PRESENT == 1) +#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ +#define MPU ((MPU_Type *)MPU_BASE) /*!< Memory Protection Unit */ +#endif + +#if (__FPU_PRESENT == 1) +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *)FPU_BASE) /*!< Floating Point Unit */ +#endif + +/*@} */ + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +/** \brief Set Priority Grouping + + The function sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = + (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= + ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ + reg_value = (reg_value | ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + +/** \brief Get Priority Grouping + + The function reads the priority grouping field from the NVIC Interrupt Controller. + + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) +{ + return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> + SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ +} + +/** \brief Enable External Interrupt + + The function enables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */ + NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = + (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */ +} + +/** \brief Disable External Interrupt + + The function disables a device-specific interrupt in the NVIC interrupt controller. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn)&0x1F)); /* disable interrupt */ +} + +/** \brief Get Pending Interrupt + + The function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + */ +__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? + 1 : + 0)); /* Return 1 if pending else 0 */ +} + +/** \brief Set Pending Interrupt + + The function sets the pending bit of an external interrupt. + + \param [in] IRQn Interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = + (1 << ((uint32_t)(IRQn)&0x1F)); /* set interrupt pending */ +} + +/** \brief Clear Pending Interrupt + + The function clears the pending bit of an external interrupt. + + \param [in] IRQn External interrupt number. Value cannot be negative. + */ +__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = + (1 << ((uint32_t)(IRQn)&0x1F)); /* Clear pending interrupt */ +} + +/** \brief Get Active Interrupt + + The function reads the active register in NVIC and returns the active bit. + + \param [in] IRQn Interrupt number. + + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + */ +__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return ((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn)&0x1F))) ? + 1 : + 0)); /* Return 1 if active else 0 */ +} + +/** \brief Set Interrupt Priority + + The function sets the priority of an interrupt. + + \note The priority cannot be set for every core interrupt. + + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + */ +__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if (IRQn < 0) { + SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for Cortex-M System Interrupts */ + else { + NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); + } /* set Priority for device specific Interrupts */ +} + +/** \brief Get Interrupt Priority + + The function reads the priority of an interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented + priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + if (IRQn < 0) { + return ((uint32_t)(SCB->SHP[((uint32_t)(IRQn)&0xF) - 4] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for Cortex-M system interrupts */ + else { + return ((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); + } /* get priority for device specific interrupts */ +} + +/** \brief Encode Priority + + The function encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set. + + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority(uint32_t PriorityGroup, uint32_t PreemptPriority, + uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : + 7 - PriorityGroupTmp; + SubPriorityBits = + ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + return (((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | + ((SubPriority & ((1 << (SubPriorityBits)) - 1)))); +} + +/** \brief Decode Priority + + The function decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set. + + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority(uint32_t Priority, uint32_t PriorityGroup, + uint32_t *pPreemptPriority, uint32_t *pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : + 7 - PriorityGroupTmp; + SubPriorityBits = + ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; + + *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); + *pSubPriority = (Priority) & ((1 << (SubPriorityBits)) - 1); +} + +/** \brief System Reset + + The function initiates a system reset request to reset the MCU. + */ +__STATIC_INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + while (1) + ; /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + The function initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + + \param [in] ticks Number of ticks between two interrupts. + + \return 0 Function succeeded. + \return 1 Function failed. + + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) + return (1); /* Reload value impossible */ + + SysTick->LOAD = ticks - 1; /* set reload register */ + NVIC_SetPriority(SysTick_IRQn, + (1 << __NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + +/* ##################################### Debug In/Output function ########################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t + ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY \ + 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + +/** \brief ITM Send Character + + The function transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + + \param [in] ch Character to transmit. + + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar(uint32_t ch) +{ + if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ + (ITM->TER & (1UL << 0))) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0].u32 == 0) + ; + ITM->PORT[0].u8 = (uint8_t)ch; + } + return (ch); +} + +/** \brief ITM Receive Character + + The function inputs a character via the external variable \ref ITM_RxBuffer. + + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar(void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + +/** \brief ITM Check Character + + The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar(void) +{ + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { + return (0); /* no character available */ + } else { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/MAX/Libraries/CMSIS/Include/core_cm4_simd.h b/MAX/Libraries/CMSIS/Include/core_cm4_simd.h new file mode 100644 index 00000000..1e3c7c4c --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/core_cm4_simd.h @@ -0,0 +1,673 @@ +/** + * @file core_cm4_simd.h + * @brief CMSIS Cortex-M4 SIMD Header File + * @version V3.20 + * @date 25. February 2013 + ******************************************************************************/ + +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef __CORE_CM4_SIMD_H +#define __CORE_CM4_SIMD_H + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1, ARG2, ARG3) \ + (((((uint32_t)(ARG1))) & 0x0000FFFFUL) | ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)) + +#define __PKHTB(ARG1, ARG2, ARG3) \ + (((((uint32_t)(ARG1))) & 0xFFFF0000UL) | ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)) + +#define __SMMLA(ARG1, ARG2, ARG3) \ + ((int32_t)((((int64_t)(ARG1) * (ARG2)) + ((int64_t)(ARG3) << 32)) >> 32)) + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +#include + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhadd16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsub16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhasx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("ssax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("shsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uqsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uhsax %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("usad8 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, + uint32_t op3) +{ + uint32_t result; + + __ASM volatile("usada8 %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SSAT16(ARG1, ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +#define __USAT16(ARG1, ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat16 %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("uxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("uxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile("sxtb16 %0, %1" : "=r"(result) : "r"(op1)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sxtab16 %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuad %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smuadx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD(uint32_t op1, uint32_t op2, + uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlad %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX(uint32_t op1, uint32_t op2, + uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smladx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SMLALD(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), \ + __ARG3_L = (uint32_t)((uint64_t)(ARG3)&0xFFFFFFFFUL); \ + __ASM volatile("smlald %0, %1, %2, %3" \ + : "=r"(__ARG3_L), "=r"(__ARG3_H) \ + : "r"(__ARG1), "r"(__ARG2), "0"(__ARG3_L), "1"(__ARG3_H)); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLALDX(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), \ + __ARG3_L = (uint32_t)((uint64_t)(ARG3)&0xFFFFFFFFUL); \ + __ASM volatile("smlaldx %0, %1, %2, %3" \ + : "=r"(__ARG3_L), "=r"(__ARG3_H) \ + : "r"(__ARG1), "r"(__ARG2), "0"(__ARG3_L), "1"(__ARG3_H)); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("smusdx %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD(uint32_t op1, uint32_t op2, + uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsd %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX(uint32_t op1, uint32_t op2, + uint32_t op3) +{ + uint32_t result; + + __ASM volatile("smlsdx %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +#define __SMLSLD(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), \ + __ARG3_L = (uint32_t)((ARG3)&0xFFFFFFFFUL); \ + __ASM volatile("smlsld %0, %1, %2, %3" \ + : "=r"(__ARG3_L), "=r"(__ARG3_H) \ + : "r"(__ARG1), "r"(__ARG2), "0"(__ARG3_L), "1"(__ARG3_H)); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +#define __SMLSLDX(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), \ + __ARG3_L = (uint32_t)((ARG3)&0xFFFFFFFFUL); \ + __ASM volatile("smlsldx %0, %1, %2, %3" \ + : "=r"(__ARG3_L), "=r"(__ARG3_H) \ + : "r"(__ARG1), "r"(__ARG2), "0"(__ARG3_L), "1"(__ARG3_H)); \ + (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("sel %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qadd %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile("qsub %0, %1, %2" : "=r"(result) : "r"(op1), "r"(op2)); + return (result); +} + +#define __PKHBT(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM("pkhbt %0, %1, %2, lsl %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) + +#define __PKHTB(ARG1, ARG2, ARG3) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM("pkhtb %0, %1, %2" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2)); \ + else \ + __ASM("pkhtb %0, %1, %2, asr %3" : "=r"(__RES) : "r"(__ARG1), "r"(__ARG2), "I"(ARG3)); \ + __RES; \ + }) + +__attribute__((always_inline)) __STATIC_INLINE uint32_t __SMMLA(int32_t op1, int32_t op2, + int32_t op3) +{ + int32_t result; + + __ASM volatile("smmla %0, %1, %2, %3" : "=r"(result) : "r"(op1), "r"(op2), "r"(op3)); + return (result); +} + +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/ +/* not yet supported */ +/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/ + +#endif + +/*@} end of group CMSIS_SIMD_intrinsics */ + +#endif /* __CORE_CM4_SIMD_H */ + +#ifdef __cplusplus +} +#endif diff --git a/MAX/Libraries/CMSIS/Include/core_cmFunc.h b/MAX/Libraries/CMSIS/Include/core_cmFunc.h new file mode 100644 index 00000000..29d3de1b --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/core_cmFunc.h @@ -0,0 +1,589 @@ +/** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V3.20 + * @date 25. February 2013 + ******************************************************************************/ + +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + +/* ########################### Core Function Access ########################### */ +/** @ingroup CMSIS_Core_FunctionInterface + @defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** @brief Get Control Register + + This function returns the content of the Control Register. + + @return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return (__regControl); +} + +/** @brief Set Control Register + + This function writes the given value to the Control Register. + + @param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + +/** @brief Get IPSR Register + + This function returns the content of the IPSR Register. + + @return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return (__regIPSR); +} + +/** @brief Get APSR Register + + This function returns the content of the APSR Register. + + @return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return (__regAPSR); +} + +/** @brief Get xPSR Register + + This function returns the content of the xPSR Register. + + @return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return (__regXPSR); +} + +/** @brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + @return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return (__regProcessStackPointer); +} + +/** @brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + @param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + +/** @brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + @return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return (__regMainStackPointer); +} + +/** @brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + @param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + +/** @brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + @return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return (__regPriMask); +} + +/** @brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + @param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + +#if (__CORTEX_M >= 0x03) + +/** @brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + +/** @brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + +/** @brief Get Base Priority + + This function returns the current value of the Base Priority register. + + @return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return (__regBasePri); +} + +/** @brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + @param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + +/** @brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + @return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return (__regFaultMask); +} + +/** @brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + @param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +#if (__CORTEX_M == 0x04) + +/** @brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + @return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return (__regfpscr); +#else + return (0); +#endif +} + +/** @brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + @param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** @brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void) +{ + __ASM volatile("cpsie i" : : : "memory"); +} + +/** @brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void) +{ + __ASM volatile("cpsid i" : : : "memory"); +} + +/** @brief Get Control Register + + This function returns the content of the Control Register. + + @return Control Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, control" : "=r"(result)); + return (result); +} + +/** @brief Set Control Register + + This function writes the given value to the Control Register. + + @param [in] control Control Register value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile("MSR control, %0" : : "r"(control) : "memory"); +} + +/** @brief Get IPSR Register + + This function returns the content of the IPSR Register. + + @return IPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, ipsr" : "=r"(result)); + return (result); +} + +/** @brief Get APSR Register + + This function returns the content of the APSR Register. + + @return APSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, apsr" : "=r"(result)); + return (result); +} + +/** @brief Get xPSR Register + + This function returns the content of the xPSR Register. + + @return xPSR Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, xpsr" : "=r"(result)); + return (result); +} + +/** @brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + @return PSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, psp\n" : "=r"(result)); + return (result); +} + +/** @brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + @param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile("MSR psp, %0\n" : : "r"(topOfProcStack) : "sp"); +} + +/** @brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + @return MSP Register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile("MRS %0, msp\n" : "=r"(result)); + return (result); +} + +/** @brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + @param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile("MSR msp, %0\n" : : "r"(topOfMainStack) : "sp"); +} + +/** @brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + @return Priority Mask value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, primask" : "=r"(result)); + return (result); +} + +/** @brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + @param [in] priMask Priority Mask + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile("MSR primask, %0" : : "r"(priMask) : "memory"); +} + +#if (__CORTEX_M >= 0x03) + +/** @brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void) +{ + __ASM volatile("cpsie f" : : : "memory"); +} + +/** @brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void) +{ + __ASM volatile("cpsid f" : : : "memory"); +} + +/** @brief Get Base Priority + + This function returns the current value of the Base Priority register. + + @return Base Priority register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, basepri_max" : "=r"(result)); + return (result); +} + +/** @brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + @param [in] basePri Base Priority value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile("MSR basepri, %0" : : "r"(value) : "memory"); +} + +/** @brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + @return Fault Mask register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile("MRS %0, faultmask" : "=r"(result)); + return (result); +} + +/** @brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + @param [in] faultMask Fault Mask value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile("MSR faultmask, %0" : : "r"(faultMask) : "memory"); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +#if (__CORTEX_M == 0x04) + +/** @brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + @return Floating Point Status/Control register value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMRS %0, fpscr" : "=r"(result)); + __ASM volatile(""); + return (result); +#else + return (0); +#endif +} + +/** @brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + @param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + /* Empty asm statement works as a scheduling barrier */ + __ASM volatile(""); + __ASM volatile("VMSR fpscr, %0" : : "r"(fpscr) : "vfpcc"); + __ASM volatile(""); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + +#endif /* __CORE_CMFUNC_H */ diff --git a/MAX/Libraries/CMSIS/Include/core_cmInstr.h b/MAX/Libraries/CMSIS/Include/core_cmInstr.h new file mode 100644 index 00000000..6820a945 --- /dev/null +++ b/MAX/Libraries/CMSIS/Include/core_cmInstr.h @@ -0,0 +1,636 @@ +/**************************************************************************/ /** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V3.20 + * @date 05. March 2013 + * + * @note + * + ******************************************************************************/ +/* Copyright (c) 2009 - 2013 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined(__CC_ARM) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) +#error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 bx lr +} +#endif + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 bx lr +} +#endif + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t)__ldrex(ptr)) + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t)__ldrex(ptr)) + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t)__ldrex(ptr)) + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + +#elif defined(__ICCARM__) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined(__TMS470__) /*---------------- TI CCS Compiler ------------------*/ +/* TI CCS specific functions */ + +#include + +#elif defined(__GNUC__) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constrant "l" + * Otherwise, use general registers, specified by constrant "r" */ +#if defined(__thumb__) && !defined(__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l"(r) +#define __CMSIS_GCC_USE_REG(r) "l"(r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r"(r) +#define __CMSIS_GCC_USE_REG(r) "r"(r) +#endif + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__((always_inline)) __STATIC_INLINE void __NOP(void) +{ + __ASM volatile("nop"); +} + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFI(void) +{ + __ASM volatile("wfi"); +} + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__((always_inline)) __STATIC_INLINE void __WFE(void) +{ + __ASM volatile("wfe"); +} + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__((always_inline)) __STATIC_INLINE void __SEV(void) +{ + __ASM volatile("sev"); +} + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__((always_inline)) __STATIC_INLINE void __ISB(void) +{ + __ASM volatile("isb"); +} + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DSB(void) +{ + __ASM volatile("dsb"); +} + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__((always_inline)) __STATIC_INLINE void __DMB(void) +{ + __ASM volatile("dmb"); +} + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile("rev %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +#endif +} + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rev16 %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +} + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __REVSH(int32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (short)__builtin_bswap16(value); +#else + uint32_t result; + + __ASM volatile("revsh %0, %1" : __CMSIS_GCC_OUT_REG(result) : __CMSIS_GCC_USE_REG(value)); + return (result); +#endif +} + +/** \brief Rotate Right in unsigned value (32 bit) + + This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + return (op1 >> op2) | (op1 << (32 - op2)); +} + +/** \brief Breakpoint + + This function causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile("bkpt " #value) + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile("rbit %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexb %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexb %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return (result); +} + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile("ldrexh %0, %1" : "=r"(result) : "Q"(*addr)); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile("ldrexh %0, [%1]" : "=r"(result) : "r"(addr) : "memory"); +#endif + return (result); +} + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("ldrex %0, %1" : "=r"(result) : "Q"(*addr)); + return (result); +} + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, + volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile("strexb %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); + return (result); +} + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, + volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile("strexh %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); + return (result); +} + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, + volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile("strex %0, %2, %1" : "=&r"(result), "=Q"(*addr) : "r"(value)); + return (result); +} + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__((always_inline)) __STATIC_INLINE void __CLREX(void) +{ + __ASM volatile("clrex" ::: "memory"); +} + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1, ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("ssat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1, ARG2) \ + ({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM("usat %0, %1, %2" : "=r"(__RES) : "I"(ARG2), "r"(__ARG1)); \ + __RES; \ + }) + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__((always_inline)) __STATIC_INLINE uint8_t __CLZ(uint32_t value) +{ + uint32_t result; + + __ASM volatile("clz %0, %1" : "=r"(result) : "r"(value)); + return (result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + +#elif defined(__TASKING__) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32520/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32520/gpio.h index 9a4028ca..9a2b4da6 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32520/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32520/gpio.h @@ -127,12 +127,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -359,6 +381,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32520/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32520/spi.h index 821cb63f..8da2c4e2 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32520/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32520/spi.h @@ -405,7 +405,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -433,7 +433,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32570/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32570/gpio.h index 93ba48c1..51698a6b 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32570/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32570/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -359,6 +381,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32570/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32570/spi.h index 127a8c2a..05fab6ef 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32570/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32570/spi.h @@ -412,7 +412,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -440,7 +440,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32572/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32572/gpio.h index 1ac45ff9..bedf6886 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32572/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32572/gpio.h @@ -127,12 +127,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -177,6 +191,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -360,6 +382,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32572/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32572/spi.h index 7f06f46d..69ef3757 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32572/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32572/spi.h @@ -4,35 +4,22 @@ */ /****************************************************************************** - * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************/ @@ -563,7 +550,7 @@ void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI instance's registers. * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -582,7 +569,7 @@ int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); * * @param spi Pointer to SPI instance's registers. * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32650/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32650/gpio.h index 3908b760..709ec65a 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32650/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32650/gpio.h @@ -126,13 +126,27 @@ typedef enum { } mxc_gpio_vssel_t; /** - * @brief Enumeration type for drive strength configuration. + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -166,6 +180,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -353,6 +375,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32650/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32650/spi.h index 9e9dc808..e16ea14a 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32650/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32650/spi.h @@ -415,7 +415,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -443,7 +443,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32655/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32655/gpio.h index 826deaea..9b51de8d 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32655/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32655/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -355,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32655/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32655/spi.h index 47c9e91e..7dd304a0 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32655/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32655/spi.h @@ -457,7 +457,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -485,7 +485,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/aes.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/aes.h new file mode 100644 index 00000000..806df3ab --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/aes.h @@ -0,0 +1,275 @@ +/** + * @file aes.h + * @brief AES driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ + +/***** Includes *****/ +#include "aes_regs.h" +#include "aeskeys_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup aes AES + * @ingroup periphlibs + * @{ + */ +/*@} end of group aes */ + +/***** Definitions *****/ + +typedef void (*mxc_aes_complete_t)(void *req, int result); + +/* ************************************************************************* */ +/* Cipher Definitions */ +/* ************************************************************************* */ + +/** + * @brief Enumeration type to select AES key + * + */ +typedef enum { + MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key + MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key + MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key +} mxc_aes_keys_t; + +/** + * @brief Enumeration type to select AES key source and encryption type + * + */ +typedef enum { + MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key + MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key + MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key +} mxc_aes_enc_type_t; + +/** + * @brief Structure used to set up AES request + * + */ +typedef struct _mxc_aes_cipher_req_t { + uint32_t length; ///< Length of the data + uint32_t *inputData; ///< Pointer to input data + uint32_t *resultData; ///< Pointer to encrypted data + mxc_aes_keys_t keySize; ///< Size of AES key + mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t + mxc_aes_complete_t callback; ///< Callback function +} mxc_aes_req_t; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the AES + * + * @param dma DMA instance used for AES + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Init(mxc_dma_regs_t *dma); + +/** + * @brief Enable AES Interrupts + * + * @param interrupt interrupt to enable + */ +void MXC_AES_EnableInt(uint32_t interrupt); + +/** + * @brief Disable AES Interrupts + * + * @param interrupt interrupt to disable + */ +void MXC_AES_DisableInt(uint32_t interrupt); + +/** + * @brief Checks the global AES Busy Status + * + * @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_IsBusy(void); + +/** + * @brief Disable and reset portions of the AES + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Shutdown(void); + +/** + * @brief This function should be called from the DMA Handler + * when using Async functions + */ +void MXC_AES_DMACallback(int ch, int error); + +/** + * @brief This function should be called before encryption to genrate external key + */ +void MXC_AES_GenerateKey(void); + +/** + * @brief Set Key size for encryption or decryption + * + * @param key Key size, see \ref mxc_aes_keys_t for a list of keys + */ +void MXC_AES_SetKeySize(mxc_aes_keys_t key); + +/** + * @brief Get the currently set key size + * + * @return mxc_aes_keys_t see \ref mxc_aes_keys_t + */ +mxc_aes_keys_t MXC_AES_GetKeySize(void); + +/** + * @brief Flush Input Data FIFO + * + */ +void MXC_AES_FlushInputFIFO(void); + +/** + * @brief Flush Output Data FIFO + * + */ +void MXC_AES_FlushOutputFIFO(void); + +/** + * @brief Start AES Calculations + * + */ +void MXC_AES_Start(void); + +/** + * @brief Get Interrupt flags set + * + * @return return the flags set in intfl register + */ +uint32_t MXC_AES_GetFlags(void); + +/** + * @brief Clear the interrupts + * + * @param flags flags to be cleared + */ +void MXC_AES_ClearFlags(uint32_t flags); + +/** + * @brief + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the encryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Generic(mxc_aes_req_t *req); + +/** + * @brief Perform an encryption + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the encryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Encrypt(mxc_aes_req_t *req); + +/** + * @brief Perform a decryption + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the decryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Decrypt(mxc_aes_req_t *req); + +/** + * @brief Perform AES TX using DMA. Configures DMA request and starts the transmission. + * + * @param src_addr source address + * @param len number of words of data + * @param dma DMA instance to configue for AES + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); + +/** + * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. + * + * @param dest_addr destination address + * @param len number of words of data + * @param dma DMA instance to configure for AES + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); + +/** + * @brief Perform encryption or decryption using DMA + * + * @param req The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * @param enc 0 for encryption and 1 for decryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc); + +/** + * @brief Perform an encryption using Interrupt + * @note The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * + * @param req Structure containing data for the encryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_EncryptAsync(mxc_aes_req_t *req); + +/** + * @brief Perform a decryption using Interrupt + * @note The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * + * @param req Structure containing data for the decryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_DecryptAsync(mxc_aes_req_t *req); + +/** + * @brief Set the external key + * @param key Buffer for the key. + * @param len Key size. + */ +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len); + +#ifdef __cplusplus +} +#endif +/**@} end of group aes */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/crc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/crc.h new file mode 100644 index 00000000..f80ed216 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/crc.h @@ -0,0 +1,168 @@ +/** + * @file crc.h + * @brief cyclic redundancy check driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ + +/***** Includes *****/ +#include "crc_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup crc CRC + * @ingroup periphlibs + * @{ + */ + +/***** CRC Definitions *****/ +/** + * @brief Structure used to set up CRC request + * + */ +typedef struct _mxc_crc_req_t { + uint32_t *dataBuffer; ///< Pointer to the data + uint32_t dataLen; ///< Length of the data + uint32_t resultCRC; ///< Calculated CRC value +} mxc_crc_req_t; + +/** + * @brief CRC data bit order + * + */ +typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the CRC + * + * @param dma DMA Instance used for CRC calculation + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Init(mxc_dma_regs_t *dma); + +/** + * @brief Disable and reset portions of the CRC + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Shutdown(void); + +/** + * @brief This function should be called from the CRC ISR Handler + * when using Async functions + * @param ch DMA channel + * @param error error + */ +void MXC_CRC_Handler(int ch, int error); + +/** + * @brief Set the bit-order of CRC calculation + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Set the bit-order of CRC calculation + * + * @return The direction of calculation, 1 for MSB first, 0 for LSB first + */ +mxc_crc_bitorder_t MXC_CRC_GetDirection(void); + +/** + * @brief Byte Swap CRC Data Input + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Byte Swap CRC Data output + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Set the Polynomial for CRC calculation + * + * @param poly The polynomial to use for CRC calculation + */ +void MXC_CRC_SetPoly(uint32_t poly); + +/** + * @brief Get the polynomial for CRC calculation + * + * @return The polynomial used in calculation + */ +uint32_t MXC_CRC_GetPoly(void); + +/** + * @brief Get the result of a CRC calculation + * + * @return The calculated CRC value + */ +uint32_t MXC_CRC_GetResult(void); + +/*******************************/ +/* High Level Functions */ +/*******************************/ + +/** + * @brief Perform a CRC computation + * @note The result of the CRC calculation will be placed in the + * mxc_crc_req_t structure + * + * @param req Structure containing the data for calculation + * + * @return see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Compute(mxc_crc_req_t *req); + +/** + * @brief Perform a CRC computation using DMA + * @note The result of the CRC calculation will be placed in the + * mxc_crc_req_t structure. The user must call + * MXC_DMA_Handler() in the ISR + * + * @param req Structure containing the data for calculation + * + * @return see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req); + +#ifdef __cplusplus +} +#endif +/**@} end of group crc */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/dma.h new file mode 100644 index 00000000..2af9f285 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -0,0 +1,443 @@ +/** + * @file dma.h + * @brief Direct Memory Access (DMA) driver function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup dma Direct Memory Access (DMA) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** + * @brief Enumeration for the DMA Channel's priority level. + * + */ +typedef enum { + MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority + MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority + MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority + MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority +} mxc_dma_priority_t; + +/** @brief DMA request select */ +// TODO(ME30): Updated DMA reqsel +typedef enum { + MXC_DMA_REQUEST_MEMTOMEM = + MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection + MXC_DMA_REQUEST_SPIRX = MXC_S_DMA_CTRL_REQUEST_SPIRX, ///< SPI Receive DMA Request Selection + MXC_DMA_REQUEST_UARTRX = MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection + MXC_DMA_REQUEST_I3CRX_CONT = + MXC_S_DMA_CTRL_REQUEST_I3CRX_CONT, ///< I3C Receive Controller DMA Request Selection + MXC_DMA_REQUEST_I3CRX_TARG = + MXC_S_DMA_CTRL_REQUEST_I3CRX_TARG, ///< I3C Receive Target DMA Request Selection + MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection + MXC_DMA_REQUEST_SPITX = MXC_S_DMA_CTRL_REQUEST_SPITX, ///< SPI Transmit DMA Request Selection + MXC_DMA_REQUEST_UARTTX = MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection + MXC_DMA_REQUEST_I3CTX_CONT = + MXC_S_DMA_CTRL_REQUEST_I3CTX_CONT, ///< I3C Transmit Controller DMA Request Selection + MXC_DMA_REQUEST_I3CTX_TARG = + MXC_S_DMA_CTRL_REQUEST_I3CTX_TARG, ///< I3C Transmit Target DMA Request Selection + MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ + MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection +} mxc_dma_reqsel_t; + +/** @brief Enumeration for the DMA prescaler */ +typedef enum { + MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled + MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 + MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 + MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 +} mxc_dma_prescale_t; + +/** @brief Enumeration for the DMA timeout value */ +typedef enum { + MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks + MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks + MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks + MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks + MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks + MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks + MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks + MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks +} mxc_dma_timeout_t; + +/** @brief DMA transfer data width */ +typedef enum { + /* Using the '_V_' define instead of the '_S_' since these same values will be used to + specify the DSTWD also. The API functions will shift the value the correct amount + prior to writing the cfg register. */ + MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes + MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words + MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words +} mxc_dma_width_t; + +/** + * @brief The basic configuration information to set up a DMA channel + * and prepare it for transfers. + * + */ +typedef struct { + int ch; ///< The channel to load the configuration data into + mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) + mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) + mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) + int srcinc_en; ///< Whether to increment the source address during the transfer + int dstinc_en; ///< Whether to increment the source address during the transfer +} mxc_dma_config_t; + +/** + * @brief The information needed to complete a DMA transfer + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + void *source; ///< Pointer to the source address, if applicable + void *dest; ///< Pointer to the destination address, if applicable + int len; ///< Number of bytes to transfer +} mxc_dma_srcdst_t; + +/** + * @brief The advanced configuration options, these are optional but could + * be needed in cases where multiple DMA channels are running concurrently + * or DMA is being used with low bandwidth peripherals. + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + mxc_dma_priority_t prio; ///< The DMA priority for the channel + unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer + mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout + mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer + unsigned int burst_size; ///< Number of bytes moved in a single burst +} mxc_dma_adv_config_t; + +/** + * @brief The callback called on completion of a DMA_MemCpy() transfer + * + * @param dest Pointer to the destination of the copy + */ +typedef void (*mxc_dma_complete_cb_t)(void *dest); + +/** + * @brief The callback called on completion of a transfer, + * @note This callback is used with MXC_DMA_DoTransfer() + * to allow the user to chain an unlimited number of + * DMA Transfers. + * + * @param trans Struct of the completed transfer + * + * @return Returns the next transfer to be completed, or NULL + * if no more transfers will be done + */ +typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); + +/* **** Function Prototypes **** */ +/*************************/ +/* Low Level Functions */ +/*************************/ +/** + * @brief Initialize DMA resources + * @details This initialization is required before using the DMA driver functions. + * @note On default this function enables DMA peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * @param dma Pointer to selected DMA instance's registers. + * + * @return #E_NO_ERROR if successful + */ +int MXC_DMA_Init(mxc_dma_regs_t *dma); + +/** + * @brief De-Initialize DMA resources. + * + * @param dma Pointer to selected DMA instance's registers. + */ +void MXC_DMA_DeInit(mxc_dma_regs_t *dma); + +/** + * @brief Request DMA channel + * @details Returns a handle to the first free DMA channel, which can be used via API calls + * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @param dma Pointer to selected DMA instance's registers. + * @return Non-negative channel handle (inclusive of zero). + * @return #E_NONE_AVAIL All channels in use. + * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. + * @return #E_BUSY DMA is currently busy (locked), try again later. + */ +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); + +/** + * @brief Release DMA channel + * @details Stops any DMA operation on the channel and returns it to the pool of free channels. + * + * @param ch DMA channel to release + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ReleaseChannel(int ch); + +/** + * @brief Configure the DMA channel + * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() + * + * @param config Struct containing DMA configuration parameters + * @param srcdst Struct containing pointers and length of DMA operation + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); + +/** + * @brief Configure the DMA channel with more advanced parameters + * + * @param advConfig Struct containing advanced DMA parameters + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); + +/** + * @brief Set channel source, destination, and count for the transfer + * @param srcdst Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); + +/** + * @brief Get channel source, destination, and count for transfer + * + * @param srcdst Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); + +/** + * @brief Set channel reload source, destination, and count for the transfer + * @param srcdstReload Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); + +/** + * @brief Get channel reload source, destination, and count for transfer + * + * @param srcdstReload Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); + +/** + * @brief Set channel interrupt callback + * @param ch DMA channel + * @param callback Pointer to a function to call when the channel + * interrupt flag is set and interrupts are enabled or + * when DMA is shutdown by the driver. + * @details Configures the channel interrupt callback. The @p callback + * function is called for two conditions: + * -# When the channel's interrupt flag is set and DMA interrupts + * are enabled. + * -# If the driver calls the MXC_DMA_Shutdown() function. The + * callback function prototype is: + * @code + * void callback_fn(int ch, int reason); + * @endcode + * @p ch indicates the channel that generated the callback, @p + * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN + * if the DMA is being shutdown. + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); + +/** + * @brief Set channel interrupt + * @note Each channel has two interrupts (complete, and count to zero). + * To enable complete, pass true for chdis. To enable count to zero, + * pass true for ctz. + * @param ch DMA channel + * @param chdis Enable channel complete interrupt + * @param ctz Enable channel count to zero interrupt. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param ch DMA channel to enable interrupts for. + * @param flags The flags to enable + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelEnableInt(int ch, int flags); + +/** + * @brief Disable channel interrupt + * @param ch DMA channel to clear flags for. + * @param flags The flags to disable + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelDisableInt(int ch, int flags); + +/** + * @brief Read channel interrupt flags + * @param ch DMA channel to get interrupt status from. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * flags otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelGetFlags(int ch); + +/** + * @brief Clear channel interrupt flags + * @param ch DMA channel to clear the interrupt flag for. + * @param flags The flags to clear + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelClearFlags(int ch, int flags); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param dma DMA instance used for the DMA channel registers. + * @param ch DMA channel to enable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch); + +/** + * @brief Disable channel interrupt + * @param dma DMA instance used for the DMA channel registers. + * @param ch DMA channel to disable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch); + +/** + * @brief Start transfer + * @param ch DMA channel + * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_Start(int ch); + +/** + * @brief Stop DMA transfer, irrespective of status (complete or in-progress) + * @param ch DMA channel + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_Stop(int ch); + +/** + * @brief Get a pointer to the DMA channel registers + * @param ch DMA channel + * @note If direct access to DMA channel registers is required, this + * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). + * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise + */ +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); + +/** + * @brief Interrupt handler function + * @param dma Pointer to DMA registers. + * @details Call this function as the ISR for each DMA channel under driver control. + * Interrupt flags for channel ch will be automatically cleared before return. + */ +void MXC_DMA_Handler(mxc_dma_regs_t *dma); + +/*************************/ +/* High Level Functions */ +/*************************/ + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param dma Pointer to DMA registers. + * @param dest pointer to destination memory + * @param src pointer to source memory + * @param len number of bytes to copy + * @param callback function to call when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param dma Pointer to DMA registers. + * @param config The channel config struct + * @param firstSrcDst The source, destination, and count for the first transfer + * @param callback function is called when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback); +/** + * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver + */ + +/**@} end of group dma */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/flc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/flc.h new file mode 100644 index 00000000..849da76e --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/flc.h @@ -0,0 +1,193 @@ +/** + * @file flc.h + * @brief Flash Controller driver. + * @details This driver can be used to operate on the embedded flash memory. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ + +/* **** Includes **** */ +#include "flc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup flc Flash Controller (FLC) + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/// Bit mask that can be used to find the starting address of a page in flash +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) + +/// Calculate the address of a page in flash from the page number +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE)) + +/***** Function Prototypes *****/ + +/** + * @brief Initializes the Flash Controller for erase/write operations + * @return #E_NO_ERROR if successful. + */ +int MXC_FLC_Init(void); + +/** + * @brief Checks if Flash Controller is busy. + * @details Reading or executing from flash is not possible if flash is busy + * with an erase or write operation. + * @return If non-zero, flash operation is in progress + */ +int MXC_FLC_Busy(void); + +/** + * @brief Erases the entire flash array. + * @note This function must be executed from RAM. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_MassErase(void); + +/** + * @brief Erases the page of flash at the specified address. + * @note This function must be executed from RAM. + * @param address Any address within the page to erase. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_PageErase(uint32_t address); + +/** + * @brief Read Data out of Flash from an address + * + * @param[in] address The address to read from + * @param buffer The buffer to read the data into + * @param[in] len The length of the buffer + * + */ +void MXC_FLC_Read(int address, void *buffer, int len); + +/** + * @brief Writes data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param length Number of bytes to be written. + * @param buffer Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer); + +/** + * @brief Writes 32 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write32(uint32_t address, uint32_t data); + +/** + * @brief Writes 128 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write128(uint32_t address, uint32_t *data); + +/** + * @brief Enable flash interrupts + * @param flags Interrupts to enable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_EnableInt(uint32_t flags); + +/** + * @brief Disable flash interrupts + * @param flags Interrupts to disable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_DisableInt(uint32_t flags); + +/** + * @brief Retrieve flash interrupt flags + * @return Interrupt flags registers + */ +int MXC_FLC_GetFlags(void); + +/** + * @brief Clear flash interrupt flags + * @note Provide the bit position to clear, even if the flag is write-0-to-clear + * @param flags Flag bit(s) to clear + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_ClearFlags(uint32_t flags); + +/** + * @brief Unlock info block + * + * @param[in] address The address in the info block needing written to + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_UnlockInfoBlock(uint32_t address); + +/** + * @brief Lock info block + * + * @param[in] address The address in the info block that was written to + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_LockInfoBlock(uint32_t address); + +/** + * @brief Blocks write operations to the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageWrite(uint32_t address); + +/** + * @brief Blocks read operations from the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageRead(uint32_t address); + +/**@} end of group flc */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/gpio.h new file mode 100644 index 00000000..2c076b28 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/gpio.h @@ -0,0 +1,398 @@ +/** + * @file gpio.h + * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ + +/* **** Includes **** */ +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gpio General-Purpose Input/Output (GPIO) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ +/** + * @defgroup gpio_port_pin Port and Pin Definitions + * @ingroup gpio + * @{ + * @defgroup gpio_port Port Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) /**< Port 0 Define*/ +#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) /**< Port 1 Define*/ +#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) /**< Port 2 Define*/ +#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) /**< Port 3 Define*/ +/**@} end of gpio_port group*/ +/** + * @defgroup gpio_pin Pin Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ +#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ +#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ +#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ +#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ +#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ +#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ +#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ +#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ +#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ +#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ +#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ +#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ +#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */ +#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */ +#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */ +#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */ +#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */ +#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */ +#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */ +#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */ +#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */ +#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */ +#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */ +#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */ +#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */ +#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */ +#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */ +#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */ +#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */ +#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */ +#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */ +/**@} end of gpio_pin group */ +/**@} end of gpio_port_pin group */ + +/** + * @brief Type alias for a GPIO callback function with prototype: + * @code + void callback_fn(void *cbdata); + * @endcode + * @param cbdata A void pointer to the data type as registered when + * MXC_GPIO_RegisterCallback() was called. + */ +typedef void (*mxc_gpio_callback_fn)(void *cbdata); + +/** + * @brief Enumeration type for the GPIO Function Type + */ +typedef enum { + MXC_GPIO_FUNC_IN, /**< GPIO Input */ + MXC_GPIO_FUNC_OUT, /**< GPIO Output */ + MXC_GPIO_FUNC_ALT1, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT2, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT3, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT4, /**< Alternate Function Selection */ +} mxc_gpio_func_t; + +/** + * @brief Enumeration type for the voltage level on a given pin. + */ +typedef enum { + MXC_GPIO_VSSEL_VDDIO, /**< Set pin to VIDDIO voltage */ + MXC_GPIO_VSSEL_VDDIOH, /**< Set pin to VIDDIOH voltage */ +} mxc_gpio_vssel_t; + +/** + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). + */ +typedef enum { + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ +} mxc_gpio_drvstr_t; + +/** + * @brief Enumeration type for the type of GPIO pad on a given pin. + */ +typedef enum { + MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */ + MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */ + MXC_GPIO_PAD_WEAK_PULL_DOWN, /**< Set pad to weak pull-down */ + MXC_GPIO_PAD_PULL_UP = MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to default (weak) pull-up */ + MXC_GPIO_PAD_PULL_DOWN = MXC_GPIO_PAD_WEAK_PULL_DOWN /**< Set pad to default (weak) pull-down */ +} mxc_gpio_pad_t; + +/** + * @brief Structure type for configuring a GPIO port. + */ +typedef struct { + mxc_gpio_regs_t *port; /**< Pointer to GPIO regs */ + uint32_t mask; /**< Pin mask (multiple pins may be set) */ + mxc_gpio_func_t func; /**< Function type */ + mxc_gpio_pad_t pad; /**< Pad type */ + mxc_gpio_vssel_t vssel; /**< Voltage select */ + mxc_gpio_drvstr_t drvstr; /**< Drive Strength select */ +} mxc_gpio_cfg_t; + +/** + * @brief Enumeration type for the interrupt modes. + */ +typedef enum { + MXC_GPIO_INT_LEVEL, /**< Interrupt is level sensitive */ + MXC_GPIO_INT_EDGE /**< Interrupt is edge sensitive */ +} mxc_gpio_int_mode_t; + +/** + * @brief Enumeration type for the interrupt polarity. + */ +typedef enum { + MXC_GPIO_INT_FALLING, /**< Interrupt triggers on falling edge */ + MXC_GPIO_INT_HIGH, /**< Interrupt triggers when level is high */ + MXC_GPIO_INT_RISING, /**< Interrupt triggers on rising edge */ + MXC_GPIO_INT_LOW, /**< Interrupt triggers when level is low */ + MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ +} mxc_gpio_int_pol_t; + +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Init(uint32_t portMask); + +/** + * @brief Shutdown GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Shutdown(uint32_t portMask); + +/** + * @brief Reset GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Reset(uint32_t portMask); + +/** + * @brief Configure GPIO pin(s). + * @param cfg Pointer to configuration structure describing the pin. + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) input state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read + * @return The requested pin state. + */ +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Sets the pin(s) to a high level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set + */ +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Clears the pin(s) to a low level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to clear + */ +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Gets the pin(s) output state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read the output state of + * @return The state of the requested pin. + * + */ +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Write the pin(s) to a desired output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set output level of + * @param val Desired output level of the pin(s). This will be masked + * with the configuration mask. + */ +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val); + +/** + * @brief Toggles the the pin(s) output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to toggle the output + */ +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Configure GPIO interrupt(s) + * @param cfg Pointer to configuration structure describing the pin. + * @param pol Requested interrupt polarity. + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); + +/** + * @brief Enables the specified GPIO interrupt + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to enable interrupts for + * + */ +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Disables the specified GPIO interrupt. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to disable interrupts for + */ +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the GPIO port registers + * + * @return The requested interrupt status. + */ +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the GPIO port registers + * @param flags The flags to clear + */ +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags); + +/** + * @brief Registers a callback for the interrupt on a given port and pin. + * @param cfg Pointer to configuration structure describing the pin + * @param callback A pointer to a function of type #callback_fn. + * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. + * + */ +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); + +/** + * @brief GPIO IRQ Handler. @note If a callback is registered for a given + * interrupt, the callback function will be called. + * + * @param port Number of the port that generated the interrupt service routine. + * + */ +void MXC_GPIO_Handler(unsigned int port); + +/** + * @brief Set Voltage select for pins to VDDIO or VDDIOH + * + * @param port Pointer to the GPIO port registers + * @param[in] vssel VDDIO or VDDIOH to set the voltatge to + * @param[in] mask Pins in the GPIO port that will be set to the voltage. + */ +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); + +/** + * @brief Enables GPIO pins to be used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be enabled as a wakeup source. + */ +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Disables GPIO pins from being used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be disabled as a wakeup source. + */ +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Returns the pins currently enabled as wakeup sources. + * + * @param port The GPIO port to check. + * + * @returns The value of the wake enable register. + */ +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); + +/** + * @brief Set Drive Strength for pins. + * + * @param port The GPIO port. + * @param[in] ds Drive strength level. Ref /mxc_gpio_ds_t enum type. + * @param[in] mask Pins in the GPIO port that will be set to the voltage. + */ +int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); + +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/i2c.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/i2c.h new file mode 100644 index 00000000..6315f749 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/i2c.h @@ -0,0 +1,928 @@ +/** +* @file i2c.h +* @brief Inter-integrated circuit (I2C) communications interface driver. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ + +#include +#include +#include "mxc_sys.h" +#include "i2c_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i2c I2C + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ +#define MXC_I2C_STD_MODE 100000 +#define MXC_I2C_FAST_SPEED 400000 +#define MXC_I2C_FASTPLUS_SPEED 1000000 +#define MXC_I2C_HIGH_SPEED 3400000 + +typedef struct _i2c_req_t mxc_i2c_req_t; +/** + * @brief The callback used by the MXC_I2C_ReadByteInteractive() function. + * + * The callback routine used by the MXC_I2C_ReadByteInteractive() function. This + * function allows the application to determine whether the byte received + * should be acknowledged or not. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte received. + * + * @return 0 if the byte should not be acknowledged (NACK), non-zero to + * acknowledge the byte. + */ +typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte); + +/** + * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() + * function to indicate the transaction has completed. + * + * @param req The details of the transaction. + * @param result 0 if all bytes are acknowledged, 1 if any byte + * transmitted is not acknowledged, negative if error. + * See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result); + +/** + * @brief The callback routine used by the I2C Read/Write FIFO DMA + * functions to indicate the transaction has completed. + * + * @param len The length of data actually read/written + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result); + +/** + * @brief The information required to perform a complete I2C transaction as + * the bus master. + * + * The information required to perform a complete I2C transaction as the bus + * master. This structure is used by the MXC_I2C_MasterTransaction() and + * MXC_I2C_MasterTransactionAsync() functions. + */ +struct _i2c_req_t { + mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the + ///< I2C block used.) + unsigned int addr; ///< The 7-bit or 10-bit address of the slave. + unsigned char *tx_buf; ///< The buffer containing the bytes to write. + unsigned int tx_len; ///< The number of bytes to write. On return + ///< from the function, this will be set to + ///< the number of bytes actually transmitted. + unsigned char *rx_buf; ///< The buffer to read the data into. + unsigned int rx_len; ///< The number of bytes to read. On return + ///< from the function, this will be set to + ///< the number of bytes actually received. + int restart; ///< Controls whether the transaction is + ///< terminated with a stop or repeated start + ///< condition. Use 0 for a stop, non-zero + ///< for repeated start. + mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the + ///< transaction is complete or an error has + ///< occurred. This field may be set to NULL + ///< if no indication is necessary. This + ///< field is only used by the + ///< MXC_I2C_MasterTransactionAsync() function. + ///< MXC_I2C_MasterTransaction() ignores the + ///< callback field. +}; + +/** + * @brief The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. + * + * The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. It is up to the calling + * application to handle these events. + */ +typedef enum { + MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master + ///< requesting a write to the slave. + MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master + ///< requesting a read from the slave. + MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its + ///< threshold level. + MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its + ///< threshold level. + MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. + MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the + ///< transmit FIFO was empty. + MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive + ///< FIFO was already full. +} mxc_i2c_slave_event_t; + +/** + * @brief The callback routine used by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync functions to handle the various I2C + * slave events. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param event The event that occurred to trigger this callback. + * @param data This field is used to pass Success/Fail for the + * MXC_I2C_EVT_TRANS_COMP event. + * + * @return The return value is only used in the case of an MXC_I2C_EVT_RX_THRESH + * event. In this case, the return specifies if the last byte + * received should be acknowledged or not. Return 0 to acknowledge, + * non-zero to not acknowledge. The return value is ignored for all + * other event types. + */ +typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event, + void *data); + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable I2C peripheral. + * + * @note On default this function enables I2C peripheral clock and i2c gpio pins. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero + * for master mode, and zero for slave mode. + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr); + +/** + * @brief Set slave address for I2C instances acting as slaves on the bus. + * @note Set idx to zero, multiple I2C instances acting as slaves on the + * bus is not yet supported. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * @param idx Index of the I2C slave. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx); + +/** + * @brief Disable and shutdown I2C peripheral. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c); + +/** + * @brief Reset the I2C peripheral. + * @note The peripheral will need to be initialized with MXC_I2C_Init() before use + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz); + +/** + * @brief Get the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The I2C bus frequency in Hertz + */ +int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c); + +/** + * @brief Checks if the given I2C bus can be placed in sleep more. + * + * This functions checks to see if there are any on-going I2C transactions in + * progress. If there are transactions in progress, the application should + * wait until the I2C bus is free before entering a low-power state. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c); + +/** + * @brief Enables or disables clock stretching by the slave. + * + * Enables or disables clock stretching by the slave. This function has no + * affect when operating as the master. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param enable Enables clock stretching if non-zero, disables if zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable); + +/** + * @brief Determines if clock stretching has been enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Zero if clock stretching is disabled, non-zero otherwise + */ +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c); + +/** + * @brief Initializes the DMA for I2C DMA transactions. + * + * This function will release any acquired DMA channels before reacquiring and + * reconfiguring selected I2C DMA TX or RX channels. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * @param dma Pointer to DMA registers (selects the DMA block used). + * @param use_dma_tx If true, acquire and configure DMA TX channel, else release any + * acquired DMA TX channel. + * @param use_dma_rx If true, acquire and configure DMA RX channel, else release any + * acquired DMA RX channel. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_Init(mxc_i2c_regs_t *i2c, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx); + +/** + * @brief Retreive the DMA TX Channel associated with I2C instance. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * + * @return If successful, the DMA TX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t *i2c); + +/** + * @brief Retreive the DMA RX Channel associated with I2C instance. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * + * @return If successful, the DMA RX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t *i2c); + +/** + * @brief Sets the I2C instance's DMA TX/RX request select. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * @param txData Pointer to transmit buffer. + * @param rxData Pointer to receive buffer. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t *i2c, uint8_t *txData, uint8_t *rxData); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Generate a start (or repeated start) condition on the I2C bus. + * + * Generate a start (or repeated start) condition on the I2C bus. This + * function may opt to delay the actual generation of the start condition + * until data is actually transferred. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Start(mxc_i2c_regs_t *i2c); + +/** + * @brief Generate a stop condition on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c); + +/** + * @brief Write a single byte to the I2C bus. + * + * Write a single byte to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). If any + * bytes are pending in the FIFO (i.e. in the case of clock stretching), this + * function will return E_OVERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte to transmit. + * + * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if + * error. See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). If the FIFO + * is empty, this function will return E_UNDERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param ack Whether or not to acknowledge the byte once received. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. After the byte is received, the + * provided callback will be used to determine if the byte should be + * acknowledged or not before continuing with the rest of the transaction. + * This function assumes the I2C bus is already in the proper state (i.e. a + * start condition has already been generated and the bus is in the read + * phase of an I2C transaction). This function must be called with clock + * stretching enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param getAck A function to be called to determine whether or not + * to acknowledge the byte once received. A non-zero + * return value will acknowledge the byte. If this + * parameter is set to NULL or its return value is 0, + * the byte received will not be acknowledged (i.e., it + * will be NACKed). + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck); + +/** + * @brief Write multiple bytes to the I2C bus. + * + * Write multiple bytes to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to transmit. + * @param len The number of bytes to write. On return from the + * function, this will be set to the number of bytes + * actually transmitted. + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len); + +/** + * @brief Read multiple bytes from the I2C bus. + * + * Read multiple byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. On return from the + * function, this will be set to the number of bytes + * actually received. + * @param ack Whether or not to acknowledge the last byte once it is + * received. All previous bytes will be acknowledged. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO using DMA for longer reads. + * + * @note The operation is not complete until the callback has been called + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values. + */ +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes. + * + * @note The operation is not complete until the callback has been called + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c); + +/** + * @brief Get the presently set interrupt flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Pointer to variable to store interrupt status for interrupt register intfl0. + * @param flags1 Pointer to variable to store interrupt status for interrupt register intfl1. + */ +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); + +/** + * @brief Clears the Interrupt Flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Flags to clear in interrupt register intfl0. + * @param flags1 Flags to clear in interrupt register intfl1. + */ +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be enabled in int->en0 + * @param flags1 Interrupts to be enabled in int->en1 + */ +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Disable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be disabled in int->en0 + * @param flags1 Interrupts to be disabled in int->en1 + */ +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enables the slave preload mode + * + * Use this mode to preload the slave TX FIFO with data that can be sent when + * the slave is addressed for a read operation without software intervention. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c); + +/** + * @brief Disable the slave preload mode + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c); + +/** + * @brief Enables the slave to respond to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c); + +/** + * @brief Prevents the slave from responding to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the I2C Timeout + * + * The I2C timeout determines the amount of time the master will wait while the + * slave is stretching the clock, and the amount of time the slave will stretch + * the clock while waiting for software to unload the fifo. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param timeout Timeout in uS + */ +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout); + +/** + * @brief Get the current I2C timeout + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The current timeout in uS + */ +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c); + +/** + * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. + * + * Attempts to recover and reset an I2C bus by sending I2C clocks. During + * each clock cycle, the SDA line is cycled to determine if the master has + * control of the line. The following steps are performed to create one SCL + * clock cycle: + * 1. Drive SCL low + * 2. Verify SCL is low + * 3. Drive SDA low + * 4. Verify SDA is low + * 5. Release SDA allowing it to return high + * 6. Verify SDA is high + * 7. Release SCL allowing it to return high. + * 8. Verify SCL is high + * If any of the steps fail, the bus is considered to still be busy and the + * sequence is repeated up to the requested number of times. If all steps + * succeed, a final stop condition is generated on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param retries Number of times to attempt the clock cycle sequence. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking I2C master transaction. + * + * Performs a blocking I2C master transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * Steps 3-6 will be skipped if req->tx_len and req->rx_len are both 0. + * Steps 2-4 will be skipped if req->tx_len equals 0. + * Steps 4-6 will be skipped if req->rx_len equals 0. + * + * @param req Pointer to details of the transaction + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req); + +/** + * @brief Performs a non-blocking I2C master transaction. + * + * Performs a non-blocking I2C master transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req); + +/** + * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time + * in the ISR. This function initializes the DMA and acquires DMA channels + * if MXC_I2C_DMA_Init(...) was not called earlier. + * + * It is recommended to initialize the DMA by calling MXC_I2C_DMA_Init(...) function + * before calling MXC_I2C_MasterTransactionDMA(...). This provides flexibility in + * setting up generic DMA channel vectors during run-time without knowing what DMA + * channels will be acquired beforehand. + * + * Performs a non-blocking I2C transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req); + +/** + * @brief Performs a blocking I2C slave transaction. + * + * Performs a blocking I2C slave transaction. This function will block until a + * complete transaction with this slave has been performed. A transaction + * begins with the master addressing the slave and ends with a repeated start + * condition, a stop condition, or a bus error. The provided callback + * function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Performs a non-blocking I2C slave transaction. + * + * Performs a non-blocking I2C slave transaction. This request will remain active + * until a complete transaction with this slave has been performed. A + * transaction begins with the master begins with the master addressing the + * slave and ends with a repeated start condition, a stop condition, or a bus + * error. The provided callback function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @note MXC_I2C_AsyncHandler() must be called peridocally for this function + * to operate properly. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Set the receive threshold level. + * + * When operating as a master, the function sets the receive threshold level + * for when the master should unload the receive FIFO. Smaller values may + * consume more CPU cycles, but decrease the chances of the master delaying + * the generation of I2C bus clocks because it has no room in the FIFO to + * receive data. Larger values may consume fewer CPU cycles, but risk delays + * of the I2C clock. When operating as a slave, this function sets the number + * of bytes the slave transaction functions should receive before issuing a + * call to their callback function. Smaller values may consume more CPU + * cycles, but reduce the risk of missing data from the master due to the + * recieve FIFO being full. Larger values may reduce the number of CPU + * cycles, but may cause bytes sent from the master to be missed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The receive threshold value (in bytes). + */ +int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the transmit threshold level. + * + * When operating as a master, the function sets the transmit threshold level + * for when the master should add additional bytes to the transmit FIFO. + * Larger values may consume more CPU cycles, but decrease the chances of the + * master delaying the generation of I2C bus clocks because it has no data in + * the FIFO to transmit. Smaller values may consume fewer CPU cycles, but + * risk delays of the I2C clock. When operating as a slave, this function + * sets the number of bytes the slave transaction functions should transmit + * before issuing a call to their callback function. Larger values may + * consume more CPU cycles, but reduce the risk of not having data ready when + * the master requests it. Smaller values may reduce the number of CPU + * cycles, but may cause the master to read from an empty FIFO. (The master + * will read 0xFF in this case.) + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The transmit threshold value (in bytes). + */ +int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c); + +/** + * @brief Stop any asynchronous requests in progress. + * + * Stop any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be NOT executed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the I2C interrupt + * handler or periodically by the application if I2C interrupts are disabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_I2C_DMACallback(int ch, int error); + +/**@} end of group i2c */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/i3c.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/i3c.h new file mode 100644 index 00000000..75a32ecf --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/i3c.h @@ -0,0 +1,646 @@ +/** +* @file i3c.h +* @brief Improved Inter Integrated Circuit (I3C) communications interface driver. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_ + +#include +#include +#include "mxc_sys.h" +#include "i3c_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i3c I3C + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief Maximum supported IBI bytes. + * + */ +#define MXC_I3C_MAX_IBI_BYTES 7U + +/** + * @brief Invalid I2C/I3C address. + * + */ +#define MXC_I3C_ADDR_INVALID 0U + +typedef struct _i3c_ccc_req_t mxc_i3c_ccc_req_t; +typedef struct _i3c_req_t mxc_i3c_req_t; + +/** + * @brief The list of high-keeper options. + * + * This setting should match the high-keeper implementation of the device. + */ +typedef enum { + MXC_I3C_HIGH_KEEPER_OFF = MXC_S_I3C_CONT_CTRL0_HKEEP_OFF, ///< No high-keeper support + MXC_I3C_HIGH_KEEPER_ON_CHIP = MXC_S_I3C_CONT_CTRL0_HKEEP_ON_CHIP, ///< SCL and SDA pads + ///< have weak pull-ups + MXC_I3C_HIGH_KEEPER_EXT_SDA = MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SDA, ///< External high-keeper + ///< support for SDA signal + MXC_I3C_HIGH_KEEPER_EXT_SCL_SDA = MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA, + ///< External high-keeper support for SCL and SDA signals +} mxc_i3c_high_keeper_t; + +/** + * @brief The list of receive FIFO trigger levels. + */ +typedef enum { + MXC_I3C_RX_TH_NOT_EMPTY = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY, ///< + MXC_I3C_RX_TH_QUARTER_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL, ///< + MXC_I3C_RX_TH_HALF_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL, ///< + MXC_I3C_RX_TH_3_4_FULL = MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL, ///< +} mxc_i3c_rx_threshold_t; + +/** + * @brief The list of transmit FIFO trigger levels. + */ +typedef enum { + MXC_I3C_TX_TH_EMPTY = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY, ///< + MXC_I3C_TX_TH_QUARTER_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL, ///< + MXC_I3C_TX_TH_HALF_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL, ///< + MXC_I3C_TX_TH_ALMOST_FULL = MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL, ///< +} mxc_i3c_tx_threshold_t; + +/** + * @brief Transfer type enumeration. + * + */ +typedef enum { + MXC_I3C_TRANSFER_TYPE_READ = 0, + MXC_I3C_TRANSFER_TYPE_WRITE = 1 +} mxc_i3c_transfer_type_t; + +/** + * @brief IBI types. + * + */ +typedef enum { + MXC_I3C_IBI_TYPE_NONE = MXC_V_I3C_CONT_STATUS_IBITYPE_NONE, ///< + MXC_I3C_IBI_TYPE_IBI = MXC_V_I3C_CONT_STATUS_IBITYPE_IBI, ///< + MXC_I3C_IBI_TYPE_CONTROLLER_REQ = MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ, ///< + MXC_I3C_IBI_TYPE_HOTJOIN_REQ = MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ, ///< +} mxc_i3c_ibi_type_t; + +/* CCC request flags */ +#define MXC_I3C_CCC_HAS_DEFINING_BYTE (1U << 0) +#define MXC_I3C_CCC_HAS_SUB_COMMAND (1U << 1) +#define MXC_I3C_CCC_HAS_DATA (1U << 2) + +/** + * @brief I3C configuration options used during initialization. + * + */ +typedef struct { + bool target_mode; ///< If the driver should be initialized in target mode. + uint8_t static_addr; ///< Static address to use if target mode is used. + uint32_t pp_hz; ///< SCL frequency to be used in push-pull operation. + uint32_t od_hz; ///< SCL frequency to be used in open-drain operation. + uint32_t i2c_hz; ///< SCL frequency to be used in I2C operation. +} mxc_i3c_config_t; + +/** + * @brief Common Command Code request structure. + * + * Broadcast and direct commands are distinguished by MSB, i.e. if MSB being set + * implies a direct CCC while MSB being 0 implies a broadcast CCC. + * + */ +struct _i3c_ccc_req_t { + uint8_t ccc; ///< CCC command to send. + uint8_t target_addr; ///< Target address if CCC is a direct command. Ignored + ///< if CCC is a broadcast command. + mxc_i3c_transfer_type_t xfer_type; ///< Transfer type. Ignored for broadcast CCCs. + uint8_t flags; ///< See request flags above. + uint8_t def_byte; ///< Optional defining byte. Defined by CCC. + uint8_t sub_cmd; ///< Optional sub-command. Defined by CCC. Only used by direct + ///< CCCs. + unsigned char *tx_buf; ///< Optional data bytes to send. + uint8_t tx_len; ///< Length of optional data. + unsigned char *rx_buf; ///< Optional data bytes to read. + uint8_t rx_len; ///< Length of optional data. +}; + +/** + * @brief Private SDR/I2C request structure. + * + * SDR/I2C read and write to an I3C target. + * + */ +struct _i3c_req_t { + uint8_t target_addr; ///< Target address. + bool is_i2c; ///< If this is a legacy I2C transfer. + bool stop; ///< Send a STOP after the transaction. + unsigned char *tx_buf; ///< Optional data bytes to send. + uint16_t tx_len; ///< Length of optional data. + unsigned char *rx_buf; ///< Optional data bytes to read. + uint16_t rx_len; ///< Length of optional data. +}; + +/** + * @brief IBI payload request callback. Write additional byte to \a byte. + * + * This function will be called as long as non-zero is returned. + * + * @return Non-zero if a byte is written to \a byte, 0 to indicate no more additional + * bytes left to send. + */ +typedef int (*mxc_i3c_ibi_getbyte_t)(mxc_i3c_regs_t *i3c, unsigned char *byte); + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable I3C peripheral. + * + * @note On default this function enables I3C peripheral clock and I3C gpio pins. + * If you wish to skip clock and gpio initialization, define MSDK_NO_GPIO_CLK_INIT + * flag in project.mk file. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param config Config options. See \ref mxc_i3c_config_t for details. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_Init(mxc_i3c_regs_t *i3c, mxc_i3c_config_t *config); + +/** + * @brief Recover I3C bus if necessary. Should only be used in controller mode. + * + * @param i3c Pointer to I3C registers. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_Recover(mxc_i3c_regs_t *i3c); + +/** + * @brief Disable and shutdown I3C peripheral. + * + * @param i3c Pointer to I3C registers. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_Shutdown(mxc_i3c_regs_t *i3c); + +/** + * @brief Sets the SCL frequency for I3C push-pull operation. + * + * Recommended value for push-pull frequency is fclk / 2, where fclk is the I3C + * peripheral clock. Note that I3C supports a maximum frequency of 12.5MHz. + * Should only be used in controller mode. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param frequency Frequency in hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I3C_SetPPFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency); + +/** + * @brief Get the frequency of the I3C push-pull mode. Should only be used in + * controller mode. + * + * @param i3c Pointer to I3C registers. + * + * @return The I3C push-pull frequency in hertz. + */ +unsigned int MXC_I3C_GetPPFrequency(mxc_i3c_regs_t *i3c); + +/** + * @brief Sets the SCL frequency for I3C open-drain operation. + * + * Note that open-drain SCL also depends on push-pull SCL settings. See + * MXC_I3C_SetPPFrequency(). Should only be used in controller mode. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param frequency Frequency in hertz. + * @param highPP Set SCL high period to high period in push-pull mode. + * This is used to prevent legacy I2C devices from detecting + * I3C messages. + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I3C_SetODFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency, bool highPP); + +/** + * @brief Get the frequency of the I3C open-drain mode. Should only be used in + * controller mode. + * + * @param i3c Pointer to I3C registers. + * + * @return The I3C open-drain frequency in hertz. + */ +unsigned int MXC_I3C_GetODFrequency(mxc_i3c_regs_t *i3c); + +/** + * @brief Sets the SCL frequency for I2C mode. Should only be used in controller mode. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param frequency Frequency in hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I3C_SetI2CFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency); + +/** + * @brief Get the frequency of the I3C in I2C mode. Should only be used in controller + * mode. + * + * @param i3c Pointer to I3C registers. + * + * @return The frequency of I2C mode in hertz. + */ +unsigned int MXC_I3C_GetI2CFrequency(mxc_i3c_regs_t *i3c); + +/** + * @brief Sets the skew value for I3C push-pull operation. + * + * Note that this setting requires peripheral clock (fclk) to SCL ratio to be at + * least 4. See MXC_I3C_SetPPFrequency(). Should only be used in controller mode. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param skew Skew value in units of peripheral clock cycles. Cannot + * be greater than 7. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_SetSkew(mxc_i3c_regs_t *i3c, uint8_t skew); + +/** + * @brief Sets the high-keeper implementation for the device. Should only be used + * in controller mode. + * + * See \ref mxc_i3c_high_keeper_t. + * + * @param i3c Pointer to I3C registers (selects the I3C block used). + * @param hkeep High-keeper option. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_SetHighKeeperMode(mxc_i3c_regs_t *i3c, mxc_i3c_high_keeper_t hkeep); + +/** + * @brief Emit an I2C or I3C start in controller mode. + * + * @param i3c Pointer to I3C registers. + * @param isI2C True if I2C, false if I3C. + * @param xferType Transfer type. See \ref mxc_i3c_transfer_type_t. + * @param addr Target address. + * @param readCount Number of bytes to read if this is a read message. + * + * @return Success/Fail. E_SUCCESS if request is successful, E_BUSY if an IBI occurrs, + * one of \ref MXC_Error_Codes otherwise. + */ +int MXC_I3C_EmitStart(mxc_i3c_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType, + uint8_t addr, uint8_t readCount); + +/** + * @brief Emit an I3C target reset pattern in controller mode. + * + * @param i3c Pointer to I3C registers. + * + * @return Success/Fail. See \ref MXC_Error_Codes for possible return codes. + */ +int MXC_I3C_ResetTarget(mxc_i3c_regs_t *i3c); + +/** + * @brief Emit an I2C STOP in controller mode. + * + * @param i3c Pointer to I3C registers. + */ +void MXC_I3C_EmitI2CStop(mxc_i3c_regs_t *i3c); + +/** + * @brief Emit an I3C STOP in controller mode. + * + * @param i3c Pointer to I3C registers. + */ +void MXC_I3C_EmitStop(mxc_i3c_regs_t *i3c); + +/** + * @brief Send or broadcast a Common Command Code (CCC). + * + * @param i3c Pointer to I3C registers. + * @param req CCC request data. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_Controller_CCC(mxc_i3c_regs_t *i3c, const mxc_i3c_ccc_req_t *req); + +/** + * @brief Perform a private SDR or a legacy I2C transfer. + * + * @param i3c Pointer to I3C registers. + * @param req Request data. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_Controller_Transaction(mxc_i3c_regs_t *i3c, const mxc_i3c_req_t *req); + +/** + * @brief Start dynamic address assignment. + * + * If E_SUCCESS is returned, PID, BCR and DCR are read into their corresponding buffers. + * Call MXC_I3C_ControllerDAA again with a valid \a addr to assign a dynamic address to + * the target and read PID, BCR and DCR of the next target. If E_SHUTDOWN is returned, + * DAA process is complete + * + * @param i3c Pointer to I3C registers. + * @param pid Buffer to store provisioned ID of a target. + * @param bcr Buffer to store Bus Characteristics Register of a target. + * @param dcr Buffer to store Device Characteristics Register of a target. + * + * @return Success/Fail, E_SUCCESS if request is successful, E_SHUTDOWN if DAA is + * finished, E_FAIL if an error occurs during DAA, one of \ref MXC_Error_Codes + * otherwise. + */ +int MXC_I3C_Controller_DAA(mxc_i3c_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr, + uint8_t *dcr); + +/** + * @brief Generate a hot-join request in target mode. + * + * Hot-Join will only be generated if the target is powered on after the bus is + * configured or physically connected to an already configured bus. If the active + * controller disables the Hot-Join events through DISEC CCCs, it will not be + * generated either. + * + * @param i3c Pointer to I3C registers. + * + * @return E_SUCCESS if request is submitted. E_BAD_STATE if operation is not allowed in + * the current state. E_NOT_SUPPORTED is returned in case HotJoin generation is not + * supported. Note that return value of E_SUCCESS does not guarantee a successful + * Hot-Join since the decision is up to the controller. + */ +int MXC_I3C_HotJoin(mxc_i3c_regs_t *i3c); + +/** + * @brief Generate an In-Band Interrupt in target mode. + * + * @param i3c Pointer to I3C registers. + * @param mdb Mandatory data byte to be sent if IBI is acknowledged. + * @param getByteCb Callback to get additional databytes from the application. Pass NULL + * if no additional data bytes except \a mdb will be sent with the IBI + * request. + * + * @return E_SUCCESS if request is submitted. E_BAD_STATE if operation is not allowed in + * the current state. E_NOT_SUPPORTED is returned in case IBI generation is not + * supported. Note that return value of E_SUCCESS does not guarantee that the + * request has been acknowledged. + */ +int MXC_I3C_RequestIBI(mxc_i3c_regs_t *i3c, unsigned char mdb, mxc_i3c_ibi_getbyte_t getByteCb); + +/** + * @brief Enter offline mode and stop participating on the bus. Valid only in target mode. + * + * Offline mode is only allowed if the target has already been assigned a dynamic address. + * + * @param i3c Pointer to I3C registers. + * + * @return E_SUCCESS if device switches to offline mode, E_BAD_STATE otherwise. + */ +int MXC_I3C_Standby(mxc_i3c_regs_t *i3c); + +/** + * @brief Exit offline mode using previously assigned dynamic address. Valid only in + * target mode. + * + * @param i3c Pointer to I3C registers. + * + * @return E_SUCCESS if device comes out of offline mode, E_BAD_STATE otherwise. + */ +int MXC_I3C_Wakeup(mxc_i3c_regs_t *i3c); + +/** + * @brief Unloads bytes from the receive FIFO. Both controller and target mode can + * use this function to read the receive FIFO. + * + * @param i3c Pointer to I3C registers. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param timeout Timeout in microseconds to wait. Use -1 to wait indefinitely. + * + * @return The number of bytes actually read. + */ +int MXC_I3C_ReadRXFIFO(mxc_i3c_regs_t *i3c, volatile unsigned char *bytes, unsigned int len, + int timeout); + +/** + * @brief Loads bytes into the transmit FIFO. Both controller and target mode can + * use this function to write into the transmit FIFO. + * + * @param i2c Pointer to I3C registers. + * @param bytes The buffer containing the bytes to write. + * @param len The number of bytes to write. + * @param end If set to true, last byte in \a bytes is marked as end-of-data. + * @param timeout Timeout in microseconds to wait. Use -1 to wait indefinitely. + * + * @return The number of bytes actually written. + */ +int MXC_I3C_WriteTXFIFO(mxc_i3c_regs_t *i3c, const unsigned char *bytes, unsigned int len, bool end, + int timeout); + +/** + * @brief Return the current error code if any. + * + * @param i3c Pointer to I3C registers. + * @return E_NO_ERROR if no error found. + * E_NO_RESPONSE if request NACKed. + * E_ABORT if write aborted. + * E_BAD_STATE if request is invalid or a message mode error occurs. + * E_TIME_OUT if a timeout error occurred. + * E_OVERFLOW in case of read data underrun or write data overflow. + * E_FAIL otherwise. + */ +int MXC_I3C_Controller_GetError(mxc_i3c_regs_t *i3c); + +/** + * @brief Clear the error register. + * + * @param i3c Pointer to I3c registers. + */ +void MXC_I3C_Controller_ClearError(mxc_i3c_regs_t *i3c); + +/** + * @brief Set the transmit threshold level. + * + * When operating as a controller, the function sets the transmit threshold level + * for when the master should add additional bytes to the transmit FIFO. Can be used in + * both controller and target mode. + * + * @param i3c Pointer to I3C registers. + * @param rxth Receive threshold level to set. See \ref mxc_i3c_rx_threshold_t + * for available options. + * @param txth Transmit threshold level to set. See \ref mxc_i3c_tx_threshold_t + * for available options. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I3C_SetRXTXThreshold(mxc_i3c_regs_t *i3c, mxc_i3c_rx_threshold_t rxth, + mxc_i3c_tx_threshold_t txth); + +/** + * @brief Returns the dynamic address in target mode. + * + * @param i3c Pointer to I3C registers. + * + * @return Dynamic address set by bus controller. If the address is invalid or + * device is not running in target mode, then 0 is returned. + */ +uint8_t MXC_I3C_GetDynamicAddress(mxc_i3c_regs_t *i3c); + +/** + * @brief Interrupt handler. + * + * @param i3c Pointer to I3C registers. + */ +void MXC_I3C_IRQHandler(mxc_i3c_regs_t *i3c); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. Valid in + * both controller and target mode. + * + * @param i3c Pointer to I3C registers. + */ +void MXC_I3C_ClearRXFIFO(mxc_i3c_regs_t *i3c); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. Valid in + * both controller and target mode. + * + * @param i3c Pointer to I3C registers. + */ +void MXC_I3C_ClearTXFIFO(mxc_i3c_regs_t *i3c); + +/** + * @brief Return the number of bytes in receive buffer or FIFO. + * + * @param i3c Pointer to I3C registers. + * + * @return Number of bytes in receive buffer or FIFO. + */ +unsigned int MXC_I3C_Controller_GetRXCount(mxc_i3c_regs_t *i3c); + +/** + * @brief Return the number of bytes in transmit buffer or FIFO. + * + * @param i3c Pointer to I3C registers. + * + * @return Number of bytes in transmit buffer or FIFO. + */ +unsigned int MXC_I3C_Controller_GetTXCount(mxc_i3c_regs_t *i3c); + +/** + * @brief Enable controller interrupts. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to set. + */ +void MXC_I3C_Controller_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask); + +/** + * @brief Disable controller interrupts. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to set. + */ +void MXC_I3C_Controller_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask); + +/** + * @brief Get the presently set interrupt flags. + * + * @param i3c Pointer to I3C registers. + * + * @return See \ref MXC_Error_Codes for a list of return values. + */ +unsigned int MXC_I3C_Controller_GetFlags(mxc_i3c_regs_t *i3c); + +/** + * @brief Clear controller interrupts. + * + * Note that some bits cannot be cleared manually and self-clear only when their + * respective conditions occur. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to clear. + */ +void MXC_I3C_Controller_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask); + +/** + * @brief Enable target interrupts. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to set. + */ +void MXC_I3C_Target_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask); + +/** + * @brief Disable target interrupts. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to set. + */ +void MXC_I3C_Target_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask); + +/** + * @brief Get the presently set target mode interrupt flags. + * + * @param i3c Pointer to I3C registers. + * + * @return See \ref MXC_Error_Codes for a list of return values. + */ +int MXC_I3C_Target_GetFlags(mxc_i3c_regs_t *i3c); + +/** + * @brief Clear target interrupts. + * + * Note that some bits cannot be cleared manually and self-clear only when their + * respective conditions occur. + * + * @param i3c Pointer to I3C registers. + * @param mask Interrupt mask to clear. + */ +void MXC_I3C_Target_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask); + +/**@} end of group i3c */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I3C_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h new file mode 100644 index 00000000..252bd958 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h @@ -0,0 +1,79 @@ +/** + * @file icc.h + * @brief Instruction Controller Cache(ICC) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ + +/* **** Includes **** */ +#include +#include "icc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup icc ICC + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for the Cache ID Register + */ +typedef enum { + ICC_INFO_RELNUM, // Identifies the RTL release version + ICC_INFO_PARTNUM, // Specifies the value of C_ID Port Number + ICC_INFO_ID // Specifies the value of Cache ID +} mxc_icc_info_t; + +/** + * @brief Reads the data from the Cache Id Register. + * @param cid Enumeration type for Cache Id Register. + * @retval Returns the contents of Cache Id Register. + */ +int MXC_ICC_ID(mxc_icc_info_t cid); + +/** + * @brief Enable the instruction cache controller. + */ +void MXC_ICC_Enable(void); + +/** + * @brief Disable the instruction cache controller. + */ +void MXC_ICC_Disable(void); + +/** + * @brief Flush the instruction cache controller. + */ +void MXC_ICC_Flush(void); + +/**@} end of group icc */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h new file mode 100644 index 00000000..0e4ea3bb --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h @@ -0,0 +1,229 @@ +/** + * @file lp.h + * @brief Low Power(LP) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ + +/* **** Includes **** */ +#include +#include "pwrseq_regs.h" +#include "mcr_regs.h" +#include "gcr_regs.h" +#include "gpio.h" +#include "tmr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup pwrseq Low Power (LP) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for voltage selection + * + */ +typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t; + +/** + * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterSleepMode(void); + +/** + * @brief Places the device into Low Power mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterLowPowerMode(void); + +/** + * @brief Places the device into Micro Power mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterMicroPowerMode(void); + +/** + * @brief Places the device into Standby mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterStandbyMode(void); + +/** + * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC or external interrupt occur. + */ +void MXC_LP_EnterBackupMode(void); + +/** + * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. + */ +void MXC_LP_EnterPowerDownMode(void); + +/** + * @brief Set ovr bits to set the voltage the micro will run at. + * + * @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t + */ +void MXC_LP_SetOVR(mxc_lp_ovr_t ovr); + +/** + * @brief Turn bandgap on + */ +void MXC_LP_BandgapOn(void); + +/** + * @brief Turn bandgap off + */ +void MXC_LP_BandgapOff(void); + +/** + * @brief Is the bandgap on or off + * + * @return 1 = bandgap on , 0 = bandgap off + */ +int MXC_LP_BandgapIsOn(void); + +/** + * @brief clear all wake up status + */ +void MXC_LP_ClearWakeStatus(void); + +/** + * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. + * Call this function multiple times to enable pins on multiple ports. This function does not configure + * the GPIO pins nor does it setup their interrupt functionality. + * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ + +void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); + +/** + * @brief Disables the selected GPIO port and its selected pins as a wake up source. + * Call this function multiple times to disable pins on multiple ports. + * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ +void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); + +/** + * @brief Enables the RTC alarm to wake up the device from any low power mode. + */ +void MXC_LP_EnableRTCAlarmWakeup(void); + +/** + * @brief Disables the RTC alarm from waking up the device. + */ +void MXC_LP_DisableRTCAlarmWakeup(void); + +/** + * @brief Enables Timer to wakeup from any low power mode. + * + * @param tmr Pointer to timer module. + */ +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr); + +/** + * @brief Disables Timer from waking up device. + * + * @param tmr Pointer to timer module. + */ +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr); + +/** + * @brief Enables the USB to wake up the device from any low power mode. + */ +void MXC_LP_EnableUSBWakeup(void); + +/** + * @brief Disables the USB from waking up the device. + */ +void MXC_LP_DisableUSBWakeup(void); + +/** + * @brief Enables the WUT alarm to wake up the device from any low power mode. + */ +void MXC_LP_EnableWUTAlarmWakeup(void); + +/** + * @brief Disables the WUT alarm from waking up the device. + */ +void MXC_LP_DisableWUTAlarmWakeup(void); + +/** + * @brief Enables the HA0 to wake up the device from any low power mode. + */ +void MXC_LP_EnableHA0Wakeup(void); + +/** + * @brief Disables the HA)0 from waking up the device. + */ +void MXC_LP_DisableHA0Wakeup(void); +/** + * @brief Enables the HA1 to wake up the device from any low power mode. + */ +void MXC_LP_EnableHA1Wakeup(void); + +/** + * @brief Disables the HA1 from waking up the device. + */ +void MXC_LP_DisableHA1Wakeup(void); + +/** + * @brief Configure which clocks are powered down at deep sleep and which are not affected. + * + * @note Need to configure all clocks at once any clock not passed in the mask will be unaffected by Deepsleep. This will + * always overwrite the previous settings of ALL clocks. + * + * @param[in] mask The mask of the clocks to power down when part goes into deepsleep + * + * @return #E_NO_ERROR or error based on /ref MXC_Error_Codes + */ +int MXC_LP_ConfigDeepSleepClocks(uint32_t mask); + +/** + * @brief Enable NFC Oscilator Bypass + */ +void MXC_LP_NFCOscBypassEnable(void); + +/** + * @brief Disable NFC Oscilator Bypass + */ +void MXC_LP_NFCOscBypassDisable(void); + +/** + * @brief Is NFC Oscilator Bypass Enabled + * + * @return 1 = enabled, 0 = disabled + */ +int MXC_LP_NFCOscBypassIsEnabled(void); + +/**@} end of group pwrseq */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mpc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mpc.h new file mode 100644 index 00000000..d3cd0488 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mpc.h @@ -0,0 +1,97 @@ +/** + * @file mpc.h + * @brief Memory Protection Controller (MPC) Header File. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#if CONFIG_TRUSTED_EXECUTION_SECURE + +/**** Includes ****/ +#include +#include "mxc_device.h" +#include "mpc_regs.h" + +/**** Defines ****/ + +/**** Function Prototypes ****/ + +/** + * @brief Checks whether a region fits within the constraints of physical + * memory (Flash or SRAM). + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_CheckPhyBoundaries(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Get the MPC register instance where the address is located. + * @param addr Address within memory. + * @return Pointer to MPC registers associated with the address. + */ +mxc_mpc_regs_t *MXC_MPC_GetInstance(uint32_t addr); + +/** + * @brief Gets the MPC block index that the register is located in which + * is associated to the bit location of MPC_BLK_LUT register. + * This function is NOT associated with the MPC_BLK_IDX register. + * @param mpc Pointer to MPC region associated with the addr (param[1]). + * @param addr Address within memory. + * @return The block index if successful. If Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_GetBlockIdx(mxc_mpc_regs_t *mpc, uint32_t addr); + +/** + * @brief Sets the region to Secure. + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_SetSecure(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Sets the region to Non-Secure. + * @param start_addr Starting address of region to check. + * @param end_addr Ending address of region to check. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_SetNonSecure(uint32_t start_addr, uint32_t end_addr); + +/** + * @brief Locks the MPC registers. Prevents write access. + * @param mpc Pointer to MPC registers to lockdown. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_MPC_Lock(mxc_mpc_regs_t *mpc); + +#endif + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MPC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc.h new file mode 100644 index 00000000..16256644 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ + +#include "mxc_device.h" +#include "mxc_delay.h" +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "mxc_lock.h" +#include "mxc_pins.h" +#include "mxc_sys.h" +#include "nvic_table.h" +#ifdef LIB_BOARD +#include "board.h" +#endif + +/* + * Peripheral Driver Includes + */ +#include "dma.h" +#include "flc.h" +#include "gpio.h" +#include "i2c.h" +#include "icc.h" +#include "lp.h" +#include "rtc.h" +#include "spi.h" +#include "tmr.h" +#include "uart.h" +#include "wdt.h" +#include "wut.h" + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h new file mode 100644 index 00000000..f87740ca --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h @@ -0,0 +1,92 @@ +/** + * @file mxc_assert.h + * @brief Assertion checks for debugging. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ + +/* **** Includes **** */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_assertions Assertion Checks for Debugging + * @brief Assertion checks for debugging. + * @{ + */ +/* **** Definitions **** */ +/** + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +///@cond +#ifdef MXC_ASSERT_ENABLE +/** + * Macro that checks the expression for true and generates an assertion. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT(expr) \ + if (!(expr)) { \ + mxc_assert(#expr, __FILE__, __LINE__); \ + } +/** + * Macro that generates an assertion with the message "FAIL". + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__); +#else +#define MXC_ASSERT(expr) +#define MXC_ASSERT_FAIL() +#endif +///@endcond +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Assert an error when the given expression fails during debugging. + * @param expr String with the expression that failed the assertion. + * @param file File containing the failed assertion. + * @param line Line number for the failed assertion. + * @note This is defined as a weak function and can be overridden at the + * application layer to print the debugging information. + * @code + * printf("%s, file: %s, line %d\n", expr, file, line); + * @endcode + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +void mxc_assert(const char *expr, const char *file, int line); + +/**@} end of group MXC_Assertions*/ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h new file mode 100644 index 00000000..e3ec9af9 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h @@ -0,0 +1,125 @@ +/** + * @file mxc_delay.h + * @brief Asynchronous delay routines based on the SysTick Timer. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup devicelibs + * @defgroup MXC_delay Delay Utility Functions + * @brief Asynchronous delay routines based on the SysTick Timer + * @{ + */ + +/***** Definitions *****/ +/** + * Macro used to specify a microsecond timing parameter in seconds. + * \code + * x = SEC(3) // 3 seconds -> x = 3,000,000 + * \endcode + */ +#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL) +/** + * Macro used to specify a microsecond timing parameter in milliseconds. + * \code + * x = MSEC(3) // 3ms -> x = 3,000 + * \endcode + */ +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +/** + * Macro used to specify a microsecond timing parameter. + * \code + * x = USEC(3) // 3us -> x = 3 + * \endcode + */ +#define MXC_DELAY_USEC(us) (us) + +/** + * @brief The callback routine used by MXC_DelayAsync() when the delay is complete + * or aborted early. + * + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_delay_complete_t)(int result); + +/***** Function Prototypes *****/ + +/** + * @brief Blocks and delays for the specified number of microseconds. + * @details Uses the SysTick to create the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_Delay(uint32_t us); + +/** + * @brief Starts a non-blocking delay for the specified number of + * microseconds. + * @details Uses the SysTick to time the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @note MXC_Delay_handler() must be called from the SysTick interrupt service + * routine or at a rate greater than the SysTick overflow rate. + * @param us microseconds to delay + * @param callback Function pointer to the function to call after the delay has expired. + * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another + * delay request. + */ +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); + +/** + * @brief Returns the status of a non-blocking delay request + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + * @return #E_BUSY until the requested delay time has expired. + */ +int MXC_DelayCheck(void); + +/** + * @brief Stops an asynchronous delay previously started. + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + */ +void MXC_DelayAbort(void); + +/** + * @brief Processes the delay interrupt. + * @details This function must be called from the SysTick IRQ or polled at a + * rate greater than the SysTick overflow rate. + */ +void MXC_DelayHandler(void); + +/**@} end of group MXC_delay */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h new file mode 100644 index 00000000..ba719631 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ + +#include "max32657.h" +#include "mxc_errors.h" +#include "mxc_pins.h" + +#ifndef TARGET +#error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV +#error TARGET_REV NOT DEFINED +#endif + +#if (TARGET_REV == 0x4131) +// A1 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 0 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif /* if(TARGET_REV == ...) */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h new file mode 100644 index 00000000..b369f402 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h @@ -0,0 +1,78 @@ +/** + * @file mxc_errors.h + * @brief List of common error return codes for Maxim Integrated libraries. +*/ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ + +/** + * @ingroup syscfg + * @defgroup MXC_Error_Codes Error Codes + * @brief A list of common error codes used by the API. + * @note A Negative Error Convention is used to avoid conflict with + * positive, Non-Error, returns. + * @{ + */ + +/** No Error */ +#define E_NO_ERROR 0 +/** No Error, success */ +#define E_SUCCESS 0 +/** Pointer is NULL */ +#define E_NULL_PTR -1 +/** No such device */ +#define E_NO_DEVICE -2 +/** Parameter not acceptable */ +#define E_BAD_PARAM -3 +/** Value not valid or allowed */ +#define E_INVALID -4 +/** Module not initialized */ +#define E_UNINITIALIZED -5 +/** Busy now, try again later */ +#define E_BUSY -6 +/** Operation not allowed in current state */ +#define E_BAD_STATE -7 +/** Generic error */ +#define E_UNKNOWN -8 +/** General communications error */ +#define E_COMM_ERR -9 +/** Operation timed out */ +#define E_TIME_OUT -10 +/** Expected response did not occur */ +#define E_NO_RESPONSE -11 +/** Operations resulted in unexpected overflow */ +#define E_OVERFLOW -12 +/** Operations resulted in unexpected underflow */ +#define E_UNDERFLOW -13 +/** Data or resource not available at this time */ +#define E_NONE_AVAIL -14 +/** Event was shutdown */ +#define E_SHUTDOWN -15 +/** Event was aborted */ +#define E_ABORT -16 +/** The requested operation is not supported */ +#define E_NOT_SUPPORTED -17 +/** The requested operation is failed */ +#define E_FAIL -255 +/**@} end of MXC_Error_Codes group */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h new file mode 100644 index 00000000..880692b0 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h @@ -0,0 +1,76 @@ +/** + * @file mxc_lock.h + * @brief Exclusive access lock utility functions. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ + +/* **** Includes **** */ +#include "mxc_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_lock_utilities Exclusive Access Locks + * @brief Lock functions to obtain and release a variable for exclusive + * access. These functions are marked interrupt safe if they are + * interrupt safe. + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Attempts to acquire the lock. + * @details This in an interrupt safe function that can be used as a mutex. + * The lock variable must remain in scope until the lock is + * released. Will not block if another thread has already acquired + * the lock. + * @param lock Pointer to variable that is used for the lock. + * @param value Value to be place in the lock. Can not be 0. + * + * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. + */ +int MXC_GetLock(uint32_t *lock, uint32_t value); + +/** + * @brief Free the given lock. + * @param[in,out] lock Pointer to the variable used for the lock. When the lock + * is free, the value pointed to by @p lock is set to zero. + */ +void MXC_FreeLock(uint32_t *lock); + +/**@} end of group mxc_lock_utilities */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h new file mode 100644 index 00000000..ee291931 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h @@ -0,0 +1,60 @@ +/** + * @file mxc_pins.h + * @brief This file contains constant pin configurations for the peripherals. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ + +#include "gpio.h" + +/***** Global Variables *****/ +// Predefined GPIO Configurations +extern const mxc_gpio_cfg_t gpio_cfg_i3c; + +extern const mxc_gpio_cfg_t gpio_cfg_uart; + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +extern const mxc_gpio_cfg_t gpio_cfg_tmr0; +extern const mxc_gpio_cfg_t gpio_cfg_tmr1; +extern const mxc_gpio_cfg_t gpio_cfg_tmr2; +extern const mxc_gpio_cfg_t gpio_cfg_tmr3; +extern const mxc_gpio_cfg_t gpio_cfg_tmr4; +extern const mxc_gpio_cfg_t gpio_cfg_tmr5; +extern const mxc_gpio_cfg_t gpio_cfg_tmr0b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr1b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr2b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr3b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr4b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr5b; + +// SPI v2 Pin Definitions +extern const mxc_gpio_cfg_t gpio_cfg_spi_standard; +extern const mxc_gpio_cfg_t gpio_cfg_spi_3wire; +extern const mxc_gpio_cfg_t gpio_cfg_spi_dual; +extern const mxc_gpio_cfg_t gpio_cfg_spi_quad; + +// SPI v2 Target Selects Pin Definitions +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts0; +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts1; +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts2; + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h new file mode 100644 index 00000000..a763886d --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -0,0 +1,356 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mxc_sys.h + * @brief System level header file. + */ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ + +#include "mxc_device.h" +#include "gcr_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mxc_sys System Configuration (MXC_SYS) + * @ingroup syscfg + * @details API for system configuration including clock source selection and entering critical sections of code. + * @{ + */ + +/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ +typedef enum { + MXC_SYS_RESET0_DMA0 = MXC_F_GCR_RST0_DMA0_POS, /**< Reset Non-Secure DMA0 */ + MXC_SYS_RESET0_WDT = MXC_F_GCR_RST0_WDT_POS, /**< Reset WDT */ + MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ + MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */ + MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */ + MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */ + MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */ + MXC_SYS_RESET0_TMR4 = MXC_F_GCR_RST0_TMR4_POS, /**< Reset TMR4 */ + MXC_SYS_RESET0_TMR5 = MXC_F_GCR_RST0_TMR5_POS, /**< Reset TMR5 */ + MXC_SYS_RESET0_UART = MXC_F_GCR_RST0_UART_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_SPI = MXC_F_GCR_RST0_SPI_POS, /**< Reset SPI */ + MXC_SYS_RESET0_I3C = MXC_F_GCR_RST0_I3C, /**< Reset I2C/I3C */ + MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ + MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ + MXC_SYS_RESET0_DMA1 = MXC_F_GCR_RST0_DMA1_POS, /**< Reset Secure DMA1 */ + MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ + MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ + MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ + /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ + MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ + MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ + MXC_SYS_RESET1_AUTOCAL = (MXC_F_GCR_RST1_AUTOCAL_POS + 32), /**< Reset AUTOCAL */ +} mxc_sys_reset_t; + +/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ +typedef enum { + MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA0 = MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable Non-Secure DMA0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI = MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ + MXC_SYS_PERIPH_CLOCK_UART = MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ + MXC_SYS_PERIPH_CLOCK_I3C = MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable TMR0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable TMR1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable TMR2 clock */ + MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable TMR3 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = MXC_F_GCR_PCLKDIS0_TMR4_POS, /**< Disable TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ + /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ + MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ + MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ + MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ + MXC_SYS_PERIPH_CLOCK_DMA1 = + (MXC_F_GCR_PCLKDIS1_DMA1_POS + 32), /**< Disable Secure DMA1 clock */ + MXC_SYS_PERIPH_CLOCK_WDT = (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ +} mxc_sys_periph_clock_t; + +/** @brief Enumeration to select System Clock source */ +// TODO(ME30): CLKCTRL sysclk_sel values seem incorrect. +typedef enum { + MXC_SYS_CLOCK_IPO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */ + MXC_SYS_CLOCK_IBRO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */ + MXC_SYS_CLOCK_ERFO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, /**< Select the External RF Crystal Oscillator */ + MXC_SYS_CLOCK_INRO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */ + MXC_SYS_CLOCK_ERTCO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */ + // MXC_SYS_CLOCK_EXTCLK = + // MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ + // TODO(JC): ^^^ EXTCLK select is missing from gcr_regs.h (should be 0x7) +} mxc_sys_system_clock_t; + +/** @brief Enumeration to set the System Clock divider */ +typedef enum { + MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1, + MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2, + MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4, + MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8, + MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16, + MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32, + MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64, + MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 +} mxc_sys_system_clock_div_t; + +#define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute +#define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN +#define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum + +/***** Function Prototypes *****/ + +typedef struct { + int ie_status; + int in_critical; +} mxc_crit_state_t; + +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; + +static inline void _mxc_crit_get_state(void) +{ +#ifndef __riscv + /* + On ARM M the 0th bit of the Priority Mask register indicates + whether interrupts are enabled or not. + + 0 = enabled + 1 = disabled + */ + uint32_t primask = __get_PRIMASK(); + _state.ie_status = (primask == 0); +#else + /* + On RISC-V bit position 3 (Machine Interrupt Enable) of the + mstatus register indicates whether interrupts are enabled. + + 0 = disabled + 1 = enabled + */ + uint32_t mstatus = get_mstatus(); + _state.ie_status = ((mstatus & (1 << 3)) != 0); +#endif +} + +/** + * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section. + * @details Ex: + * @code + * MXC_SYS_Crit_Enter(); + * printf("Hello critical section!\n"); + * MXC_SYS_Crit_Exit(); + * @endcode + * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way. + * @returns None + */ +static inline void MXC_SYS_Crit_Enter(void) +{ + _mxc_crit_get_state(); + if (_state.ie_status) + __disable_irq(); + _state.in_critical = 1; +} + +/** + * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter + * @returns None + */ +static inline void MXC_SYS_Crit_Exit(void) +{ + if (_state.ie_status) { + __enable_irq(); + } + _state.in_critical = 0; + _mxc_crit_get_state(); + /* + ^ Reset the state again to prevent edge case + where interrupts get disabled, then Crit_Exit() gets + called, which would inadvertently re-enable interrupts + from old state. + */ +} + +/** + * @brief Polls whether code is currently executing from a critical section. + * @returns 1 if code is currently in a critical section (interrupts are disabled). + * 0 if code is not in a critical section. + */ +static inline int MXC_SYS_In_Crit_Section(void) +{ + return _state.in_critical; +} + +// clang-format off +/** + * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro + * does not support nesting. + * @details + * Ex: + * \code + * MXC_CRITICAL( + * printf("Hello critical section!\n"); + * ) + * \endcode + * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after. + * @param code The code section to wrap. + */ +#define MXC_CRITICAL(code) {\ + MXC_SYS_Crit_Enter();\ + code;\ + MXC_SYS_Crit_Exit();\ +} +// clang-format on + +/** + * @brief Reads the device USN and verifies the checksum. + * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long. + * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine. + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum); + +/** + * @brief Determines if the selected peripheral clock is enabled. + * @param clock Enumeration for desired clock. + * @returns 0 is the clock is disabled, non 0 if the clock is enabled. + */ +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock); + +/** + * @brief Disables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the 32kHz oscillator + * @param mxc_sys_cfg Not used, may be NULL. + */ +void MXC_SYS_RTCClockEnable(void); + +/** + * @brief Disables the 32kHz oscillator + * @returns E_NO_ERROR if everything is successful + */ +int MXC_SYS_RTCClockDisable(void); + +/** + * @brief Enables the 32kHz oscillator to be powered down when not in use. + * Only available for ME17 Rev. B and older chips. This has no effect on ME17 + * Rev. A chips. + * + * @returns E_NO_ERROR if everything is successful + */ +void MXC_SYS_RTCClockPowerDownEn(void); + +/** + * @brief Disables the 32kHz oscillator from being powered down when not in use. + * Only available for ME17 Rev. B and older chips. This has no effect on ME17 + * Rev. A chips. + * + * @returns E_NO_ERROR if everything is successful + */ +void MXC_SYS_RTCClockPowerDownDis(void); + +/** + * @brief Enable System Clock Source without switching to it + * @param clock The clock to enable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock); + +/** + * @brief Disable System Clock Source + * @param clock The clock to disable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock); + +/** + * @brief Select the system clock. + * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly. + * The default EXTCLK_FREQ value is defined in the system_max32655.h file and can be overridden at compile time. + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); + +/** + * @brief Set the system clock divider. + * @param div Enumeration for desired clock divider. + */ +void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div); + +/** + * @brief Get the system clock divider. + * @returns System clock divider. + */ +mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void); + +/** + * @brief Wait for a clock to enable with timeout + * @param ready The clock to wait for + * @return E_NO_ERROR if ready, E_TIME_OUT if timeout + */ +int MXC_SYS_Clock_Timeout(uint32_t ready); +/** + * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. + * @param Enumeration for what to reset. Can reset multiple items at once. + */ +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset); + +/** + * @brief Setup and run RISCV core + */ +void MXC_SYS_RISCVRun(void); + +/** + * @brief Shutdown the RISCV core + */ +void MXC_SYS_RISCVShutdown(void); + +/** + * @brief Returns the clock rate (in Hz) of the Risc-V core. + */ +uint32_t MXC_SYS_RiscVClockRate(void); + +/** + * @brief This function PERMANENTLY locks the Debug Access Port. + * + * @warning After executing this function you will never be able + * to reprogram the target micro. + */ +int MXC_SYS_LockDAP_Permanent(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/nspc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nspc.h new file mode 100644 index 00000000..bff02dbd --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nspc.h @@ -0,0 +1,97 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ + +#include "mxc_device.h" +#include "nspc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nspc NSPC + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief NSPC Peripheral Definition for setting the Privilege State. + */ +typedef enum { + MXC_NSPC_PERIPH_GCR = MXC_S_NSPC_APBPRIV_PERIPH_GCR, /**< GCR */ + MXC_NSPC_PERIPH_SIR = MXC_S_NSPC_APBPRIV_PERIPH_SIR, /**< SIR */ + MXC_NSPC_PERIPH_FCR = MXC_S_NSPC_APBPRIV_PERIPH_FCR, /**< FCR */ + MXC_NSPC_PERIPH_WDT = MXC_S_NSPC_APBPRIV_PERIPH_WDT, /**< WDT */ + MXC_NSPC_PERIPH_AES = MXC_S_NSPC_APBPRIV_PERIPH_AES, /**< AES */ + MXC_NSPC_PERIPH_AESKEYS = MXC_S_NSPC_APBPRIV_PERIPH_AESKEYS, /**< AESKEYS */ + MXC_NSPC_PERIPH_GPIO0 = MXC_S_NSPC_APBPRIV_PERIPH_GPIO0, /**< GPIO0 */ + MXC_NSPC_PERIPH_CRC = MXC_S_NSPC_APBPRIV_PERIPH_CRC, /**< CRC */ + MXC_NSPC_PERIPH_TMR0 = MXC_S_NSPC_APBPRIV_PERIPH_TMR0, /**< TMR0 */ + MXC_NSPC_PERIPH_TMR1 = MXC_S_NSPC_APBPRIV_PERIPH_TMR1, /**< TMR1 */ + MXC_NSPC_PERIPH_TMR2 = MXC_S_NSPC_APBPRIV_PERIPH_TMR2, /**< TMR2 */ + MXC_NSPC_PERIPH_TMR3 = MXC_S_NSPC_APBPRIV_PERIPH_TMR3, /**< TMR3 */ + MXC_NSPC_PERIPH_TMR4 = MXC_S_NSPC_APBPRIV_PERIPH_TMR4, /**< TMR4 */ + MXC_NSPC_PERIPH_TMR5 = MXC_S_NSPC_APBPRIV_PERIPH_TMR5, /**< TMR5 */ + MXC_NSPC_PERIPH_I3C = MXC_S_NSPC_APBPRIV_PERIPH_I3C, /**< I3C */ + MXC_NSPC_PERIPH_UART = MXC_S_NSPC_APBPRIV_PERIPH_UART, /**< UART */ + MXC_NSPC_PERIPH_SPI = MXC_S_NSPC_APBPRIV_PERIPH_SPI, /**< SPI */ + MXC_NSPC_PERIPH_TRNG = MXC_S_NSPC_APBPRIV_PERIPH_TRNG, /**< TRNG */ + MXC_NSPC_PERIPH_BTLE_DBB = MXC_S_NSPC_APBPRIV_PERIPH_BTLE_DBB, /**< BTLE DBB */ + MXC_NSPC_PERIPH_BTLE_RFFE = MXC_S_NSPC_APBPRIV_PERIPH_BTLE_RFFE, /**< BTLE RFFE */ + MXC_NSPC_PERIPH_RSTZ = MXC_S_NSPC_APBPRIV_PERIPH_RSTZ, /**< RSTZ */ + MXC_NSPC_PERIPH_BOOST = MXC_S_NSPC_APBPRIV_PERIPH_BOOST, /**< BOOST */ + MXC_NSPC_PERIPH_TRIMSIR = MXC_S_NSPC_APBPRIV_PERIPH_TRIMSIR, /**< TRIMSIR */ + MXC_NSPC_PERIPH_RTC = MXC_S_NSPC_APBPRIV_PERIPH_RTC, /**< RTC */ + MXC_NSPC_PERIPH_WUT0 = MXC_S_NSPC_APBPRIV_PERIPH_WUT0, /**< WUT0 */ + MXC_NSPC_PERIPH_WUT1 = MXC_S_NSPC_APBPRIV_PERIPH_WUT1, /**< WUT1 */ + MXC_NSPC_PERIPH_PWRSEQ = MXC_S_NSPC_APBPRIV_PERIPH_PWRSEQ, /**< PWRSEQ */ + MXC_NSPC_PERIPH_MCR = MXC_S_NSPC_APBPRIV_PERIPH_MCR, /**< MCR */ + MXC_NSPC_PERIPH_ALL = MXC_S_NSPC_APBPRIV_PERIPH_ALL, /**< All */ +} mxc_nspc_periph_t; + +/** @brief Enumeration for ARM privilege settings. */ +typedef enum { + MXC_NSPC_PRIVILEGED = 0, + MXC_NSPC_UNPRIVILEGED = 1, +} mxc_nspc_priv_t; + +/***** Function Prototypes *****/ + +/** + * @brief Sets the privilege level for a Peripheral. + * @param periph Enumeration for desired peripheral. + * @param priv Enumeration for desired privilege level. + */ +void MXC_NSPC_SetPrivAccess(mxc_nspc_periph_t periph, mxc_nspc_priv_t priv); + +/** + * @brief Sets the privilege level for Non-Secure DMA. + * @param priv Enumeration for desired privilege level. + */ +void MXC_NSPC_DMA_SetPrivAccess(mxc_nspc_priv_t priv); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NSPC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h new file mode 100644 index 00000000..6367d3ea --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h @@ -0,0 +1,63 @@ +/** + * @file nvic_table.h + * @brief Interrupt vector table manipulation functions. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "max32657.h" + +/** + * @brief Set an IRQ hander callback function. If the IRQ table is in + * flash, this will copy it to RAM and set NVIC to RAM based table. + * + * @param irqn ARM external IRQ number + * @param irq_callback Function to be called at IRQ context + * + */ +void MXC_NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)); + +/** + * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. + * + */ +void NVIC_SetRAM(void); + +/** + * @brief Get Interrupt Vector + * @details Reads an interrupt vector from interrupt vector table. The + * interrupt number can be positive to specify a device specific + * interrupt, or negative to specify a processor exception. + * @param[in] IRQn Interrupt number. + * @return Address of interrupt handler function + */ +uint32_t MXC_NVIC_GetVector(IRQn_Type IRQn); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/rtc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/rtc.h new file mode 100644 index 00000000..187e70ec --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/rtc.h @@ -0,0 +1,226 @@ +/** + * @file rtc.h + * @brief Real Time Clock (RTC) functions and prototypes. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "rtc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup rtc Real Time Clock (RTC) + * @ingroup periphlibs + * @{ + */ + +#define MXC_RTC_MAX_SSEC (MXC_F_RTC_SSEC_SSEC + 1) +#define MXC_RTC_TRIM_TMR_IRQ \ + 0x0 //Place holder to prevent build errors, RevA function which uses this will never be called + +/* **** Definitions **** */ +/** + * Bitmasks for each of the RTC's Frequency. + */ +typedef enum { + MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, /**< 1Hz (Compensated) */ + MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, /**< 512Hz (Compensated) */ + MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, /**< 4Khz */ + MXC_RTC_F_32KHZ = 32, /**< 32Khz */ +} mxc_rtc_freq_sel_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt enables. + */ +typedef enum { + MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, /**< Long-interval alarm interrupt enable */ + MXC_RTC_INT_EN_SHORT = + MXC_F_RTC_CTRL_SSEC_ALARM_IE, /**< Short-interval alarm interrupt enable */ + MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, /**< Timer ready interrupt enable */ +} mxc_rtc_int_en_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt flags. + */ +typedef enum { + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IF, /**< Long-interval alarm interrupt flag */ + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IF, /**< Short-interval alarm interrupt flag */ + MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, /**< Timer ready interrupt flag */ +} mxc_rtc_int_fl_t; + +/** + * @brief Set Time-of-Day alarm value and enable Interrupt + * @param ras 20-bit value 0-0xFFFFF + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras); + +/** + * @brief Set Sub-Second alarm value and enable interrupt, + * @brief this is to be called after the init_rtc() function + * @param rssa 32-bit value 0-0xFFFFFFFF + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa); + +/** + * @brief Start the Real Time Clock (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Start(void); +/** + * @brief Stop the Real Time Clock (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Stop(void); + +/** + * @brief Initialize the sec and ssec registers and enable RTC (Blocking function) + * @param sec set the RTC Sec counter (32-bit) + * @param ssec set the RTC Sub-second counter (12-bit) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Init(uint32_t sec, uint16_t ssec); + +/** + * @brief Allow generation of Square Wave on the SQW pin (Blocking function) + * @param fq Frequency output selection + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq); + +/** + * @brief Stop the generation of square wave (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SquareWaveStop(void); + +/** + * @brief Set Trim register value (Blocking function) + * @param trm set the RTC Trim (8-bit, +/- 127) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Trim(int8_t trm); + +/** + * @brief Enable Interurpts (Blocking function) + * @param mask The bitwise OR of interrupts to enable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_EnableInt(uint32_t mask); + +/** + * @brief Disable Interurpts (Blocking function) + * @param mask The mask of interrupts to disable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_DisableInt(uint32_t mask); + +/** + * @brief Gets interrupt flags. + * @retval The bitwise OR of any interrupts flags that are + * currently set. See #mxc_rtc_int_fl_t for the list + * of possible flags. + */ +int MXC_RTC_GetFlags(void); + +/** + * @brief Clear interrupt flags. + * @param flags The bitwise OR of the interrupts flags to cleear. + * See #mxc_rtc_int_fl_t for the list of possible flags. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_ClearFlags(int flags); + +/** + * @brief Get SubSecond or E_BUSY, see /ref MXC_ERROR_CODES + * @retval Returns subsecond value + */ +#ifdef __GNUC__ +__attribute__((deprecated("Use MXC_RTC_GetSubSeconds() instead."))) +#endif +int MXC_RTC_GetSubSecond(void); + +/** + * @brief This function stores the current value of the sub-seconds counter into a + * pointer if the RTC is not busy. If the RTC is busy, an error is returned. + * @param ssec Pointer to the variable to store the current sub-seconds value. + * @retval E_NO_ERROR if successful, otherwise an error code (see /ref MXC_ERROR_CODES). + */ +int MXC_RTC_GetSubSeconds(uint32_t *ssec); + +/** + * @brief Get Second or E_BUSY, see /ref MXC_ERROR_CODES + * @retval returns second value + */ +#ifdef __GNUC__ +__attribute__((deprecated("Use MXC_RTC_GetSeconds() instead."))) +#endif +int MXC_RTC_GetSecond(void); + +/** + * @brief This function stores the current value of the seconds counter into a + * pointer if the RTC is not busy. If the RTC is busy, an error is returned. + * @param sec Pointer to the variable to store the current seconds value. + * @retval E_NO_ERROR if successful, otherwise an error code (see /ref MXC_ERROR_CODES). + */ +int MXC_RTC_GetSeconds(uint32_t *sec); + +/** + * @brief Get the current second and sub-second counts + * @param sec pointer to store seconds value + * @param subsec pointer to store subseconds value + * @retval returns Success or Fail, see /ref MXC_ERROR_CODES + */ +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec); + +/** + * @brief Get RTC busy flag. + * @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES + */ +int MXC_RTC_GetBusyFlag(void); + +/** + * @brief Use the 32 MHz crystal to trim the 32 kHz crystal. + * @details Assumes that RTC interrupts are disabled and 32 MHz crystal is + * enabled and selected as the system clock. + * @retval returns trimmed value of 32 kHz crystal or error, + * see /ref MXC_ERROR_CODES + */ +int MXC_RTC_TrimCrystal(void); + +/**@} end of group rtc */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/spc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/spc.h new file mode 100644 index 00000000..ab1c87ba --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/spc.h @@ -0,0 +1,212 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ + +#include +#include +#include "mxc_device.h" +#include "spc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spc SPC + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief SPC Peripheral Definition for setting the Security and Privilege State. + * The SPC_APBSEC register definitions are used, but this can also be used + * for the SPC_APBPRIV register as well since the peripheral fields are a + * one-to-one match. + */ +typedef enum { + MXC_SPC_PERIPH_GCR = MXC_S_SPC_APBSEC_PERIPH_GCR, /**< GCR */ + MXC_SPC_PERIPH_SIR = MXC_S_SPC_APBSEC_PERIPH_SIR, /**< SIR */ + MXC_SPC_PERIPH_FCR = MXC_S_SPC_APBSEC_PERIPH_FCR, /**< FCR */ + MXC_SPC_PERIPH_WDT = MXC_S_SPC_APBSEC_PERIPH_WDT, /**< WDT */ + MXC_SPC_PERIPH_AES = MXC_S_SPC_APBSEC_PERIPH_AES, /**< AES */ + MXC_SPC_PERIPH_AESKEYS = MXC_S_SPC_APBSEC_PERIPH_AESKEYS, /**< AESKEYS */ + MXC_SPC_PERIPH_GPIO0 = MXC_S_SPC_APBSEC_PERIPH_GPIO0, /**< GPIO0 */ + MXC_SPC_PERIPH_CRC = MXC_S_SPC_APBSEC_PERIPH_CRC, /**< CRC */ + MXC_SPC_PERIPH_TMR0 = MXC_S_SPC_APBSEC_PERIPH_TMR0, /**< TMR0 */ + MXC_SPC_PERIPH_TMR1 = MXC_S_SPC_APBSEC_PERIPH_TMR1, /**< TMR1 */ + MXC_SPC_PERIPH_TMR2 = MXC_S_SPC_APBSEC_PERIPH_TMR2, /**< TMR2 */ + MXC_SPC_PERIPH_TMR3 = MXC_S_SPC_APBSEC_PERIPH_TMR3, /**< TMR3 */ + MXC_SPC_PERIPH_TMR4 = MXC_S_SPC_APBSEC_PERIPH_TMR4, /**< TMR4 */ + MXC_SPC_PERIPH_TMR5 = MXC_S_SPC_APBSEC_PERIPH_TMR5, /**< TMR5 */ + MXC_SPC_PERIPH_I3C = MXC_S_SPC_APBSEC_PERIPH_I3C, /**< I3C */ + MXC_SPC_PERIPH_UART = MXC_S_SPC_APBSEC_PERIPH_UART, /**< UART */ + MXC_SPC_PERIPH_SPI = MXC_S_SPC_APBSEC_PERIPH_SPI, /**< SPI */ + MXC_SPC_PERIPH_TRNG = MXC_S_SPC_APBSEC_PERIPH_TRNG, /**< TRNG */ + MXC_SPC_PERIPH_BTLE_DBB = MXC_S_SPC_APBSEC_PERIPH_BTLE_DBB, /**< BTLE DBB */ + MXC_SPC_PERIPH_BTLE_RFFE = MXC_S_SPC_APBSEC_PERIPH_BTLE_RFFE, /**< BTLE RFFE */ + MXC_SPC_PERIPH_RSTZ = MXC_S_SPC_APBSEC_PERIPH_RSTZ, /**< RSTZ */ + MXC_SPC_PERIPH_BOOST = MXC_S_SPC_APBSEC_PERIPH_BOOST, /**< BOOST */ + MXC_SPC_PERIPH_TRIMSIR = MXC_S_SPC_APBSEC_PERIPH_TRIMSIR, /**< TRIMSIR */ + MXC_SPC_PERIPH_RTC = MXC_S_SPC_APBSEC_PERIPH_RTC, /**< RTC */ + MXC_SPC_PERIPH_WUT0 = MXC_S_SPC_APBSEC_PERIPH_WUT0, /**< WUT0 */ + MXC_SPC_PERIPH_WUT1 = MXC_S_SPC_APBSEC_PERIPH_WUT1, /**< WUT1 */ + MXC_SPC_PERIPH_PWRSEQ = MXC_S_SPC_APBSEC_PERIPH_PWRSEQ, /**< PWRSEQ */ + MXC_SPC_PERIPH_MCR = MXC_S_SPC_APBSEC_PERIPH_MCR, /**< MCR */ + MXC_SPC_PERIPH_ALL = MXC_S_SPC_APBSEC_PERIPH_ALL, /**< All */ +} mxc_spc_periph_t; + +/** @brief Enumeration for ARM privilege settings. */ +typedef enum { + MXC_SPC_PRIVILEGED = 0, + MXC_SPC_UNPRIVILEGED = 1, +} mxc_spc_priv_t; + +/***** Function Prototypes *****/ + +/** + * @brief Locks the SPC registers related to setting the security + * or privilege states. Once locked, the affected SPC registers + * can not be unlocked until a reset. + */ +void MXC_SPC_Lock(void); + +/** + * @brief Locks the Cortex-M33 Core registers: + * - AIRCR and VTOR_S + * - VTOR_NS + * - MPU_S + * - MPU_NS + * - SAU + */ +void MXC_SPC_Core_Lock(void); + +/** + * @brief Unlocks the Cortex-M33 Core registers: + * - AIRCR and VTOR_S + * - VTOR_NS + * - MPU_S + * - MPU_NS + * - SAU + */ +void MXC_SPC_Core_UnLock(void); + +/** + * @brief Sets the privilege level of a peripheral. + * @param periph Enumeration for desired peripheral. + * @param priv Enumeration for desired privilege level. + */ +void MXC_SPC_SetPrivAccess(mxc_spc_periph_t periph, mxc_spc_priv_t priv); + +/** + * @brief Sets the peripheral to only be accessible from the Secure world. + * @param periph Enumeration for desired peripheral. + */ +void MXC_SPC_SetSecure(mxc_spc_periph_t periph); + +/** + * @brief Sets the peripheral to only be accessible from the Non-Secure world. + * @param periph Enumeration for desired peripheral. + */ +void MXC_SPC_SetNonSecure(mxc_spc_periph_t periph); + +/** + * @brief Sets the privilege level for Secure DMA. + * @param priv Enumeration for desired privilege level. + */ +void MXC_SPC_DMA_SetPrivAccess(mxc_spc_priv_t priv); + +/** + * @brief Sets the pins for a GPIO instance to only be accessible from the Secure world. + * @param gpio Pointer to the GPIO port's registers. + * @param pins mask of pins to set to Secure mode. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPC_GPIO_SetSecure(mxc_gpio_regs_t *gpio, uint32_t pins); + +/** + * @brief Sets the pins for a GPIO instance to only be accessible from the Non-Secure world. + * @param gpio Pointer to the GPIO port's registers. + * @param pins mask of pins to set to Non-Secure mode. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPC_GPIO_SetNonSecure(mxc_gpio_regs_t *gpio, uint32_t pins); + +/** + * @brief Enable the interrupts for each Memory Protection Controller (MPC) region. + * @param intr mask of MPC regions to interrupt for. + */ +void MXC_SPC_MPC_EnableInt(uint32_t intr); + +/** + * @brief Disable the interrupts for each Memory Protection Controller (MPC) region. + * @param intr mask of MPC regions to disable interrupt for. + */ +void MXC_SPC_MPC_DisableInt(uint32_t intr); + +/** + * @brief Gets the Memory Protection Controller (MPC) interrupt flags that are currently set. + * @return MPC interrupt flags. + */ +uint32_t MXC_SPC_MPC_GetFlags(void); + +/** + * @brief Enable the interrupts for Peripheral Protection Controllers (PPC). + * @param intr mask of PPC regions to disable interrupt for. + */ +void MXC_SPC_PPC_EnableInt(uint32_t intr); + +/** + * @brief Disable the interrupts for Peripheral Protection Controllers (PPC). + * @param intr mask of PPC regions to disable interrupt for. + */ +void MXC_SPC_PPC_DisableInt(uint32_t intr); + +/** + * @brief Gets the Peripheral Protection Controller (PPC) interrupt flags + * that are currently set. + * @return PPC interrupt flags. + */ +uint32_t MXC_SPC_PPC_GetFlags(void); + +/** + * @brief Clears the Peripheral Protection Controllers (PPC) Interrupt Flags. + * @param flags mask of PPC interrupt flags to clear. + */ +void MXC_SPC_PPC_ClearFlags(uint32_t flags); + +/** + * @brief Sets the CODE region to be Non-Secure Callable. + * @param isNSC Option to set CODE region as non-secure callable (True) or not (False). + */ +void MXC_SPC_SetCode_NSC(bool isNSC); + +/** + * @brief Sets the CODE region to be Non-Secure Callable. + * @param isNSC Option to set CODE region as non-secure callable (True) or not (False). + */ +void MXC_SPC_SetSRAM_NSC(bool isNSC); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/spi.h new file mode 100644 index 00000000..45ddea84 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -0,0 +1,706 @@ +/** + * @file spi.h + * @brief Serial Peripheral Interface (SPI) communications driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ + +/***** includes *******/ +#include +#include "spi_regs.h" +#include "mxc_sys.h" +#include "mxc_assert.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "mxc_lock.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spi SPI + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief The list of SPI Widths supported + * + * The SPI Width can be set on a per-transaction basis. + * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is + * given. + * + * Using a MAX31865 RTD-to-SPI IC, read back the temperature + * The IC requires a SPI Read to be executed as + * 1. Assert SS + * 2. Write an 8bit register address + * 3. Read back the 8 bit register + * 4. Deassert SS + * This can be accomplished with the STANDARD_HALFDUPLEX width + * 1. set txData to the address, txLen=1 + * 2. set rxData to a buffer of 1 byte, rxLen=1 + * 3. The driver will transmit the txData, and after completion of + * txData begin to recieve data, padding MOSI with DefaultTXData + * + */ +typedef enum { + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex + SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex +} mxc_spi_width_t; + +/** + * @brief The list of SPI modes + * + * SPI supports four combinations of clock and phase polarity + * + * Clock polarity is controlled using the bit SPIn_CTRL2.cpol + * and determines if the clock is active high or active low + * + * Clock phase determines when the data must be stable for sampling + * + */ +typedef enum { + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 + SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 + SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 +} mxc_spi_mode_t; + +typedef struct _mxc_spi_pins_t mxc_spi_pins_t; + +/** + * @brief Structure used to initialize SPI pins. + * + * @note All values must be initialized. + * + * @note True equals pin is set for the spi function false the pin is left to its latest state. + */ +struct _mxc_spi_pins_t { + bool clock; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData + + spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete +}; + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable SPI peripheral. + * + * This function initializes everything necessary to call a SPI transaction function. + * Some parameters are set to defaults as follows: + * SPI Mode - 0 + * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) + * + * These parameters can be modified after initialization using low level functions + * + * @note On default this function enables SPI peripheral clock and spi gpio pins. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero for master mode, and zero for slave mode. + * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use + * non-zero if the pins are needed (if Quad Mode will + * be used), and zero if they are not needed (quad mode + * will never be used). + * @param numSlaves The number of slaves used, if in master mode. This + * is used to obtain control of the necessary SS pins. + * In slave mode this is ignored and SS1 is used. + * @param ssPolarity This field sets the SS active polarity for each + * slave, each bit position corresponds to each SS line. + * @param hz The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. Used in + * master mode only. + * @param pins SPI pin structure. Pins selected as true will be initialized + * for the requested SPI block. Has no effect incase of + * MSDK_NO_GPIO_CLK_INIT has been defined. + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins); + +/** + * @brief Disable and shutdown SPI peripheral. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); + +/** + * @brief Checks if the given SPI bus can be placed in sleep mode. + * + * This functions checks to see if there are any on-going SPI transactions in + * progress. If there are transactions in progress, the application should + * wait until the SPI bus is free before entering a low-power state. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); + +/** + * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Frequency of the clock used as the bit rate generator + */ +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); + +/** + * @brief Set the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); + +/** + * @brief Get the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The SPI bus frequency in Hertz + */ +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); + +/** + * @brief Sets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param dataSize The number of bits per character + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); + +/** + * @brief Gets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); + +/** + * @brief Sets Multi-Transaction (MT) mode on or off + * + * This function allows Multi-Transaction Mode to be enabled or disabled. MT Mode + * provides a performance improvement on back-to-back DMA operations. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param mtMode 1 to enable, 0 to disable (default) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMTMode(mxc_spi_regs_t *spi, int mtMode); + +/** + * @brief Gets the current setting for Multi-Transaction (MT) mode + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The current value of MT mode, either 1 (enabled) or 0 (disabled) + */ +int MXC_SPI_GetMTMode(mxc_spi_regs_t *spi); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Sets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param ssIdx Slave select index + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); + +/** + * @brief Gets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return slave slect + */ +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); + +/** + * @brief Sets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); + +/** + * @brief Gets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Spi Width + */ +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); + +/** + * @brief Sets the spi mode using clock polarity and clock phase + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiMode \ref mxc_spi_mode_t + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); + +/** + * @brief Gets the spi mode + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return mxc_spi_mode_t \ref mxc_spi_mode_t + */ +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); + +/** + * @brief Starts a SPI Transmission + * + * This function is applicable in Master mode only + * + * The user must ensure that there are no ongoing transmissions before + * calling this function + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); + +/** + * @brief Checks the SPI Peripheral for an ongoing transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetActive(mxc_spi_regs_t *spi); + +/** + * @brief Aborts an ongoing SPI Transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); + +/** + * @brief Set the receive threshold level. + * + * RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 30 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); + +/** + * @brief Set the transmit threshold level. + * + * TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 30 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); + +/** + * @brief Gets the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); + +/** + * @brief Clears the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + */ +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); + +/** + * @brief Enables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param intEn The interrupts to be enabled + */ +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn); + +/** + * @brief Disables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param intDis The interrupts to be disabled + */ +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Master Mode: + * 1. Assert the specified SS + * 2. In Full Duplex Modes, send TX data while receiving RX Data + * if rxLen > txLen, pad txData with DefaultTXData + * if txLen > rxLen, discard rxData where rxCnt > rxLen + * 3. In Half Duplex Modes, send TX Data, then receive RX Data + * 4. Deassert the specified SS + * + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transactionz + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); + +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the SPI interrupt + * handler or periodically by the application if SPI interrupts are disabled. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); + +/** + * @brief Enable/Disable HW CS control feature. + * + * Depending on the application, the user might need to manually drive the slave select pin. + * The SPI driver automatically drives the SS pin and this function enables/disables this + * feature. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. + */ +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); + +/**@} end of group spi */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/tmr.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/tmr.h new file mode 100644 index 00000000..9fd2c7d9 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/tmr.h @@ -0,0 +1,412 @@ +/** + * @file tmr.h + * @brief Timer (TMR) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "tmr_regs.h" +#include "mxc_sys.h" +#include "gcr_regs.h" +#include "mcr_regs.h" +#include "stdbool.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup tmr Timer (TMR) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Timer prescaler values + */ +typedef enum { + MXC_TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, /**< Divide input clock by 1 */ + MXC_TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, /**< Divide input clock by 2 */ + MXC_TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, /**< Divide input clock by 4 */ + MXC_TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, /**< Divide input clock by 8 */ + MXC_TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, /**< Divide input clock by 16 */ + MXC_TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, /**< Divide input clock by 32 */ + MXC_TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, /**< Divide input clock by 64 */ + MXC_TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, /**< Divide input clock by 128 */ + MXC_TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, /**< Divide input clock by 256 */ + MXC_TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, /**< Divide input clock by 512 */ + MXC_TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, /**< Divide input clock by 1024 */ + MXC_TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, /**< Divide input clock by 2048 */ + MXC_TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096, /**< Divide input clock by 4096 */ + + // Legacy names + TMR_PRES_1 = MXC_TMR_PRES_1, + TMR_PRES_2 = MXC_TMR_PRES_2, + TMR_PRES_4 = MXC_TMR_PRES_4, + TMR_PRES_8 = MXC_TMR_PRES_8, + TMR_PRES_16 = MXC_TMR_PRES_16, + TMR_PRES_32 = MXC_TMR_PRES_32, + TMR_PRES_64 = MXC_TMR_PRES_64, + TMR_PRES_128 = MXC_TMR_PRES_128, + TMR_PRES_256 = MXC_TMR_PRES_256, + TMR_PRES_512 = MXC_TMR_PRES_512, + TMR_PRES_1024 = MXC_TMR_PRES_1024, + TMR_PRES_2048 = MXC_TMR_PRES_2048, + TMR_PRES_4096 = MXC_TMR_PRES_4096 +} mxc_tmr_pres_t; + +/** + * @brief Timer modes + */ +typedef enum { + MXC_TMR_MODE_ONESHOT = MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT + MXC_TMR_MODE_CONTINUOUS = MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS + MXC_TMR_MODE_COUNTER = MXC_V_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER + MXC_TMR_MODE_PWM = MXC_V_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM + MXC_TMR_MODE_CAPTURE = MXC_V_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE + MXC_TMR_MODE_COMPARE = MXC_V_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE + MXC_TMR_MODE_GATED = MXC_V_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED + MXC_TMR_MODE_CAPTURE_COMPARE = MXC_V_TMR_CTRL0_MODE_A_CAPCOMP, ///< Timer Mode CAPTURECOMPARE + MXC_TMR_MODE_DUAL_EDGE = MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE, ///< Timer Mode DUALEDGE + + // Legacy names + TMR_MODE_ONESHOT = MXC_TMR_MODE_ONESHOT, + TMR_MODE_CONTINUOUS = MXC_TMR_MODE_CONTINUOUS, + TMR_MODE_COUNTER = MXC_TMR_MODE_COUNTER, + TMR_MODE_PWM = MXC_TMR_MODE_PWM, + TMR_MODE_CAPTURE = MXC_TMR_MODE_CAPTURE, + TMR_MODE_COMPARE = MXC_TMR_MODE_COMPARE, + TMR_MODE_GATED = MXC_TMR_MODE_GATED, + TMR_MODE_CAPTURE_COMPARE = MXC_TMR_MODE_CAPTURE_COMPARE, + TMR_MODE_DUAL_EDGE = MXC_TMR_MODE_DUAL_EDGE +} mxc_tmr_mode_t; + +/** + * @brief Timer bit mode + * + */ +typedef enum { + MXC_TMR_BIT_MODE_32 = 0, /**< Timer Mode 32 bit */ + MXC_TMR_BIT_MODE_16A, /**< Timer Mode Lower 16 bit */ + MXC_TMR_BIT_MODE_16B, /**< Timer Mode Upper 16 bit */ + + // Legacy names + TMR_BIT_MODE_32 = MXC_TMR_BIT_MODE_32, + TMR_BIT_MODE_16A = MXC_TMR_BIT_MODE_16A, + TMR_BIT_MODE_16B = MXC_TMR_BIT_MODE_16B, +} mxc_tmr_bit_mode_t; + +/** + * @brief Timer units of time enumeration + */ +typedef enum { + MXC_TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator */ + MXC_TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator */ + MXC_TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator */ + MXC_TMR_UNIT_SEC, /**< Second Unit Indicator */ + + // Legacy names + TMR_UNIT_NANOSEC = MXC_TMR_UNIT_NANOSEC, + TMR_UNIT_MICROSEC = MXC_TMR_UNIT_MICROSEC, + TMR_UNIT_MILLISEC = MXC_TMR_UNIT_MILLISEC, + TMR_UNIT_SEC = MXC_TMR_UNIT_SEC, +} mxc_tmr_unit_t; + +/** + * @brief Peripheral Clock settings + */ +// TODO(ME30): TMR clock sources +typedef enum { + MXC_TMR_APB_CLK = 0, /**< PCLK */ + MXC_TMR_EXT_CLK = 1, /**< External Clock */ + MXC_TMR_IBRO_CLK = 3, /**< 7.3728MHz Clock */ + MXC_TMR_ERTCO_CLK = 4, /**< 32.768KHz Clock */ + MXC_TMR_INRO_CLK = 5, /**< 8-30KHz Clock */ + MXC_TMR_IBRO_DIV8_CLK = 6, /**< (7.3728/8)MHz Clock */ + + // Legacy names + /*8M and 60M clocks can be used for Timers 0,1,2 and 3*/ + MXC_TMR_32M_CLK, // Not supported as TMR clock source + MXC_TMR_8M_CLK = MXC_TMR_IBRO_CLK, + /*32K clock can be used for Timers 0,1,2,3 and 4*/ + MXC_TMR_32K_CLK = MXC_TMR_ERTCO_CLK, + /*8K and EXT clocks can only be used for Timers 4 and 5*/ + MXC_TMR_8K_CLK = MXC_TMR_INRO_CLK, +} mxc_tmr_clock_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + mxc_tmr_pres_t pres; /**< Desired timer prescaler */ + mxc_tmr_mode_t mode; /**< Desired timer mode */ + mxc_tmr_bit_mode_t bitMode; /**< Desired timer bits */ + mxc_tmr_clock_t clock; /**< Desired clock source */ + uint32_t cmp_cnt; /**< Compare register value in timer ticks */ + unsigned pol; /**< Polarity (0 or 1) */ +} mxc_tmr_cfg_t; + +/* **** Definitions **** */ +typedef void (*mxc_tmr_complete_t)(int error); + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @note On default this function enables TMR peripheral clock and related GPIOs. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + * @param init_pins True will initialize pins corresponding to the TMR and False will not if pins are pinned out otherwise it will not + * be used, has no effect incase of MSDK_NO_GPIO_CLK_INIT has been defined. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins); + +/** + * @brief Shutdown timer module clock. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr); + +/** + * @brief Start the timer counting. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Start(mxc_tmr_regs_t *tmr); + +/** + * @brief Stop the timer. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Set the value of the first transition in PWM mode + * @param tmr Pointer to timer module to initialize. + * @param pwm New pwm count. + * @note Will block until safe to change the period count. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm); + +/** + * @brief Get the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current compare count. + */ +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer capture count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the most recent capture count. + */ +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current count. + */ +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr); + +/** + * @brief Calculate count for required frequency. + * @param tmr Timer + * @param clock Clock source. + * @param prescalar prescalar + * @param frequency required frequency. + * @return Returns the period count. + */ +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency); + +/** + * @brief Clear the timer interrupt. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer interrupt status. + * @param tmr Pointer to timer module to initialize. + * @return Returns the interrupt status. 1 if interrupt has occured. + */ +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr); + +/** + * @brief enable interupt + * + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr); + +/** + * @brief disable interupt + * + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr); + +/** + * @brief Enable wakeup from sleep + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + */ +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); + +/** + * @brief Disable wakeup from sleep + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + */ +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); + +/** + * @brief Set the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @param cmp_cnt New compare count. + * @note In PWM Mode use this to set the value of the second transition. + */ +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param tmr Pointer to timer module to initialize. + * @param cnt New count. + */ +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt); + +/** + * @brief Dealay for a set periord of time measured in microseconds + * + * @param tmr The timer + * @param us microseconds to delay for + */ +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us); + +/** + * @brief Start a timer that will time out after a certain number of microseconds + * + * @param tmr The timer + * @param us microseconds to time out after + */ +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); + +/** + * @brief Check on time out timer + * + * @param tmr The timer + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr); + +/** + * @brief Stop the Timeout timer + * + * @param tmr The timer + */ +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Clear timeout timer back to zero + * + * @param tmr The timer + */ +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr); + +/** + * @brief Get elapsed time of timeout timer + * + * @param tmr The timer + * + * @return Time that has elapsed in timeout timer + */ +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr); + +/** + * @brief Amount of time remaining until timeour + * + * @param tmr The timer + * + * @return Time that is left until timeout + */ +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr); + +/** + * @brief Start stopwatch + * + * @param tmr The timer + */ +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr); + +/** + * @brief Stopwatch stop + * + * @param tmr The timer + * + * @return the time when the stopwatch is stopped. + */ +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Get time from timer + * + * @param tmr The timer + * @param ticks The ticks + * @param time The time + * @param units The units + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); + +/** + * @brief Get ticks from timer + * + * @param tmr The timer + * @param time The time + * @param units The units + * @param ticks The ticks + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks); + +/**@} end of group tmr */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/trng.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/trng.h new file mode 100644 index 00000000..6d524edc --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/trng.h @@ -0,0 +1,127 @@ +/** + * @file trng.h + * @brief Random number generator driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ + +/***** Includes *****/ +#include "trng_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup trng TRNG + * @ingroup periphlibs + * @{ + */ + +/* IN ADDITION TO THIS HEADER, FCL WILL BE SUPPORTED AND PROVIDED IN BINARY FORM */ + +/***** Function Prototypes *****/ +typedef void (*mxc_trng_complete_t)(void *req, int result); + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the TRNG + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Init(void); + +/** + * @brief Enable TRNG Interrupts + * + */ +void MXC_TRNG_EnableInt(void); + +/** + * @brief Disable TRNG Interrupts + * + */ +void MXC_TRNG_DisableInt(void); + +/** + * @brief Disable and reset portions of the TRNG + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Shutdown(void); + +/** + * @brief This function should be called from the TRNG ISR Handler + * when using Async functions + */ +void MXC_TRNG_Handler(void); + +/* ************************************************************************* */ +/* True Random Number Generator (TRNG) functions */ +/* ************************************************************************* */ + +/** + * @brief Get a random number + * + * @return A random 32-bit number + */ +int MXC_TRNG_RandomInt(void); + +/** + * @brief Get a random number of length len + * + * @param data Pointer to a location to store the number + * @param len Length of random number in bytes + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Random(uint8_t *data, uint32_t len); + +/** + * @brief Get a random number of length len, do not block while generating data + * @note The user must call MXC_TRNG_Handler() in the ISR + * + * @param data Pointer to a location to store the number + * @param len Length of random number in bytes + * @param callback Function that will be called when all data has been generated + * + */ +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback); + +/** + * @brief Perform health test of the TRNG entropy source + * + * @return If test fails the function will return E_BAD_STATE (-7), otherwise it will return E_NO_ERROR. + * + * @warning MAX32655 with Rev. A Silicon does not support health tests. (Check MXC_GCR->revision to see which revision your chip is.) + */ +int MXC_TRNG_HealthTest(void); + +#ifdef __cplusplus +} +#endif +/**@} end of group trng */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/uart.h new file mode 100644 index 00000000..17c77244 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -0,0 +1,740 @@ +/** + * @file uart.h + * @brief Serial Peripheral Interface (UART) communications driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ + +/***** Definitions *****/ +#include +#include "mxc_sys.h" +#include "uart_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UART_EXTCLK_FREQ E_BAD_PARAM + +/** + * @defgroup uart UART + * @ingroup periphlibs + * @{ + */ + +typedef struct _mxc_uart_req_t mxc_uart_req_t; +/** + * @brief The list of UART stop bit lengths supported + * + */ +typedef enum { + MXC_UART_STOP_1, ///< UART Stop 1 clock cycle + MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) +} mxc_uart_stop_t; + +/** + * @brief The list of UART Parity options supported + * + */ +typedef enum { + MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based + MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based + MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based + MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based +} mxc_uart_parity_t; + +/** + * @brief The list of UART flow control options supported + * + */ +typedef enum { + MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled + MXC_UART_FLOW_EN, ///< UART Flow Control Enabled +} mxc_uart_flow_t; + +/** + * @brief Clock settings */ +typedef enum { + /*Only available for UARTS 0-2*/ + MXC_UART_APB_CLK = 0, + /*Available for all UARTs*/ + MXC_UART_IBRO_CLK = 2, + /*ERTCO clock can only be used for UART3*/ + MXC_UART_ERTCO_CLK = 4, +} mxc_uart_clock_t; + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); + +/** + * @brief The information required to perform a complete UART transaction + * + * @note This structure is used by blocking, async, and DMA based transactions. + * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. + */ +struct _mxc_uart_req_t { + mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData + volatile uint32_t rxCnt; ///< Number of bytes stored in rxData + + mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete +}; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable UART peripheral. + * + * This function initializes everything necessary to call a UART transaction function. + * Some parameters are set to defaults as follows: + * UART Data Size - 8 bits + * UART Stop Bits - 1 bit + * UART Parity - None + * UART Flow Control - None + * + * These parameters can be modified after initialization using low level functions + * + * @note On default this function enables UART peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * @param clock Clock source + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); + +/** + * @brief Disable and shutdown UART peripheral. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief Checks if the given UART bus can be placed in sleep more. + * + * @note This functions checks to see if there are any on-going UART transactions in + * progress. If there are transactions in progress, the application should + * wait until the UART bus is free before entering a low-power state. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); + +/** + * @brief Set the frequency of the UART interface. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate + * @param clock Clock source + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); + +/** + * @brief Get the frequency of the UART interface. + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The UART baud rate + */ +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); + +/** + * @brief Sets the number of bits per character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); + +/** + * @brief Sets the number of stop bits sent at the end of a character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); + +/** + * @brief Sets the type of parity generation used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref UART Parity Types for details + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); + +/** + * @brief Sets the flow control used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); + +/** + * @brief Sets the clock source for the baud rate generator + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param clock Clock source + * + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * for a list of return codes. + */ +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Checks the UART Peripheral for an ongoing transmission + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_GetActive(mxc_uart_regs_t *uart); + +/** + * @brief Aborts an ongoing UART Transmission + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); + +/** + * @brief Reads the next available character. If no character is available, this function + * will return an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); + +/** + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); + +/** + * @brief Reads the next available character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); + +/** + * @brief Writes a character on the UART + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); + +/** + * @brief Reads the next available character + * @note This function blocks until len characters are received + * See MXC_UART_TransactionAsync() for a non-blocking version + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param buffer Buffer to store data in + * @param len Number of characters + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); + +/** + * @brief Writes a byte on the UART + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param byte The buffer of characters to write + * @param len The number of characters to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO user DMA for longer reads. + * + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers to use for UART DMA. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_ERROR_CODES for a list of return values + */ +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes + * + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers to use for UART DMA. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete + * + * @return See \ref MXC_ERROR_CODES for a list of return values + */ +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); + +/** + * @brief Set the receive threshold level. + * + * @note RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); + +/** + * @brief Set the transmit threshold level. + * + * @note TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); + +/** + * @brief Gets the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); + +/** + * @brief Clears the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flags mask of flags to clear + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); + +/** + * @brief Enables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be enabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); + +/** + * @brief Disables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be disabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); + +/** + * @brief Gets the status flags that are currently set + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The status flags + */ +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking UART transaction. + * + * @note Performs a blocking UART transaction as follows. + * If tx_len is non-zero, transmit TX data + * Once tx_len has been sent, if rx_len is non-zero, receive data + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_Transaction(mxc_uart_req_t *req); + +/** + * @brief Setup an interrupt-driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionAsync(mxc_uart_req_t *req); + +/** + * @brief Setup a DMA driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and + * returned to the system at the end of the transaction. + * + * @param req Pointer to details of the transaction + * @param dma Pointer to DMA registers to use for UART DMA + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_UART_DMACallback(int ch, int error); + +/** + * @brief Async callback + * + * @param uart The uart + * @param retVal The ret value + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); + +/** + * @brief stop any async callbacks + * + * @param uart The uart + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); + +/** + * @brief Abort any asynchronous requests in progress. + * + * @note Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); + +/** + * @brief The processing function for asynchronous transactions. + * + * @note When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the UART interrupt + * handler or periodically by the application if UART interrupts are disabled. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); + +/** + * @brief Provide TXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns transmit bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); + +/** + * @brief Provide RXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns receive bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req); + +/** + * @brief Enable or disable automatic DMA interrupt handlers for the UART module. + * + * The @ref MXC_UART_TransactionDMA functions require special interrupt handlers to work. + * + * When "Auto" DMA handlers are enabled, the UART drivers will acquire DMA channels + * and assign the appropriate handlers automatically. The acquired channels are + * released after each transaction. + * + * If "Auto" DMA handlers are disabled, the user must acquire DMA channels manually + * and assign them to the drivers with the @ref MXC_UART_SetTXDMAChannel and + * @ref MXC_UART_SetRXDMAChannel functions. + * + * @param uart Pointer to the UART module's registers. + * @param enable true to enable Auto DMA handlers, false to disable. + * @return 0 on success, or a non-zero error code on failure. + */ +int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable); + +/** + * @brief Set the TX (Transmit) DMA channel for a UART module. + * + * This function assigns the DMA channel for transmitting data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @param channel The DMA channel number to be used for @ref MXC_UART_TransactionDMA. + */ +int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel); + +/** + * @brief Get the TX (Transmit) DMA channel for a UART module. + * + * This function retrieves the currently assigned DMA channel for transmitting data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @return The currently assigned TX DMA channel. + */ +int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart); + +/** + * @brief Set the RX (Receive) DMA channel for a UART module. + * + * This function assigns the DMA channel for receiving data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @param channel The DMA channel number to be used for @ref MXC_UART_TransactionDMA. + */ +int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel); + +/** + * @brief Get the RX (Receive) DMA channel for a UART module. + * + * This function retrieves the currently configured DMA channel for receiving data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @return The currently configured RX DMA channel. + */ +int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart); + +/**@} end of group uart */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/wdt.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/wdt.h new file mode 100644 index 00000000..df1cb667 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/wdt.h @@ -0,0 +1,227 @@ +/** + * @file wdt.h + * @brief Watchdog timer (WDT) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "wdt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wdt WDT + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** @brief Watchdog upper limit period enumeration. + Used to configure the period of the watchdog interrupt */ +typedef enum { + MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31 + MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30 + MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29 + MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28 + MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27 + MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26 + MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25 + MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24 + MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23 + MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22 + MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21 + MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20 + MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19 + MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18 + MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17 + MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16 +} mxc_wdt_period_t; + +/** + * @brief Watchdog interrupt flag enumeration + */ +typedef enum { + MXC_WDT_INT_TOO_LATE = MXC_F_WDT_CTRL_INT_LATE, + MXC_WDT_INT_TOO_SOON = MXC_F_WDT_CTRL_INT_EARLY, +} mxc_wdt_int_t; + +/** + * @brief Watchdog reset flag enumeration + */ +typedef enum { + MXC_WDT_RST_TOO_LATE = MXC_F_WDT_CTRL_RST_LATE, + MXC_WDT_RST_TOO_SOON = MXC_F_WDT_CTRL_RST_EARLY, +} mxc_wdt_rst_t; + +/** + * @brief Watchdog mode enumeration + */ +typedef enum { + MXC_WDT_COMPATIBILITY = 0, + MXC_WDT_WINDOWED = 1, +} mxc_wdt_mode_t; + +/** + * @brief Peripheral Clock settings + */ +typedef enum { + MXC_WDT_PCLK = 0, + MXC_WDT_IBRO_CLK, + MXC_WDT_INRO_CLK, + MXC_WDT_ERTCO_CLK +} mxc_wdt_clock_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + mxc_wdt_mode_t mode; ///< WDT mode + mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit + mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit + mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit + mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit +} mxc_wdt_cfg_t; +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the Watchdog Timer + * @note On default this function enables WDT peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param wdt Pointer to the watchdog registers + * @param cfg watchdog configuration + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Shutdown the Watchdog Timer + * @param wdt Pointer to the watchdog registers + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt); + +/** + * @brief Set the period of the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + * @param cfg watchdog configuration. + */ +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Set the period of the watchdog reset. + * @param wdt Pointer to watchdog registers. + * @param cfg watchdog configuration. + */ +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Enable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt); + +/** + * @brief Enable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt); + +/** + * @brief Enable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt); + +/** + * @brief Reset the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt); + +/** + * @brief Get the status of the reset flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. + */ +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Clears the reset flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Get the status of the interrupt flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the interrupt is pending, 0 otherwise. + */ +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Clears the interrupt flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Sets clock source. + * @param wdt Pointer to watchdog registers. + * @param clock_source Clock source. + */ +int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source); + +/**@} end of group wdt */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/wut.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/wut.h new file mode 100644 index 00000000..187fff5d --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/wut.h @@ -0,0 +1,285 @@ +/** + * @file wut.h + * @brief Wakeup Timer (WUT) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "wut_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wut Wakeup Timer (WUT) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Wakeup Timer prescaler values + */ +typedef enum { + MXC_WUT_PRES_1 = MXC_S_WUT_CTRL_PRES_DIV1, /// Divide input clock by 1 + MXC_WUT_PRES_2 = MXC_S_WUT_CTRL_PRES_DIV2, /// Divide input clock by 2 + MXC_WUT_PRES_4 = MXC_S_WUT_CTRL_PRES_DIV4, /// Divide input clock by 4 + MXC_WUT_PRES_8 = MXC_S_WUT_CTRL_PRES_DIV8, /// Divide input clock by 8 + MXC_WUT_PRES_16 = MXC_S_WUT_CTRL_PRES_DIV16, /// Divide input clock by 16 + MXC_WUT_PRES_32 = MXC_S_WUT_CTRL_PRES_DIV32, /// Divide input clock by 32 + MXC_WUT_PRES_64 = MXC_S_WUT_CTRL_PRES_DIV64, /// Divide input clock by 64 + MXC_WUT_PRES_128 = MXC_S_WUT_CTRL_PRES_DIV128, /// Divide input clock by 128 + MXC_WUT_PRES_256 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV1, /// Divide input clock by 256 + MXC_WUT_PRES_512 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV2, /// Divide input clock by 512 + MXC_WUT_PRES_1024 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV4, /// Divide input clock by 1024 + MXC_WUT_PRES_2048 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV8, /// Divide input clock by 2048 + MXC_WUT_PRES_4096 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV16 /// Divide input clock by 4096 +} mxc_wut_pres_t; + +/** + * @brief Wakeup Timer modes + */ +typedef enum { + MXC_WUT_MODE_ONESHOT = MXC_V_WUT_CTRL_TMODE_ONESHOT, /// Wakeup Timer Mode ONESHOT + MXC_WUT_MODE_CONTINUOUS = MXC_V_WUT_CTRL_TMODE_CONTINUOUS, /// Wakeup Timer Mode CONTINUOUS + MXC_WUT_MODE_COUNTER = MXC_V_WUT_CTRL_TMODE_COUNTER, /// Wakeup Timer Mode COUNTER + MXC_WUT_MODE_CAPTURE = MXC_V_WUT_CTRL_TMODE_CAPTURE, /// Wakeup Timer Mode CAPTURE + MXC_WUT_MODE_COMPARE = MXC_V_WUT_CTRL_TMODE_COMPARE, /// Wakeup Timer Mode COMPARE + MXC_WUT_MODE_GATED = MXC_V_WUT_CTRL_TMODE_GATED, /// Wakeup Timer Mode GATED + MXC_WUT_MODE_CAPTURE_COMPARE = + MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE /// Wakeup Timer Mode CAPTURECOMPARE +} mxc_wut_mode_t; + +/** + * @brief Wakeup Timer units of time enumeration + */ +typedef enum { + MXC_WUT_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */ + MXC_WUT_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */ + MXC_WUT_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */ + MXC_WUT_UNIT_SEC /**< Second Unit Indicator. */ +} mxc_wut_unit_t; + +/** + * @brief Wakeup Timer Configuration + */ +typedef struct { + mxc_wut_mode_t mode; /// Desired timer mode + uint32_t cmp_cnt; /// Compare register value in timer ticks +} mxc_wut_cfg_t; + +/** + * @brief The callback routine used by the MXC_WUT_TrimCrystalAsync() + * function to indicate the transaction has completed. + * + * @param result Error code. + */ +typedef void (*mxc_wut_complete_cb_t)(int result); + +/* **** Definitions **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @param wut Pointer to Wakeup Timer instance to initialize. + * @param pres Prescaler value. + */ +void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres); + +/** + * @brief Shutdown timer module clock. + * @param wut Pointer to Wakeup Timer instance to shutdown. + */ +void MXC_WUT_Shutdown(mxc_wut_regs_t *wut); + +/** + * @brief Enable the timer. + * @param wut Pointer to Wakeup Timer instance to enable. + */ +void MXC_WUT_Enable(mxc_wut_regs_t *wut); + +/** + * @brief Disable the timer. + * @param wut Pointer to Wakeup Timer instance to disable. + */ +void MXC_WUT_Disable(mxc_wut_regs_t *wut); + +/** + * @brief Configure the timer. + * @param wut Pointer to Wakeup Timer instance to configure. + * @param cfg Pointer to timer configuration struct. + */ +void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg); + +/** + * @brief Get the timer compare count. + * @param wut Pointer to Wakeup Timer instance to get compare value from. + * @return Returns the current compare count. + */ +uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut); + +/** + * @brief Get the timer count. + * @param wut Pointer to Wakeup Timer instance to get count value from. + * @return Returns the current count. + */ +uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut); + +/** + * @brief Clear the timer interrupt. + * @param wut Pointer to Wakeup Timer instance to clear interrupts for. + */ +void MXC_WUT_IntClear(mxc_wut_regs_t *wut); + +/** + * @brief Get the timer interrupt status. + * @param wut Pointer to Wakeup Timer instance to get interrupt staus from. + * @return Returns the interrupt status. 1 if interrupt has occurred. + */ +uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut); + +/** + * @brief Set the timer compare count. + * @param wut Pointer to Wakeup Timer instance to set compare value for. + * @param cmp_cnt New compare count. + * @note This function does not protect against output glitches in PWM mode. + * Use MXC_WUT_PWMSetPeriod when in PWM mode. + */ +void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param wut Pointer to Wakeup Timer instance to set count value for. + * @param cnt New count. + */ +void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt); + +/** + * @brief Convert real time to timer ticks. + * @param wut Pointer to Wakeup Timer instance to get tick count for. + * @param time Number of units of time. + * @param units Which units of time you want to convert. + * @param ticks Pointer to store the number of ticks calculated. + * @return #E_NO_ERROR If everything is successful. + * @return @ref MXC_Error_Codes If function is unsuccessful. + */ +int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks); + +/** + * @brief Convert timer ticks to real time. + * @param wut Pointer to Wakeup Timer instance to get time for. + * @param ticks Number of ticks. + * @param time Pointer to store number of units of time. + * @param units Pointer to store the units that time represents. + * @return #E_NO_ERROR If everything is successful. + * @return @ref MXC_Error_Codes If function is unsuccessful. + */ +int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units); + +/** + * @brief Wait for an edge of the WUT count register. + * @param wut Pointer to Wakeup Timer instance to wait on. + */ +void MXC_WUT_Edge(mxc_wut_regs_t *wut); + +/** + * @brief Store the count and snapshot values. + * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for. + */ +void MXC_WUT_Store(mxc_wut_regs_t *wut); + +/** + * @brief Restore the DBB clock with the stored count and snapshot values. + * @param wut Pointer to Wakeup Timer instance restore count and snapshot values for. + * @param dbbFreq Frequency of DBB clock. + */ +void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq); + +/** + * @brief Get the difference between the stored counter value + * and the current counter value. + * @param wut Pointer to Wakeup Timer instance to get current sleep ticks for. + * @return Returns the current counter value - stored counter value. + */ +uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut); + +/** + * @brief Delays for the given number of milliseconds. + * @param wut Pointer to Wakeup Timer instance to use as the delay timer. + * @param waitMs Number of milliseconds to wait. + */ +void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs); + +/** + * @brief Trim the 32 kHz crystal load settings, blocks until complete. + * @param wut Pointer to Wakeup Timer instance to trim. + * @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal, + * to trim the load settings of the 32 kHz crystal. This procedure will only + * work if the BLE DBB is initialized and running. + * + * @return #E_NO_ERROR If everything is successful. + */ +int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut); + +/** + * @brief Trim the 32 kHz crystal load settings, non-blocking interrupt based. + * @param wut Pointer to Wakeup Timer instance to trim. + * @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal, + * to trim the load settings of the 32 kHz crystal. This procedure will only + * work if the BLE DBB is initialized and running. + * + * @param cb Callback for when the trim is complete. + * @return #E_NO_ERROR If everything is successful. + */ +int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb); + +/** + * @brief Check to see if the trim procedure is ongoing. + * @param wut Pointer to Wakeup Timer instance to check trim status for. + * @details Must leave the 32 MHz clock and BLE DBB running while the trim procedure is pending. + * @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing. + */ +int MXC_WUT_TrimPending(mxc_wut_regs_t *wut); + +/** + * @brief Interrupt handler for trim procedure. + * @param wut Pointer to Wakeup Timer instance to handle interrupts for. + * @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing. + */ +int MXC_WUT_Handler(mxc_wut_regs_t *wut); + +/**@} end of group wut */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32660/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32660/gpio.h index 7b6882ec..abdfbfb0 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32660/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32660/gpio.h @@ -105,12 +105,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -155,6 +169,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -336,6 +358,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32660/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32660/spi.h index b6175e15..5469796c 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32660/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32660/spi.h @@ -411,7 +411,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -439,7 +439,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32662/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32662/gpio.h index 7c1ce1d0..dfe4ff2f 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32662/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32662/gpio.h @@ -125,12 +125,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -175,6 +189,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -354,6 +376,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32662/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32662/spi.h index e712099a..e6bddafe 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32662/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32662/spi.h @@ -435,7 +435,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -463,7 +463,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h b/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h index 6cf98e7c..eb8e86c6 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32665/core1.h @@ -25,6 +25,12 @@ extern "C" { #endif +#include "mxc_device.h" + +#warning "core1.h is deprecated (05-24-2024)." +#warning "Use mxc_device.h instead, and set `ARM_DUALCORE=1` in project.mk" +#warning "Core 1 Startup/System code is located at Libraries/CMSIS/Device/Maxim/MAX32665/" + /** * @file core1.h * @brief Startup Code for MAX32665 Family CPU1 @@ -35,32 +41,36 @@ extern "C" { * @brief Starts the code on core 1 * Core1 code beings executing from Core1_Main() */ -void Core1_Start(void); +#if defined(__GNUC__) +inline __attribute__((deprecated("Use Start_Core1(); instead."))) void Core1_Start(void) +{ + Start_Core1(); +} +#endif /** * @brief Stops code executing in Core 1 */ -void Core1_Stop(void); +#if defined(__GNUC__) +inline __attribute__((deprecated("Use Stop_Core1(); instead."))) void Core1_Stop(void) +{ + Stop_Core1(); +} +#endif /** * @brief Main function for Core 1 Code * The user should override this function * in their application code */ -int Core1_Main(void); - -/** - * @brief Equivalent to PreInit for Core 0 - * Can be used for preliminary initialization - */ -void PreInit_Core1(void); +#if defined(__GNUC__) +inline __attribute__((deprecated( + "Use `int main_core1(void)` instead - main_core1 is Core 1's entry point where code starts, not Core1_Main."))) int +Core1_Main(void); +#endif -/** - * @brief Equivalent to PreInit for Core 1 - * Enables FPU, and ICache - * Sets interrupt vector - */ -void SystemInit_Core1(void); +// void PreInit_Core1(void) is now located in system_core_max32665.h +// void SystemInit_Core1(void) is now located in system_core_max32665.h #ifdef __cplusplus } diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32665/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32665/gpio.h index 3637e4ab..8f68f8f0 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32665/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32665/gpio.h @@ -124,13 +124,27 @@ typedef enum { } mxc_gpio_vssel_t; /** - * @brief Enumeration type for drive strength configuration. + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -175,6 +189,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -358,6 +380,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32665/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32665/spi.h index 234d2a0e..f521807f 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32665/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32665/spi.h @@ -413,7 +413,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -441,7 +441,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32670/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32670/gpio.h index 6c12e686..de6ea6ef 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32670/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32670/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -357,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32670/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32670/spi.h index 00ea93e3..532d040b 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32670/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32670/spi.h @@ -411,7 +411,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -439,7 +439,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32672/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32672/gpio.h index 936199c0..496b33f9 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32672/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32672/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -357,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32672/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32672/spi.h index 43a4ceee..dd95f5e8 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32672/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32672/spi.h @@ -410,7 +410,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -438,7 +438,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32675/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32675/gpio.h index 6839e0ba..dbfe5c0e 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32675/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32675/gpio.h @@ -125,13 +125,27 @@ typedef enum { } mxc_gpio_vssel_t; /** - * @brief Enumeration type for the voltage level on a given pin. + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, ///< Drive Strength 0 - MXC_GPIO_DRVSTR_1, ///< Drive Strength 1 - MXC_GPIO_DRVSTR_2, ///< Drive Strength 2 - MXC_GPIO_DRVSTR_3, ///< Drive Strength 3 + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -357,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h b/MAX/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h index e610fd44..37004110 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32675/mxc_pins.h @@ -38,14 +38,12 @@ extern const mxc_gpio_cfg_t gpio_cfg_hfextclk; extern const mxc_gpio_cfg_t gpio_cfg_i2c0; extern const mxc_gpio_cfg_t gpio_cfg_i2c1; extern const mxc_gpio_cfg_t gpio_cfg_i2c2; -extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; -extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; extern const mxc_gpio_cfg_t gpio_cfg_uart0; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; -//extern const mxc_gpio_cfg_t gpio_cfg_uart1; -//extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart1; +extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart2; extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable; @@ -53,14 +51,10 @@ extern const mxc_gpio_cfg_t gpio_cfg_uart3; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow; extern const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable; -// extern const mxc_gpio_cfg_t gpio_cfg_spi0; -// NOTE: SPI1 definied here with SS1 only, SS0 is on port0 by itself. +// NOTE: SPI1 definied here with SS1 only. extern const mxc_gpio_cfg_t gpio_cfg_spi1; -// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2 +// NOTE: SPI2 defined here with SS0 only. extern const mxc_gpio_cfg_t gpio_cfg_spi2; -// extern const mxc_gpio_cfg_t gpio_cfg_spi2b; -// NOTE: SPI3 defined here with SS0 only, and NOT SS1, SS2, or SS3 -// extern const mxc_gpio_cfg_t gpio_cfg_spi3; // Timers are only defined once, depending on package, each timer could be mapped to other pins extern const mxc_gpio_cfg_t gpio_cfg_tmr0; @@ -88,8 +82,12 @@ extern const mxc_gpio_cfg_t gpio_cfg_chrg_lc2; extern const mxc_gpio_cfg_t gpio_cfg_spi1_standard; extern const mxc_gpio_cfg_t gpio_cfg_spi1_3wire; // MXC_SPI1 does not support Dual or Quad modes. +extern const mxc_gpio_cfg_t gpio_cfg_spi2_standard; +extern const mxc_gpio_cfg_t gpio_cfg_spi2_3wire; +// MXC_SPI2 does not support Dual or Quad modes. // SPI v2 Target Selects Pin Definitions extern const mxc_gpio_cfg_t gpio_cfg_spi1_ts0; +extern const mxc_gpio_cfg_t gpio_cfg_spi2_ts0; #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32675_MXC_PINS_H_ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32675/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32675/spi.h index b417cc2c..5b7b068b 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32675/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32675/spi.h @@ -410,7 +410,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -438,7 +438,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32680/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32680/gpio.h index b4ddc6d3..071f6d1b 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32680/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32680/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, ///< Drive Strength GPIO_DS[2][pin]=0b00 + MXC_GPIO_DRVSTR_1, ///< Drive Strength GPIO_DS[2][pin]=0b01 + MXC_GPIO_DRVSTR_2, ///< Drive Strength GPIO_DS[2][pin]=0b10 + MXC_GPIO_DRVSTR_3, ///< Drive Strength GPIO_DS[2][pin]=0b11 } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -355,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32680/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32680/spi.h index c337cb45..2c35dce6 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32680/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32680/spi.h @@ -433,7 +433,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -461,7 +461,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32690/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX32690/gpio.h index 5e5f3f1a..096bd839 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32690/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32690/gpio.h @@ -127,12 +127,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0 = 0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -177,6 +191,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -356,6 +378,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32690/mxc_pins.h b/MAX/Libraries/PeriphDrivers/Include/MAX32690/mxc_pins.h index 569453bd..9228a80f 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32690/mxc_pins.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32690/mxc_pins.h @@ -154,7 +154,7 @@ extern const mxc_gpio_cfg_t gpio_cfg_spi0_dual; extern const mxc_gpio_cfg_t gpio_cfg_spi0_quad; extern const mxc_gpio_cfg_t gpio_cfg_spi1_standard; extern const mxc_gpio_cfg_t gpio_cfg_spi1_3wire; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_dua; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_dual; extern const mxc_gpio_cfg_t gpio_cfg_spi1_quad_0; extern const mxc_gpio_cfg_t gpio_cfg_spi1_quad_1; extern const mxc_gpio_cfg_t gpio_cfg_spi2_standard; diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32690/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX32690/spi.h index a64595dc..d8d36f96 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32690/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32690/spi.h @@ -28,12 +28,13 @@ /***** includes *******/ #include -#include "spi_regs.h" #include "mxc_sys.h" #include "mxc_assert.h" -#include "gpio.h" #include "mxc_pins.h" #include "mxc_lock.h" +#include "gpio.h" +#include "spi_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -47,31 +48,74 @@ extern "C" { /***** Definitions *****/ +// clang-format off + +/** + * @brief The list of types for the SPI peripheral. + */ +typedef enum { + MXC_SPI_TYPE_SLAVE = 0, + MXC_SPI_TYPE_TARGET = 0, + MXC_SPI_TYPE_MASTER = 1, + MXC_SPI_TYPE_CONTROLLER = 1 +} mxc_spi_type_t; + +/** + * @brief The list of Target Select Control Scheme Options for + * target assertion/deassertion. + */ +typedef enum { + MXC_SPI_TSCONTROL_HW_AUTO = 0, ///< Automatically by hardware + MXC_SPI_TSCONTROL_SW_APP = 1 ///< Through software in the application +} mxc_spi_tscontrol_t; + +/** + * @brief The list of possible states for an SPI instance. + */ +typedef enum { + MXC_SPI_STATE_READY = 0, ///< Ready for transaction + MXC_SPI_STATE_BUSY = 1 ///< Busy transferring +} mxc_spi_state_t; + +/** + * @brief The list of supported SPI Interface Modes. + */ +typedef enum { + MXC_SPI_INTERFACE_STANDARD = 0, + MXC_SPI_INTERFACE_4WIRE = 0, + MXC_SPI_INTERFACE_QUAD = 1, + MXC_SPI_INTERFACE_3WIRE = 2, + MXC_SPI_INTERFACE_DUAL = 3 +} mxc_spi_interface_t; + +/** + * @brief The list of SPI clock modes + * + * SPI supports four combinations of clock and phase polarity. + * + * Clock polarity is controlled using the bit SPIn_CTRL2.cpol + * and determines if the clock is active high or active low + * + * Clock phase determines when the data must be stable for sampling + */ +typedef enum { + MXC_SPI_CLKMODE_0 = 0, ///< CPOL: 0 CPHA: 0 + MXC_SPI_CLKMODE_1 = 1, ///< CPOL: 0 CPHA: 1 + MXC_SPI_CLKMODE_2 = 2, ///< CPOL: 1 CPHA: 0 + MXC_SPI_CLKMODE_3 = 3 ///< CPOL: 1 CPHA: 1 +} mxc_spi_clkmode_t; + +///>>> @deprecated /** * @brief The list of SPI Widths supported - * - * The SPI Width can be set on a per-transaction basis. - * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is - * given. - * - * Using a MAX31865 RTD-to-SPI IC, read back the temperature - * The IC requires a SPI Read to be executed as - * 1. Assert SS - * 2. Write an 8bit register address - * 3. Read back the 8 bit register - * 4. Deassert SS - * This can be accomplished with the STANDARD_HALFDUPLEX width - * 1. set txData to the address, txLen=1 - * 2. set rxData to a buffer of 1 byte, rxLen=1 - * 3. The driver will transmit the txData, and after completion of - * txData begin to recieve data, padding MOSI with DefaultTXData - * + * + * @deprecated. */ typedef enum { - SPI_WIDTH_3WIRE = 0, ///< 1 Data line, half duplex + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex - SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex - SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex } mxc_spi_width_t; /** @@ -86,61 +130,68 @@ typedef enum { * */ typedef enum { - SPI_MODE_0 = 0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 } mxc_spi_mode_t; - -typedef struct _mxc_spi_pins_t mxc_spi_pins_t; - -/** - * @brief Structure used to initialize SPI pins. - * - * @note All values must be initialized. - * - * @note True equals pin is set for the spi function false the pin is left to its latest state. - */ -struct _mxc_spi_pins_t { - bool ss0; ///< Slave select pin 0 - bool ss1; ///< Slave select pin 1 - bool ss2; ///< Slave select pin 2 -}; +///<<< Deprecated typedef struct _mxc_spi_req_t mxc_spi_req_t; + /** * @brief The callback routine used to indicate the transaction has terminated. * * @param req The details of the transaction. * @param result See \ref MXC_Error_Codes for the list of error codes. */ -typedef void (*spi_complete_cb_t)(void *req, int result); +typedef void (*mxc_spi_callback_t)(void *, int result); +typedef mxc_spi_callback_t spi_complete_cb_t; // Support SPI v1 name. -/** - * @brief The information required to perform a complete SPI transaction - * - * This structure is used by blocking, async, and DMA based transactions. - * @note "completeCB" only needs to be initialized for interrupt driven (Async) and DMA transactions. - */ +typedef struct _mxc_spi_pins_t mxc_spi_pins_t; +struct _mxc_spi_pins_t { + bool ss0; ///< Target select pin 0. + bool ss1; ///< Target select pin 1. + bool ss2; ///< Target select pin 2. + + bool vddioh; ///< VDDIOH Select + + bool clock; ///< Clock pin + bool miso; ///< miso pin + bool mosi; ///< mosi pin + bool sdio2; ///< SDIO2 pin + bool sdio3; ///< SDIO3 pin + + mxc_gpio_drvstr_t drvstr; ///< Drive strength setting +}; + +typedef struct { + // SPI Settings. + mxc_spi_regs_t *spi; ///< Selected SPI Instance + mxc_spi_clkmode_t clk_mode; ///< Clock modes + uint8_t frame_size; ///< Number of bits per character sent + + // DMA Settings. + bool use_dma_tx; ///< Enable DMA TX. + bool use_dma_rx; ///< Enable DMA RX. (use_dma_tx must be true to use DMA RX). + mxc_dma_regs_t *dma; ///< Select DMA instance for SPI DMA. +} mxc_spi_cfg_t; + +// Suppport names for backwards compatibility. struct _mxc_spi_req_t { - mxc_spi_regs_t *spi; /// 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros - uint8_t *rxData; ///< Buffer to store received data For character sizes - ///< < 8 bits, pad the MSB of each byte with zeros. For - ///< character sizes > 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros - uint32_t txLen; ///< Number of bytes to be sent from txData - uint32_t rxLen; ///< Number of bytes to be stored in rxData - uint32_t txCnt; ///< Number of bytes actually transmitted from txData - uint32_t rxCnt; ///< Number of bytes stored in rxData - - spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete + mxc_spi_regs_t *spi; ///< Pointer to SPI registers + int ssIdx; ///< Target Select (TS) Index for this request + int ssDeassert; ///< Deassert Target Select (TS) line at end of transaction. + uint8_t *txData; + uint8_t *rxData; + uint32_t txLen; ///< Number of frames to be stored in txData + uint32_t rxLen; ///< Number of frames to be stored in rxData + uint32_t txCnt; ///< Number of bytes transmitted from txData (Unused for SPI v2) + uint32_t rxCnt; ///< Number of bytes stored in rxData (Unused for SPI v2) + mxc_spi_callback_t completeCB; ///< Callback at the end of transaction + uint16_t txDummyValue; ///< Value of dummy bytes to be sent }; +// clang-format on /* ************************************************************************* */ /* Control/Configuration functions */ @@ -148,273 +199,360 @@ struct _mxc_spi_req_t { /** * @brief Initialize and enable SPI peripheral. - * - * This function initializes everything necessary to call a SPI transaction function. - * Some parameters are set to defaults as follows: - * SPI Mode - 0 - * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) - * - * These parameters can be modified after initialization using low level functions * - * @note On default this function enables SPI peripheral clock and spi gpio pins. - * if you wish to manage clock and gpio related things in upper level instead of here. - * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. - * By this flag this function will remove clock and gpio related codes from file - * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param masterMode Whether to put the device in master or slave mode. Use - * non-zero for master mode, and zero for slave mode. - * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use - * non-zero if the pins are needed (if Quad Mode will - * be used), and zero if they are not needed (quad mode - * will never be used). - * @param numSlaves The number of slaves used, if in master mode. This - * is used to obtain control of the necessary SS pins. - * In slave mode this is ignored and SS1 is used. - * @param ssPolarity This field sets the SS active polarity for each - * slave, each bit position corresponds to each SS line. - * @param hz The requested clock frequency. The actual clock frequency - * will be returned by the function if successful. Used in - * master mode only. - * @param pins SPI pin structure. Pins selected as true will be initialized - * for the requested SPI block. Has no effect incase of - * MSDK_NO_GPIO_CLK_INIT has been defined. + * This function does not set the Clock Mode (defaults to Clock Mode 0) and + * only two interface modes are selectable (Quad Mode or 4-Wire Standard Mode). + * To change the clock mode, call MXC_SPI_SetClkMode(..).. + * To select another interface mode, call MXC_SPI_SetInterface(..).. + * + * These parameters can be modified after cfgialization using low level functions + * + * @param spi Pointer to SPI instance's registers. + * @param controller_target Whether to put the device in controller or target mode. Use + * non-zero for controller mode, and zero for target mode. + * MXC_SPI_TYPE_CONTROLLER - 1 + * MXC_SPI_TYPE_TARGET - 0 + * @param if_mode Set the interface mode. + * MXC_SPI_INTERFACE_STANDARD - 0 (4 wire) + * MXC_SPI_INTERFACE_QUAD - 1 + * MXC_SPI_INTERFACE_3WIRE - 2 + * MXC_SPI_INTERFACE_DUAL - 3 + * @param numTargets This parameter is UNUSED for SPI v2. + * The number of target used, if in controller mode. This + * is used to obtain control of the necessary TS pins. + * In target mode this is ignored and TS1 is used. + * @param ts_active_pol_mask This field sets the TS active polarity for each + * target, each bit position corresponds to each TS line. + * ts_active_pol_mask[0] - TS0 + * ts_active_pol_mask[1] - TS1 + * ts_active_pol_mask[n] - TSn + * @param freq The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. Used in + * master mode only. + * @param pins SPI pin structure. Pins selected as true will be initialized + * for the requested SPI block. * * @return If successful, the actual clock frequency is returned. Otherwise, see * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins); +int MXC_SPI_Init(mxc_spi_regs_t *spi, mxc_spi_type_t controller_target, mxc_spi_interface_t if_mode, + int numTargets, uint8_t ts_active_pol_mask, uint32_t freq, mxc_spi_pins_t pins); /** - * @brief Disable and shutdown SPI peripheral. + * @brief Configure the SPI peripheral. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * List of Setting that will be updated: + * Clock Mode. + * Frame Size (bits). + * Interface Mode (Dual, Quad, Standard, 3-Wire). + * If DMA selections are true, configure and acquire DMA channels. + * + * @param cfg Pointer to SPI configuration struct. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); +int MXC_SPI_Config(mxc_spi_cfg_t *cfg); /** - * @brief Checks if the given SPI bus can be placed in sleep mode. + * @brief Overwrite the cfg struct with default values. * - * This functions checks to see if there are any on-going SPI transactions in - * progress. If there are transactions in progress, the application should - * wait until the SPI bus is free before entering a low-power state. + * Settings: + * SPI APB (SPI1) instance + * Default, predefined SPI pins at VDDIO + * Controller Mode + * Standard 4-wire mode + * 100KHz speed + * CPOL: 0, CPHA: 0 + * Automatic Hardware mode for TS Control + * TS0 pin + * Target active polarity is LOW (0) + * If use_dma = true, set DMATX and RX to true and set the DMA0 as the default instance. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param cfg Pointer to SPI configuration struct. + * @param use_dma_tx True/False option to configure DMA TX. + * @param use_dma_rx True/False option to configure DMA RX. * - * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref - * MXC_Error_Codes for the list of error return codes. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes.odes. */ -int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); +int MXC_SPI_ConfigStruct(mxc_spi_cfg_t *cfg, bool use_dma_tx, bool use_dma_rx); /** - * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. + * @brief Disable and shutdown the SPI instance. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * - * @return Frequency of the clock used as the bit rate generator + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); /** - * @brief Set the frequency of the SPI interface. + * @brief Gets the interrupt flags that are currently set * - * This function is applicable in Master mode only + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param hz The desired frequency in Hertz. + * @param spi Pointer to SPI registers (selects the SPI block used). * - * @return Negative if error, otherwise actual speed set. See \ref - * MXC_Error_Codes for the list of error return codes. + * @return The interrupt flags. */ -int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); /** - * @brief Get the frequency of the SPI interface. + * @brief Clears the interrupt flags that are currently set. * - * This function is applicable in Master mode only + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA). + * + * @param spi Pointer to SPI registers (selects the SPI block used). + */ +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); + +/** + * @brief Enables specific interrupts * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA). * - * @return The SPI bus frequency in Hertz + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param intEn The interrupts to be enabled. */ -unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn); /** - * @brief Sets the number of bits per character + * @brief Disables specific interrupts * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param dataSize The number of bits per character + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param intDis The interrupts to be disabled */ -int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); /** - * @brief Gets the number of bits per character + * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @return Frequency of the clock used as the bit rate generator */ -int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); -/* ************************************************************************* */ -/* Low-level functions */ -/* ************************************************************************* */ +/** + * @brief Configures the Pre-defined SPI Target Select pins for a specific instance. + * + * @param spi Pointer to SPI instance's registers. + * @param ts_control Target Select Control Scheme (\ref mxc_spi_tscontrol_t). + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetTSControl(mxc_spi_regs_t *spi, mxc_spi_tscontrol_t ts_control); /** - * @brief Sets the slave select (SS) line used for transmissions + * @brief Set the frequency of the SPI interface. * * This function is applicable in Master mode only * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param ssIdx Slave select index + * @param spi Pointer to SPI instance's registers. + * @param hz The desired frequency in Hertz. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); /** - * @brief Gets the slave select (SS) line used for transmissions + * @brief Get the frequency of the SPI interface. * * This function is applicable in Master mode only * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * - * @return slave slect + * @return If successful, the SPI instance's set frequency value is returned. + * Otherwise, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); /** - * @brief Sets the SPI width used for transmissions + * @brief Sets the number of bits per frame. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) + * @param spi Pointer to SPI instance's registers. + * @param frame_size The number of bits per frame. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); +int MXC_SPI_SetFrameSize(mxc_spi_regs_t *spi, int frame_size); /** - * @brief Gets the SPI width used for transmissions + * @brief Gets the number of bits per frame. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * - * @return Spi Width + * @return If successful, the SPI instance's set data size is returned. + * Otherwise, see \ref MXC_Error_Codes for a list of return codes. */ -mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); +int MXC_SPI_GetFrameSize(mxc_spi_regs_t *spi); /** - * @brief Sets the spi mode using clock polarity and clock phase + * @brief Sets the SPI interface mode used for transmissions. + * + * 3-Wire, Standard (4-Wire), Quad, Dual Modes + * + * @param spi Pointer to SPI instance's registers. + * @param if_mode SPI interface mode (3-Wire, Standard, Dual SPI, Quad SPI). + * See \ref mxc_spi_datawidth_t + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetInterface(mxc_spi_regs_t *spi, mxc_spi_interface_t if_mode); + +/** + * @brief Gets the SPI interface mode used for transmissions. + * + * 3-Wire, Standard (4-Wire), Quad, Dual Modes + * + * @param spi Pointer to SPI instance's registers. + * + * @return The selected SPI instance's data line width. See \ref mxc_spi_datawidth_t. + */ +mxc_spi_interface_t MXC_SPI_GetInterface(mxc_spi_regs_t *spi); + +/** + * @brief Sets the SPI clock mode (clock polarity and clock phase). * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param spiMode \ref mxc_spi_mode_t + * @param spi Pointer to SPI instance's registers. + * @param clk_mode SPI clock mode. See \ref mxc_spi_clkmode_t. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); +int MXC_SPI_SetClkMode(mxc_spi_regs_t *spi, mxc_spi_clkmode_t clk_mode); /** - * @brief Gets the spi mode + * @brief Gets the SPI clock mode (clock polarity and clock phase). * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. + * @param clk_mode SPI clock mode. See \ref mxc_spi_clkmode_t + * + * @return The selected SPI instance's clock mode. See \ref mxc_spi_clkwidth_t. + */ +mxc_spi_clkmode_t MXC_SPI_GetClkMode(mxc_spi_regs_t *spi); + +/** + * @brief Sets the SPI instance's callback function. * - * @return mxc_spi_mode_t \ref mxc_spi_mode_t + * @param spi Pointer to SPI instance's registers. + * @param callback Pointer to callback function called when transaction is complete. + * @param data Pointer for data to pass through callback funciton. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); +int MXC_SPI_SetCallback(mxc_spi_regs_t *spi, mxc_spi_callback_t callback, void *data); /** - * @brief Starts a SPI Transmission + * @brief Checks the SPI instance for an ongoing transmission * - * This function is applicable in Master mode only + * This function is applicable in Controller mode only. * - * The user must ensure that there are no ongoing transmissions before - * calling this function + * @param spi Pointer to SPI instance's registers. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetActive(mxc_spi_regs_t *spi); + +/** + * @brief Checks whether the SPI instance is ready for sleep. * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @param spi Pointer to SPI instance's registers. + * + * @return Busy/Ready, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); /** - * @brief Checks the SPI Peripheral for an ongoing transmission + * @brief Starts a SPI Transmission * * This function is applicable in Master mode only * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * The user must ensure that there are no ongoing transmissions before + * calling this function * - * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + * @param spi Pointer to SPI instance's registers. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_GetActive(mxc_spi_regs_t *spi); +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); /** * @brief Aborts an ongoing SPI Transmission * * This function is applicable in Master mode only * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); /** - * @brief Unloads bytes from the receive FIFO. + * @brief Abort any asynchronous requests in progress. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. * - * @return The number of bytes actually read. + * @param spi Pointer to SPI instance's registers. */ -unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); /** - * @brief Get the number of bytes currently available in the receive FIFO. + * @brief Get the amount of free space available in the transmit FIFO. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * * @return The number of bytes available. */ -unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); /** - * @brief Loads bytes into the transmit FIFO. + * @brief Get the number of bytes currently available in the receive FIFO. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. + * @param spi Pointer to SPI instance's registers. * - * @return The number of bytes actually written. + * @return The number of bytes available. */ -unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); /** - * @brief Get the amount of free space available in the transmit FIFO. - * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @brief Removes and discards all bytes currently in the transmit FIFO. * - * @return The number of bytes available. + * @param spi Pointer to SPI instance's registers. */ -unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); /** * @brief Removes and discards all bytes currently in the receive FIFO. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. */ void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); /** - * @brief Removes and discards all bytes currently in the transmit FIFO. + * @brief Set the transmit threshold level. + * + * TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param spi Pointer to SPI instance's registers. + * @param numBytes The threshold level to set. This value must be + * between 0 and 30 inclusive. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); /** * @brief Set the receive threshold level. @@ -427,99 +565,220 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * cause the driver to use the value already set in the * appropriate register. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); +/** + * @brief Get the current transmit threshold level. + * + * @param spi Pointer to SPI instance's registers. + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); + /** * @brief Get the current receive threshold level. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * * @return The receive threshold value (in bytes). */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); +//////>>> Previous Implementation (SPI v1) /** - * @brief Set the transmit threshold level. + * @brief Sets the number of bits per character * - * TX FIFO threshold. Smaller values will cause interrupts - * to occur more often, but reduce the possibility of terminating - * a transaction early in master mode, or transmitting invalid data - * in slave mode. Larger values will reduce the time required by - * the ISR, but increase the possibility errors occurring. Passing - * an invalid value will cause the driver to use the value already - * set in the appropriate register. + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param dataSize The number of bits per character * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); + +/** + * @brief Gets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used). * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); /** - * @brief Get the current transmit threshold level. + * @brief Sets the SPI width used for transmissions * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) * - * @return The transmit threshold value (in bytes). + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); /** - * @brief Gets the interrupt flags that are currently set + * @brief Gets the SPI width used for transmissions * - * These functions should not be used while using non-blocking Transaction Level - * functions (Async or DMA) + * @param spi Pointer to SPI registers (selects the SPI block used). * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @return Spi Width + */ +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); + +/** + * @brief Sets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI instance's registers. + * @param ssIdx Slave select index * - * @return The interrupt flags + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); /** - * @brief Clears the interrupt flags that are currently set + * @brief Gets the slave select (SS) line used for transmissions * - * These functions should not be used while using non-blocking Transaction Level - * functions (Async or DMA) + * This function is applicable in Master mode only * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. * + * @return slave slect */ -void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); /** - * @brief Enables specific interrupts + * @brief Sets the spi mode using clock polarity and clock phase + * + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param spiMode \ref mxc_spi_mode_t + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); + +/** + * @brief Gets the spi mode + * + * @param spi Pointer to SPI registers (selects the SPI block used). + * + * @return mxc_spi_mode_t \ref mxc_spi_mode_t + */ +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); + +/** + * @brief Loads bytes into the transmit FIFO. * - * These functions should not be used while using non-blocking Transaction Level - * functions (Async or DMA) + * @param spi Pointer to SPI instance's registers. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param intEn The interrupts to be enabled + * @return The number of bytes actually written. */ -void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn); +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); /** - * @brief Disables specific interrupts + * @brief Unloads bytes from the receive FIFO. * - * These functions should not be used while using non-blocking Transaction Level - * functions (Async or DMA) + * @param spi Pointer to SPI instance's registers. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param intDis The interrupts to be disabled + * @return The number of bytes actually read. */ -void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); -/* ************************************************************************* */ -/* Transaction level functions */ -/* ************************************************************************* */ +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); + +/** + * @brief Enable/Disable HW CS control feature. + * + * Depending on the application, the user might need to manually drive the slave select pin. + * The SPI driver automatically drives the SS pin and this function enables/disables this + * feature. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. + */ +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); +//////<<< Previous Implementation (SPI v1) + +/* ** DMA Functions ** */ + +/** + * @brief This function initializes the DMA for SPI DMA transactions. + * + * @note This function must run before any SPI DMA transactions. + * + * @param spi Pointer to SPI registers (selects the SPI block used). + * @param dma Pointer to DMA registers (selects the DMA block used). + * @param use_dma_tx True/False setting to initialize SPI DMA TX. Acquire DMA TX channel. + * @param use_dma_rx True/False setting to initialize SPI DMA RX. Acquire DMA RX channel. + * use_dma_tx must be true even if use_dma_rx is false. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_DMA_Init(mxc_spi_regs_t *spi, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx); + +/** + * @brief Helper function that checks whether the MXC_SPI_Init function + * cfgalized DMA for SPI DMA transactons. + * + * @param spi Pointer to SPI instance's registers. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +bool MXC_SPI_DMA_GetInitialized(mxc_spi_regs_t *spi); + +/** + * @brief Retreive the DMA TX Channel associated with SPI instance. + * + * @param spi Pointer to SPI instance's registers. + * + * @return If successful, the DMA TX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_DMA_GetTXChannel(mxc_spi_regs_t *spi); + +/** + * @brief Retreive the DMA RX Channel associated with SPI instance. + * + * @param spi Pointer to SPI instance's registers. + * + * @return If successful, the DMA RX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_DMA_GetRXChannel(mxc_spi_regs_t *spi); + +/** + * @brief Sets the SPI instance's DMA TX/RX request select. + * + * @param spi Pointer to SPI instance's registers. + * @param use_dma_tx True/False setting to set SPI DMA TX request select. + * @param use_dma_rx True/False setting to set SPI DMA RX request select. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_DMA_SetRequestSelect(mxc_spi_regs_t *spi, bool use_dma_tx, bool use_dma_rx); + +/* ** Transaction Functions ** */ /** * @brief Performs a blocking SPI transaction. @@ -540,7 +799,7 @@ void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); * 4. Unload RX FIFO as needed * 5. On SS Deassert, return * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction. * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -552,7 +811,7 @@ int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction. * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -569,22 +828,57 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); * possible. The channel will be reset and returned to the system at the end of * the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction. * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); /** - * @brief Performs a blocking SPI transaction. + * @brief Set up a blocking, non-interrupt-driven SPI controller transaction. + * + * @param req Pointer to details of the transaction. * - * Performs a blocking SPI transaction. - * These actions will be performed in Slave Mode: - * 1. Fill FIFO with txData - * 2. Wait for SS Assert - * 3. If needed, pad txData with DefaultTXData - * 4. Unload RX FIFO as needed - * 5. On SS Deassert, return + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ControllerTransaction(mxc_spi_req_t *req); + +/** + * @brief Set up a non-blocking, interrupt-driven SPI controller transaction. + * + * The MXC_SPI_Handler function must be called in the selected SPI instance's + * interrupt handler to process the transaction. + * + * @param req Pointer to details of the transaction. + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ControllerTransactionAsync(mxc_spi_req_t *req); + +/** + * @brief Set up a non-blocking, DMA-driven SPI controller transaction. + * + * The MXC_SPI_Config(...) or MXC_SPI_DMA_Init(..). functions must be + * called before calling this DMA transaction function. This function + * does not initialize the DMA. + * + * @param req Pointer to details of the transaction. + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ControllerTransactionDMA(mxc_spi_req_t *req); + +/** + * @brief Set up a blocking, DMA-driven SPI controller transaction. + * + * @param req Pointer to details of the transaction. + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ControllerTransactionDMAB(mxc_spi_req_t *req); + +/** + * @brief Performs a blocking SPI transaction. * * @param req Pointer to details of the transaction * @@ -595,9 +889,6 @@ int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); /** * @brief Setup an interrupt-driven SPI transaction * - * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary - * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) - * * @param req Pointer to details of the transactionz * * @return See \ref MXC_Error_Codes for the list of error return codes. @@ -622,28 +913,37 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); /** - * @brief Sets the TX data to transmit as a 'dummy' byte - * - * In single wire master mode, this data is transmitted on MOSI when performing - * an RX (MISO) only transaction. This defaults to 0. + * @brief Setup a blocking SPI Target transaction. + * + * @param req Pointer to details of the transaction. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param defaultTXData Data to shift out in RX-only transactions + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_TargetTransaction(mxc_spi_req_t *req); + +/** + * @brief Setup an interrupt-driven, non-blocking SPI Target transaction. + * + * @param req Pointer to details of the transaction. * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); +int MXC_SPI_TargetTransactionAsync(mxc_spi_req_t *req); /** - * @brief Abort any asynchronous requests in progress. + * @brief Setup a DMA-driven SPI Target transaction. * - * Abort any asynchronous requests in progress. Any callbacks associated with - * the active transaction will be executed to indicate when the transaction - * has been terminated. + * The MXC_SPI_Config(...) or MXC_SPI_DMA_Init(..). functions must be + * called before calling this DMA transaction function. This function + * does not initialize the DMA. + * + * @param req Pointer to details of the transaction. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @return See \ref MXC_Error_Codes for the list of error return codes. */ -void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); +int MXC_SPI_TargetTransactionDMA(mxc_spi_req_t *req); + +/* ** Handler Functions ** */ /** * @brief The processing function for asynchronous transactions. @@ -652,21 +952,38 @@ void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); * function periodically. This can be done from within the SPI interrupt * handler or periodically by the application if SPI interrupts are disabled. * - * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spi Pointer to SPI instance's registers. */ void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); /** - * @brief Enable/Disable HW CS control feature. + * @brief The processing function for asynchronous transactions. * - * Depending on the application, the user might need to manually drive the slave select pin. - * The SPI driver automatically drives the SS pin and this function enables/disables this - * feature. + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the SPI interrupt + * handler or periodically by the application if SPI interrupts are disabled. * - * @param spi Pointer to SPI registers (selects the SPI block used.) - * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. + * @param spi Pointer to SPI instance's registers. */ -void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); +void MXC_SPI_Handler(mxc_spi_regs_t *spi); + +/** + * @brief The processing function for DMA TX transactions. + * + * This function calls the callback function if only TX transaction was made. + * + * @param spi Pointer to SPI instance's registers. + */ +void MXC_SPI_DMA_TX_Handler(mxc_spi_regs_t *spi); + +/** + * @brief The processing function for DMA RX transactions. + * + * This function calls the callback function at the end of a TX/RX transaction. + * + * @param spi Pointer to SPI instance's registers. + */ +void MXC_SPI_DMA_RX_Handler(mxc_spi_regs_t *spi); /**@} end of group spi */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX78000/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX78000/gpio.h index dc9499e9..b97fd17e 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX78000/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX78000/gpio.h @@ -126,12 +126,26 @@ typedef enum { /** * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -357,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX78000/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX78000/spi.h index bed7bb11..1792808d 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX78000/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX78000/spi.h @@ -428,7 +428,7 @@ void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -456,7 +456,7 @@ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI registers (selects the SPI block used.) * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX78002/csi2.h b/MAX/Libraries/PeriphDrivers/Include/MAX78002/csi2.h index 5a748095..190e18dd 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX78002/csi2.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX78002/csi2.h @@ -330,17 +330,19 @@ int MXC_CSI2_Stop(void); /** * @brief Capture an image frame using DMA. Same as MXC_CSI2_CaptureFrameDMA. - * @param num_data_lanes Number of data lanes used. + * @note API changed on 7-8-2024 to remove 'num_data_lanes' as an argument. Set + * 'num_lanes' in @ref mxc_csi2_ctrl_cfg_t instead, which is passed to + * @ref MXC_CSI2_Init * @return #E_NO_ERROR if everything is successful. */ -int MXC_CSI2_CaptureFrame(int num_data_lanes); +int MXC_CSI2_CaptureFrame(void); /** * @brief Capture an image frame using DMA. * @param num_data_lanes Number of data lanes used. * @return #E_NO_ERROR if everything is successful. */ -int MXC_CSI2_CaptureFrameDMA(); +int MXC_CSI2_CaptureFrameDMA(void); /** * @brief Select Lane Control Source for D0-D4 and C0. @@ -588,7 +590,7 @@ int MXC_CSI2_PPI_Stop(void); bool MXC_CSI2_DMA_Frame_Complete(void); -mxc_csi2_capture_stats_t MXC_CSI2_GetCaptureStats(); +mxc_csi2_capture_stats_t MXC_CSI2_GetCaptureStats(void); /** * @brief Clears the interrupt flags for PPI. diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX78002/gpio.h b/MAX/Libraries/PeriphDrivers/Include/MAX78002/gpio.h index efe98e93..218a7dda 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX78002/gpio.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX78002/gpio.h @@ -125,13 +125,27 @@ typedef enum { } mxc_gpio_vssel_t; /** - * @brief Enumeration type for drive strength configuration. + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). */ typedef enum { - MXC_GPIO_DRVSTR_0, /**< Drive Strength 0 */ - MXC_GPIO_DRVSTR_1, /**< Drive Strength 1 */ - MXC_GPIO_DRVSTR_2, /**< Drive Strength 2 */ - MXC_GPIO_DRVSTR_3, /**< Drive Strength 3 */ + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ } mxc_gpio_drvstr_t; /** @@ -176,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -355,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX78002/spi.h b/MAX/Libraries/PeriphDrivers/Include/MAX78002/spi.h index 4d99415b..5e68a225 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX78002/spi.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX78002/spi.h @@ -549,7 +549,7 @@ void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); * * @param spi Pointer to SPI instance's registers. * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -568,7 +568,7 @@ int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); * * @param spi Pointer to SPI instance's registers. * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * between 0 and 30 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ diff --git a/MAX/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c b/MAX/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c index 6fa2ec4c..7a38c231 100644 --- a/MAX/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/ADC/adc_ai87.c @@ -37,9 +37,9 @@ */ #define MXC_F_MCR_ADCCFG2_CH 0x3 -#define TEMP_FACTOR 530.582f / 4096.0 -#define TEMP_FACTOR1V25 1.25 * TEMP_FACTOR -#define TEMP_FACTOR2V048 2.048 * TEMP_FACTOR +#define TEMP_FACTOR 530.582f / 4096.0f +#define TEMP_FACTOR1V25 1.25f * TEMP_FACTOR +#define TEMP_FACTOR2V048 2.048f * TEMP_FACTOR static void initGPIOForChannel(mxc_adc_chsel_t channel) { @@ -397,7 +397,7 @@ int MXC_ConvertTemperature_ToF(uint16_t tempSensor_Readout, mxc_adc_refsel_t ref float *temp) { if (MXC_ConvertTemperature_ToK(tempSensor_Readout, ref, ext_ref, temp) == E_NO_ERROR) { - *temp = ((*temp * 1.8) - 459.67f); + *temp = (*temp * 1.8f) - 459.67f; return E_NO_ERROR; } else { return E_BAD_PARAM; diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_ai87.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_ai87.c index 594d8611..d5a3eea3 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_ai87.c @@ -46,7 +46,7 @@ int MXC_AES_Init(void) // Start with a randomly generated key. MXC_AES_GenerateKey(); - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } @@ -138,12 +138,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me12.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me12.c index 87e6b35c..c66daaea 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me12.c @@ -41,7 +41,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); } void MXC_AES_EnableInt(uint32_t interrupt) @@ -131,12 +131,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me15.c index d35812e0..0a238ee8 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -63,7 +63,7 @@ int MXC_AES_Init(void) // Start with a randomly generated key. MXC_AES_GenerateKey(); - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } @@ -155,12 +155,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me17.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me17.c index 27ac05bc..50c75247 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me17.c @@ -42,7 +42,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); } void MXC_AES_EnableInt(uint32_t interrupt) @@ -132,12 +132,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me21.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me21.c index 1eaf61ca..83d50ad0 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me21.c @@ -40,7 +40,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } @@ -126,12 +126,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_me30.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me30.c new file mode 100644 index 00000000..575f8abe --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_me30.c @@ -0,0 +1,156 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "aes_revb.h" +#include "trng.h" +#include "trng_revb.h" +#include "dma.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +int MXC_AES_Init(mxc_dma_regs_t *dma) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); +#endif + + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, dma); +} + +void MXC_AES_EnableInt(uint32_t interrupt) +{ + MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); +} + +void MXC_AES_DisableInt(uint32_t interrupt) +{ + MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); +} + +int MXC_AES_IsBusy(void) +{ + return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t *)MXC_AES); +} + +int MXC_AES_Shutdown(void) +{ + int error = MXC_AES_RevB_Shutdown((mxc_aes_revb_regs_t *)MXC_AES); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES); + + return error; +} + +void MXC_AES_DMACallback(int ch, int error) +{ + MXC_AES_RevB_DMACallback(ch, error); +} + +void MXC_AES_GenerateKey(void) +{ + // Generating a random key is part of the TRNG block. + MXC_TRNG_RevB_GenerateKey((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +void MXC_AES_SetKeySize(mxc_aes_keys_t key) +{ + MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_keys_t)key); +} + +mxc_aes_keys_t MXC_AES_GetKeySize(void) +{ + return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_FlushInputFIFO(void) +{ + MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_FlushOutputFIFO(void) +{ + MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_Start(void) +{ + MXC_AES_RevB_Start((mxc_aes_revb_regs_t *)MXC_AES); +} + +uint32_t MXC_AES_GetFlags(void) +{ + return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_ClearFlags(uint32_t flags) +{ + MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t *)MXC_AES, flags); +} + +int MXC_AES_Generic(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_Encrypt(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_Decrypt(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) +{ + return MXC_AES_RevB_TXDMAConfig(src_addr, len, dma); +} + +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) +{ + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, dma); +} + +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) +{ + return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req, + enc); +} + +int MXC_AES_EncryptAsync(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_DecryptAsync(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len) +{ + MXC_AES_RevB_SetExtKey((mxc_aeskeys_revb_regs_t *)MXC_AESKEYS, key, len); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 6fb97bf3..f729102e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -33,6 +33,7 @@ /* **** Variable Declaration **** */ typedef struct { uint8_t enc; + mxc_dma_regs_t *dma; uint8_t channelRX; uint8_t channelTX; uint32_t remain; @@ -47,7 +48,10 @@ static mxc_aes_revb_dma_req_t dma_state; (((x) << 24) & 0xFF000000)) /* Prevent GCC from optimimzing this function to memcpy */ -static void __attribute__((optimize("no-tree-loop-distribute-patterns"))) +#if !(defined(__CC_ARM) || defined(__ARMCC_VERSION)) +__attribute__((optimize("no-tree-loop-distribute-patterns"))) +#endif +static void memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) { uint32_t *dstr = dst + (len / 4) - 1; @@ -59,7 +63,7 @@ memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) } } -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma) { aes->ctrl = 0x00; @@ -67,6 +71,8 @@ int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; + dma_state.dma = dma; + return E_NO_ERROR; } @@ -223,7 +229,7 @@ int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { uint8_t channel; mxc_dma_config_t config; @@ -237,9 +243,16 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_BAD_PARAM; } +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelTX = channel; config.reqsel = MXC_DMA_REQUEST_AESTX; @@ -266,7 +279,12 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -274,7 +292,7 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_NO_ERROR; } -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { if (dest_addr == NULL) { return E_NULL_PTR; @@ -288,9 +306,16 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelRX = channel; config.reqsel = MXC_DMA_REQUEST_AESRX; @@ -317,7 +342,12 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -356,7 +386,8 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != + E_NO_ERROR) { return E_BAD_PARAM; } @@ -382,7 +413,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) if (dma_state.remain < 4) { MXC_AES_Start(); } - MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); + MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain, dma_state.dma); } else if (dma_state.channelRX == ch) { if (dma_state.remain > 4) { dma_state.remain -= 4; @@ -391,7 +422,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) } MXC_DMA_ReleaseChannel(dma_state.channelRX); if (dma_state.remain > 0) { - MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); + MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma); } } } diff --git a/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.h index 3f00bda6..0c8b318a 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/MAX/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -26,6 +26,7 @@ #include "aes_revb_regs.h" #include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" +#include "dma.h" /** * @brief Enumeration type to select AES key @@ -60,7 +61,7 @@ typedef struct _mxc_aes_revb_cipher_req_t { mxc_aes_complete_t callback; ///< Callback function } mxc_aes_revb_req_t; -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes); +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma); void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes); @@ -76,8 +77,8 @@ void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags); int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc); int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); diff --git a/MAX/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd b/MAX/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd index e84348df..287bf658 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd +++ b/MAX/Libraries/PeriphDrivers/Source/AFE/afe_adc_zero_reva.svd @@ -702,7 +702,7 @@ REV_ID Description not included 0 - 3 + 6 read-only @@ -2811,4 +2811,4 @@ - + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd b/MAX/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd new file mode 100644 index 00000000..aa7e5c55 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/BOOST/boost_reva.svd @@ -0,0 +1,159 @@ + + + + + BOOST + Boost Controller + 0x40004C00 + + 0x00 + 0x400 + registers + + + BOOST + 46 + + + + DISABLE + Boost Disable Register. + 0x000 + 32 + + + DIS + This bit allows softwaree to disable the boost regulator for the VDD18 supply. + [0:0] + read-write + + + + + VREGCTRL + Boost Voltage Regulator Control Register. + 0x004 + + + SET + Sets the target voltage for the boost regulator output. + [4:0] + read-write + + + + + IPEAK + Low Side FET Peak Current Register. + 0x008 + read-only + + + SET + Sets the peak current threshold for the regulator. + [2:0] + read-only + + + + + MAXTON + Maximum Low Side FET Time-On Register. + 0x00C + read-only + + + THD + Sets a threshold for when time-on out toggles. + [3:0] + read-only + + + + + ILOAD + Boost Cycle Count Register. + 0x010 + read-only + + + CNT + Indicates the last load cycle count value. + [7:0] + read-only + + + + + ALERT + Boost Cycle Count Alert Register. + 0x014 + + + THD + Determines the threshold for when the boost alert interruptis fired. + [7:0] + read-write + + + + + RDY + Boost Output Ready Register. + 0x018 + read-only + + + OUT + Indicates ready out status for boost regulator. + [0:0] + read-only + + + + + ZXCAL + Zero Cross Calibration Register. + 0x01C + read-only + + + VAL + Read back of auto-calibration values. + [4:0] + read-only + + + + + INTEN + Boost Alert Interrupt Enable Register. + 0x020 + read-write + + + ALERT + Boost alert enable/ + [0:0] + read-write + + + + + INTFL + Boost Alert Interrupt Status Register. + 0x024 + read-write + + + ALERT + Boost alert has occurred. + [0:0] + read-write + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S b/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S deleted file mode 100644 index 328a4dde..00000000 --- a/MAX/Libraries/PeriphDrivers/Source/CORE1/startup_core1.S +++ /dev/null @@ -1,156 +0,0 @@ - .syntax unified - .arch armv7-m - - .section .stack_core1 - .align 3 - .globl Stack_Size_Core1 -#ifdef __STACK_SIZE_CORE1 - .equ Stack_Size_Core1, __STACK_SIZE -#else - .equ Stack_Size_Core1, 0x00001000 -#endif - .globl __StackTop_Core1 -__StackTop_Core1: - .size __StackTop_Core1, . - __StackTop_Core1 - - .section .text - .align 0x10 - .globl __isr_vector_core1 -__isr_vector_core1: - .long __StackTop_Core1 /* Top of Core 1 Stack */ - .long Reset_Handler_Core1 /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* Device-specific Interrupts */ - .long PF_IRQHandler /* 0x10 0x0040 16: Power Fail */ - .long WDT0_IRQHandler /* 0x11 0x0044 17: Watchdog 0 */ - .long USB_IRQHandler /* 0x12 0x0048 18: USB */ - .long RTC_IRQHandler /* 0x13 0x004C 19: RTC */ - .long TRNG_IRQHandler /* 0x14 0x0050 20: True Random Number Generator */ - .long TMR0_IRQHandler /* 0x15 0x0054 21: Timer 0 */ - .long TMR1_IRQHandler /* 0x16 0x0058 22: Timer 1 */ - .long TMR2_IRQHandler /* 0x17 0x005C 23: Timer 2 */ - .long TMR3_IRQHandler /* 0x18 0x0060 24: Timer 3*/ - .long TMR4_IRQHandler /* 0x19 0x0064 25: Timer 4*/ - .long TMR5_IRQHandler /* 0x1A 0x0068 26: Timer 5 */ - .long RSV11_IRQHandler /* 0x1B 0x006C 27: Reserved */ - .long RSV12_IRQHandler /* 0x1C 0x0070 28: Reserved */ - .long I2C0_IRQHandler /* 0x1D 0x0074 29: I2C0 */ - .long UART0_IRQHandler /* 0x1E 0x0078 30: UART 0 */ - .long UART1_IRQHandler /* 0x1F 0x007C 31: UART 1 */ - .long SPI1_IRQHandler /* 0x20 0x0080 32: SPI1 */ - .long SPI2_IRQHandler /* 0x21 0x0084 33: SPI2 */ - .long RSV18_IRQHandler /* 0x22 0x0088 34: Reserved */ - .long RSV19_IRQHandler /* 0x23 0x008C 35: Reserved */ - .long ADC_IRQHandler /* 0x24 0x0090 36: ADC */ - .long RSV21_IRQHandler /* 0x25 0x0094 37: Reserved */ - .long RSV22_IRQHandler /* 0x26 0x0098 38: Reserved */ - .long FLC0_IRQHandler /* 0x27 0x009C 39: Flash Controller */ - .long GPIO0_IRQHandler /* 0x28 0x00A0 40: GPIO0 */ - .long GPIO1_IRQHandler /* 0x29 0x00A4 41: GPIO2 */ - .long RSV26_IRQHandler /* 0x2A 0x00A8 42: GPIO3 */ - .long TPU_IRQHandler /* 0x2B 0x00AC 43: Crypto */ - .long DMA0_IRQHandler /* 0x2C 0x00B0 44: DMA0 */ - .long DMA1_IRQHandler /* 0x2D 0x00B4 45: DMA1 */ - .long DMA2_IRQHandler /* 0x2E 0x00B8 46: DMA2 */ - .long DMA3_IRQHandler /* 0x2F 0x00BC 47: DMA3 */ - .long RSV32_IRQHandler /* 0x30 0x00C0 48: Reserved */ - .long RSV33_IRQHandler /* 0x31 0x00C4 49: Reserved */ - .long UART2_IRQHandler /* 0x32 0x00C8 50: UART 2 */ - .long RSV35_IRQHandler /* 0x33 0x00CC 51: Reserved */ - .long I2C1_IRQHandler /* 0x34 0x00D0 52: I2C1 */ - .long RSV37_IRQHandler /* 0x35 0x00D4 53: Reserved */ - .long SPIXFC_IRQHandler /* 0x36 0x00D8 54: SPI execute in place */ - .long BTLE_TX_DONE_IRQHandler /* 0x37 0x00DC 55: BTLE TX Done */ - .long BTLE_RX_RCVD_IRQHandler /* 0x38 0x00E0 56: BTLE RX Recived */ - .long BTLE_RX_ENG_DET_IRQHandler /* 0x39 0x00E4 57: BTLE RX Energy Dectected */ - .long BTLE_SFD_DET_IRQHandler /* 0x3A 0x00E8 58: BTLE SFD Detected */ - .long BTLE_SFD_TO_IRQHandler /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ - .long BTLE_GP_EVENT_IRQHandler /* 0x3C 0x00F0 60: BTLE Timestamp*/ - .long BTLE_CFO_IRQHandler /* 0x3D 0x00F4 61: BTLE CFO Done */ - .long BTLE_SIG_DET_IRQHandler /* 0x3E 0x00F8 62: BTLE Signal Detected */ - .long BTLE_AGC_EVENT_IRQHandler /* 0x3F 0x00FC 63: BTLE AGC Event */ - .long BTLE_RFFE_SPIM_IRQHandler /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ - .long BTLE_TX_AES_IRQHandler /* 0x41 0x0104 65: BTLE TX AES Done */ - .long BTLE_RX_AES_IRQHandler /* 0x42 0x0108 66: BTLE RX AES Done */ - .long BTLE_INV_APB_ADDR_IRQHandler /* 0x43 0x010C 67: BTLE Invalid APB Address*/ - .long BTLE_IQ_DATA_VALID_IRQHandler /* 0x44 0x0110 68: BTLE IQ Data Valid */ - .long WUT_IRQHandler /* 0x45 0x0114 69: WUT Wakeup */ - .long GPIOWAKE_IRQHandler /* 0x46 0x0118 70: GPIO Wakeup */ - .long RSV55_IRQHandler /* 0x47 0x011C 71: Reserved */ - .long SPI0_IRQHandler /* 0x48 0x0120 72: SPI AHB */ - .long WDT1_IRQHandler /* 0x49 0x0124 73: Watchdog 1 */ - .long RSV58_IRQHandler /* 0x4A 0x0128 74: Reserved */ - .long PT_IRQHandler /* 0x4B 0x012C 75: Pulse train */ - .long SDMA0_IRQHandler /* 0x4C 0x0130 76: Smart DMA 0 */ - .long RSV61_IRQHandler /* 0x4D 0x0134 77: Reserved */ - .long I2C2_IRQHandler /* 0x4E 0x0138 78: I2C 2 */ - .long RSV63_IRQHandler /* 0x4F 0x013C 79: Reserved */ - .long RSV64_IRQHandler /* 0x50 0x0140 80: Reserved */ - .long RSV65_IRQHandler /* 0x51 0x0144 81: Reserved */ - .long SDHC_IRQHandler /* 0x52 0x0148 82: SDIO/SDHC */ - .long OWM_IRQHandler /* 0x53 0x014C 83: One Wire Master */ - .long DMA4_IRQHandler /* 0x54 0x0150 84: DMA4 */ - .long DMA5_IRQHandler /* 0x55 0x0154 85: DMA5 */ - .long DMA6_IRQHandler /* 0x56 0x0158 86: DMA6 */ - .long DMA7_IRQHandler /* 0x57 0x015C 87: DMA7 */ - .long DMA8_IRQHandler /* 0x58 0x0160 88: DMA8 */ - .long DMA9_IRQHandler /* 0x59 0x0164 89: DMA9 */ - .long DMA10_IRQHandler /* 0x5A 0x0168 90: DMA10 */ - .long DMA11_IRQHandler /* 0x5B 0x016C 91: DMA11 */ - .long DMA12_IRQHandler /* 0x5C 0x0170 92: DMA12 */ - .long DMA13_IRQHandler /* 0x5D 0x0174 93: DMA13 */ - .long DMA14_IRQHandler /* 0x5E 0x0178 94: DMA14 */ - .long DMA15_IRQHandler /* 0x5F 0x017C 95: DMA15 */ - .long USBDMA_IRQHandler /* 0x60 0x0180 96: USB DMA */ - .long WDT2_IRQHandler /* 0x61 0x0184 97: Watchdog Timer 2 */ - .long ECC_IRQHandler /* 0x62 0x0188 98: Error Correction */ - .long DVS_IRQHandler /* 0x63 0x018C 99: DVS Controller */ - .long SIMO_IRQHandler /* 0x64 0x0190 100: SIMO Controller */ - .long SCA_IRQHandler /* 0x65 0x0194 101: SCA */ - .long AUDIO_IRQHandler /* 0x66 0x0198 102: Audio subsystem */ - .long FLC1_IRQHandler /* 0x67 0x019C 103: Flash Control 1 */ - .long RSV88_IRQHandler /* 0x68 0x01A0 104: UART 3 */ - .long RSV89_IRQHandler /* 0x69 0x01A4 105: UART 4 */ - .long RSV90_IRQHandler /* 0x6A 0x01A8 106: UART 5 */ - .long RSV91_IRQHandler /* 0x6B 0x01AC 107: Camera IF */ - .long RSV92_IRQHandler /* 0x6C 0x01B0 108: I3C */ - .long HTMR0_IRQHandler /* 0x6D 0x01B4 109: HTimer */ - .long HTMR1_IRQHandler /* 0x6E 0x01B8 109: HTimer */ - .thumb - .thumb_func - .align 2 - .globl Core1_Init - .type Core1_Init, %function -Reset_Handler_Core1: - ldr r0, =__StackTop_Core1 - mov sp, r0 - /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ - ldr r0, =PreInit_Core1 - blx r0 - - /* Perform system initialization after RAM initialization */ - - ldr r0, =SystemInit_Core1 - blx r0 - - /* Transfer control to users main program */ - ldr r0, =Core1_Main - blx r0 - -.SPINC1: - /* spin if main ever returns. */ - bl .SPINC1 diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c index 8e09e2dc..e75000fe 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me15.c b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me15.c index 8e09e2dc..e75000fe 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me15.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me17.c b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me17.c index 8e09e2dc..e75000fe 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me17.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me30.c b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me30.c new file mode 100644 index 00000000..1d1bcf41 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_me30.c @@ -0,0 +1,100 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" + +#include "crc.h" +#include "crc_reva.h" +#include "dma.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +int MXC_CRC_Init(mxc_dma_regs_t *dma) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); +#endif + + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, dma); + + return E_NO_ERROR; +} + +int MXC_CRC_Shutdown(void) +{ + int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t *)MXC_CRC); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC); + + return error; +} + +void MXC_CRC_Handler(int ch, int error) +{ + MXC_CRC_RevA_Handler(ch, error); +} + +void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +mxc_crc_bitorder_t MXC_CRC_GetDirection(void) +{ + return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t *)MXC_CRC); +} + +void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +void MXC_CRC_SetPoly(uint32_t poly) +{ + MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t *)MXC_CRC, poly); +} + +uint32_t MXC_CRC_GetPoly(void) +{ + return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t *)MXC_CRC); +} + +uint32_t MXC_CRC_GetResult(void) +{ + return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t *)MXC_CRC); +} + +int MXC_CRC_Compute(mxc_crc_req_t *req) +{ + return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); +} + +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req) +{ + return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.c b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.c index 4cdb5e5e..a84b553a 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.c @@ -33,13 +33,16 @@ /***** Global Variables *****/ static mxc_crc_reva_req_t *CRCreq; +static mxc_dma_regs_t *CRCdma; /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc) +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma) { + CRCdma = dma; + crc->ctrl = 0x00; crc->val = 0xFFFFFFFF; return E_NO_ERROR; @@ -160,9 +163,15 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) CRCreq = req; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(CRCdma); + + channel = MXC_DMA_AcquireChannel(CRCdma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif config.reqsel = MXC_DMA_REQUEST_CRCTX; @@ -183,7 +192,13 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_CRC_Handler); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(CRCdma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.h b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.h index d4a06efe..8e2c46f9 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.h +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.h @@ -23,6 +23,7 @@ #include "crc.h" #include "crc_reva_regs.h" +#include "dma.h" /***** CRC Definitions *****/ /** @@ -41,7 +42,7 @@ typedef struct _mxc_crc_reva_req_t { */ typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t; -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma); int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc); int MXC_CRC_RevA_Handler(int ch, int error); void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); diff --git a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd index 0ac8fba3..f6c9dee7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd +++ b/MAX/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd @@ -69,9 +69,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -87,9 +85,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 diff --git a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_ai87.c b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_ai87.c index 449ff44f..0acb2722 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_ai87.c @@ -87,12 +87,12 @@ int MXC_CSI2_Stop(void) return MXC_CSI2_RevA_Stop((mxc_csi2_reva_regs_t *)MXC_CSI2); } -int MXC_CSI2_CaptureFrame(int num_data_lanes) +int MXC_CSI2_CaptureFrame(void) { - return MXC_CSI2_RevA_CaptureFrameDMA(num_data_lanes); + return MXC_CSI2_RevA_CaptureFrameDMA(); } -int MXC_CSI2_CaptureFrameDMA() +int MXC_CSI2_CaptureFrameDMA(void) { return MXC_CSI2_RevA_CaptureFrameDMA(); } diff --git a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.c b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.c index dd3512b8..d3813cbe 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.c @@ -103,7 +103,7 @@ void _free_line_buffer(void) } } -int _init_line_buffer() +int _init_line_buffer(void) { _free_line_buffer(); @@ -117,7 +117,7 @@ int _init_line_buffer() return E_NO_ERROR; } -void _swap_line_buffer() +void _swap_line_buffer(void) { uint8_t *temp = lb.active; lb.active = lb.inactive; @@ -274,7 +274,7 @@ int MXC_CSI2_RevA_Stop(mxc_csi2_reva_regs_t *csi2) return E_NO_ERROR; } -int MXC_CSI2_RevA_CaptureFrameDMA() +int MXC_CSI2_RevA_CaptureFrameDMA(void) { int i; int error; @@ -406,7 +406,7 @@ void MXC_CSI2_RevA_GetImageDetails(uint32_t *imgLen, uint32_t *w, uint32_t *h) *h = csi2_state.req->lines_per_frame; } -void MXC_CSI2_RevA_Handler() +void MXC_CSI2_RevA_Handler(void) { uint32_t ctrl_flags, vfifo_flags, ppi_flags; @@ -1043,12 +1043,12 @@ bool MXC_CSI2_RevA_DMA_Frame_Complete(void) return g_frame_complete; } -mxc_csi2_reva_capture_stats_t MXC_CSI2_RevA_DMA_GetCaptureStats() +mxc_csi2_reva_capture_stats_t MXC_CSI2_RevA_DMA_GetCaptureStats(void) { return csi2_state.capture_stats; } -void MXC_CSI2_RevA_DMA_Handler() +void MXC_CSI2_RevA_DMA_Handler(void) { // Clear CTZ Status Flag if (MXC_DMA->ch[csi2_state.dma_channel].status & MXC_F_DMA_STATUS_CTZ_IF) { diff --git a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.h b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.h index e28898fb..3a52369c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.h +++ b/MAX/Libraries/PeriphDrivers/Source/CSI2/csi2_reva.h @@ -66,7 +66,7 @@ int MXC_CSI2_RevA_Start(mxc_csi2_reva_regs_t *csi2, int num_data_lanes); int MXC_CSI2_RevA_Stop(mxc_csi2_reva_regs_t *csi2); -int MXC_CSI2_RevA_CaptureFrameDMA(); +int MXC_CSI2_RevA_CaptureFrameDMA(void); int MXC_CSI2_RevA_SetLaneCtrlSource(mxc_csi2_reva_regs_t *csi2, mxc_csi2_lane_src_t *src); @@ -76,7 +76,7 @@ void MXC_CSI2_RevA_GetImageDetails(uint32_t *imgLen, uint32_t *w, uint32_t *h); int MXC_CSI2_RevA_Callback(mxc_csi2_req_t *req, int retVal); -void MXC_CSI2_RevA_Handler(); +void MXC_CSI2_RevA_Handler(void); /********************************/ /* CSI2 RX Controller Functions */ @@ -159,7 +159,7 @@ int MXC_CSI2_RevA_PPI_Stop(void); /* CSI2 DMA - Used for all features */ /************************************/ -mxc_csi2_reva_capture_stats_t MXC_CSI2_RevA_DMA_GetCaptureStats(); +mxc_csi2_reva_capture_stats_t MXC_CSI2_RevA_DMA_GetCaptureStats(void); bool MXC_CSI2_RevA_DMA_Frame_Complete(void); @@ -171,6 +171,6 @@ int MXC_CSI2_RevA_DMA_GetCurrentLineCnt(void); int MXC_CSI2_RevA_DMA_GetCurrentFrameEndCnt(void); -void MXC_CSI2_RevA_DMA_Callback(); +void MXC_CSI2_RevA_DMA_Callback(mxc_dma_reva_regs_t *dma, int a, int b); #endif // LIBRARIES_PERIPHDRIVERS_SOURCE_CSI2_CSI2_REVA_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_me30.c new file mode 100644 index 00000000..df94a934 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -0,0 +1,169 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/****** Includes *******/ +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "dma_reva.h" + +/***** Definitions *****/ + +/******* Globals *******/ + +/****** Functions ******/ + +int MXC_DMA_Init(mxc_dma_regs_t *dma) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + if (dma == MXC_DMA0_NS && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); +#if CONFIG_TRUSTED_EXECUTION_SECURE + // DMA1 is only accessible from Secure world. + } else if (dma == MXC_DMA1_S && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + } +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); +} + +void MXC_DMA_DeInit(mxc_dma_regs_t *dma) +{ + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); +} + +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) +{ + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); +} + +int MXC_DMA_ReleaseChannel(int ch) +{ + return MXC_DMA_RevA_ReleaseChannel(ch); +} + +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_ConfigChannel(config, srcdst); +} + +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) +{ + return MXC_DMA_RevA_AdvConfigChannel(advConfig); +} + +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcDst(srcdst); +} + +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcDst(srcdst); +} + +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcReload(srcdst); +} + +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcReload(srcdst); +} + +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)) +{ + return MXC_DMA_RevA_SetCallback(ch, callback); +} + +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) +{ + return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); +} + +int MXC_DMA_ChannelEnableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelEnableInt(ch, flags); +} + +int MXC_DMA_ChannelDisableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelDisableInt(ch, flags); +} + +int MXC_DMA_ChannelGetFlags(int ch) +{ + return MXC_DMA_RevA_ChannelGetFlags(ch); +} + +int MXC_DMA_ChannelClearFlags(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelClearFlags(ch, flags); +} + +// TODO(DMA): Check ME14 becasue you can only get ME14 intrs from MXC_DMA0. +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) +{ + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); +} + +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch) +{ + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); +} + +int MXC_DMA_Start(int ch) +{ + return MXC_DMA_RevA_Start(ch); +} + +int MXC_DMA_Stop(int ch) +{ + return MXC_DMA_RevA_Stop(ch); +} + +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) +{ + return MXC_DMA_RevA_GetCHRegs(ch); +} + +void MXC_DMA_Handler(mxc_dma_regs_t *dma) +{ + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); +} + +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback) +{ + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); +} + +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback) +{ + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index 6b8ac9a8..05ba7bbb 100644 --- a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -470,7 +470,7 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len mxc_dma_srcdst_t transfer; int channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -500,7 +500,11 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; @@ -535,7 +539,7 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, { int retval, channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -553,7 +557,11 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd new file mode 100644 index 00000000..e2880fab --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd @@ -0,0 +1,650 @@ + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0_CH0 + 32 + + + DMA0_CH1 + 33 + + + DMA0_CH2 + 34 + + + DMA0_CH3 + 35 + + + + INTEN + DMA Control Register. + 0x000 + + + CH0 + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1 + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2 + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3 + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTFL + DMA Interrupt Register. + 0x004 + read-only + + + CH0 + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1 + 1 + 1 + + + CH2 + 2 + 1 + + + CH3 + 3 + 1 + + + + + 4 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CTRL + DMA Channel Control Register. + 0x000 + + + EN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQUEST + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPIRX + SPI RX + 0x01 + + + UARTRX + UART RX + 0x04 + + + I3CRX_CONT + I3C RX Controller + 0x07 + + + I3CRX_TARG + I3C RX Target + 0x08 + + + AESRX + AES RX + 0x10 + + + SPITX + SPI TX + 0x21 + + + UARTTX + UART TX + 0x24 + + + I3CTX_CONT + I3C TX + 0x27 + + + I3CTX_TARG + I3C TX + 0x28 + + + CRCTX + CRC TX + 0x2C + + + AESTX + AES TX + 0x30 + + + + + TO_WAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TO_PER + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + TO_CLKDIV + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BURST_SIZE + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + DIS_IE + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZ_IE + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STATUS + DMA Channel Status Register. + 0x004 + + + STATUS + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_IF + Count-to-Zero (CTZ) Interrupt Flag + 2 + 1 + oneToClear + + + RLD_IF + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_IF + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRCRLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + ADDR + Source Address Reload Value. + 0 + 31 + + + + + DSTRLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + ADDR + Destination Address Reload Value. + 0 + 31 + + + + + CNTRLD + DMA Channel Count Reload Register. + 0x01C + + + CNT + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + EN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.c b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.c deleted file mode 100644 index e91c3328..00000000 --- a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.c +++ /dev/null @@ -1,507 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -/****** Includes *******/ -#include -#include -#include "mxc_device.h" -#include "mxc_assert.h" -#include "mxc_lock.h" -#include "mxc_sys.h" -#include "dma.h" -#include "dma_revb.h" - -/***** Definitions *****/ -#define CHECK_HANDLE(x) ((x >= 0) && (x < MXC_DMA_CHANNELS) && (dma_resource[x].valid)) - -typedef struct { - void *userCallback; // user given callback - void *dest; // memcpy destination -} mxc_dma_highlevel_t; - -typedef struct { - unsigned int valid; // Flag to invalidate this resource - unsigned int instance; // Hardware instance of this DMA controller - unsigned int id; // Channel ID, which matches the index into the underlying hardware - mxc_dma_ch_regs_t *regs; // Pointer to the registers for this channel - void (*cb)(int, int); // Pointer to a callback function type -} mxc_dma_channel_t; - -/******* Globals *******/ -static unsigned int dma_initialized = 0; -static mxc_dma_channel_t dma_resource[MXC_DMA_CHANNELS]; -static mxc_dma_highlevel_t memcpy_resource[MXC_DMA_CHANNELS]; -static uint32_t dma_lock; - -/****** Functions ******/ -static void memcpy_callback(int ch, int error); -static void transfer_callback(int ch, int error); - -int MXC_DMA_RevB_Init(void) -{ - int i; - - if (dma_initialized) { - return E_BAD_STATE; - } - - //TODO(ADI): Necessary? - ///* Initialize any system-level DMA settings */ - //SYS_DMA_Init(); - - /* Initialize mutex */ - MXC_FreeLock(&dma_lock); - - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - /* Ensure all channels are disabled at start, clear flags, init handles */ - MXC_DMA->inten = 0; - - for (i = 0; i < MXC_DMA_CHANNELS; i++) { - dma_resource[i].valid = 0; - dma_resource[i].instance = 0; - dma_resource[i].id = i; - dma_resource[i].regs = (mxc_dma_ch_regs_t *)&MXC_DMA->ch[i]; - dma_resource[i].regs->ctrl = 0; - dma_resource[i].regs->status = dma_resource[i].regs->status; - - dma_resource[i].cb = NULL; - } - - dma_initialized++; - MXC_FreeLock(&dma_lock); - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_AcquireChannel(void) -{ - int i, channel; - - /* Check for initialization */ - if (!dma_initialized) { - return E_BAD_STATE; - } - - /* If DMA is locked return busy */ - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - /* Default is no channel available */ - channel = E_NONE_AVAIL; - - if (dma_initialized) { - for (i = 0; i < MXC_DMA_CHANNELS; i++) { - if (!dma_resource[i].valid) { - /* Found one */ - channel = i; - dma_resource[i].valid = 1; - dma_resource[i].regs->ctrl = 0; - dma_resource[i].regs->cntrld = - 0; /* Used by DMA_Start() to conditionally set RLDEN */ - break; - } - } - } - - MXC_FreeLock(&dma_lock); - - return channel; -} - -int MXC_DMA_RevB_ReleaseChannel(int ch) -{ - if (CHECK_HANDLE(ch)) { - if (MXC_GetLock(&dma_lock, 1) != E_NO_ERROR) { - return E_BUSY; - } - - dma_resource[ch].valid = 0; - dma_resource[ch].regs->ctrl = 0; - dma_resource[ch].regs->status = dma_resource[ch].regs->status; - MXC_FreeLock(&dma_lock); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(config.ch)) { - /* Designed to be safe, not speedy. Should not be called often */ - dma_resource[config.ch].regs->ctrl = - ((config.srcinc_en ? MXC_F_DMA_CTRL_SRCINC : 0) | - (config.dstinc_en ? MXC_F_DMA_CTRL_DSTINC : 0) | config.reqsel | - (config.srcwd << MXC_F_DMA_CTRL_SRCWD_POS) | - (config.dstwd << MXC_F_DMA_CTRL_DSTWD_POS)); - } else { - return E_BAD_PARAM; - } - - return MXC_DMA_RevB_SetSrcDst(srcdst); -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig) -{ - if (CHECK_HANDLE(advConfig.ch) && (advConfig.burst_size > 0)) { - dma_resource[advConfig.ch].regs->ctrl &= ~(0x1F00FC0C); // Clear all fields we set here - /* Designed to be safe, not speedy. Should not be called often */ - dma_resource[advConfig.ch].regs->ctrl |= - ((advConfig.reqwait_en ? MXC_F_DMA_CTRL_TO_WAIT : 0) | advConfig.prio | - advConfig.tosel | advConfig.pssel | - (((advConfig.burst_size - 1) << MXC_F_DMA_CTRL_BURST_SIZE_POS) & - MXC_F_DMA_CTRL_BURST_SIZE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetSrcDst(mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->src = (unsigned int)srcdst.source; - dma_resource[srcdst.ch].regs->dst = (unsigned int)srcdst.dest; - dma_resource[srcdst.ch].regs->cnt = srcdst.len; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetSrcDst(mxc_dma_srcdst_t *srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - srcdst->source = (void *)dma_resource[srcdst->ch].regs->src; - srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dst; - srcdst->len = (dma_resource[srcdst->ch].regs->cnt) & ~MXC_F_DMA_CNTRLD_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetSrcReload(mxc_dma_srcdst_t srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - dma_resource[srcdst.ch].regs->srcrld = (unsigned int)srcdst.source; - dma_resource[srcdst.ch].regs->dstrld = (unsigned int)srcdst.dest; - - if (dma_resource[srcdst.ch].regs->ctrl & MXC_F_DMA_CTRL_EN) { - /* If channel is already running, set RLDEN to enable next reload */ - dma_resource[srcdst.ch].regs->cntrld = MXC_F_DMA_CNTRLD_EN | srcdst.len; - } else { - /* Otherwise, this is the initial setup, so DMA_Start() will handle setting that bit */ - dma_resource[srcdst.ch].regs->cntrld = srcdst.len; - } - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetSrcReload(mxc_dma_srcdst_t *srcdst) -{ - if (CHECK_HANDLE(srcdst.ch)) { - srcdst->source = (void *)dma_resource[srcdst->ch].regs->srcrld; - srcdst->dest = (void *)dma_resource[srcdst->ch].regs->dstrld; - srcdst->len = (dma_resource[srcdst->ch].regs->cntrld) & ~MXC_F_DMA_CNTRLD_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_SetCallback(int ch, void (*callback)(int, int)) -{ - if (CHECK_HANDLE(ch)) { - /* Callback for interrupt handler, no checking is done, as NULL is valid for (none) */ - dma_resource[ch].cb = callback; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_SetChannelInterruptEn(int ch, int chdis, int ctz) -{ - return E_NOT_SUPPORTED; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_GetChannelInterruptEn(int ch) -{ - return E_NOT_SUPPORTED; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelEnableInt(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl |= (flags & (MXC_F_DMA_CTRL_DIS_IE | MXC_F_DMA_CTRL_CTZ_IE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelDisableInt(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~(flags & (MXC_F_DMA_CTRL_DIS_IE | MXC_F_DMA_CTRL_CTZ_IE)); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_EnableInt(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA->inten |= (1 << ch); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_DisableInt(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA->inten &= ~(1 << ch); - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelGetFlags(int ch) -{ - if (CHECK_HANDLE(ch)) { - return dma_resource[ch].regs->status; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_ChannelClearFlags(int ch, int flags) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->status |= (flags & 0x5F); // Mask for Interrupt flags - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_Start(int ch) -{ - if (CHECK_HANDLE(ch)) { - MXC_DMA_ChannelClearFlags(ch, MXC_DMA_RevB_ChannelGetFlags(ch)); - - if (dma_resource[ch].regs->cntrld) { - dma_resource[ch].regs->ctrl |= (MXC_F_DMA_CTRL_EN | MXC_F_DMA_CTRL_RLDEN); - } else { - dma_resource[ch].regs->ctrl |= MXC_F_DMA_CTRL_EN; - } - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -int MXC_DMA_RevB_Stop(int ch) -{ - if (CHECK_HANDLE(ch)) { - dma_resource[ch].regs->ctrl &= ~MXC_F_DMA_CTRL_EN; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -mxc_dma_ch_regs_t *MXC_DMA_RevB_GetCHRegs(int ch) -{ - if (CHECK_HANDLE(ch)) { - return dma_resource[ch].regs; - } else { - return NULL; - } -} - -void MXC_DMA_RevB_Handler() -{ - /* Do callback, if enabled */ - for (int i = 0; i < MXC_DMA_CHANNELS; i++) { - if (CHECK_HANDLE(i)) { - if (MXC_DMA->intfl & (0x1 << i)) { - if (dma_resource[i].cb != NULL) { - dma_resource[i].cb(i, E_NO_ERROR); - } - - MXC_DMA_ChannelClearFlags(i, MXC_DMA_RevB_ChannelGetFlags(i)); - break; - } - } - } -} - -void memcpy_callback(int ch, int error) -{ - mxc_dma_complete_cb_t callback; - callback = (mxc_dma_complete_cb_t)memcpy_resource[ch].userCallback; - - if (error != E_NO_ERROR) { - callback(NULL); - } - - callback(memcpy_resource[ch].dest); - - callback = NULL; - MXC_DMA_ReleaseChannel(ch); -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) -{ - int retval; - mxc_dma_config_t config; - mxc_dma_srcdst_t transfer; - int channel = MXC_DMA_AcquireChannel(); - - if (memcpy_resource[channel].userCallback != NULL) { - // We acquired a channel we haven't cleared yet - MXC_DMA_ReleaseChannel(channel); - return E_UNKNOWN; - } - - transfer.ch = channel; - transfer.source = src; - transfer.dest = dest; - transfer.len = len; - - config.ch = channel; - config.reqsel = MXC_DMA_REQUEST_MEMTOMEM; - config.srcwd = MXC_DMA_WIDTH_WORD; - config.dstwd = MXC_DMA_WIDTH_WORD; - config.srcinc_en = 1; - config.dstinc_en = 1; - - retval = MXC_DMA_ConfigChannel(config, transfer); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_EnableInt(channel); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_CTRL_CTZ_IE); - - if (retval != E_NO_ERROR) { - return retval; - } - - MXC_DMA_SetCallback(channel, memcpy_callback); - - memcpy_resource[channel].userCallback = (void *)callback; - memcpy_resource[channel].dest = dest; - - return MXC_DMA_Start(channel); -} - -//TODO(ADI): Necessary? -void transfer_callback(int ch, int error) -{ - // Unimplemented - // Check for reason - // Call user callback for next transfer - // determine whether to load into the transfer slot or reload slot - // continue on or stop - while (1) {} -} - -//TODO(ADI): Necessary? -int MXC_DMA_RevB_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, - mxc_dma_trans_chain_t callback) -{ - int retval; - int channel = MXC_DMA_AcquireChannel(); - - if (memcpy_resource[channel].userCallback != NULL) { - // We acquired a channel we haven't cleared yet - MXC_DMA_ReleaseChannel(channel); - return E_UNKNOWN; - } - - retval = MXC_DMA_ConfigChannel(config, firstSrcDst); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_EnableInt(channel); - - if (retval != E_NO_ERROR) { - return retval; - } - - retval = MXC_DMA_ChannelEnableInt(channel, MXC_F_DMA_CTRL_CTZ_IE); - - if (retval != E_NO_ERROR) { - return retval; - } - - MXC_DMA_SetCallback(channel, transfer_callback); - - memcpy_resource[channel].userCallback = (void *)callback; - - return MXC_DMA_Start(channel); -} diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.h b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.h deleted file mode 100644 index dd81bc12..00000000 --- a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_revb.h +++ /dev/null @@ -1,55 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ -#define LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ - -/****** Includes *******/ - -/***** Definitions *****/ - -/******* Globals *******/ - -/****** Functions ******/ -int MXC_DMA_RevB_Init(void); -int MXC_DMA_RevB_AcquireChannel(void); -int MXC_DMA_RevB_ReleaseChannel(int ch); -int MXC_DMA_RevB_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_AdvConfigChannel(mxc_dma_adv_config_t advConfig); -int MXC_DMA_RevB_SetSrcDst(mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_GetSrcDst(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevB_SetSrcReload(mxc_dma_srcdst_t srcdst); -int MXC_DMA_RevB_GetSrcReload(mxc_dma_srcdst_t *srcdst); -int MXC_DMA_RevB_SetCallback(int ch, void (*callback)(int, int)); -int MXC_DMA_RevB_ChannelEnableInt(int ch, int flags); -int MXC_DMA_RevB_ChannelDisableInt(int ch, int flags); -int MXC_DMA_RevB_ChannelGetFlags(int ch); -int MXC_DMA_RevB_ChannelClearFlags(int ch, int flags); -int MXC_DMA_RevB_EnableInt(int ch); -int MXC_DMA_RevB_DisableInt(int ch); -int MXC_DMA_RevB_Start(int ch); -int MXC_DMA_RevB_Stop(int ch); -mxc_dma_ch_regs_t *MXC_DMA_RevB_GetCHRegs(int ch); -void MXC_DMA_RevB_Handler(); -int MXC_DMA_RevB_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); -int MXC_DMA_RevB_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, - mxc_dma_trans_chain_t callback); - -#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_DMA_DMA_REVB_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me16.c b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me16.c new file mode 100644 index 00000000..54d9aee1 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me16.c @@ -0,0 +1,335 @@ +/** + * @file flc_ME16.c + * @brief Flash Controler driver. + * @details This driver can be used to operate on the embedded flash memory. + */ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_reva.h" +#include "flc_common.h" +#include "ecc_regs.h" // For ECCEN registers. +#include "mcr_regs.h" // For ECCEN registers. + +//****************************************************************************** +void MXC_FLC_ME16_Flash_Operation(void) +{ + /* Flush all instruction caches */ + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; + + /* Wait for flush to complete */ + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {} +} + +//****************************************************************************** +int MXC_FLC_ME16_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) +{ + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *flc = MXC_FLC0; + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *flc = MXC_FLC0; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_ME16_GetPhysicalAddress(uint32_t addr, uint32_t *result) +{ + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *result = addr - MXC_FLASH_MEM_BASE; + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + /* For ME16, the info block base was located at the next power of 2 address beyond the main flash. + The ME16 ends at 0x5FFFF, so the info block starts at 0x80000. */ + *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + 0x80000; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_Init(void) +{ + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_Busy(void) +{ + return MXC_FLC_RevA_Busy(); +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_PageErase(uint32_t address) +{ + int err; + uint32_t addr; + mxc_flc_regs_t *flc = NULL; + + // Get FLC Instance + if ((err = MXC_FLC_ME16_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME16_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); + // Flush the cache + MXC_FLC_ME16_Flash_Operation(); + + return err; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_Write128(uint32_t address, uint32_t *data) +{ + int err; + mxc_flc_regs_t *flc = NULL; + uint32_t addr; + + // Address checked if it is 128-bit aligned + if (address & 0xF) { + return E_BAD_PARAM; + } + + // Get FLC Instance + if ((err = MXC_FLC_ME16_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME16_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data)) != E_NO_ERROR) { + return err; + } + + // Flush the cache + MXC_FLC_ME16_Flash_Operation(); + + if ((err = MXC_FLC_Com_VerifyData(address, 4, data)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_Write32(uint32_t address, uint32_t data) +{ + uint32_t addr, aligned; + int err; + mxc_flc_regs_t *flc = NULL; + + // Address checked if it is byte addressable + if (address & 0x3) { + return E_BAD_PARAM; + } + + // Align address to 128-bit word + aligned = address & 0xfffffff0; + + // Get FLC Instance + if ((err = MXC_FLC_ME16_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME16_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { + return err; + } + + if (MXC_ECC->en & MXC_F_ECC_EN_FLASH) { + return E_BAD_STATE; + } + + return MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr); +} + +//****************************************************************************** +int MXC_FLC_MassErase(void) +{ + int err, i; + mxc_flc_regs_t *flc; + + for (i = 0; i < MXC_FLC_INSTANCES; i++) { + flc = MXC_FLC_GET_FLC(i); + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc); + + if (err != E_NO_ERROR) { + return err; + } + + MXC_FLC_ME16_Flash_Operation(); + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_UnlockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if ((err = MXC_FLC_ME16_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address); +} + +//****************************************************************************** +int MXC_FLC_LockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if ((err = MXC_FLC_ME16_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address); +} + +//****************************************************************************** +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer) +{ + return MXC_FLC_Com_Write(address, length, buffer); +} + +//****************************************************************************** +void MXC_FLC_Read(int address, void *buffer, int len) +{ + MXC_FLC_Com_Read(address, buffer, len); +} + +//****************************************************************************** +int MXC_FLC_EnableInt(uint32_t flags) +{ + return MXC_FLC_RevA_EnableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_DisableInt(uint32_t flags) +{ + return MXC_FLC_RevA_DisableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_GetFlags(void) +{ + return MXC_FLC_RevA_GetFlags(); +} + +//****************************************************************************** +int MXC_FLC_ClearFlags(uint32_t flags) +{ + return MXC_FLC_RevA_ClearFlags(flags); +} + +//****************************************************************************** +int MXC_FLC_BlockPageWrite(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +int MXC_FLC_BlockPageRead(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> + 5; // Divide by 32 to get WELR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC0->welr0); + case 1: + return &(MXC_FLC0->welr1); + } + + return NULL; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC0->rlr0); + case 1: + return &(MXC_FLC0->rlr1); + } + + return NULL; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me30.c new file mode 100644 index 00000000..eaacb6b8 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_me30.c @@ -0,0 +1,263 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_reva.h" +#include "flc_common.h" +#include "mcr_regs.h" // For ECCEN registers. + +//****************************************************************************** +void MXC_FLC_ME30_Flash_Operation(void) +{ + /* + This function should be called after modifying the contents of flash memory. + It flushes the instruction caches and line fill buffer. + + It should be called _afterwards_ because after flash is modified the cache + may contain instructions that may no longer be valid. _Before_ the + flash modifications the ICC may contain relevant cached instructions related to + the incoming flash instructions (especially relevant in the case of external memory), + and these instructions will be valid up until the point that the modifications are made. + + The line fill buffer is a FLC-related buffer that also may no longer be valid. + It's flushed by reading 2 pages of flash. + */ + + /* Flush all instruction caches */ + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC_FLUSH; + + /* Wait for flush to complete */ + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC_FLUSH) {} + + // Clear the line fill buffer by reading 2 pages from flash + volatile uint32_t *line_addr; + volatile uint32_t __unused line; // __unused attribute removes warning + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); + line = *line_addr; + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); + line = *line_addr; +} + +//****************************************************************************** +int MXC_FLC_ME30_GetPhysicalAddress(uint32_t addr, uint32_t *result) +{ + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *result = addr & (MXC_FLASH_MEM_SIZE - 1); +#if CONFIG_TRUSTED_EXECUTION_SECURE + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE; +#endif + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_Init(void) +{ + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_Busy(void) +{ + return MXC_FLC_RevA_Busy(); +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_PageErase(uint32_t address) +{ + int err; + uint32_t addr; + + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)MXC_FLC, addr); + + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); + + return err; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_Write128(uint32_t address, uint32_t *data) +{ + int err; + uint32_t addr; + + // Address checked if it is 128-bit aligned + if (address & 0xF) { + return E_BAD_PARAM; + } + + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)MXC_FLC, addr, data); + + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); + + return err; +} + +//****************************************************************************** +int MXC_FLC_Write32(uint32_t address, uint32_t data) +{ + uint32_t addr, aligned; + int err; + + // Address checked if it is byte addressable + if (address & 0x3) { + return E_BAD_PARAM; + } + + // Align address to 128-bit word + aligned = address & 0xfffffff0; + + if ((err = MXC_FLC_ME30_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)MXC_FLC, address, data, addr); + + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); + + return err; +} + +//****************************************************************************** +int MXC_FLC_MassErase(void) +{ + int err; + + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)MXC_FLC); + + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); + + return err; +} + +//****************************************************************************** +__weak int MXC_FLC_UnlockInfoBlock(uint32_t address) +{ + return E_NOT_SUPPORTED; +} + +//****************************************************************************** +int MXC_FLC_LockInfoBlock(uint32_t address) +{ + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address); +} + +//****************************************************************************** +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer) +{ + return MXC_FLC_Com_Write(address, length, buffer); +} + +//****************************************************************************** +void MXC_FLC_Read(int address, void *buffer, int len) +{ + MXC_FLC_Com_Read(address, buffer, len); +} + +//****************************************************************************** +int MXC_FLC_EnableInt(uint32_t flags) +{ + return MXC_FLC_RevA_EnableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_DisableInt(uint32_t flags) +{ + return MXC_FLC_RevA_DisableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_GetFlags(void) +{ + return MXC_FLC_RevA_GetFlags(); +} + +//****************************************************************************** +int MXC_FLC_ClearFlags(uint32_t flags) +{ + return MXC_FLC_RevA_ClearFlags(flags); +} + +//****************************************************************************** +int MXC_FLC_BlockPageWrite(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +int MXC_FLC_BlockPageRead(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) +{ + return NULL; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) +{ + return NULL; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/FLC/flc_reva.c b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_reva.c index e8252128..8302a80a 100644 --- a/MAX/Libraries/PeriphDrivers/Source/FLC/flc_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_reva.c @@ -31,6 +31,8 @@ #include "flc_reva.h" #include "flc.h" +// TODO(CM33): Check for secure vs non-secure accesses here. + /** * @ingroup flc * @{ @@ -405,10 +407,13 @@ int MXC_FLC_RevA_ClearFlags(uint32_t mask) //****************************************************************************** int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { +#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || \ + (TARGET_NUM != 32657) if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } +#endif /* Make sure the info block is locked */ flc->actrl = 0x1234; @@ -424,10 +429,13 @@ int MXC_FLC_RevA_UnlockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) //****************************************************************************** int MXC_FLC_RevA_LockInfoBlock(mxc_flc_reva_regs_t *flc, uint32_t address) { +#if defined(CONFIG_TRUSTED_EXECUTION_SECURE) || (CONFIG_TRUSTED_EXECUTION_SECURE != 0) || \ + (TARGET_NUM != 32657) if ((address < MXC_INFO_MEM_BASE) || (address >= (MXC_INFO_MEM_BASE + (MXC_INFO_MEM_SIZE * 2)))) { return E_BAD_PARAM; } +#endif flc->actrl = 0xDEADBEEF; return E_NO_ERROR; diff --git a/MAX/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd new file mode 100644 index 00000000..78ff2ae0 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd @@ -0,0 +1,270 @@ + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + FLC + + FLC Interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE_IF + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF_IF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONE_IE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AF_IE + 9 + 1 + + + + + ECCDATA + ECC Data Register. + 0x2C + + + EVEN + Error Correction Code Odd Data. + 0 + 9 + + + ODD + Error Correction Code Even Data. + 16 + 9 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c index a6c5c31a..665aeab5 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -170,28 +175,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -413,3 +420,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c index a6c5c31a..665aeab5 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -170,28 +175,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -413,3 +420,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c index fad63225..e5717e2a 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c @@ -29,6 +29,7 @@ static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *); static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; static uint8_t initialized = 0; +static mxc_gpio_config_lock_t cfg_lock = MXC_GPIO_CONFIG_UNLOCKED; /* **** Functions **** */ int MXC_GPIO_Common_Init(uint32_t portmask) @@ -94,3 +95,13 @@ void MXC_GPIO_Common_Handler(unsigned int port) stat >>= 1; } } + +void MXC_GPIO_Common_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + cfg_lock = locked; +} + +mxc_gpio_config_lock_t MXC_GPIO_Common_GetConfigLock(void) +{ + return cfg_lock; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h index ac5cdd5e..ecef4865 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h @@ -35,6 +35,8 @@ int MXC_GPIO_Common_Init(uint32_t portmask); void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); void MXC_GPIO_Common_Handler(unsigned int port); +void MXC_GPIO_Common_SetConfigLock(mxc_gpio_config_lock_t locked); +mxc_gpio_config_lock_t MXC_GPIO_Common_GetConfigLock(void); /**@} end of group gpio */ diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c index f741c1b6..34ef4e74 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c @@ -74,6 +74,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -94,28 +99,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->pdpu_sel1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->pdpu_sel0 |= cfg->mask; gpio->pdpu_sel1 &= ~cfg->mask; - gpio->pssel &= ~cfg->mask; + gpio->pssel |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->pdpu_sel0 |= cfg->mask; gpio->pdpu_sel1 &= ~cfg->mask; - gpio->pssel |= cfg->mask; + gpio->pssel &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->pdpu_sel0 &= ~cfg->mask; gpio->pdpu_sel1 |= cfg->mask; - gpio->pssel &= ~cfg->mask; + gpio->pssel |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->pdpu_sel0 &= ~cfg->mask; gpio->pdpu_sel1 |= cfg->mask; - gpio->pssel |= cfg->mask; + gpio->pssel &= ~cfg->mask; break; default: @@ -219,3 +226,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c index 83c5bf20..46740343 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c @@ -101,6 +101,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int err; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel err = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (err != E_NO_ERROR) { @@ -259,3 +264,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c index 91fb1548..b6ed678b 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c @@ -62,6 +62,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -223,3 +228,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c index 16704782..abee1ac3 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c @@ -69,6 +69,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -217,3 +222,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c index b3f30928..66271b87 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c @@ -98,6 +98,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -118,28 +123,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->pad_cfg2 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->pad_cfg1 |= cfg->mask; gpio->pad_cfg2 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->pad_cfg1 |= cfg->mask; gpio->pad_cfg2 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->pad_cfg1 &= ~cfg->mask; gpio->pad_cfg2 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->pad_cfg1 &= ~cfg->mask; gpio->pad_cfg2 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -243,3 +250,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c index 7803d5f7..38e489f1 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c @@ -78,6 +78,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -98,35 +103,42 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->pad_cfg2 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->pad_cfg1 |= cfg->mask; gpio->pad_cfg2 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->pad_cfg1 |= cfg->mask; gpio->pad_cfg2 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->pad_cfg1 &= ~cfg->mask; gpio->pad_cfg2 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->pad_cfg1 &= ~cfg->mask; gpio->pad_cfg2 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: return E_BAD_PARAM; } - return E_NO_ERROR; + // Configure the drive strength + if (cfg->func == MXC_GPIO_FUNC_IN) { + return E_NO_ERROR; + } else { + return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask); + } } /* ************************************************************************** */ @@ -236,3 +248,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c index 8d49fc89..09962f49 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c @@ -73,6 +73,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); @@ -197,3 +202,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c index 73e45fc1..3a31217e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c @@ -75,6 +75,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -198,3 +203,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c index a6c5c31a..665aeab5 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -170,28 +175,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -413,3 +420,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c index a7576e73..9fc43f77 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c @@ -138,6 +138,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) // Initialize callback function pointers MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel if (port < 4) { error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); @@ -189,28 +194,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -443,3 +450,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c index fc5ddec7..b50bd341 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c @@ -81,6 +81,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); if (cfg->port == MXC_GPIO3) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + if (cfg->mask & MXC_GPIO_PIN_0) { switch (cfg->func) { case MXC_GPIO_FUNC_IN: @@ -142,6 +147,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); } + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -162,28 +172,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; + gpio->ps |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; + gpio->ps &= ~cfg->mask; break; default: @@ -368,3 +380,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c index afb9ef1f..01ce3065 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c @@ -76,6 +76,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -199,3 +204,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c new file mode 100644 index 00000000..335e2a3d --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -0,0 +1,242 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "gpio.h" +#include "gpio_reva.h" +#include "gpio_common.h" +#include "mxc_sys.h" +#include "mcr_regs.h" +#include "pwrseq_regs.h" + +/* **** Definitions **** */ +// Pin 3.0 Definitions +#define P30_DATA_OUT(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_DO : 0) +#define P30_OUT_EN(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_OE : 0) +#define P30_PULL_DIS(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_PE : 0) +#define P30_DATA_IN(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_IN : 0) +#define PDOWN_OUT_EN(pin_mask) \ + ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_OUTEN_PDOWN_OUT_EN : 0) + +// Pin 3.1 Definitions +#define P31_DATA_OUT(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_DO : 0) +#define P31_OUT_EN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_OE : 0) +#define P31_PULL_DIS(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_PE : 0) +#define P31_DATA_IN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_IN : 0) +#define SQWAVE_OUT_EN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_OUTEN_SQWOUT_EN : 0) + +/* **** Globals **** */ + +/* **** Functions **** */ +int MXC_GPIO_Init(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + return MXC_GPIO_Common_Init(portmask); +} + +int MXC_GPIO_Shutdown(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Reset(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) +{ + int port, error; + mxc_gpio_regs_t *gpio = cfg->port; + + port = MXC_GPIO_GET_IDX(cfg->port); + + MXC_GPIO_Init(1 << port); + + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + + // Configure alternate function + error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); + if (error != E_NO_ERROR) { + return error; + } + + // Configure the pad + switch (cfg->pad) { + case MXC_GPIO_PAD_NONE: + gpio->padctrl &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_UP: + gpio->padctrl |= cfg->mask; + gpio->pssel |= cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_DOWN: + gpio->padctrl |= cfg->mask; + gpio->pssel &= ~cfg->mask; + break; + + default: + return E_BAD_PARAM; + } + + // Configure the drive strength + if (cfg->func == MXC_GPIO_FUNC_IN) { + return E_NO_ERROR; + } else { + return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask); + } +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) +{ + MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) +{ + return MXC_GPIO_RevA_IntConfig(cfg, pol); +} + +/* ************************************************************************** */ +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata) +{ + MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata); +} + +/* ************************************************************************** */ +void MXC_GPIO_Handler(unsigned int port) +{ + MXC_GPIO_Common_Handler(port); +} + +/* ************************************************************************** */ +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) +{ + MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) +{ + return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); +} + +/* ************************************************************************** */ +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) +{ + return E_NOT_SUPPORTED; +} + +/* ************************************************************************** */ +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port) +{ + return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port); +} + +/* ************************************************************************** */ +int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask) +{ + return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c index 00911926..ea673348 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c @@ -76,6 +76,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -96,28 +101,30 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) gpio->padctrl1 &= ~cfg->mask; break; + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way case MXC_GPIO_PAD_WEAK_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->pssel &= ~cfg->mask; + gpio->pssel |= cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - gpio->pssel |= cfg->mask; + gpio->pssel &= ~cfg->mask; break; case MXC_GPIO_PAD_WEAK_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->pssel &= ~cfg->mask; + gpio->pssel |= cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - gpio->pssel |= cfg->mask; + gpio->pssel &= ~cfg->mask; break; default: @@ -221,3 +228,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c index 8455802b..aeb33c59 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c @@ -121,6 +121,11 @@ uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port) int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: @@ -140,6 +145,11 @@ int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, u int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + //This is required for new devices going forward. port->inen |= mask; @@ -226,6 +236,11 @@ uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port) int MXC_GPIO_RevA_SetDriveStrength(mxc_gpio_reva_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the drive strength. switch (drvstr) { case MXC_GPIO_DRVSTR_0: diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd new file mode 100644 index 00000000..a9a08a0a --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd @@ -0,0 +1,682 @@ + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ALTERNATE + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PADCTRL + GPIO Pad Control. Each bit in this register configures the pad for the associated GPIO pin in this port. + 0x60 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + FAST + Fast Slew Rate selected. + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + + + + + + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PSSEL + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c index 7064344a..541f5715 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c @@ -27,10 +27,17 @@ #include "gpio_common.h" /* **** Functions **** */ +// NOTE(JC): This function doesn't actually seem to be used anywhere. The MEXX parts re-implement this... +// TODO(JC): Consolidate to actually use this (would help with code repetition) but psMask seems dubious int MXC_GPIO_RevB_Config(const mxc_gpio_cfg_t *cfg, uint8_t psMask) { mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Set the GPIO type switch (cfg->func) { case MXC_GPIO_FUNC_IN: @@ -70,29 +77,25 @@ int MXC_GPIO_RevB_Config(const mxc_gpio_cfg_t *cfg, uint8_t psMask) } // Configure the pad + // Note: for "ps" field set 1 for weak and 0 for strong. + // As of 8-28-2024 most UG tables have this flipped the wrong way switch (cfg->pad) { case MXC_GPIO_PAD_NONE: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 &= ~cfg->mask; - if (psMask == MXC_GPIO_PS_PULL_SELECT) { - gpio->ps &= ~cfg->mask; - } + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_PULL_UP: gpio->padctrl0 |= cfg->mask; gpio->padctrl1 &= ~cfg->mask; - if (psMask == MXC_GPIO_PS_PULL_SELECT) { - gpio->ps |= cfg->mask; - } + gpio->ps &= ~cfg->mask; break; case MXC_GPIO_PAD_PULL_DOWN: gpio->padctrl0 &= ~cfg->mask; gpio->padctrl1 |= cfg->mask; - if (psMask == MXC_GPIO_PS_PULL_SELECT) { - gpio->ps &= ~cfg->mask; - } + gpio->ps |= cfg->mask; break; default: @@ -198,6 +201,11 @@ uint32_t MXC_GPIO_RevB_GetFlags(mxc_gpio_regs_t *port) int MXC_GPIO_RevB_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: diff --git a/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c index 315372c7..b038559e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me18.c @@ -54,18 +54,29 @@ int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) * * See MAX32690 Rev A2 Errata #16: * https://www.analog.com/media/en/technical-documentation/data-sheets/max32690_a2_errata_rev2.pdf + * + * Additionally, note that the TQFN package does not expose some of the duplicate pins. For this package, + * enabling the un-routed GPIOs has been shown to cause initialization issues with the I2C block. + * To work around this, "MAX32690GTK_PACKAGE_TQFN" can be defined by the build system. The recommend place + * to do it is in the "board.mk" file of the BSP. This will prevent the inaccessible pins from being configured. */ if (i2c == MXC_I2C0) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); MXC_GPIO_Config(&gpio_cfg_i2c0); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c0a); +#endif } else if (i2c == MXC_I2C1) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); MXC_GPIO_Config(&gpio_cfg_i2c1); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c1a); +#endif } else if (i2c == MXC_I2C2) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); +#ifndef MAX32690GTK_PACKAGE_TQFN MXC_GPIO_Config(&gpio_cfg_i2c2); +#endif MXC_GPIO_Config(&gpio_cfg_i2c2c); } else { return E_NO_DEVICE; diff --git a/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c new file mode 100644 index 00000000..dacc6e77 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c @@ -0,0 +1,413 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "i2c_regs.h" +#include "dma_regs.h" +#include "i2c.h" +#include "i2c_reva.h" + +/* **** Variable Declaration **** */ +uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR; + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_I2C_Shutdown(i2c); // Clear everything out + + if (i2c == MXC_I2C0) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_GPIO_Config(&gpio_cfg_i2c0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); + MXC_GPIO_Config(&gpio_cfg_i2c1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); + MXC_GPIO_Config(&gpio_cfg_i2c2); + } else { + return E_NO_DEVICE; + } +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); +} + +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) +{ + if (idx != 0) { + // MAX32655 only supports one slave device + return E_NOT_SUPPORTED; + } + + return MXC_I2C_RevA_SetSlaveAddr((mxc_i2c_reva_regs_t *)i2c, slaveAddr, idx); +} + +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) +{ + // Configure GPIO for I2C + if (i2c == MXC_I2C0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2); + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); + } else { + return E_NO_DEVICE; + } + + return MXC_I2C_RevA_Shutdown((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c) +{ + // Configure GPIO for I2C + if (i2c == MXC_I2C0) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); + } else { + return E_NO_DEVICE; + } + + return E_NO_ERROR; +} + +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) +{ + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); +} + +int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) +{ + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); +} + +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_Init(mxc_i2c_regs_t *i2c, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx) +{ + return MXC_I2C_RevA_DMA_Init((mxc_i2c_reva_regs_t *)i2c, (mxc_dma_reva_regs_t *)dma, use_dma_tx, + use_dma_rx); +} + +int MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_DMA_GetTXChannel((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_DMA_GetRXChannel((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t *i2c, uint8_t *txData, uint8_t *rxData) +{ + int i2cNum; + int txReqSel = -1; + int rxReqSel = -1; + + if (i2c == NULL) { + return E_NULL_PTR; + } + + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + + if (txData != NULL) { + switch (i2cNum) { + case 0: + txReqSel = MXC_DMA_REQUEST_I2C0TX; + break; + + case 1: + txReqSel = MXC_DMA_REQUEST_I2C1TX; + break; + + case 2: + txReqSel = MXC_DMA_REQUEST_I2C2TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if (rxData != NULL) { + switch (i2cNum) { + case 0: + rxReqSel = MXC_DMA_REQUEST_I2C0RX; + break; + + case 1: + rxReqSel = MXC_DMA_REQUEST_I2C1RX; + break; + + case 2: + rxReqSel = MXC_DMA_REQUEST_I2C2RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_I2C_RevA_DMA_SetRequestSelect((mxc_i2c_reva_regs_t *)i2c, + (mxc_dma_reva_regs_t *)MXC_DMA, txReqSel, rxReqSel); +} + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) +{ + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); +} + +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) +{ + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); +} + +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck) +{ + return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte, + (mxc_i2c_reva_getAck_t)getAck); +} + +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) +{ + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) +{ + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); +} + +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) +{ + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) +{ + // The callback parameter was previously unused but keeping it for backwards-compatibility. + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA); +} + +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) +{ + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) +{ + // The callback parameter was previously unused but keeping it for backwards-compatibility. + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA); +} + +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) +{ + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) +{ + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); +} + +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) +{ + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); +} + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); +} + +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); +} + +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); +} + +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); +} + +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); +} + +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); +} + +int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); +} + +int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); +} + +void MXC_I2C_DMACallback(int ch, int error) +{ + MXC_I2C_RevA_DMACallback(ch, error); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h new file mode 100644 index 00000000..6bc3ba13 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_ccc.h @@ -0,0 +1,88 @@ +/** +* @file i3c_ccc.h +* @brief Improved Inter Integrated Circuit (I3C) Common Command Codes (CCC). +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_ + +/* Broadcast CCCs */ +#define MXC_I3C_CCC_B_ENEC 0x00 /* Enable Events Command */ +#define MXC_I3C_CCC_B_DISEC 0x01 /* Disable Events Command */ +#define MXC_I3C_CCC_B_ENTAS0 0x02 /* Enter Activity State 0 */ +#define MXC_I3C_CCC_B_ENTAS1 0x03 /* Enter Activity State 1 */ +#define MXC_I3C_CCC_B_ENTAS2 0x04 /* Enter Activity State 2 */ +#define MXC_I3C_CCC_B_ENTAS3 0x05 /* Enter Activity State 3 */ +#define MXC_I3C_CCC_B_RSTDAA 0x06 /* Reset Dynamic Address Assignment */ +#define MXC_I3C_CCC_B_ENTDAA 0x07 /* Enter Dynamic Address Assignment */ +#define MXC_I3C_CCC_B_DEFTGTS 0x08 /* Define List of Targets */ +#define MXC_I3C_CCC_B_SETMWL 0x09 /* Set Max Write Length */ +#define MXC_I3C_CCC_B_SETMRL 0x0A /* Set Max Read Length */ +#define MXC_I3C_CCC_B_ENTTM 0x0B /* Enter Test Mode */ +#define MXC_I3C_CCC_B_SETBUSCON 0x0C /* Set Bus Context */ +#define MXC_I3C_CCC_B_ENDXFR 0x12 /* Data Transfer Ending Procedure Control */ +#define MXC_I3C_CCC_B_ENTHDR0 0x20 /* Enter HDR Mode 0 */ +#define MXC_I3C_CCC_B_ENTHDR1 0x21 /* Enter HDR Mode 1 */ +#define MXC_I3C_CCC_B_ENTHDR2 0x22 /* Enter HDR Mode 2 */ +#define MXC_I3C_CCC_B_ENTHDR3 0x23 /* Enter HDR Mode 3 */ +#define MXC_I3C_CCC_B_ENTHDR4 0x24 /* Enter HDR Mode 4 */ +#define MXC_I3C_CCC_B_ENTHDR5 0x25 /* Enter HDR Mode 5 */ +#define MXC_I3C_CCC_B_ENTHDR6 0x26 /* Enter HDR Mode 6 */ +#define MXC_I3C_CCC_B_ENTHDR7 0x27 /* Enter HDR Mode 7 */ +#define MXC_I3C_CCC_B_SETXTIME 0x28 /* Exchange Timing Information */ +#define MXC_I3C_CCC_B_SETAASA 0x29 /* Set Dynamic Address as Static Address */ +#define MXC_I3C_CCC_B_RSTACT 0x2A /* Target Reset Action */ +#define MXC_I3C_CCC_B_DEFGRPA 0x2B /* Define List of Group Addresses */ +#define MXC_I3C_CCC_B_RSTGRPA 0x2C /* Reset Group Address */ +#define MXC_I3C_CCC_B_MLANE 0x2D /* Multi-Land Data Transfer Control */ + +/* Direct CCCs */ +#define MXC_I3C_CCC_D_ENEC 0x80 /* Enable Events Command */ +#define MXC_I3C_CCC_D_DISEC 0x81 /* Disable Events Command */ +#define MXC_I3C_CCC_D_ENTAS0 0x82 /* Enter Activity State 0 */ +#define MXC_I3C_CCC_D_ENTAS1 0x83 /* Enter Activity State 1 */ +#define MXC_I3C_CCC_D_ENTAS2 0x84 /* Enter Activity State 2 */ +#define MXC_I3C_CCC_D_ENTAS3 0x85 /* Enter Activity State 3 */ +#define MXC_I3C_CCC_D_RSTDAA 0x86 /* Reset Dynamic Address Assignment NACKed */ +#define MXC_I3C_CCC_D_SETDASA 0x87 /* Set Dynamic Address from Static Address */ +#define MXC_I3C_CCC_D_SETNEWDA 0x88 /* Set New Dynamic Address */ +#define MXC_I3C_CCC_D_SETMWL 0x89 /* Set Max Write Length */ +#define MXC_I3C_CCC_D_SETMRL 0x8A /* Set Max Read Length */ +#define MXC_I3C_CCC_D_GETMWL 0x8B /* Get Max Write Length */ +#define MXC_I3C_CCC_D_GETMRL 0x8C /* Get Max Read Length */ +#define MXC_I3C_CCC_D_GETPID 0x8D /* Get Provisioned ID */ +#define MXC_I3C_CCC_D_GETBCR 0x8E /* Get Bus Characteristics Register */ +#define MXC_I3C_CCC_D_GETDCR 0x8F /* Get Device Characteristics Register */ +#define MXC_I3C_CCC_D_GETSTATUS 0x90 /* Get Device Status */ +#define MXC_I3C_CCC_D_GETACCCR 0x91 /* Get Accept Controller Role */ +#define MXC_I3C_CCC_D_ENDXFR 0x92 /* Data Transfer Ending Procedure Control */ +#define MXC_I3C_CCC_D_SETBRGTGT 0x93 /* Set Bridge Targets */ +#define MXC_I3C_CCC_D_GETMXDS 0x94 /* Get Max Data Speed */ +#define MXC_I3C_CCC_D_GETCAPS 0x95 /* Get Optional Feature Capabilities */ +#define MXC_I3C_CCC_D_D2DXFER 0x97 /* Device to Device(s) Tunneling Control */ +#define MXC_I3C_CCC_D_SETXTIME 0x98 /* Set Exchange Timing Information */ +#define MXC_I3C_CCC_D_GETXTIME 0x99 /* Get Exchange Timing Information */ +#define MXC_I3C_CCC_D_RSTACT 0x9A /* Target Reset Action */ +#define MXC_I3C_CCC_D_SETGRPA 0x9B /* Set Group Address */ +#define MXC_I3C_CCC_D_RSTGRPA 0x9C /* Reset Group Address */ +#define MXC_I3C_CCC_D_MLANE 0x9D /* Multi-Lane Data Transfer Control */ + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_CCC_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c new file mode 100644 index 00000000..7a0a9dfc --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_me30.c @@ -0,0 +1,281 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "i3c.h" +#include "i3c_reva.h" +#include "i3c_ccc.h" + +/* **** Definitions **** */ + +/* **** Functions **** */ +int MXC_I3C_Init(mxc_i3c_regs_t *i3c, mxc_i3c_config_t *config) +{ + int ret; + +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I3C); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I3C); + MXC_GPIO_Config(&gpio_cfg_i3c); +#endif + + if (!config->target_mode) { + /* Controller mode initialization */ + /* 1. SCL frequency and duty cycle */ + ret = MXC_I3C_SetPPFrequency(i3c, config->pp_hz); + if (ret < 0) { + return ret; + } + + ret = MXC_I3C_SetODFrequency(i3c, config->od_hz, false); + if (ret < 0) { + return ret; + } + + ret = MXC_I3C_SetI2CFrequency(i3c, config->i2c_hz); + if (ret < 0) { + return ret; + } + } + + return MXC_I3C_RevA_Init((mxc_i3c_reva_regs_t *)i3c, config->target_mode, config->static_addr); +} + +int MXC_I3C_Recover(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Recover((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_Shutdown(mxc_i3c_regs_t *i3c) +{ + int ret; + + ret = MXC_I3C_RevA_Shutdown((mxc_i3c_reva_regs_t *)i3c); + if (ret < 0) { + return ret; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I3C); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I3C); +#endif + + return E_SUCCESS; +} + +int MXC_I3C_SetPPFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency) +{ + return MXC_I3C_RevA_SetPPFrequency((mxc_i3c_reva_regs_t *)i3c, frequency); +} + +unsigned int MXC_I3C_GetPPFrequency(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_GetPPFrequency((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_SetODFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency, bool highPP) +{ + return MXC_I3C_RevA_SetODFrequency((mxc_i3c_reva_regs_t *)i3c, frequency, highPP); +} + +unsigned int MXC_I3C_GetODFrequency(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_GetODFrequency((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_SetI2CFrequency(mxc_i3c_regs_t *i3c, unsigned int frequency) +{ + return MXC_I3C_RevA_SetI2CFrequency((mxc_i3c_reva_regs_t *)i3c, frequency); +} + +unsigned int MXC_I3C_GetI2CFrequency(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_GetI2CFrequency((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_SetSkew(mxc_i3c_regs_t *i3c, uint8_t skew) +{ + return MXC_I3C_RevA_SetSkew((mxc_i3c_reva_regs_t *)i3c, skew); +} + +int MXC_I3C_SetHighKeeperMode(mxc_i3c_regs_t *i3c, mxc_i3c_high_keeper_t hkeep) +{ + return MXC_I3C_RevA_SetHighKeeperMode((mxc_i3c_reva_regs_t *)i3c, hkeep); +} + +int MXC_I3C_EmitStart(mxc_i3c_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType, + uint8_t addr, uint8_t readCount) +{ + return MXC_I3C_RevA_EmitStart((mxc_i3c_reva_regs_t *)i3c, isI2C, xferType, addr, readCount); +} + +int MXC_I3C_ResetTarget(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_ResetTarget((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_EmitStop(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_EmitStop((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_EmitI2CStop(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_EmitI2CStop((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_Controller_CCC(mxc_i3c_regs_t *i3c, const mxc_i3c_ccc_req_t *req) +{ + return MXC_I3C_RevA_Controller_CCC((mxc_i3c_reva_regs_t *)i3c, (mxc_i3c_reva_ccc_req_t *)req); +} + +int MXC_I3C_Controller_Transaction(mxc_i3c_regs_t *i3c, const mxc_i3c_req_t *req) +{ + return MXC_I3C_RevA_Controller_Transaction((mxc_i3c_reva_regs_t *)i3c, + (mxc_i3c_reva_req_t *)req); +} + +int MXC_I3C_Controller_DAA(mxc_i3c_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr, + uint8_t *dcr) +{ + return MXC_I3C_RevA_Controller_DAA((mxc_i3c_reva_regs_t *)i3c, addr, pid, bcr, dcr); +} + +int MXC_I3C_HotJoin(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_HotJoin((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_RequestIBI(mxc_i3c_regs_t *i3c, unsigned char mdb, mxc_i3c_ibi_getbyte_t getByteCb) +{ + return MXC_I3C_RevA_RequestIBI((mxc_i3c_reva_regs_t *)i3c, mdb, + (mxc_i3c_reva_ibi_getbyte_t)getByteCb); +} + +int MXC_I3C_Standby(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Standby((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_Wakeup(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Wakeup((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_ReadRXFIFO(mxc_i3c_regs_t *i3c, volatile unsigned char *bytes, unsigned int len, + int timeout) +{ + return MXC_I3C_RevA_ReadRXFIFO((mxc_i3c_reva_regs_t *)i3c, bytes, len, timeout); +} + +int MXC_I3C_WriteTXFIFO(mxc_i3c_regs_t *i3c, const unsigned char *bytes, unsigned int len, bool end, + int timeout) +{ + return MXC_I3C_RevA_WriteTXFIFO((mxc_i3c_reva_regs_t *)i3c, bytes, len, end, timeout); +} + +int MXC_I3C_Controller_GetError(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Controller_GetError((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_Controller_ClearError(mxc_i3c_regs_t *i3c) +{ + MXC_I3C_RevA_Controller_ClearError((mxc_i3c_reva_regs_t *)i3c); +} + +int MXC_I3C_SetRXTXThreshold(mxc_i3c_regs_t *i3c, mxc_i3c_rx_threshold_t rxth, + mxc_i3c_tx_threshold_t txth) +{ + return MXC_I3C_RevA_SetRXTXThreshold((mxc_i3c_reva_regs_t *)i3c, + (mxc_i3c_reva_rx_threshold_t)rxth, + (mxc_i3c_reva_tx_threshold_t)txth); +} + +uint8_t MXC_I3C_GetDynamicAddress(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_GetDynamicAddress((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_IRQHandler(mxc_i3c_regs_t *i3c) +{ + MXC_I3C_RevA_IRQHandler((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_ClearRXFIFO(mxc_i3c_regs_t *i3c) +{ + MXC_I3C_RevA_ClearRXFIFO((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_ClearTXFIFO(mxc_i3c_regs_t *i3c) +{ + MXC_I3C_RevA_ClearTXFIFO((mxc_i3c_reva_regs_t *)i3c); +} + +unsigned int MXC_I3C_Controller_GetRXCount(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Controller_GetRXCount((mxc_i3c_reva_regs_t *)i3c); +} + +unsigned int MXC_I3C_Controller_GetTXCount(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Controller_GetTXCount((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_Controller_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Controller_EnableInt((mxc_i3c_reva_regs_t *)i3c, mask); +} + +void MXC_I3C_Controller_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Controller_DisableInt((mxc_i3c_reva_regs_t *)i3c, mask); +} + +unsigned int MXC_I3C_Controller_GetFlags(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Controller_GetFlags((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_Controller_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Controller_ClearFlags((mxc_i3c_reva_regs_t *)i3c, mask); +} + +void MXC_I3C_Target_EnableInt(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Target_EnableInt((mxc_i3c_reva_regs_t *)i3c, mask); +} + +void MXC_I3C_Target_DisableInt(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Target_DisableInt((mxc_i3c_reva_regs_t *)i3c, mask); +} + +int MXC_I3C_Target_GetFlags(mxc_i3c_regs_t *i3c) +{ + return MXC_I3C_RevA_Target_GetFlags((mxc_i3c_reva_regs_t *)i3c); +} + +void MXC_I3C_Target_ClearFlags(mxc_i3c_regs_t *i3c, uint32_t mask) +{ + MXC_I3C_RevA_Target_ClearFlags((mxc_i3c_reva_regs_t *)i3c, mask); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c new file mode 100644 index 00000000..0c453044 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.c @@ -0,0 +1,927 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_errors.h" +#include "mxc_sys.h" +#include "i3c_regs.h" +#include "i3c.h" +#include "i3c_reva.h" +#include "i3c_ccc.h" + +/* **** Definitions **** */ +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(x)[0]) +#endif + +#define MXC_I3C_REVA_MAX_FIFO_TRANSACTION 255U + +#define GET_FIELD(reg, field) ((i3c->reg & MXC_F_I3C_REVA_##field) >> MXC_F_I3C_REVA_##field##_POS) +#define SET_FIELD(reg, field, value) \ + do { \ + i3c->reg &= ~MXC_F_I3C_REVA_##field; \ + i3c->reg |= value << MXC_F_I3C_##field##_POS; \ + } while (0); + +#define MXC_F_I3C_REVA_CONT_ERRWARN_MASK \ + (MXC_F_I3C_REVA_CONT_ERRWARN_NACK | MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT | \ + MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM | MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR | \ + MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC | MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR | \ + MXC_F_I3C_REVA_CONT_ERRWARN_MSG | MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ | \ + MXC_F_I3C_REVA_CONT_ERRWARN_TO) + +#define MXC_F_I3C_REVA_CONT_STATUS_MASK \ + (MXC_F_I3C_REVA_CONT_STATUS_IBI_WON | MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS | \ + MXC_F_I3C_REVA_CONT_STATUS_DONE | MXC_F_I3C_REVA_CONT_STATUS_NACK | \ + MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE | MXC_F_I3C_REVA_CONT_STATUS_TARG_START) + +/* MCTRL_TYPE values if request is EmitStartAddr */ +typedef enum { + MXC_I3C_REVA_START_TYPE_SDR = 0, + MXC_I3C_REVA_START_TYPE_I2C = 1 +} mxc_i3c_reva_start_type_t; + +/* MCTRL_IBIRESP values if request is EmitStartAddr and AutoIBI */ +#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_ACK 0x00U +#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_NACK 0x01U +#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_ACK_WITH_MB 0x02U +#define MXC_I3C_REVA_CONT_CTRL1_IBIRESP_MANUAL 0x03U + +/* Provisioned ID length */ +#define MXC_I3C_PROVISIONED_ID_LEN 6U + +/* Broadcast address */ +#define MXC_I3C_BROADCAST_ADDR 0x7EU + +typedef struct { + mxc_i3c_reva_regs_t *regs; ///< Pointer to regs of this I3C instance. + mxc_i3c_reva_ibi_getbyte_t ibiGetByteCB; ///< IBI additional data callback. +} mxc_i3c_reva_controller_t; + +typedef enum { + MXC_I3C_REVA_IBIRESP_ACK = 0, + MXC_I3C_REVA_IBIRESP_NACK = 1, + MXC_I3C_REVA_IBIRESP_ACK_WITH_MB = 2, + MXC_I3C_REVA_IBIRESP_MANUAL = 3 +} mxc_i3c_reva_ibiresp_t; + +#define MXC_I3C_REVA_ADDR_INVALID 0x00U + +/* **** Globals **** */ +/** + * @brief I3C controller instances. + * + */ +mxc_i3c_reva_controller_t controller[MXC_CFG_I3C_INSTANCES]; + +/* **** Functions **** */ +int MXC_I3C_RevA_Init(mxc_i3c_reva_regs_t *i3c, bool targetMode, uint8_t staticAddr) +{ + int ret = E_NO_ERROR; + int idx; + uint8_t val; + + idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c); + if (idx < 0) { + return E_BAD_PARAM; + } + + if (!targetMode) { + /* Controller mode initialization */ + + /* SCL-to-SDA skew */ + ret = MXC_I3C_RevA_SetSkew(i3c, 0); + if (ret < 0) { + return ret; + } + + /* High-Keeper implementation selection */ + ret = MXC_I3C_RevA_SetHighKeeperMode(i3c, MXC_I3C_HIGH_KEEPER_OFF); + if (ret < 0) { + return ret; + } + + /* 2. If using fifos, set tx rx fifo trigger levels */ + if (i3c->targ_cap1 & MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG) { + MXC_I3C_RevA_SetRXTXThreshold(i3c, MXC_I3C_REVA_RX_TH_NOT_EMPTY, + MXC_I3C_REVA_TX_TH_ALMOST_FULL); + } + + /* 3. Optionally write IBIRULES reg to optimize response to incoming IBIs */ + + /* 4. Enable controller mode */ + SET_FIELD(cont_ctrl0, CONT_CTRL0_EN, MXC_V_I3C_REVA_CONT_CTRL0_EN_ON); + } else { + /* Target mode initialization */ + /* 1. After reset, write setup registers needed for optional features */ + + if (i3c->targ_cap1 & MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG) { + MXC_I3C_RevA_SetRXTXThreshold(i3c, MXC_I3C_REVA_RX_TH_NOT_EMPTY, + MXC_I3C_REVA_TX_TH_ALMOST_FULL); + } + + /* Set BCR, DCR */ + val = 0 << 6; /* Device role: target */ + if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_CCCH_LIMITS) { + val |= 1 << 0; /* Max data speed limitation */ + } + if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_CCCH_BASIC) { + val |= 1 << 5; /* Supports advanced capabiliries */ + } + if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI) { + val |= 1 << 1; /* Supports IBI generation */ + } + if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD) { + val |= 1 << 2; /* MDB and additional data bytes may follow the IBI */ + } + val |= 1 << 3; /* Offline capable */ + SET_FIELD(targ_idext, TARG_IDEXT_BUSCHAR, val); + + /* Set DCR to generic device */ + SET_FIELD(targ_idext, TARG_IDEXT_DEVCHAR, 0); + + /* Enable CCC handling */ + MXC_I3C_RevA_Target_EnableInt(i3c, MXC_F_I3C_REVA_TARG_INTEN_CCC); + + /* 2. Write 1 to CONFIG.TGTENA */ + SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 1); + + /* Clear STOP bit */ + SET_FIELD(targ_status, TARG_STATUS_STOP, 0); + } + + controller[idx].regs = i3c; + + return E_NO_ERROR; +} + +static inline uint8_t MXC_I3C_RevA_Controller_GetState(mxc_i3c_reva_regs_t *i3c) +{ + return (uint8_t)GET_FIELD(cont_status, CONT_STATUS_STATE); +} + +static inline int MXC_I3C_RevA_Controller_WaitForDone(mxc_i3c_reva_regs_t *i3c, int timeout) +{ + while (!(i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_DONE)) { + if (timeout == 0) { + return E_TIME_OUT; + } + if (timeout > 0) { + timeout--; + } + } + + return E_SUCCESS; +} + +static inline int MXC_I3C_RevA_Controller_WaitForReqDone(mxc_i3c_reva_regs_t *i3c, int timeout) +{ + while (!(i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE)) { + if (timeout == 0) { + return E_TIME_OUT; + } + if (timeout > 0) { + timeout--; + } + } + + return E_SUCCESS; +} + +static inline int MXC_I3C_RevA_Controller_WaitForIdle(mxc_i3c_reva_regs_t *i3c, int timeout) +{ + while ((i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_STATE) != + MXC_S_I3C_REVA_CONT_STATUS_STATE_IDLE) { + if (timeout == 0) { + return E_TIME_OUT; + } + if (timeout > 0) { + timeout--; + } + } + + return E_SUCCESS; +} + +int MXC_I3C_RevA_Recover(mxc_i3c_reva_regs_t *i3c) +{ + int retries = 3; + + while (retries && + MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM) { + MXC_I3C_RevA_EmitStop(i3c); + retries--; + } + + while (GET_FIELD(cont_status, CONT_STATUS_TARG_START)) { + SET_FIELD(cont_status, CONT_STATUS_TARG_START, 1); + MXC_I3C_RevA_AutoIBI(i3c); + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + MXC_I3C_RevA_ClearRXFIFO(i3c); + } + + retries = 1000; + while (retries && + MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE) { + retries--; + } + + if (retries == 0) { + return E_TIME_OUT; + } + + return 0; +} + +int MXC_I3C_RevA_Shutdown(mxc_i3c_reva_regs_t *i3c) +{ + int idx; + + idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c); + if (idx < 0) { + return E_BAD_PARAM; + } + + if (GET_FIELD(cont_ctrl0, CONT_CTRL0_EN)) { + SET_FIELD(cont_ctrl0, CONT_CTRL0_EN, MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF); + MXC_I3C_RevA_Controller_DisableInt(i3c, i3c->cont_inten); + MXC_I3C_RevA_Controller_ClearFlags(i3c, i3c->cont_intfl); + } else if (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN)) { + SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0); + MXC_I3C_RevA_Target_DisableInt(i3c, i3c->targ_inten); + MXC_I3C_RevA_Target_ClearFlags(i3c, i3c->targ_intfl); + } + + MXC_I3C_RevA_ClearRXFIFO(i3c); + MXC_I3C_RevA_ClearTXFIFO(i3c); + controller[idx].ibiGetByteCB = NULL; + + return E_SUCCESS; +} + +int MXC_I3C_RevA_SetPPFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency) +{ + uint32_t ticks, highPeriod, lowPeriod; + + ticks = PeripheralClock / frequency; + /* Frequency must be less than or equal to half of peripheral clock */ + if (ticks < 2 || ticks > 32) { + return E_BAD_PARAM; + } + + highPeriod = ticks / 2; + lowPeriod = ticks / 2; + if (ticks % 2) { + lowPeriod++; + } + + i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD; + i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD; + i3c->cont_ctrl0 |= (highPeriod - 1) << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS; + i3c->cont_ctrl0 |= (lowPeriod - highPeriod) << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS; + + return (int)MXC_I3C_RevA_GetPPFrequency(i3c); +} + +unsigned int MXC_I3C_RevA_GetPPFrequency(mxc_i3c_reva_regs_t *i3c) +{ + uint8_t highPeriod, lowPeriod; + + highPeriod = 1 + ((i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS); + lowPeriod = highPeriod + ((i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS); + + return PeripheralClock / (highPeriod + lowPeriod); +} + +int MXC_I3C_RevA_SetODFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency, bool highPP) +{ + uint32_t lowPeriod; + uint8_t ppBaud; + + /* + * Minimum low period = 200ns + * Minimum high period = 200ns for first broadcast address + * Maximum high period = 41ns + */ + if ((!highPP && frequency > 2500000U) || frequency > 5000000U) { + return E_BAD_PARAM; + } + + ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS; + lowPeriod = PeripheralClock / frequency; + if (highPP) { + lowPeriod = (lowPeriod / (ppBaud + 1)) - 2; + } else { + lowPeriod = (lowPeriod / (2 * (ppBaud + 1))) - 1; + } + + i3c->cont_ctrl0 &= ~(MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD | MXC_F_I3C_REVA_CONT_CTRL0_OD_HP); + i3c->cont_ctrl0 |= lowPeriod << MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS; + i3c->cont_ctrl0 |= (highPP ? 1 : 0) << MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS; + + return (int)MXC_I3C_RevA_GetODFrequency(i3c); +} + +unsigned int MXC_I3C_RevA_GetODFrequency(mxc_i3c_reva_regs_t *i3c) +{ + uint8_t highPeriod, lowPeriod, odBaud, ppBaud; + + ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS; + odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS; + lowPeriod = (odBaud + 1) * (ppBaud + 1); + if (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_HP) { + highPeriod = ppBaud + 1; + } else { + highPeriod = lowPeriod; + } + + return PeripheralClock / (highPeriod + lowPeriod); +} + +int MXC_I3C_RevA_SetI2CFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency) +{ + uint8_t odBaud, ppBaud; + uint32_t lowPeriod; + + ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS; + odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS; + + lowPeriod = PeripheralClock / frequency; + lowPeriod /= (odBaud + 1) * (ppBaud + 1); + lowPeriod = (lowPeriod >> 1) - 1; + lowPeriod = lowPeriod << 1; + + if (lowPeriod > 0xF) { + lowPeriod = 0xF; + } + i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD; + i3c->cont_ctrl0 |= lowPeriod << MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS; + + return (int)MXC_I3C_RevA_GetI2CFrequency(i3c); +} + +unsigned int MXC_I3C_RevA_GetI2CFrequency(mxc_i3c_reva_regs_t *i3c) +{ + uint8_t i2cBaud, odBaud, ppBaud; + uint32_t lowPeriod, highPeriod; + + i2cBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS; + ppBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS; + odBaud = (i3c->cont_ctrl0 & MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD) >> + MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS; + + lowPeriod = (odBaud + 1) * (ppBaud + 1) * ((i2cBaud >> 1) + 1); + highPeriod = lowPeriod; + if ((i2cBaud % 2) != 0) { + highPeriod++; + } + + return PeripheralClock / (lowPeriod + highPeriod); +} + +uint8_t MXC_I3C_RevA_GetDynamicAddress(mxc_i3c_reva_regs_t *i3c) +{ + if (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN) && GET_FIELD(targ_dynaddr, TARG_DYNADDR_VALID)) { + return GET_FIELD(targ_dynaddr, TARG_DYNADDR_ADDR); + } + + return MXC_I3C_ADDR_INVALID; +} + +int MXC_I3C_RevA_SetSkew(mxc_i3c_reva_regs_t *i3c, uint8_t skew) +{ + unsigned int ppFreq; + + if (skew > 7) { + return E_BAD_PARAM; + } + + if (skew > 0) { + ppFreq = MXC_I3C_RevA_GetPPFrequency(i3c); + if ((PeripheralClock / ppFreq) < 4) { + return E_BAD_STATE; + } + } + + i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW; + i3c->cont_ctrl0 |= (uint32_t)skew << MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS; + + return E_SUCCESS; +} + +int MXC_I3C_RevA_SetHighKeeperMode(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_high_keeper_t hkeep) +{ + if (hkeep > MXC_I3C_REVA_HIGH_KEEPER_EXT_SCL_SDA) { + return E_BAD_PARAM; + } + + i3c->cont_ctrl0 &= ~MXC_F_I3C_REVA_CONT_CTRL0_HKEEP; + i3c->cont_ctrl0 |= hkeep; + + return E_SUCCESS; +} + +/** + * @brief Request an I3C or I2C bus operation. + * + * @param i3c Pointer to I3C registers. + * @param request Request type. e.g. MXC_V_I3C_REVA_CONT_CTRL1_REQUEST_EMIT_START_ADDR. + * @param type Request type if EmitStartAddr is requested. For other requests, pass 0. + * @param xferType 1 if this is a read request, 0 if write. + * @param addr Target address. This is usually 7'h7E for I3C broadcast messages, + * target's static address for I2C messages and target's dynamic + * address for I3C SDR messages. + * @param readCount Maximum bytes allowed to be read from the target. Set to 0 if you wish + * to allow the read until the target stops sending. + */ +static void MXC_I3C_RevA_Controller_Request(mxc_i3c_reva_regs_t *i3c, uint8_t request, + mxc_i3c_reva_start_type_t type, + mxc_i3c_transfer_type_t xferType, uint8_t addr, + uint8_t readCount) +{ + uint32_t cont1; + + cont1 = (request << MXC_F_I3C_CONT_CTRL1_REQ_POS) | (addr << MXC_F_I3C_CONT_CTRL1_ADDR_POS) | + (type << MXC_F_I3C_CONT_CTRL1_TYPE_POS) | + (MXC_I3C_REVA_CONT_CTRL1_IBIRESP_NACK << MXC_F_I3C_CONT_CTRL1_IBIRESP_POS); + if (xferType == MXC_I3C_TRANSFER_TYPE_READ) { + cont1 |= 1U << MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS; + cont1 |= readCount << MXC_F_I3C_CONT_CTRL1_TERM_RD_POS; + } + + i3c->cont_ctrl1 = cont1; +} + +int MXC_I3C_RevA_EmitStart(mxc_i3c_reva_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType, + uint8_t addr, uint8_t readCount) +{ + MXC_I3C_RevA_Controller_ClearError(i3c); + MXC_I3C_RevA_Controller_ClearFlags(i3c, MXC_F_I3C_REVA_CONT_STATUS_MASK); + + MXC_I3C_RevA_Controller_Request(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START, + isI2C ? MXC_I3C_REVA_START_TYPE_I2C : + MXC_I3C_REVA_START_TYPE_SDR, + xferType, addr, readCount); + + if (MXC_I3C_RevA_Controller_WaitForReqDone(i3c, 1000) < 0) { + return E_TIME_OUT; + } + + return MXC_I3C_RevA_Controller_GetError(i3c); +} + +int MXC_I3C_RevA_ResetTarget(mxc_i3c_reva_regs_t *i3c) +{ + MXC_I3C_RevA_Controller_ClearError(i3c); + MXC_I3C_RevA_Controller_ClearFlags(i3c, MXC_F_I3C_REVA_CONT_STATUS_MASK); + + MXC_I3C_RevA_Controller_Request(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST, + MXC_I3C_REVA_START_TYPE_SDR, 0, 0, 0); + + if (MXC_I3C_RevA_Controller_WaitForReqDone(i3c, 1000) < 0) { + return E_TIME_OUT; + } + + return MXC_I3C_RevA_Controller_GetError(i3c); +} + +void MXC_I3C_RevA_EmitStop(mxc_i3c_reva_regs_t *i3c) +{ + /* Configure MCTRL register for STOP */ + i3c->cont_ctrl1 &= ~(MXC_F_I3C_REVA_CONT_CTRL1_REQ | MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR | + MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD); + i3c->cont_ctrl1 |= MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP; + /* Wait for IDLE state */ + MXC_I3C_RevA_Controller_WaitForIdle(i3c, 1000); +} + +void MXC_I3C_RevA_EmitI2CStop(mxc_i3c_reva_regs_t *i3c) +{ + /* Configure MCTRL register for STOP */ + i3c->cont_ctrl1 = MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP | + (1 << MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS); + /* Wait for IDLE state */ + MXC_I3C_RevA_Controller_WaitForIdle(i3c, 1000); +} + +int MXC_I3C_RevA_Controller_CCC(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_ccc_req_t *req) +{ + int ret; + + MXC_I3C_RevA_ClearTXFIFO(i3c); + MXC_I3C_RevA_ClearRXFIFO(i3c); + MXC_I3C_RevA_EmitStart(i3c, false, MXC_I3C_TRANSFER_TYPE_WRITE, MXC_I3C_BROADCAST_ADDR, 0); + + MXC_I3C_RevA_WriteTXFIFO(i3c, &req->ccc, 1, req->flags == 0, 100); + if (req->flags & MXC_I3C_CCC_HAS_DEFINING_BYTE) { + MXC_I3C_RevA_WriteTXFIFO(i3c, &req->def_byte, 1, req->tx_len == 0, 100); + } + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + + if (req->ccc & 0x80) { + /* Direct CCC */ + ret = MXC_I3C_RevA_EmitStart(i3c, false, req->xfer_type, req->target_addr, req->rx_len); + if (ret < 0) { + goto err; + } + if (req->xfer_type == MXC_I3C_TRANSFER_TYPE_WRITE) { + /* Write message */ + if (req->flags & MXC_I3C_CCC_HAS_SUB_COMMAND) { + MXC_I3C_RevA_WriteTXFIFO(i3c, &req->sub_cmd, 1, (req->tx_len == 0), 100); + } + if (req->tx_len) { + MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100); + } + } else { + /* Read message */ + MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf, req->rx_len, -1); + } + } else { + /* Broadcast CCC */ + if (req->tx_len) { + MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100); + } + } + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + + /* Check for errors */ + ret = MXC_I3C_RevA_Controller_GetError(i3c); +err: + MXC_I3C_RevA_EmitStop(i3c); + + return ret; +} + +int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req) +{ + int ret; + uint8_t readCount; + uint16_t remaining; + + if (MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE && + MXC_I3C_RevA_Controller_GetState(i3c) != MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM) { + return E_BUSY; + } + + if (req->tx_len == 0 && req->rx_len == 0) { + return E_BAD_PARAM; + } + + MXC_I3C_RevA_ClearTXFIFO(i3c); + MXC_I3C_RevA_ClearRXFIFO(i3c); + + if (!req->is_i2c) { + ret = MXC_I3C_RevA_EmitStart(i3c, req->is_i2c, MXC_I3C_TRANSFER_TYPE_WRITE, + MXC_I3C_BROADCAST_ADDR, 0); + + if (ret < 0) { + goto err; + } + } + + /* Restart with write */ + if (req->tx_len) { + ret = MXC_I3C_RevA_EmitStart(i3c, req->is_i2c, MXC_I3C_TRANSFER_TYPE_WRITE, + req->target_addr, 0); + if (ret < 0) { + goto err; + } + + ret = MXC_I3C_RevA_WriteTXFIFO(i3c, req->tx_buf, req->tx_len, true, 100); + if (ret < 0) { + goto err; + } + + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + } + + if (req->rx_len) { + remaining = req->rx_len; + while (remaining > 0) { + readCount = (remaining < MXC_I3C_REVA_MAX_FIFO_TRANSACTION) ? + remaining : + MXC_I3C_REVA_MAX_FIFO_TRANSACTION; + + ret = MXC_I3C_RevA_EmitStart(i3c, req->is_i2c, MXC_I3C_TRANSFER_TYPE_READ, + req->target_addr, readCount); + if (ret < 0) { + goto err; + } + + ret = MXC_I3C_RevA_ReadRXFIFO(i3c, req->rx_buf + (req->rx_len - remaining), readCount, + 1000); + if (ret == readCount) { + remaining -= readCount; + } else { + ret = MXC_I3C_RevA_Controller_GetError(i3c); + goto err; + } + } + + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + } + + /* Check for errors */ + ret = MXC_I3C_RevA_Controller_GetError(i3c); +err: + if (req->stop || ret != E_SUCCESS) { + MXC_I3C_RevA_EmitStop(i3c); + } + + return ret; +} + +int MXC_I3C_RevA_Controller_DAA(mxc_i3c_reva_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr, + uint8_t *dcr) +{ + int ret; + + MXC_I3C_RevA_ClearTXFIFO(i3c); + MXC_I3C_RevA_ClearRXFIFO(i3c); + + if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA && + GET_FIELD(cont_status, CONT_STATUS_WAIT)) { + MXC_I3C_RevA_WriteTXFIFO(i3c, &addr, 1, true, 10); + MXC_I3C_RevA_Controller_WaitForDone(i3c, 1000); + } + + MXC_I3C_RevA_Controller_Request(i3c, MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA, + MXC_I3C_REVA_START_TYPE_SDR, 0, 0, 0); + ret = MXC_I3C_RevA_Controller_WaitForReqDone(i3c, 1000); + + if (ret == E_SUCCESS) { + if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA && + GET_FIELD(cont_status, CONT_STATUS_WAIT)) { + MXC_I3C_RevA_ReadRXFIFO(i3c, pid, MXC_I3C_PROVISIONED_ID_LEN, 10); + MXC_I3C_RevA_ReadRXFIFO(i3c, bcr, 1, 1); + MXC_I3C_RevA_ReadRXFIFO(i3c, dcr, 1, 1); + } else if (MXC_I3C_RevA_Controller_GetState(i3c) == MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE && + GET_FIELD(cont_status, CONT_STATUS_DONE)) { + ret = E_SHUTDOWN; + } else { + ret = E_FAIL; + } + } + + return ret; +} + +int MXC_I3C_RevA_AutoIBI(mxc_i3c_reva_regs_t *i3c) +{ + int timeout = 500; + i3c->cont_ctrl1 &= ~(MXC_F_I3C_CONT_CTRL1_REQ | MXC_F_I3C_CONT_CTRL1_IBIRESP); + i3c->cont_ctrl1 |= MXC_S_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI | + (MXC_I3C_REVA_IBIRESP_ACK << MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS); + + while (!GET_FIELD(cont_status, CONT_STATUS_IBI_WON)) { + if (--timeout == 0) { + return E_TIME_OUT; + } + } + SET_FIELD(cont_status, CONT_STATUS_IBI_WON, 0); + + return 0; +} + +int MXC_I3C_RevA_HotJoin(mxc_i3c_reva_regs_t *i3c) +{ + if (!(i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ)) { + return E_NOT_SUPPORTED; + } + + if ((MXC_I3C_RevA_GetDynamicAddress(i3c) != MXC_I3C_ADDR_INVALID) || + (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS)) { + return E_BAD_STATE; + } + + SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0); + SET_FIELD(targ_ctrl1, TARG_CTRL1_EVENT, MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ); + SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 1); + + return E_SUCCESS; +} + +int MXC_I3C_RevA_RequestIBI(mxc_i3c_reva_regs_t *i3c, unsigned char mdb, + mxc_i3c_reva_ibi_getbyte_t getByteCb) +{ + int ret, idx; + unsigned char byte; + + idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c); + if (idx < 0) { + return E_BAD_PARAM; + } + + if (!(i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ)) { + return E_NOT_SUPPORTED; + } + + if ((MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) || + (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS)) { + return E_BAD_STATE; + } + + if (i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_EVENT) { + return E_BUSY; + } + + /* Write MDB and additional data bytes to TX FIFO */ + controller[idx].ibiGetByteCB = getByteCb; + if (i3c->targ_cap1 & MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD) { + if (getByteCb) { + while ((i3c->targ_status & MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL)) { + ret = getByteCb(i3c, &byte); + if (ret) { + i3c->targ_txfifo8 = byte; + } else { + break; + } + } + } + SET_FIELD(targ_ctrl1, TARG_CTRL1_IBIDATA, mdb); + SET_FIELD(targ_ctrl1, TARG_CTRL1_EXTIBI, + !!(i3c->targ_fifoctrl & MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL)); + } + + MXC_I3C_RevA_Target_EnableInt(i3c, MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ | + MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL | + MXC_F_I3C_REVA_TARG_INTEN_STOP); + + SET_FIELD(targ_ctrl1, TARG_CTRL1_EVENT, MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI); + + return E_SUCCESS; +} + +int MXC_I3C_RevA_Standby(mxc_i3c_reva_regs_t *i3c) +{ + if (MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) { + return E_BAD_STATE; + } + + SET_FIELD(targ_ctrl0, TARG_CTRL0_EN, 0); + + return E_SUCCESS; +} + +int MXC_I3C_RevA_Wakeup(mxc_i3c_reva_regs_t *i3c) +{ + if ((MXC_I3C_RevA_GetDynamicAddress(i3c) == MXC_I3C_ADDR_INVALID) || + (GET_FIELD(targ_ctrl0, TARG_CTRL0_EN))) { + return E_BAD_STATE; + } + + i3c->targ_ctrl0 |= (MXC_F_I3C_REVA_TARG_CTRL0_EN | MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE); + + return E_SUCCESS; +} + +void MXC_I3C_RevA_SetIBIPayloadCallback(mxc_i3c_reva_regs_t *i3c, + mxc_i3c_reva_ibi_getbyte_t payloadCb) +{ + int idx; + + idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c); + if (idx >= 0) { + controller[idx].ibiGetByteCB = payloadCb; + } +} + +int MXC_I3C_RevA_Controller_GetError(mxc_i3c_reva_regs_t *i3c) +{ + uint32_t errFlags = i3c->cont_errwarn & MXC_F_I3C_REVA_CONT_ERRWARN_MASK; + + if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_NACK) { + return E_NO_RESPONSE; + } else if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT) { + return E_ABORT; + } else if (errFlags & (MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ | MXC_F_I3C_REVA_CONT_ERRWARN_MSG)) { + return E_BAD_STATE; + } else if (errFlags & MXC_F_I3C_REVA_CONT_ERRWARN_TO) { + return E_TIME_OUT; + } else if (errFlags & + (MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR | MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR)) { + return E_OVERFLOW; + } + + return E_NO_ERROR; +} + +void MXC_I3C_RevA_Controller_ClearError(mxc_i3c_reva_regs_t *i3c) +{ + i3c->cont_errwarn = MXC_F_I3C_REVA_CONT_ERRWARN_MASK; +} + +int MXC_I3C_RevA_SetRXTXThreshold(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_rx_threshold_t rxth, + mxc_i3c_reva_tx_threshold_t txth) +{ + if (rxth > MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL || + txth > MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL) { + return E_BAD_PARAM; + } + + i3c->cont_fifoctrl &= + ~(MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL | MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL); + i3c->cont_fifoctrl = (rxth << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) | + (txth << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) | + MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK; + + return E_SUCCESS; +} + +int MXC_I3C_RevA_ReadRXFIFO(mxc_i3c_reva_regs_t *i3c, volatile unsigned char *bytes, + unsigned int len, int timeout) +{ + unsigned int readb = 0; + + if (timeout == 0) { + timeout = 1; + } else if ((timeout > 0) && (timeout < (len + 1))) { + timeout = len + 1; + } + + while ((len > readb) && (timeout != 0)) { + if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_RX_RDY) { + bytes[readb++] = i3c->cont_rxfifo8; + } + if (timeout > 0) { + timeout--; + } + } + + return readb; +} + +int MXC_I3C_RevA_WriteTXFIFO(mxc_i3c_reva_regs_t *i3c, const unsigned char *bytes, unsigned int len, + bool end, int timeout) +{ + unsigned int written = 0; + + if (len == 0) { + return 0; + } + + if (timeout == 0) { + timeout = 1; + } else if ((timeout > 0) && (timeout < (len + 1))) { + timeout = len + 1; + } + + while ((len - 1 > written) && (timeout != 0)) { + if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL) { + i3c->cont_txfifo8o = bytes[written++]; + } + if (timeout > 0) { + timeout--; + } + } + + while ((len == written + 1) && (timeout != 0)) { + if (i3c->cont_status & MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL) { + if (end) { + i3c->cont_txfifo8e = bytes[written++]; + } else { + i3c->cont_txfifo8o = bytes[written++]; + } + } + if (timeout > 0) { + timeout--; + } + } + + return written; +} + +void MXC_I3C_RevA_IRQHandler(mxc_i3c_reva_regs_t *i3c) +{ + int idx; + + idx = MXC_I3C_GET_IDX((mxc_i3c_regs_t *)i3c); + if (idx < 0) { + return; + } +} diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h new file mode 100644 index 00000000..5540a194 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.h @@ -0,0 +1,255 @@ +/** +* @file i3c.h +* @brief Improved Inter Integrated Circuit (I3C) communications interface driver. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_ + +/* **** Includes **** */ +#include +#include "i3c.h" +#include "i3c_reva.h" +#include "i3c_reva_regs.h" +#include "mxc_sys.h" + +/****** Definitions *****/ + +/** + * @brief Maximum supported IBI bytes. + * + */ +#define MXC_I3C_REVA_MAX_IBI_BYTES 7U + +typedef struct _i3c_reva_ccc_req_t mxc_i3c_reva_ccc_req_t; +typedef struct _i3c_reva_req_t mxc_i3c_reva_req_t; + +/** + * @brief The list of high-keeper options. + * + * This setting should match the high-keeper implementation of the device. + */ +typedef enum { + MXC_I3C_REVA_HIGH_KEEPER_OFF = MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_OFF, ///< No high-keeper support + MXC_I3C_REVA_HIGH_KEEPER_ON_CHIP = + MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP, ///< SCL and SDA pads + ///< have weak pull-ups + MXC_I3C_REVA_HIGH_KEEPER_EXT_SDA = + MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA, ///< External high-keeper + ///< support for SDA signal + MXC_I3C_REVA_HIGH_KEEPER_EXT_SCL_SDA = MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA, + ///< External high-keeper support for SCL and SDA signals +} mxc_i3c_reva_high_keeper_t; + +/** + * @brief The list of receive FIFO trigger levels. + */ +typedef enum { + MXC_I3C_REVA_RX_TH_NOT_EMPTY = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY, ///< + MXC_I3C_REVA_RX_TH_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL, ///< + MXC_I3C_REVA_RX_TH_HALF_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL, ///< + MXC_I3C_REVA_RX_TH_3_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL, ///< +} mxc_i3c_reva_rx_threshold_t; + +/** + * @brief The list of transmit FIFO trigger levels. + */ +typedef enum { + MXC_I3C_REVA_TX_TH_EMPTY = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY, ///< + MXC_I3C_REVA_TX_TH_QUARTER_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL, ///< + MXC_I3C_REVA_TX_TH_HALF_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL, ///< + MXC_I3C_REVA_TX_TH_ALMOST_FULL = MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL, ///< +} mxc_i3c_reva_tx_threshold_t; + +/** + * @brief IBI types. + * + */ +typedef enum { + MXC_I3C_REVA_IBI_TYPE_NONE = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE, ///< + MXC_I3C_REVA_IBI_TYPE_IBI = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI, ///< + MXC_I3C_REVA_IBI_TYPE_CONTROLLER_REQ = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ, ///< + MXC_I3C_REVA_IBI_TYPE_HOTJOIN_REQ = MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ, ///< +} mxc_i3c_reva_ibi_type_t; + +/** + * @brief Common Command Code request structure. + * + * Broadcast and direct commands are distinguished by MSB, i.e. if MSB being set + * implies a direct CCC while MSB being 0 implies a broadcast CCC. + * + */ +struct _i3c_reva_ccc_req_t { + uint8_t ccc; ///< CCC command to send. + uint8_t target_addr; ///< Target address if CCC is a direct command. Ignored + ///< if CCC is a broadcast command. + mxc_i3c_transfer_type_t xfer_type; ///< Transfer type. Ignored for broadcast CCCs. + uint8_t flags; ///< See request flags above. + uint8_t def_byte; ///< Optional defining byte. Defined by CCC. + uint8_t sub_cmd; ///< Optional sub-command. Defined by CCC. Only used by direct + ///< CCCs. + unsigned char *tx_buf; ///< Optional data bytes to send. + uint8_t tx_len; ///< Length of optional data. + unsigned char *rx_buf; ///< Optional data bytes to read. + uint8_t rx_len; ///< Length of optional data. +}; + +/** + * @brief Private SDR request structure. + * + * SDR read and write to an I3C target. + * + */ +struct _i3c_reva_req_t { + uint8_t target_addr; ///< Target address. + bool is_i2c; ///< If this is a legacy I2C transfer. + bool stop; ///< Send a STOP after the transaction. + unsigned char *tx_buf; ///< Optional data bytes to send. + uint16_t tx_len; ///< Length of optional data. + unsigned char *rx_buf; ///< Optional data bytes to read. + uint16_t rx_len; ///< Length of optional data. +}; + +/** + * @brief IBI payload request callback. Write additional byte to \a byte. + * + * This function will be called as long as non-zero is returned. + * + * @return Non-zero if a byte is written to \a byte, 0 to indicate no more additional + * bytes left to send. + */ +typedef int (*mxc_i3c_reva_ibi_getbyte_t)(mxc_i3c_reva_regs_t *i3c, unsigned char *byte); + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +int MXC_I3C_RevA_Init(mxc_i3c_reva_regs_t *i3c, bool targetMode, uint8_t staticAddr); +int MXC_I3C_RevA_Recover(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_Shutdown(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_SetPPFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency); +unsigned int MXC_I3C_RevA_GetPPFrequency(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_SetODFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency, bool highPP); +unsigned int MXC_I3C_RevA_GetODFrequency(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_SetI2CFrequency(mxc_i3c_reva_regs_t *i3c, unsigned int frequency); +unsigned int MXC_I3C_RevA_GetI2CFrequency(mxc_i3c_reva_regs_t *i3c); +uint8_t MXC_I3C_RevA_GetDynamicAddress(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_SetSkew(mxc_i3c_reva_regs_t *i3c, uint8_t skew); +int MXC_I3C_RevA_SetHighKeeperMode(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_high_keeper_t hkeep); + +/* ************************************************************************* */ +/* Protocol functions */ +/* ************************************************************************* */ +int MXC_I3C_RevA_EmitStart(mxc_i3c_reva_regs_t *i3c, bool isI2C, mxc_i3c_transfer_type_t xferType, + uint8_t addr, uint8_t readCount); +int MXC_I3C_RevA_ResetTarget(mxc_i3c_reva_regs_t *i3c); +void MXC_I3C_RevA_EmitStop(mxc_i3c_reva_regs_t *i3c); +void MXC_I3C_RevA_EmitI2CStop(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_Controller_CCC(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_ccc_req_t *req); +int MXC_I3C_RevA_Controller_Transaction(mxc_i3c_reva_regs_t *i3c, const mxc_i3c_reva_req_t *req); +int MXC_I3C_RevA_Controller_DAA(mxc_i3c_reva_regs_t *i3c, uint8_t addr, uint8_t *pid, uint8_t *bcr, + uint8_t *dcr); +int MXC_I3C_RevA_AutoIBI(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_HotJoin(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_RequestIBI(mxc_i3c_reva_regs_t *i3c, unsigned char mdb, + mxc_i3c_reva_ibi_getbyte_t getByteCb); +int MXC_I3C_RevA_Standby(mxc_i3c_reva_regs_t *i3c); +int MXC_I3C_RevA_Wakeup(mxc_i3c_reva_regs_t *i3c); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I3C_RevA_Controller_GetError(mxc_i3c_reva_regs_t *i3c); +void MXC_I3C_RevA_Controller_ClearError(mxc_i3c_reva_regs_t *i3c); + +int MXC_I3C_RevA_SetRXTXThreshold(mxc_i3c_reva_regs_t *i3c, mxc_i3c_reva_rx_threshold_t rxth, + mxc_i3c_reva_tx_threshold_t txth); +int MXC_I3C_RevA_ReadRXFIFO(mxc_i3c_reva_regs_t *i3c, volatile unsigned char *bytes, + unsigned int len, int timeout); +int MXC_I3C_RevA_WriteTXFIFO(mxc_i3c_reva_regs_t *i3c, const unsigned char *bytes, unsigned int len, + bool end, int timeout); +void MXC_I3C_RevA_IRQHandler(mxc_i3c_reva_regs_t *i3c); + +static inline void MXC_I3C_RevA_ClearRXFIFO(mxc_i3c_reva_regs_t *i3c) +{ + i3c->cont_fifoctrl |= MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH; +} + +static inline void MXC_I3C_RevA_ClearTXFIFO(mxc_i3c_reva_regs_t *i3c) +{ + i3c->cont_fifoctrl |= MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH; +} + +static inline unsigned int MXC_I3C_RevA_Controller_GetRXCount(mxc_i3c_reva_regs_t *i3c) +{ + return ((i3c->cont_fifoctrl & MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL) >> + MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS); +} + +static inline unsigned int MXC_I3C_RevA_Controller_GetTXCount(mxc_i3c_reva_regs_t *i3c) +{ + return ((i3c->cont_fifoctrl & MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL) >> + MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS); +} + +static inline void MXC_I3C_RevA_Controller_EnableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->cont_inten |= mask; +} + +static inline void MXC_I3C_RevA_Controller_DisableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->cont_intclr |= mask; +} + +static inline unsigned int MXC_I3C_RevA_Controller_GetFlags(mxc_i3c_reva_regs_t *i3c) +{ + return i3c->cont_intfl; +} + +static inline void MXC_I3C_RevA_Controller_ClearFlags(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->cont_status |= mask; +} + +static inline void MXC_I3C_RevA_Target_EnableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->targ_inten |= mask; +} + +static inline void MXC_I3C_RevA_Target_DisableInt(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->targ_intclr |= mask; +} + +static inline int MXC_I3C_RevA_Target_GetFlags(mxc_i3c_reva_regs_t *i3c) +{ + return i3c->targ_intfl; +} + +static inline void MXC_I3C_RevA_Target_ClearFlags(mxc_i3c_reva_regs_t *i3c, uint32_t mask) +{ + i3c->targ_status |= mask; +} + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd new file mode 100644 index 00000000..a177eab9 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd @@ -0,0 +1,2455 @@ + + + + I3C0 + Improved Inter-Integrated Circuit. + I3C + 0x40018000 + 32 + + 0x00 + 0x1000 + registers + + + I3C0 + I3C0 IRQ + 30 + + + + CONT_CTRL0 + Controller Control 0 (Configuration) Register. + 0x000 + + + EN + I3C Device Enable. + [1:0] + read-write + + + OFF + Off. + 0 + + + ON + On. + 1 + + + CAP + I23 Bug Target with secondary controller capability. + 2 + + + + + TO_DIS + Disable Timeout error. + [3:3] + read-write + + + HKEEP + High-keepr implementation. + [5:4] + read-write + + + OFF + No high-keeper support. + 0 + + + ON_CHIP + On-chip high-keeper support. + 1 + + + EXT_SDA + External high-keeper support for SDA. + 2 + + + EXT_SCL_SDA + External high-keeper support for SCL and SDA. + 3 + + + + + OD_STOP + Use open-drain speed for STOP. + [6:6] + read-write + + + PP_BAUD + SCL Frequency for push-pull drive. + [11:8] + read-write + + + 1_FCLK + SCL High Period is one FCLK Period. + 0 + + + 2_FCLK + SCL High Period is two FLCK Periods. + 1 + + + 3_FCLK + SCL High Period is three FCLK Period. + 2 + + + 4_FCLK + SCL High Period is four FCLK Period. + 3 + + + 5_FCLK + SCL High Period is five FCLK Period. + 4 + + + 6_FCLK + SCL High Period is six FCLK Period. + 5 + + + 7_FCLK + SCL High Period is seven FCLK Period. + 6 + + + 8_FCLK + SCL High Period is eight FCLK Period. + 7 + + + 9_FCLK + SCL High Period is nine FCLK Period. + 8 + + + 10_FCLK + SCL High Period is ten FCLK Period. + 9 + + + 11_FCLK + SCL High Period is eleven FCLK Period. + 10 + + + 12_FCLK + SCL High Period is twelve FCLK Period. + 11 + + + 13_FCLK + SCL High Period is thirteen FCLK Period. + 12 + + + 14_FCLK + SCL High Period is fourteen FCLK Period. + 13 + + + 15_FCLK + SCL High Period is fifthteen FCLK Period. + 14 + + + 16_FCLK + SCL High Period is sixteen FCLK Period. + 15 + + + + + PP_ADD_LBAUD + Number of FCLK periods to add to the base of SCL low period. + [15:12] + read-write + + + 0_FCLK + Adds zero FCLK periods to the SCL low period. + 0 + + + 1_FCLK + Adds one FCLK period to the SCL low period. + 1 + + + 2_FCLK + Adds two FCLK periods to the SCL low period. + 2 + + + 3_FCLK + Adds three FCLK periods to the SCL low period. + 3 + + + 4_FCLK + Adds four FCLK periods to the SCL low period. + 4 + + + 5_FCLK + Adds five FCLK periods to the SCL low period. + 5 + + + 6_FCLK + Adds six FCLK periods to the SCL low period. + 6 + + + 7_FCLK + Adds seven FCLK periods to the SCL low period. + 7 + + + 8_FCLK + Adds eight FCLK periods to the SCL low period. + 8 + + + 9_FCLK + Adds nine FCLK periods to the SCL low period. + 9 + + + 10_FCLK + Adds ten FCLK periods to the SCL low period. + 10 + + + 11_FCLK + Adds eleven FCLK periods to the SCL low period. + 11 + + + 12_FCLK + Adds twelve FCLK periods to the SCL low period. + 12 + + + 13_FCLK + Adds thirteen FCLK periods to the SCL low period. + 13 + + + 14_FCLK + Adds fourteen FCLK periods to the SCL low period. + 14 + + + 15_FCLK + Adds fifthteen FCLK periods to the SCL low period. + 15 + + + + + OD_LBAUD + Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods. + [23:16] + read-write + + + OD_HP + Controls SCL high period for I3C oepn-drain operation. + [24:24] + read-write + + + PP_SKEW + Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation. + [27:25] + read-write + + + I2C_BAUD + Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period. + [31:28] + read-write + + + + + TARG_CTRL0 + Target Control 0 (Configuration) Register. + 0x004 + + + EN + Target device enable. + [0:0] + read-write + + + MATCHSS + Match STOP and START. + [2:2] + read-write + + + TO_IGN + Ignore Timeout Errors. + [3:3] + read-write + + + OFFLINE + Rejoin I3C bus with existing dynamic address. + [9:9] + read-write + + + + + TARG_STATUS + Target Status Register. + 0x008 + + + BUSY + Not stopped. + [0:0] + read-only + + + LIST_RESP + Message status - listening/responding or not. + [1:1] + read-only + + + CCCH + CCC is being handled. + [2:2] + read-only + + + RX_SDR + SDR Read. + [3:3] + + + TX_SDR + SDR Write. + [4:4] + + + DAA + Dynamic Address Assignment Mode. + [5:5] + read-only + + + HDR + HDR Mode. + [6:6] + read-only + + + START + START Detected. + [8:8] + read-write + + + ADDRMATCH + Address Matched. + [9:9] + read-write + + + STOP + STOP Detected. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO is not full, ready to accept more data. + [12:12] + read-write + + + DYNADDR_CHG + Dynamic address changed. + [13:13] + read-write + + + CCC + CCC received. + [14:14] + read-write + + + ERRWARN + An error or warning has occurred. + [15:15] + read-only + + + CCCH_DONE + CCC Handled. + [17:17] + read-write + + + EVENT_REQ + Event Requested. + [18:18] + read-write + + + TARG_RST + Target Reset. + [19:19] + read-write + + + EVENT + Event Status. + [21:20] + read-only + + + NONE + No event. + 0 + + + REQ_PEND + Request not yet sent. + 1 + + + REQ_NACK + Request was sent and NACKed and will be tried again. + 2 + + + REQ_ACK + Request was sent and ACKed. + 3 + + + + + IBI_DIS + Indicates whether IBI events are disabled. + [24:24] + read-only + + + CONTREQ_DIS + Indicates whether bus controller request events are disabled. + [25:25] + read-only + + + HJ_DIS + Indicates whether Hot-Joinevents are disabled. + [27:27] + read-only + + + ACTSTATE + Holds the current activity state. + [29:28] + read-only + + + NORMAL + No latency, normal bus operation. + 0 + + + 1MS_LAT + 1 ms latency. + 1 + + + 100MS_LAT + 100 ms latency. + 2 + + + 10S_LAT + 10 s latency. + 3 + + + + + TIMECTRL + Time Control mode. + [31:30] + read-only + + + DIS + No timing control mode is enabled. + 0 + + + SYNC + Synchronous Mode is enabled. + 1 + + + ASYNC + Asynchronous Mode is enabled. + 2 + + + BOTH + Both synchronous and asynchronous modes are enabled. + 3 + + + + + + + TARG_CTRL1 + Target Control 1 Register. + 0x00C + + + EVENT + Sets respecive I3C target event request. + [1:0] + read-write + + + NORMAL + Normal mode. + 0 + + + IBI + Generate an IBI on the I3C bus. + 1 + + + CONTREQ + Request control of the I3C bus. + 2 + + + HJ + Generate a Hot-Join request. + 3 + + + + + EXTIBI + Indicates there are extended IBI data bytes. + [3:3] + read-write + + + DYNADDR_IDX + Index of dynamic address for the current IBI request. + [7:4] + read-write + + + IBIDATA + Contains the mandatory data byte to be sent when generating an IBI. + [15:8] + read-write + + + + + TARG_INTEN + Target Interrupt Enable Register. + 0x010 + read-write + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTCLR + Target Interrupt Clear Register. + 0x014 + write-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTFL + Target Interrupt Flag Register. + 0x018 + read-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_ERRWARN + Target Error and Warning Register. + 0x01C + read-write + + + OVR + Internal FIFO overrun flag. + [0:0] + + + UNR + Internal FIFO underrun flag. + [1:1] + + + UNR_NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + CONT_RX_TERM + Controller terminated read in message mode. + [3:3] + + + INVSTART + Invalid START. + [4:4] + + + SDR_PAR + SDR Parity Error. + [8:8] + + + TO + Timeout Error. + [11:11] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + + + TARG_DMACTRL + Target DMA Control Register. + 0x020 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + TARG_FIFOCTRL + Target FIFO Control Register. + 0x02C + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + TARG_TXFIFO8 + Target Write Byte Data Register. + 0x030 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + TARG_TXFIFO8E + Target Write Byte Data as End Register. + 0x034 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + TARG_TXFIFO16 + Target Write Half-Word Data Register. + 0x038 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + TARG_TXFIFO16E + Target Write Half-Word Data as End Register. + 0x03C + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + TARG_RXFIFO8 + Target Read Byte Data Register. + 0x040 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + TARG_RXFIFO16 + Target Read Half-Word Data Register. + 0x048 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + TARG_TXFIFO8O + Target Byte-Only Write Byte Data Register. + 0x054 + write-only + + + DATA + Data byte to send. + [7:0] + + + + + TARG_CAP0 + Target Capabilities 0 Register. + 0x05C + read-only + + + MAPCNT + Number of mapped target addresses supported. + [3:0] + + + I2C_10BADDR + I2C 10-bit address support. + [4:4] + + + I2C_SWRST + I2C Software Reset Support. + [5:5] + + + I2C_DEVID + I2C Device ID Support. + [6:6] + + + FIFO32_REG + FIFO 32 registers available. + [7:7] + + + EXTIBI + Extended IBI data support. + [8:8] + + + EXTIBI_REG + Extended IBI data register support. + [9:9] + + + HDRBT_LANES + Multi-lane support for HDR-BT mode. + [13:12] + + + CCC_V1_1 + CCC V1.1 Support. + [16:16] + + + TARG_RST + Target Reset Support. + [17:17] + + + GROUPADDR + Group address support. + [19:18] + + + AASA_CCC + SETAASA CCC Support. + [21:21] + + + T2T_SUBSC + Target-to-target subscriber support. + [22:22] + + + T2T_WR + Target-to-target write support. + [23:23] + + + + + TARG_CAP1 + TARG_Capabilities 1 Register. + 0x060 + read-only + + + PROVID + Provisioned ID implementation. + [1:0] + + + PROVID_REG + Provision ID, Bus Characteristics, Device Characteristics implementation. + [5:2] + + + HDR_MODES + Supported HDR modes. + [8:6] + + + CONT + Controller mode capable. + [9:9] + + + STATADDR + I2C-style static address implementation. + [11:10] + + + CCCH + CCC Handled by IP. + [15:12] + + + BASIC + Basic CCCs. + 1 + + + LIMITS + CCCs related to maximum transfer lengths and speed. + 2 + + + INTACT + Pending Interrupt and Activity Mode fields of GETSTATUS CCC. + 4 + + + VENDOR + Vendor Reserved field of GETSTATUS CCC. + 8 + + + + + IBI_EVENTS + Supported IBI events. + [20:16] + + + IBI + IBI support. + 1 + + + PAYLOAD + IBI has payload. + 2 + + + CONTREQ + Controller request support. + 4 + + + HJ + Hot-Join support. + 8 + + + BAMATCH + Use BAMATCH field of CONFIG register to measure 1us Bus Available timing. + 16 + + + + + TIMECTRL + Timing Control Support. + [21:21] + + + EXTFIFO + External FIFO configuration. + [25:23] + + + TXFIFO_CFG + TX FIFO configuration. + [27:26] + + + RXFIFO_CFG + RX FIFO configuration. + [29:28] + + + INTR + Interrupt support. + [30:30] + + + DMA + DMA support. + [31:31] + + + + + TARG_DYNADDR + Target Dynamic Address Register. + 0x064 + read-write + + + VALID + Address valid check. + [0:0] + + + ADDR + The assigned dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynnamic address value change occurred. + [10:8] + + + + + TARG_MAXLIMITS + Maximum Limits Register. + 0x068 + read-write + + + RX + The maximum number of bytes that the I3C controller may read from this I3C target device per message. + [11:0] + + + TX + The maximum number of bytes that the I3C controller may write from this I3C target device per message. + [27:16] + + + + + TARG_IDEXT + ID Extension Register. + 0x070 + read-write + + + DEVCHAR + Device Characteristics Register. + [15:8] + + + BUSCHAR + Bus Characteristics Register. + [23:16] + + + + + TARG_MSGLAST + Target Matching Address Index Register. + 0x07C + read-only + + + IDX + Index or group number of last matched address. + [3:0] + + + STATADDR + Last matched address was a I2C static address. + [4:4] + + + GROUP + Last matched address was a group address. + [5:5] + + + MODE + Indicates the mode of the last access. + [7:6] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + PREV_IDX + Index or group number of previous matched address. + [11:8] + + + PREV_GROUP + Last matched address was a previous group address. + [13:13] + + + PREV_MODE + Indicates the mode of the previous access. + [15:14] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + SECPREV_IDX + Index or group number of secondary previous matched address. + [19:16] + + + SECPREV_GROUP + Last matched address was a secondary previous group address. + [21:21] + + + SECPREV_MODE + Indicates the mode of the secondary previous access. + [23:22] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + + + CONT_CTRL1 + Controller Control 1 Register. + 0x084 + + + REQ + Requests an I3C or I2C bus operation. + [2:0] + read-write + + + NONE + None operation. + 0 + + + EMIT_START + Emit a START with address and read-write bit from stopped state or in the middle of an SDR message. + 1 + + + EMIT_STOP + Emit a STOP. + 2 + + + IBI_ACKNACK + Manually ACK or NACK an IBI. + 3 + + + PROCESS_DAA + Process Dynamic Address Assignment. + 4 + + + EXIT_RST + Emit HDR Exit Pattern or Target Reset pattern. + 6 + + + AUTO_IBI + Automatic IBI response. + 7 + + + + + TYPE + Controls type of operation for REQ field. + [5:4] + read-write + + + IBIRESP + Response to use when an IBI occurs. + [7:6] + read-write + + + RDWR_DIR + Direction of the transfer. + [8:8] + read-write + + + ADDR + Address to send with START. + [15:9] + read-write + + + TERM_RD + Termination count for read. + [23:16] + read-write + + + + + CONT_STATUS + Controller Status Register. + 0x088 + + + STATE + Current working state. + [2:0] + read-only + + + IDLE + Bus Idle. + 0 + + + TARG_REQ + I3C Bus i stopped and a target is holding SDA low. + 1 + + + SDR_TXSDRMSG + SDR Message Mode using SDRMSG registers. + 2 + + + SDR_NORM + Normal SDR message mode. + 3 + + + DDR + DDR Message mode + 4 + + + DAA + Dynamic Address Assignment mode. + 5 + + + IBI_ACKNACK + IP is waiting for the application to provide an ACK or NACK decision. + 6 + + + IBI_RX + IP is receiving an IBI. + 7 + + + + + WAIT + Depending on STATE, WAIT is 1 when it's waiting in an intermediary state. + [4:4] + read-only + + + NACK + Address was NACKed. + [5:5] + read-only + + + IBITYPE + The type of event for which arbitration was last won. + [7:6] + + + NONE + None. + 0 + + + IBI + In-band Interrupt. + 1 + + + CONT_REQ + Controller request. + 2 + + + HOTJOIN_REQ + Hot-Join request. + 3 + + + + + TARG_START + Target START detected. + [8:8] + + + REQ_DONE + CTRL1 Request completed. + [9:9] + read-only + + + DONE + Message completed. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO Not Full flag. + [12:12] + read-only + + + IBI_WON + IBI Arbitration won. + [13:13] + read-write + + + ERRWARN + Error or warning status. + [15:15] + read-only + + + CONT_TRANS + IP transitioned from I3C target to controller. + [19:19] + read-write + + + IBI_ADDR + The address of a received IBI or dcontroller request. + [30:24] + read-only + + + + + CONT_IBIRULES + Controller IBI Registry and Rules Register. + 0x08C + + + ADDR0 + Target 0 dynamic address. + [5:0] + read-write + + + ADDR1 + Target 1 dynamic address. + [11:6] + read-write + + + ADDR2 + Target 2 dynamic address. + [17:12] + read-write + + + ADDR3 + Target 3 dynamic address. + [23:18] + read-write + + + ADDR4 + Target 4 dynamic address. + [29:24] + read-write + + + MSB0 + Implementation of MSb for I3C dynamic addresses. + [30:30] + read-write + + + NOBYTE + Specifies the function of ADDR0 to ADDR4 + [31:31] + read-write + + + + + CONT_INTEN + Controller Interrupt Enable Register. + 0x090 + read-write + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTCLR + Controller Interrupt Clear Register. + 0x094 + write-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTFL + Controller Interrupt Flag Register. + 0x098 + read-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_ERRWARN + Controller Error and Warning Register. + 0x09C + read-write + + + NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + TX_ABT + Write aborted due to data NACK. + [3:3] + + + RX_TERM + Controller terminated read in messaage mode. + [4:4] + + + HDR_PAR + HDR Parity Error. + [9:9] + + + HDR_CRC + HDR-DDR CRC Error. + [10:10] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + MSG + Message mode error. + [18:18] + + + INV_REQ + Invalid use of request from CTRL register. + [19:19] + + + TO + Timeout error. + [20:20] + + + + + CONT_DMACTRL + Controller DMA Control Register. + 0x0A0 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + CONT_FIFOCTRL + Controller FIFO Control Register. + 0x0AC + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + CONT_TXFIFO8 + Controller Write Byte Data Register. + 0x0B0 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + CONT_TXFIFO8E + Controller Write Byte Data as End Register. + 0x0B4 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + CONT_TXFIFO16 + Controller Write Half-Word Data Register. + 0x0B8 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + CONT_TXFIFO16E + Controller Write Half-Word Data as End Register. + 0x0BC + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + CONT_RXFIFO8 + Controller Read Byte Data Register. + 0x0C0 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + CONT_RXFIFO16 + Controller Read Half-Word Data Register. + 0x0C8 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + CONT_TXFIFO8O + Controller Byte-Only Write Byte Data Register. + 0x0CC + write-only + + + DATA + Data byte to send. + [7:0] + + + + + CONT_TXSDRMSG_CTRL + Controller Start or Continue SDR Message Register. + 0x0D0 + read-write + + + RDWR_DIR + Direction of the transfer. + [0:0] + + + ADDR + Destination address of message. + [7:1] + + + END + Select how to end message. + [8:8] + + + I2C_EN + I2C Mode Enable. + [10:10] + + + LEN + Message length in bytes. + [15:11] + + + + + CONT_TXSDRMSG_FIFO + Controller Start or Continue SDR Message Register. + 0x0D0 + write-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_RXSDRMSG + Controller Read SDR Message Data Register. + 0x0D4 + read-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_TXDDRMSG + Controller Start or Continue DDR Message Register. + 0x0D8 + write-only + + + MSG + Data, address/command, and control information. + [15:0] + + + + + CONT_RXDDR16 + Controller Read DDR Message Data Register. + 0x0DC + read-only + + + DATA + Read data (16bits). + [15:0] + + + + + CONT_DYNADDR + Controller Dynamic Address Register. + 0x0E4 + read-write + + + ADDR + The assigned dynamic address. + [7:1] + + + VALID + Address valid check. + [8:8] + + + + + TARG_GROUPDEF + Target Group Definition Register. + 0x114 + read-only + + + ADDR_EN + Group Address enable. + [0:0] + + + ADDR + Group Address . + [7:1] + + + + + TARG_MAPCTRL0 + Target Primary Map Control Register. + 0x11C + read-write + + + DYNADDR_EN + Dynamic address is enabled. + [0:0] + + + DYNADDR + Dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynamic address value change occurred. + [10:8] + + + + + TARG_MAPCTRL1 + Target Map Control 1 Register. + 0x120 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + STATADDR_10B + Contains the upper 3 bits of a 10-bit I2C Static Address. + [11:9] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + + + TARG_MAPCTRL2 + Target Map Control 2 Register. + 0x124 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + AUTO_EN + Enable slot for automatic dynamic address assignment. + [13:13] + + + PID + Indicates how the last primary dynamic address value change occurred. + [31:14] + + + + + + + diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h new file mode 100644 index 00000000..d26b8710 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva_regs.h @@ -0,0 +1,1619 @@ +/** + * @file i3c_reva_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I3C_REVA Peripheral Module. + * @note This file is @generated. + * @ingroup i3c_reva_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_ +#define LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i3c_reva + * @defgroup i3c_reva_registers I3C_REVA_Registers + * @brief Registers, Bit Masks and Bit Positions for the I3C_REVA Peripheral Module. + * @details Improved Inter-Integrated Circuit. + */ + +/** + * @ingroup i3c_reva_registers + * Structure type to access the I3C_REVA Registers. + */ +typedef struct { + __IO uint32_t cont_ctrl0; /**< \b 0x000: I3C_REVA CONT_CTRL0 Register */ + __IO uint32_t targ_ctrl0; /**< \b 0x004: I3C_REVA TARG_CTRL0 Register */ + __IO uint32_t targ_status; /**< \b 0x008: I3C_REVA TARG_STATUS Register */ + __IO uint32_t targ_ctrl1; /**< \b 0x00C: I3C_REVA TARG_CTRL1 Register */ + __IO uint32_t targ_inten; /**< \b 0x010: I3C_REVA TARG_INTEN Register */ + __O uint32_t targ_intclr; /**< \b 0x014: I3C_REVA TARG_INTCLR Register */ + __I uint32_t targ_intfl; /**< \b 0x018: I3C_REVA TARG_INTFL Register */ + __IO uint32_t targ_errwarn; /**< \b 0x01C: I3C_REVA TARG_ERRWARN Register */ + __IO uint32_t targ_dmactrl; /**< \b 0x020: I3C_REVA TARG_DMACTRL Register */ + __R uint32_t rsv_0x24_0x2b[2]; + __IO uint32_t targ_fifoctrl; /**< \b 0x02C: I3C_REVA TARG_FIFOCTRL Register */ + __O uint32_t targ_txfifo8; /**< \b 0x030: I3C_REVA TARG_TXFIFO8 Register */ + __O uint32_t targ_txfifo8e; /**< \b 0x034: I3C_REVA TARG_TXFIFO8E Register */ + __O uint32_t targ_txfifo16; /**< \b 0x038: I3C_REVA TARG_TXFIFO16 Register */ + __O uint32_t targ_txfifo16e; /**< \b 0x03C: I3C_REVA TARG_TXFIFO16E Register */ + __I uint32_t targ_rxfifo8; /**< \b 0x040: I3C_REVA TARG_RXFIFO8 Register */ + __R uint32_t rsv_0x44; + __I uint32_t targ_rxfifo16; /**< \b 0x048: I3C_REVA TARG_RXFIFO16 Register */ + __R uint32_t rsv_0x4c_0x53[2]; + __O uint32_t targ_txfifo8o; /**< \b 0x054: I3C_REVA TARG_TXFIFO8O Register */ + __R uint32_t rsv_0x58; + __I uint32_t targ_cap0; /**< \b 0x05C: I3C_REVA TARG_CAP0 Register */ + __I uint32_t targ_cap1; /**< \b 0x060: I3C_REVA TARG_CAP1 Register */ + __IO uint32_t targ_dynaddr; /**< \b 0x064: I3C_REVA TARG_DYNADDR Register */ + __IO uint32_t targ_maxlimits; /**< \b 0x068: I3C_REVA TARG_MAXLIMITS Register */ + __R uint32_t rsv_0x6c; + __IO uint32_t targ_idext; /**< \b 0x070: I3C_REVA TARG_IDEXT Register */ + __R uint32_t rsv_0x74_0x7b[2]; + __I uint32_t targ_msglast; /**< \b 0x07C: I3C_REVA TARG_MSGLAST Register */ + __R uint32_t rsv_0x80; + __IO uint32_t cont_ctrl1; /**< \b 0x084: I3C_REVA CONT_CTRL1 Register */ + __IO uint32_t cont_status; /**< \b 0x088: I3C_REVA CONT_STATUS Register */ + __IO uint32_t cont_ibirules; /**< \b 0x08C: I3C_REVA CONT_IBIRULES Register */ + __IO uint32_t cont_inten; /**< \b 0x090: I3C_REVA CONT_INTEN Register */ + __O uint32_t cont_intclr; /**< \b 0x094: I3C_REVA CONT_INTCLR Register */ + __I uint32_t cont_intfl; /**< \b 0x098: I3C_REVA CONT_INTFL Register */ + __IO uint32_t cont_errwarn; /**< \b 0x09C: I3C_REVA CONT_ERRWARN Register */ + __IO uint32_t cont_dmactrl; /**< \b 0x0A0: I3C_REVA CONT_DMACTRL Register */ + __R uint32_t rsv_0xa4_0xab[2]; + __IO uint32_t cont_fifoctrl; /**< \b 0x0AC: I3C_REVA CONT_FIFOCTRL Register */ + __O uint32_t cont_txfifo8; /**< \b 0x0B0: I3C_REVA CONT_TXFIFO8 Register */ + __O uint32_t cont_txfifo8e; /**< \b 0x0B4: I3C_REVA CONT_TXFIFO8E Register */ + __O uint32_t cont_txfifo16; /**< \b 0x0B8: I3C_REVA CONT_TXFIFO16 Register */ + __O uint32_t cont_txfifo16e; /**< \b 0x0BC: I3C_REVA CONT_TXFIFO16E Register */ + __I uint32_t cont_rxfifo8; /**< \b 0x0C0: I3C_REVA CONT_RXFIFO8 Register */ + __R uint32_t rsv_0xc4; + __I uint32_t cont_rxfifo16; /**< \b 0x0C8: I3C_REVA CONT_RXFIFO16 Register */ + __O uint32_t cont_txfifo8o; /**< \b 0x0CC: I3C_REVA CONT_TXFIFO8O Register */ + union { + __IO uint32_t cont_txsdrmsg_ctrl; /**< \b 0x0D0: I3C_REVA CONT_TXSDRMSG_CTRL Register */ + __O uint32_t cont_txsdrmsg_fifo; /**< \b 0x0D0: I3C_REVA CONT_TXSDRMSG_FIFO Register */ + }; + __I uint32_t cont_rxsdrmsg; /**< \b 0x0D4: I3C_REVA CONT_RXSDRMSG Register */ + __O uint32_t cont_txddrmsg; /**< \b 0x0D8: I3C_REVA CONT_TXDDRMSG Register */ + __I uint32_t cont_rxddr16; /**< \b 0x0DC: I3C_REVA CONT_RXDDR16 Register */ + __R uint32_t rsv_0xe0; + __IO uint32_t cont_dynaddr; /**< \b 0x0E4: I3C_REVA CONT_DYNADDR Register */ + __R uint32_t rsv_0xe8_0x113[11]; + __I uint32_t targ_groupdef; /**< \b 0x114: I3C_REVA TARG_GROUPDEF Register */ + __R uint32_t rsv_0x118; + __IO uint32_t targ_mapctrl0; /**< \b 0x11C: I3C_REVA TARG_MAPCTRL0 Register */ + __IO uint32_t targ_mapctrl1; /**< \b 0x120: I3C_REVA TARG_MAPCTRL1 Register */ + __IO uint32_t targ_mapctrl2; /**< \b 0x124: I3C_REVA TARG_MAPCTRL2 Register */ +} mxc_i3c_reva_regs_t; + +/* Register offsets for module I3C_REVA */ +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_Register_Offsets Register Offsets + * @brief I3C_REVA Peripheral Register Offsets from the I3C_REVA Base Peripheral Address. + * @{ + */ +#define MXC_R_I3C_REVA_CONT_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I3C_REVA Base Address: 0x0000 */ +#define MXC_R_I3C_REVA_TARG_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from I3C_REVA Base Address: 0x0004 */ +#define MXC_R_I3C_REVA_TARG_STATUS ((uint32_t)0x00000008UL) /**< Offset from I3C_REVA Base Address: 0x0008 */ +#define MXC_R_I3C_REVA_TARG_CTRL1 ((uint32_t)0x0000000CUL) /**< Offset from I3C_REVA Base Address: 0x000C */ +#define MXC_R_I3C_REVA_TARG_INTEN ((uint32_t)0x00000010UL) /**< Offset from I3C_REVA Base Address: 0x0010 */ +#define MXC_R_I3C_REVA_TARG_INTCLR ((uint32_t)0x00000014UL) /**< Offset from I3C_REVA Base Address: 0x0014 */ +#define MXC_R_I3C_REVA_TARG_INTFL ((uint32_t)0x00000018UL) /**< Offset from I3C_REVA Base Address: 0x0018 */ +#define MXC_R_I3C_REVA_TARG_ERRWARN ((uint32_t)0x0000001CUL) /**< Offset from I3C_REVA Base Address: 0x001C */ +#define MXC_R_I3C_REVA_TARG_DMACTRL ((uint32_t)0x00000020UL) /**< Offset from I3C_REVA Base Address: 0x0020 */ +#define MXC_R_I3C_REVA_TARG_FIFOCTRL ((uint32_t)0x0000002CUL) /**< Offset from I3C_REVA Base Address: 0x002C */ +#define MXC_R_I3C_REVA_TARG_TXFIFO8 ((uint32_t)0x00000030UL) /**< Offset from I3C_REVA Base Address: 0x0030 */ +#define MXC_R_I3C_REVA_TARG_TXFIFO8E ((uint32_t)0x00000034UL) /**< Offset from I3C_REVA Base Address: 0x0034 */ +#define MXC_R_I3C_REVA_TARG_TXFIFO16 ((uint32_t)0x00000038UL) /**< Offset from I3C_REVA Base Address: 0x0038 */ +#define MXC_R_I3C_REVA_TARG_TXFIFO16E ((uint32_t)0x0000003CUL) /**< Offset from I3C_REVA Base Address: 0x003C */ +#define MXC_R_I3C_REVA_TARG_RXFIFO8 ((uint32_t)0x00000040UL) /**< Offset from I3C_REVA Base Address: 0x0040 */ +#define MXC_R_I3C_REVA_TARG_RXFIFO16 ((uint32_t)0x00000048UL) /**< Offset from I3C_REVA Base Address: 0x0048 */ +#define MXC_R_I3C_REVA_TARG_TXFIFO8O ((uint32_t)0x00000054UL) /**< Offset from I3C_REVA Base Address: 0x0054 */ +#define MXC_R_I3C_REVA_TARG_CAP0 ((uint32_t)0x0000005CUL) /**< Offset from I3C_REVA Base Address: 0x005C */ +#define MXC_R_I3C_REVA_TARG_CAP1 ((uint32_t)0x00000060UL) /**< Offset from I3C_REVA Base Address: 0x0060 */ +#define MXC_R_I3C_REVA_TARG_DYNADDR ((uint32_t)0x00000064UL) /**< Offset from I3C_REVA Base Address: 0x0064 */ +#define MXC_R_I3C_REVA_TARG_MAXLIMITS ((uint32_t)0x00000068UL) /**< Offset from I3C_REVA Base Address: 0x0068 */ +#define MXC_R_I3C_REVA_TARG_IDEXT ((uint32_t)0x00000070UL) /**< Offset from I3C_REVA Base Address: 0x0070 */ +#define MXC_R_I3C_REVA_TARG_MSGLAST ((uint32_t)0x0000007CUL) /**< Offset from I3C_REVA Base Address: 0x007C */ +#define MXC_R_I3C_REVA_CONT_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from I3C_REVA Base Address: 0x0084 */ +#define MXC_R_I3C_REVA_CONT_STATUS ((uint32_t)0x00000088UL) /**< Offset from I3C_REVA Base Address: 0x0088 */ +#define MXC_R_I3C_REVA_CONT_IBIRULES ((uint32_t)0x0000008CUL) /**< Offset from I3C_REVA Base Address: 0x008C */ +#define MXC_R_I3C_REVA_CONT_INTEN ((uint32_t)0x00000090UL) /**< Offset from I3C_REVA Base Address: 0x0090 */ +#define MXC_R_I3C_REVA_CONT_INTCLR ((uint32_t)0x00000094UL) /**< Offset from I3C_REVA Base Address: 0x0094 */ +#define MXC_R_I3C_REVA_CONT_INTFL ((uint32_t)0x00000098UL) /**< Offset from I3C_REVA Base Address: 0x0098 */ +#define MXC_R_I3C_REVA_CONT_ERRWARN ((uint32_t)0x0000009CUL) /**< Offset from I3C_REVA Base Address: 0x009C */ +#define MXC_R_I3C_REVA_CONT_DMACTRL ((uint32_t)0x000000A0UL) /**< Offset from I3C_REVA Base Address: 0x00A0 */ +#define MXC_R_I3C_REVA_CONT_FIFOCTRL ((uint32_t)0x000000ACUL) /**< Offset from I3C_REVA Base Address: 0x00AC */ +#define MXC_R_I3C_REVA_CONT_TXFIFO8 ((uint32_t)0x000000B0UL) /**< Offset from I3C_REVA Base Address: 0x00B0 */ +#define MXC_R_I3C_REVA_CONT_TXFIFO8E ((uint32_t)0x000000B4UL) /**< Offset from I3C_REVA Base Address: 0x00B4 */ +#define MXC_R_I3C_REVA_CONT_TXFIFO16 ((uint32_t)0x000000B8UL) /**< Offset from I3C_REVA Base Address: 0x00B8 */ +#define MXC_R_I3C_REVA_CONT_TXFIFO16E ((uint32_t)0x000000BCUL) /**< Offset from I3C_REVA Base Address: 0x00BC */ +#define MXC_R_I3C_REVA_CONT_RXFIFO8 ((uint32_t)0x000000C0UL) /**< Offset from I3C_REVA Base Address: 0x00C0 */ +#define MXC_R_I3C_REVA_CONT_RXFIFO16 ((uint32_t)0x000000C8UL) /**< Offset from I3C_REVA Base Address: 0x00C8 */ +#define MXC_R_I3C_REVA_CONT_TXFIFO8O ((uint32_t)0x000000CCUL) /**< Offset from I3C_REVA Base Address: 0x00CC */ +#define MXC_R_I3C_REVA_CONT_TXSDRMSG_CTRL ((uint32_t)0x000000D0UL) /**< Offset from I3C_REVA Base Address: 0x00D0 */ +#define MXC_R_I3C_REVA_CONT_TXSDRMSG_FIFO ((uint32_t)0x000000D0UL) /**< Offset from I3C_REVA Base Address: 0x00D0 */ +#define MXC_R_I3C_REVA_CONT_RXSDRMSG ((uint32_t)0x000000D4UL) /**< Offset from I3C_REVA Base Address: 0x00D4 */ +#define MXC_R_I3C_REVA_CONT_TXDDRMSG ((uint32_t)0x000000D8UL) /**< Offset from I3C_REVA Base Address: 0x00D8 */ +#define MXC_R_I3C_REVA_CONT_RXDDR16 ((uint32_t)0x000000DCUL) /**< Offset from I3C_REVA Base Address: 0x00DC */ +#define MXC_R_I3C_REVA_CONT_DYNADDR ((uint32_t)0x000000E4UL) /**< Offset from I3C_REVA Base Address: 0x00E4 */ +#define MXC_R_I3C_REVA_TARG_GROUPDEF ((uint32_t)0x00000114UL) /**< Offset from I3C_REVA Base Address: 0x0114 */ +#define MXC_R_I3C_REVA_TARG_MAPCTRL0 ((uint32_t)0x0000011CUL) /**< Offset from I3C_REVA Base Address: 0x011C */ +#define MXC_R_I3C_REVA_TARG_MAPCTRL1 ((uint32_t)0x00000120UL) /**< Offset from I3C_REVA Base Address: 0x0120 */ +#define MXC_R_I3C_REVA_TARG_MAPCTRL2 ((uint32_t)0x00000124UL) /**< Offset from I3C_REVA Base Address: 0x0124 */ +/**@} end of group i3c_reva_registers */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_CTRL0 I3C_REVA_CONT_CTRL0 + * @brief Controller Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_CTRL0_EN_POS 0 /**< CONT_CTRL0_EN Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS)) /**< CONT_CTRL0_EN Mask */ +#define MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_EN_OFF Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_EN_OFF (MXC_V_I3C_REVA_CONT_CTRL0_EN_OFF << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_OFF Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_EN_ON ((uint32_t)0x1UL) /**< CONT_CTRL0_EN_ON Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_EN_ON (MXC_V_I3C_REVA_CONT_CTRL0_EN_ON << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_ON Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_EN_CAP ((uint32_t)0x2UL) /**< CONT_CTRL0_EN_CAP Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_EN_CAP (MXC_V_I3C_REVA_CONT_CTRL0_EN_CAP << MXC_F_I3C_REVA_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_CAP Setting */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS_POS 3 /**< CONT_CTRL0_TO_DIS Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_TO_DIS_POS)) /**< CONT_CTRL0_TO_DIS Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS 4 /**< CONT_CTRL0_HKEEP Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_HKEEP ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS)) /**< CONT_CTRL0_HKEEP Mask */ +#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_HKEEP_OFF Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_OFF (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_OFF << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_OFF Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP ((uint32_t)0x1UL) /**< CONT_CTRL0_HKEEP_ON_CHIP Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_ON_CHIP << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_ON_CHIP Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA ((uint32_t)0x2UL) /**< CONT_CTRL0_HKEEP_EXT_SDA Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SDA << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SDA Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA ((uint32_t)0x3UL) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA (MXC_V_I3C_REVA_CONT_CTRL0_HKEEP_EXT_SCL_SDA << MXC_F_I3C_REVA_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Setting */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP_POS 6 /**< CONT_CTRL0_OD_STOP Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_OD_STOP_POS)) /**< CONT_CTRL0_OD_STOP Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS 8 /**< CONT_CTRL0_PP_BAUD Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS)) /**< CONT_CTRL0_PP_BAUD Mask */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_BAUD_1_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_1_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_1_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_BAUD_2_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_2_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_2_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_BAUD_3_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_3_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_3_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_BAUD_4_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_4_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_4_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_BAUD_5_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_5_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_5_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_BAUD_6_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_6_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_6_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_BAUD_7_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_7_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_7_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_BAUD_8_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_8_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_8_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_BAUD_9_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_9_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_9_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_BAUD_10_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_10_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_10_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_BAUD_11_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_11_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_11_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_BAUD_12_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_12_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_12_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_BAUD_13_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_13_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_13_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_BAUD_14_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_14_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_14_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_BAUD_15_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_15_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_15_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_BAUD_16_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_BAUD_16_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_16_FCLK Setting */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS 12 /**< CONT_CTRL0_PP_ADD_LBAUD Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS)) /**< CONT_CTRL0_PP_ADD_LBAUD Mask */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK (MXC_V_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK << MXC_F_I3C_REVA_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Setting */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS 16 /**< CONT_CTRL0_OD_LBAUD Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_CTRL0_OD_LBAUD_POS)) /**< CONT_CTRL0_OD_LBAUD Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS 24 /**< CONT_CTRL0_OD_HP Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_OD_HP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL0_OD_HP_POS)) /**< CONT_CTRL0_OD_HP Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS 25 /**< CONT_CTRL0_PP_SKEW Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_CTRL0_PP_SKEW_POS)) /**< CONT_CTRL0_PP_SKEW Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS 28 /**< CONT_CTRL0_I2C_BAUD Position */ +#define MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_REVA_CONT_CTRL0_I2C_BAUD_POS)) /**< CONT_CTRL0_I2C_BAUD Mask */ + +/**@} end of group I3C_REVA_CONT_CTRL0_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_CTRL0 I3C_REVA_TARG_CTRL0 + * @brief Target Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_CTRL0_EN_POS 0 /**< TARG_CTRL0_EN Position */ +#define MXC_F_I3C_REVA_TARG_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_EN_POS)) /**< TARG_CTRL0_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS_POS 2 /**< TARG_CTRL0_MATCHSS Position */ +#define MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_MATCHSS_POS)) /**< TARG_CTRL0_MATCHSS Mask */ + +#define MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN_POS 3 /**< TARG_CTRL0_TO_IGN Position */ +#define MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_TO_IGN_POS)) /**< TARG_CTRL0_TO_IGN Mask */ + +#define MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE_POS 9 /**< TARG_CTRL0_OFFLINE Position */ +#define MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL0_OFFLINE_POS)) /**< TARG_CTRL0_OFFLINE Mask */ + +/**@} end of group I3C_REVA_TARG_CTRL0_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_STATUS I3C_REVA_TARG_STATUS + * @brief Target Status Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_STATUS_BUSY_POS 0 /**< TARG_STATUS_BUSY Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_BUSY_POS)) /**< TARG_STATUS_BUSY Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP_POS 1 /**< TARG_STATUS_LIST_RESP Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_LIST_RESP_POS)) /**< TARG_STATUS_LIST_RESP Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_POS 2 /**< TARG_STATUS_CCCH Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_CCCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCCH_POS)) /**< TARG_STATUS_CCCH Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_RX_SDR_POS 3 /**< TARG_STATUS_RX_SDR Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_RX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_RX_SDR_POS)) /**< TARG_STATUS_RX_SDR Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_TX_SDR_POS 4 /**< TARG_STATUS_TX_SDR Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_TX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TX_SDR_POS)) /**< TARG_STATUS_TX_SDR Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_DAA_POS 5 /**< TARG_STATUS_DAA Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_DAA ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_DAA_POS)) /**< TARG_STATUS_DAA Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_HDR_POS 6 /**< TARG_STATUS_HDR Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_HDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_HDR_POS)) /**< TARG_STATUS_HDR Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_START_POS 8 /**< TARG_STATUS_START Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_START_POS)) /**< TARG_STATUS_START Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH_POS 9 /**< TARG_STATUS_ADDRMATCH Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_ADDRMATCH_POS)) /**< TARG_STATUS_ADDRMATCH Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_STOP_POS 10 /**< TARG_STATUS_STOP Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_STOP_POS)) /**< TARG_STATUS_STOP Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_RX_RDY_POS 11 /**< TARG_STATUS_RX_RDY Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_RX_RDY_POS)) /**< TARG_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL_POS 12 /**< TARG_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TX_NFULL_POS)) /**< TARG_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG_POS 13 /**< TARG_STATUS_DYNADDR_CHG Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_DYNADDR_CHG_POS)) /**< TARG_STATUS_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_CCC_POS 14 /**< TARG_STATUS_CCC Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCC_POS)) /**< TARG_STATUS_CCC Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_ERRWARN_POS 15 /**< TARG_STATUS_ERRWARN Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_ERRWARN_POS)) /**< TARG_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE_POS 17 /**< TARG_STATUS_CCCH_DONE Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CCCH_DONE_POS)) /**< TARG_STATUS_CCCH_DONE Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ_POS 18 /**< TARG_STATUS_EVENT_REQ Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_EVENT_REQ_POS)) /**< TARG_STATUS_EVENT_REQ Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_TARG_RST_POS 19 /**< TARG_STATUS_TARG_RST Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_TARG_RST_POS)) /**< TARG_STATUS_TARG_RST Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS 20 /**< TARG_STATUS_EVENT Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS)) /**< TARG_STATUS_EVENT Mask */ +#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_NONE ((uint32_t)0x0UL) /**< TARG_STATUS_EVENT_NONE Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_NONE (MXC_V_I3C_REVA_TARG_STATUS_EVENT_NONE << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_NONE Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND ((uint32_t)0x1UL) /**< TARG_STATUS_EVENT_REQ_PEND Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_PEND << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_PEND Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK ((uint32_t)0x2UL) /**< TARG_STATUS_EVENT_REQ_NACK Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_NACK << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_NACK Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK ((uint32_t)0x3UL) /**< TARG_STATUS_EVENT_REQ_ACK Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK (MXC_V_I3C_REVA_TARG_STATUS_EVENT_REQ_ACK << MXC_F_I3C_REVA_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_ACK Setting */ + +#define MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS_POS 24 /**< TARG_STATUS_IBI_DIS Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_IBI_DIS_POS)) /**< TARG_STATUS_IBI_DIS Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS_POS 25 /**< TARG_STATUS_CONTREQ_DIS Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_CONTREQ_DIS_POS)) /**< TARG_STATUS_CONTREQ_DIS Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS_POS 27 /**< TARG_STATUS_HJ_DIS Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_STATUS_HJ_DIS_POS)) /**< TARG_STATUS_HJ_DIS Mask */ + +#define MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS 28 /**< TARG_STATUS_ACTSTATE Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS)) /**< TARG_STATUS_ACTSTATE Mask */ +#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL ((uint32_t)0x0UL) /**< TARG_STATUS_ACTSTATE_NORMAL Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_NORMAL << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_NORMAL Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT ((uint32_t)0x1UL) /**< TARG_STATUS_ACTSTATE_1MS_LAT Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_1MS_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_1MS_LAT Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT ((uint32_t)0x2UL) /**< TARG_STATUS_ACTSTATE_100MS_LAT Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_100MS_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_100MS_LAT Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT ((uint32_t)0x3UL) /**< TARG_STATUS_ACTSTATE_10S_LAT Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT (MXC_V_I3C_REVA_TARG_STATUS_ACTSTATE_10S_LAT << MXC_F_I3C_REVA_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_10S_LAT Setting */ + +#define MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS 30 /**< TARG_STATUS_TIMECTRL Position */ +#define MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS)) /**< TARG_STATUS_TIMECTRL Mask */ +#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_DIS ((uint32_t)0x0UL) /**< TARG_STATUS_TIMECTRL_DIS Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_DIS (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_DIS << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_DIS Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC ((uint32_t)0x1UL) /**< TARG_STATUS_TIMECTRL_SYNC Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_SYNC << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_SYNC Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC ((uint32_t)0x2UL) /**< TARG_STATUS_TIMECTRL_ASYNC Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_ASYNC << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_ASYNC Setting */ +#define MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH ((uint32_t)0x3UL) /**< TARG_STATUS_TIMECTRL_BOTH Value */ +#define MXC_S_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH (MXC_V_I3C_REVA_TARG_STATUS_TIMECTRL_BOTH << MXC_F_I3C_REVA_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_BOTH Setting */ + +/**@} end of group I3C_REVA_TARG_STATUS_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_CTRL1 I3C_REVA_TARG_CTRL1 + * @brief Target Control 1 Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS 0 /**< TARG_CTRL1_EVENT Position */ +#define MXC_F_I3C_REVA_TARG_CTRL1_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS)) /**< TARG_CTRL1_EVENT Mask */ +#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_NORMAL ((uint32_t)0x0UL) /**< TARG_CTRL1_EVENT_NORMAL Value */ +#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_NORMAL (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_NORMAL << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_NORMAL Setting */ +#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI ((uint32_t)0x1UL) /**< TARG_CTRL1_EVENT_IBI Value */ +#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_IBI (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_IBI << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_IBI Setting */ +#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ ((uint32_t)0x2UL) /**< TARG_CTRL1_EVENT_CONTREQ Value */ +#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_CONTREQ << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_CONTREQ Setting */ +#define MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ ((uint32_t)0x3UL) /**< TARG_CTRL1_EVENT_HJ Value */ +#define MXC_S_I3C_REVA_TARG_CTRL1_EVENT_HJ (MXC_V_I3C_REVA_TARG_CTRL1_EVENT_HJ << MXC_F_I3C_REVA_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_HJ Setting */ + +#define MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI_POS 3 /**< TARG_CTRL1_EXTIBI Position */ +#define MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CTRL1_EXTIBI_POS)) /**< TARG_CTRL1_EXTIBI Mask */ + +#define MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX_POS 4 /**< TARG_CTRL1_DYNADDR_IDX Position */ +#define MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CTRL1_DYNADDR_IDX_POS)) /**< TARG_CTRL1_DYNADDR_IDX Mask */ + +#define MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA_POS 8 /**< TARG_CTRL1_IBIDATA Position */ +#define MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_CTRL1_IBIDATA_POS)) /**< TARG_CTRL1_IBIDATA Mask */ + +/**@} end of group I3C_REVA_TARG_CTRL1_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_INTEN I3C_REVA_TARG_INTEN + * @brief Target Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_INTEN_START_POS 8 /**< TARG_INTEN_START Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_START_POS)) /**< TARG_INTEN_START Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH_POS 9 /**< TARG_INTEN_ADDRMATCH Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_ADDRMATCH_POS)) /**< TARG_INTEN_ADDRMATCH Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_STOP_POS 10 /**< TARG_INTEN_STOP Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_STOP_POS)) /**< TARG_INTEN_STOP Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_RX_RDY_POS 11 /**< TARG_INTEN_RX_RDY Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_RX_RDY_POS)) /**< TARG_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL_POS 12 /**< TARG_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_TX_NFULL_POS)) /**< TARG_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG_POS 13 /**< TARG_INTEN_DYNADDR_CHG Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_DYNADDR_CHG_POS)) /**< TARG_INTEN_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_CCC_POS 14 /**< TARG_INTEN_CCC Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_CCC_POS)) /**< TARG_INTEN_CCC Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_ERRWARN_POS 15 /**< TARG_INTEN_ERRWARN Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_ERRWARN_POS)) /**< TARG_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE_POS 17 /**< TARG_INTEN_CCCH_DONE Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_CCCH_DONE_POS)) /**< TARG_INTEN_CCCH_DONE Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ_POS 18 /**< TARG_INTEN_EVENT_REQ Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_EVENT_REQ_POS)) /**< TARG_INTEN_EVENT_REQ Mask */ + +#define MXC_F_I3C_REVA_TARG_INTEN_TARG_RST_POS 19 /**< TARG_INTEN_TARG_RST Position */ +#define MXC_F_I3C_REVA_TARG_INTEN_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTEN_TARG_RST_POS)) /**< TARG_INTEN_TARG_RST Mask */ + +/**@} end of group I3C_REVA_TARG_INTEN_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_INTCLR I3C_REVA_TARG_INTCLR + * @brief Target Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_INTCLR_START_POS 8 /**< TARG_INTCLR_START Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_START_POS)) /**< TARG_INTCLR_START Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH_POS 9 /**< TARG_INTCLR_ADDRMATCH Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_ADDRMATCH_POS)) /**< TARG_INTCLR_ADDRMATCH Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_STOP_POS 10 /**< TARG_INTCLR_STOP Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_STOP_POS)) /**< TARG_INTCLR_STOP Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY_POS 11 /**< TARG_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_RX_RDY_POS)) /**< TARG_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL_POS 12 /**< TARG_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_TX_NFULL_POS)) /**< TARG_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG_POS 13 /**< TARG_INTCLR_DYNADDR_CHG Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_DYNADDR_CHG_POS)) /**< TARG_INTCLR_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_CCC_POS 14 /**< TARG_INTCLR_CCC Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_CCC_POS)) /**< TARG_INTCLR_CCC Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN_POS 15 /**< TARG_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_ERRWARN_POS)) /**< TARG_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE_POS 17 /**< TARG_INTCLR_CCCH_DONE Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_CCCH_DONE_POS)) /**< TARG_INTCLR_CCCH_DONE Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ_POS 18 /**< TARG_INTCLR_EVENT_REQ Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_EVENT_REQ_POS)) /**< TARG_INTCLR_EVENT_REQ Mask */ + +#define MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST_POS 19 /**< TARG_INTCLR_TARG_RST Position */ +#define MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTCLR_TARG_RST_POS)) /**< TARG_INTCLR_TARG_RST Mask */ + +/**@} end of group I3C_REVA_TARG_INTCLR_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_INTFL I3C_REVA_TARG_INTFL + * @brief Target Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_INTFL_START_POS 8 /**< TARG_INTFL_START Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_START_POS)) /**< TARG_INTFL_START Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH_POS 9 /**< TARG_INTFL_ADDRMATCH Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_ADDRMATCH_POS)) /**< TARG_INTFL_ADDRMATCH Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_STOP_POS 10 /**< TARG_INTFL_STOP Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_STOP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_STOP_POS)) /**< TARG_INTFL_STOP Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_RX_RDY_POS 11 /**< TARG_INTFL_RX_RDY Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_RX_RDY_POS)) /**< TARG_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL_POS 12 /**< TARG_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_TX_NFULL_POS)) /**< TARG_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG_POS 13 /**< TARG_INTFL_DYNADDR_CHG Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_DYNADDR_CHG_POS)) /**< TARG_INTFL_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_CCC_POS 14 /**< TARG_INTFL_CCC Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_CCC_POS)) /**< TARG_INTFL_CCC Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_ERRWARN_POS 15 /**< TARG_INTFL_ERRWARN Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_ERRWARN_POS)) /**< TARG_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE_POS 17 /**< TARG_INTFL_CCCH_DONE Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_CCCH_DONE_POS)) /**< TARG_INTFL_CCCH_DONE Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ_POS 18 /**< TARG_INTFL_EVENT_REQ Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_EVENT_REQ_POS)) /**< TARG_INTFL_EVENT_REQ Mask */ + +#define MXC_F_I3C_REVA_TARG_INTFL_TARG_RST_POS 19 /**< TARG_INTFL_TARG_RST Position */ +#define MXC_F_I3C_REVA_TARG_INTFL_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_INTFL_TARG_RST_POS)) /**< TARG_INTFL_TARG_RST Mask */ + +/**@} end of group I3C_REVA_TARG_INTFL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_ERRWARN I3C_REVA_TARG_ERRWARN + * @brief Target Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_OVR_POS 0 /**< TARG_ERRWARN_OVR Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_OVR_POS)) /**< TARG_ERRWARN_OVR Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_POS 1 /**< TARG_ERRWARN_UNR Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_UNR_POS)) /**< TARG_ERRWARN_UNR Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK_POS 2 /**< TARG_ERRWARN_UNR_NACK Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_UNR_NACK_POS)) /**< TARG_ERRWARN_UNR_NACK Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM_POS 3 /**< TARG_ERRWARN_CONT_RX_TERM Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_CONT_RX_TERM_POS)) /**< TARG_ERRWARN_CONT_RX_TERM Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART_POS 4 /**< TARG_ERRWARN_INVSTART Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_INVSTART_POS)) /**< TARG_ERRWARN_INVSTART Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR_POS 8 /**< TARG_ERRWARN_SDR_PAR Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_SDR_PAR_POS)) /**< TARG_ERRWARN_SDR_PAR Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_TO_POS 11 /**< TARG_ERRWARN_TO Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_TO_POS)) /**< TARG_ERRWARN_TO Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR_POS 16 /**< TARG_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_RX_UNR_POS)) /**< TARG_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR_POS 17 /**< TARG_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_ERRWARN_TX_OVR_POS)) /**< TARG_ERRWARN_TX_OVR Mask */ + +/**@} end of group I3C_REVA_TARG_ERRWARN_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_DMACTRL I3C_REVA_TARG_DMACTRL + * @brief Target DMA Control Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS 0 /**< TARG_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS)) /**< TARG_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_DIS (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_DIS << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_RX_EN_EN (MXC_V_I3C_REVA_TARG_DMACTRL_RX_EN_EN << MXC_F_I3C_REVA_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS 2 /**< TARG_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS)) /**< TARG_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_DIS (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_DIS << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_TX_EN_EN (MXC_V_I3C_REVA_TARG_DMACTRL_TX_EN_EN << MXC_F_I3C_REVA_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS 4 /**< TARG_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS)) /**< TARG_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< TARG_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE (MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_BYTE << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< TARG_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_REVA_TARG_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_REVA_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_REVA_TARG_DMACTRL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_FIFOCTRL I3C_REVA_TARG_FIFOCTRL + * @brief Target FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH_POS 0 /**< TARG_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FLUSH_POS)) /**< TARG_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH_POS 1 /**< TARG_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_FLUSH_POS)) /**< TARG_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK_POS 3 /**< TARG_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_UNLOCK_POS)) /**< TARG_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS 4 /**< TARG_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS)) /**< TARG_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS 6 /**< TARG_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS)) /**< TARG_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL_POS 16 /**< TARG_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_LVL_POS)) /**< TARG_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL_POS 24 /**< TARG_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_LVL_POS)) /**< TARG_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL_POS 30 /**< TARG_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_TX_FULL_POS)) /**< TARG_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM_POS 31 /**< TARG_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_FIFOCTRL_RX_EM_POS)) /**< TARG_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_REVA_TARG_FIFOCTRL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_TXFIFO8 I3C_REVA_TARG_TXFIFO8 + * @brief Target Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8_DATA_POS 0 /**< TARG_TXFIFO8_DATA Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8_DATA_POS)) /**< TARG_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_REVA_TARG_TXFIFO8_END_POS 8 /**< TARG_TXFIFO8_END Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO8_END_POS)) /**< TARG_TXFIFO8_END Mask */ + +#define MXC_F_I3C_REVA_TARG_TXFIFO8_END2_POS 16 /**< TARG_TXFIFO8_END2 Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO8_END2_POS)) /**< TARG_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_REVA_TARG_TXFIFO8_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_TXFIFO8E I3C_REVA_TARG_TXFIFO8E + * @brief Target Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA_POS 0 /**< TARG_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8E_DATA_POS)) /**< TARG_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_REVA_TARG_TXFIFO8E_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_TXFIFO16 I3C_REVA_TARG_TXFIFO16 + * @brief Target Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_TXFIFO16_DATA_POS 0 /**< TARG_TXFIFO16_DATA Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_TXFIFO16_DATA_POS)) /**< TARG_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_REVA_TARG_TXFIFO16_END_POS 16 /**< TARG_TXFIFO16_END Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_TXFIFO16_END_POS)) /**< TARG_TXFIFO16_END Mask */ + +/**@} end of group I3C_REVA_TARG_TXFIFO16_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_TXFIFO16E I3C_REVA_TARG_TXFIFO16E + * @brief Target Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA_POS 0 /**< TARG_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_TXFIFO16E_DATA_POS)) /**< TARG_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_REVA_TARG_TXFIFO16E_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_RXFIFO8 I3C_REVA_TARG_RXFIFO8 + * @brief Target Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_RXFIFO8_DATA_POS 0 /**< TARG_RXFIFO8_DATA Position */ +#define MXC_F_I3C_REVA_TARG_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_RXFIFO8_DATA_POS)) /**< TARG_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_REVA_TARG_RXFIFO8_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_RXFIFO16 I3C_REVA_TARG_RXFIFO16 + * @brief Target Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_RXFIFO16_DATA_POS 0 /**< TARG_RXFIFO16_DATA Position */ +#define MXC_F_I3C_REVA_TARG_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_TARG_RXFIFO16_DATA_POS)) /**< TARG_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_REVA_TARG_RXFIFO16_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_TXFIFO8O I3C_REVA_TARG_TXFIFO8O + * @brief Target Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA_POS 0 /**< TARG_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_TXFIFO8O_DATA_POS)) /**< TARG_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_REVA_TARG_TXFIFO8O_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_CAP0 I3C_REVA_TARG_CAP0 + * @brief Target Capabilities 0 Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_CAP0_MAPCNT_POS 0 /**< TARG_CAP0_MAPCNT Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_MAPCNT ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP0_MAPCNT_POS)) /**< TARG_CAP0_MAPCNT Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR_POS 4 /**< TARG_CAP0_I2C_10BADDR Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_10BADDR_POS)) /**< TARG_CAP0_I2C_10BADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST_POS 5 /**< TARG_CAP0_I2C_SWRST Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_SWRST_POS)) /**< TARG_CAP0_I2C_SWRST Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID_POS 6 /**< TARG_CAP0_I2C_DEVID Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_I2C_DEVID_POS)) /**< TARG_CAP0_I2C_DEVID Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG_POS 7 /**< TARG_CAP0_FIFO32_REG Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_FIFO32_REG_POS)) /**< TARG_CAP0_FIFO32_REG Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_POS 8 /**< TARG_CAP0_EXTIBI Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_POS)) /**< TARG_CAP0_EXTIBI Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG_POS 9 /**< TARG_CAP0_EXTIBI_REG Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_EXTIBI_REG_POS)) /**< TARG_CAP0_EXTIBI_REG Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES_POS 12 /**< TARG_CAP0_HDRBT_LANES Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP0_HDRBT_LANES_POS)) /**< TARG_CAP0_HDRBT_LANES Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1_POS 16 /**< TARG_CAP0_CCC_V1_1 Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_CCC_V1_1_POS)) /**< TARG_CAP0_CCC_V1_1 Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_TARG_RST_POS 17 /**< TARG_CAP0_TARG_RST Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_TARG_RST_POS)) /**< TARG_CAP0_TARG_RST Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR_POS 18 /**< TARG_CAP0_GROUPADDR Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP0_GROUPADDR_POS)) /**< TARG_CAP0_GROUPADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC_POS 21 /**< TARG_CAP0_AASA_CCC Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_AASA_CCC_POS)) /**< TARG_CAP0_AASA_CCC Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC_POS 22 /**< TARG_CAP0_T2T_SUBSC Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_T2T_SUBSC_POS)) /**< TARG_CAP0_T2T_SUBSC Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP0_T2T_WR_POS 23 /**< TARG_CAP0_T2T_WR Position */ +#define MXC_F_I3C_REVA_TARG_CAP0_T2T_WR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP0_T2T_WR_POS)) /**< TARG_CAP0_T2T_WR Mask */ + +/**@} end of group I3C_REVA_TARG_CAP0_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_CAP1 I3C_REVA_TARG_CAP1 + * @brief TARG_Capabilities 1 Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_POS 0 /**< TARG_CAP1_PROVID Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_PROVID ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_PROVID_POS)) /**< TARG_CAP1_PROVID Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG_POS 2 /**< TARG_CAP1_PROVID_REG Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP1_PROVID_REG_POS)) /**< TARG_CAP1_PROVID_REG Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES_POS 6 /**< TARG_CAP1_HDR_MODES Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_CAP1_HDR_MODES_POS)) /**< TARG_CAP1_HDR_MODES Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_CONT_POS 9 /**< TARG_CAP1_CONT Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_CONT_POS)) /**< TARG_CAP1_CONT Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_STATADDR_POS 10 /**< TARG_CAP1_STATADDR Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_STATADDR ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_STATADDR_POS)) /**< TARG_CAP1_STATADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS 12 /**< TARG_CAP1_CCCH Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_CCCH ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS)) /**< TARG_CAP1_CCCH Mask */ +#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_BASIC ((uint32_t)0x1UL) /**< TARG_CAP1_CCCH_BASIC Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_BASIC (MXC_V_I3C_REVA_TARG_CAP1_CCCH_BASIC << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_BASIC Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_LIMITS ((uint32_t)0x2UL) /**< TARG_CAP1_CCCH_LIMITS Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_LIMITS (MXC_V_I3C_REVA_TARG_CAP1_CCCH_LIMITS << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_LIMITS Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_INTACT ((uint32_t)0x4UL) /**< TARG_CAP1_CCCH_INTACT Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_INTACT (MXC_V_I3C_REVA_TARG_CAP1_CCCH_INTACT << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_INTACT Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_CCCH_VENDOR ((uint32_t)0x8UL) /**< TARG_CAP1_CCCH_VENDOR Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_CCCH_VENDOR (MXC_V_I3C_REVA_TARG_CAP1_CCCH_VENDOR << MXC_F_I3C_REVA_TARG_CAP1_CCCH_POS) /**< TARG_CAP1_CCCH_VENDOR Setting */ + +#define MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS 16 /**< TARG_CAP1_IBI_EVENTS Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS ((uint32_t)(0x1FUL << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS)) /**< TARG_CAP1_IBI_EVENTS Mask */ +#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI ((uint32_t)0x1UL) /**< TARG_CAP1_IBI_EVENTS_IBI Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_IBI << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_IBI Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD ((uint32_t)0x2UL) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_PAYLOAD << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_PAYLOAD Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ ((uint32_t)0x4UL) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_CONTREQ << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_CONTREQ Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ ((uint32_t)0x8UL) /**< TARG_CAP1_IBI_EVENTS_HJ Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_HJ << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_HJ Setting */ +#define MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH ((uint32_t)0x10UL) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Value */ +#define MXC_S_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH (MXC_V_I3C_REVA_TARG_CAP1_IBI_EVENTS_BAMATCH << MXC_F_I3C_REVA_TARG_CAP1_IBI_EVENTS_POS) /**< TARG_CAP1_IBI_EVENTS_BAMATCH Setting */ + +#define MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL_POS 21 /**< TARG_CAP1_TIMECTRL Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_TIMECTRL_POS)) /**< TARG_CAP1_TIMECTRL Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO_POS 23 /**< TARG_CAP1_EXTFIFO Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_CAP1_EXTFIFO_POS)) /**< TARG_CAP1_EXTFIFO Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG_POS 26 /**< TARG_CAP1_TXFIFO_CFG Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_TXFIFO_CFG_POS)) /**< TARG_CAP1_TXFIFO_CFG Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG_POS 28 /**< TARG_CAP1_RXFIFO_CFG Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_CAP1_RXFIFO_CFG_POS)) /**< TARG_CAP1_RXFIFO_CFG Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_INTR_POS 30 /**< TARG_CAP1_INTR Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_INTR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_INTR_POS)) /**< TARG_CAP1_INTR Mask */ + +#define MXC_F_I3C_REVA_TARG_CAP1_DMA_POS 31 /**< TARG_CAP1_DMA Position */ +#define MXC_F_I3C_REVA_TARG_CAP1_DMA ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_CAP1_DMA_POS)) /**< TARG_CAP1_DMA Mask */ + +/**@} end of group I3C_REVA_TARG_CAP1_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_DYNADDR I3C_REVA_TARG_DYNADDR + * @brief Target Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_DYNADDR_VALID_POS 0 /**< TARG_DYNADDR_VALID Position */ +#define MXC_F_I3C_REVA_TARG_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_DYNADDR_VALID_POS)) /**< TARG_DYNADDR_VALID Mask */ + +#define MXC_F_I3C_REVA_TARG_DYNADDR_ADDR_POS 1 /**< TARG_DYNADDR_ADDR Position */ +#define MXC_F_I3C_REVA_TARG_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_DYNADDR_ADDR_POS)) /**< TARG_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE_POS 8 /**< TARG_DYNADDR_CAUSE Position */ +#define MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_DYNADDR_CAUSE_POS)) /**< TARG_DYNADDR_CAUSE Mask */ + +/**@} end of group I3C_REVA_TARG_DYNADDR_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_MAXLIMITS I3C_REVA_TARG_MAXLIMITS + * @brief Maximum Limits Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_MAXLIMITS_RX_POS 0 /**< TARG_MAXLIMITS_RX Position */ +#define MXC_F_I3C_REVA_TARG_MAXLIMITS_RX ((uint32_t)(0xFFFUL << MXC_F_I3C_REVA_TARG_MAXLIMITS_RX_POS)) /**< TARG_MAXLIMITS_RX Mask */ + +#define MXC_F_I3C_REVA_TARG_MAXLIMITS_TX_POS 16 /**< TARG_MAXLIMITS_TX Position */ +#define MXC_F_I3C_REVA_TARG_MAXLIMITS_TX ((uint32_t)(0xFFFUL << MXC_F_I3C_REVA_TARG_MAXLIMITS_TX_POS)) /**< TARG_MAXLIMITS_TX Mask */ + +/**@} end of group I3C_REVA_TARG_MAXLIMITS_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_IDEXT I3C_REVA_TARG_IDEXT + * @brief ID Extension Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR_POS 8 /**< TARG_IDEXT_DEVCHAR Position */ +#define MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_IDEXT_DEVCHAR_POS)) /**< TARG_IDEXT_DEVCHAR Mask */ + +#define MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR_POS 16 /**< TARG_IDEXT_BUSCHAR Position */ +#define MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_TARG_IDEXT_BUSCHAR_POS)) /**< TARG_IDEXT_BUSCHAR Mask */ + +/**@} end of group I3C_REVA_TARG_IDEXT_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_MSGLAST I3C_REVA_TARG_MSGLAST + * @brief Target Matching Address Index Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_IDX_POS 0 /**< TARG_MSGLAST_IDX Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_IDX_POS)) /**< TARG_MSGLAST_IDX Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR_POS 4 /**< TARG_MSGLAST_STATADDR Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_STATADDR_POS)) /**< TARG_MSGLAST_STATADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_GROUP_POS 5 /**< TARG_MSGLAST_GROUP Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_GROUP_POS)) /**< TARG_MSGLAST_GROUP Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS 6 /**< TARG_MSGLAST_MODE Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS)) /**< TARG_MSGLAST_MODE Mask */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_MODE_HDR_DDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_MODE_HDR_BT Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX_POS 8 /**< TARG_MSGLAST_PREV_IDX Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_IDX_POS)) /**< TARG_MSGLAST_PREV_IDX Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP_POS 13 /**< TARG_MSGLAST_PREV_GROUP Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_GROUP_POS)) /**< TARG_MSGLAST_PREV_GROUP Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS 14 /**< TARG_MSGLAST_PREV_MODE Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS)) /**< TARG_MSGLAST_PREV_MODE Mask */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_PREV_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX_POS 16 /**< TARG_MSGLAST_SECPREV_IDX Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_IDX_POS)) /**< TARG_MSGLAST_SECPREV_IDX Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP_POS 21 /**< TARG_MSGLAST_SECPREV_GROUP Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_GROUP_POS)) /**< TARG_MSGLAST_SECPREV_GROUP Mask */ + +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS 22 /**< TARG_MSGLAST_SECPREV_MODE Position */ +#define MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS)) /**< TARG_MSGLAST_SECPREV_MODE Mask */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_DDR << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT (MXC_V_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_HDR_BT << MXC_F_I3C_REVA_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Setting */ + +/**@} end of group I3C_REVA_TARG_MSGLAST_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_CTRL1 I3C_REVA_CONT_CTRL1 + * @brief Controller Control 1 Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS 0 /**< CONT_CTRL1_REQ Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_REQ ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS)) /**< CONT_CTRL1_REQ Mask */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_NONE ((uint32_t)0x0UL) /**< CONT_CTRL1_REQ_NONE Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_NONE (MXC_V_I3C_REVA_CONT_CTRL1_REQ_NONE << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_NONE Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START ((uint32_t)0x1UL) /**< CONT_CTRL1_REQ_EMIT_START Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_START (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_START << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_START Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP ((uint32_t)0x2UL) /**< CONT_CTRL1_REQ_EMIT_STOP Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EMIT_STOP << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_STOP Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK ((uint32_t)0x3UL) /**< CONT_CTRL1_REQ_IBI_ACKNACK Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK (MXC_V_I3C_REVA_CONT_CTRL1_REQ_IBI_ACKNACK << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_IBI_ACKNACK Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA ((uint32_t)0x4UL) /**< CONT_CTRL1_REQ_PROCESS_DAA Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA (MXC_V_I3C_REVA_CONT_CTRL1_REQ_PROCESS_DAA << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_PROCESS_DAA Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST ((uint32_t)0x6UL) /**< CONT_CTRL1_REQ_EXIT_RST Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST (MXC_V_I3C_REVA_CONT_CTRL1_REQ_EXIT_RST << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EXIT_RST Setting */ +#define MXC_V_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI ((uint32_t)0x7UL) /**< CONT_CTRL1_REQ_AUTO_IBI Value */ +#define MXC_S_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI (MXC_V_I3C_REVA_CONT_CTRL1_REQ_AUTO_IBI << MXC_F_I3C_REVA_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_AUTO_IBI Setting */ + +#define MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS 4 /**< CONT_CTRL1_TYPE Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_TYPE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL1_TYPE_POS)) /**< CONT_CTRL1_TYPE Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS 6 /**< CONT_CTRL1_IBIRESP Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_CTRL1_IBIRESP_POS)) /**< CONT_CTRL1_IBIRESP Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR_POS 8 /**< CONT_CTRL1_RDWR_DIR Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_CTRL1_RDWR_DIR_POS)) /**< CONT_CTRL1_RDWR_DIR Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL1_ADDR_POS 9 /**< CONT_CTRL1_ADDR Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_CTRL1_ADDR_POS)) /**< CONT_CTRL1_ADDR Mask */ + +#define MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD_POS 16 /**< CONT_CTRL1_TERM_RD Position */ +#define MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_CTRL1_TERM_RD_POS)) /**< CONT_CTRL1_TERM_RD Mask */ + +/**@} end of group I3C_REVA_CONT_CTRL1_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_STATUS I3C_REVA_CONT_STATUS + * @brief Controller Status Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_STATUS_STATE_POS 0 /**< CONT_STATUS_STATE Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_STATE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS)) /**< CONT_STATUS_STATE Mask */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE ((uint32_t)0x0UL) /**< CONT_STATUS_STATE_IDLE Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IDLE (MXC_V_I3C_REVA_CONT_STATUS_STATE_IDLE << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IDLE Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_TARG_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_STATE_TARG_REQ Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_TARG_REQ (MXC_V_I3C_REVA_CONT_STATUS_STATE_TARG_REQ << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_TARG_REQ Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG ((uint32_t)0x2UL) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG (MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_TXSDRMSG << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM ((uint32_t)0x3UL) /**< CONT_STATUS_STATE_SDR_NORM Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_SDR_NORM (MXC_V_I3C_REVA_CONT_STATUS_STATE_SDR_NORM << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_NORM Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_DDR ((uint32_t)0x4UL) /**< CONT_STATUS_STATE_DDR Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_DDR (MXC_V_I3C_REVA_CONT_STATUS_STATE_DDR << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DDR Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA ((uint32_t)0x5UL) /**< CONT_STATUS_STATE_DAA Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_DAA (MXC_V_I3C_REVA_CONT_STATUS_STATE_DAA << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DAA Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK ((uint32_t)0x6UL) /**< CONT_STATUS_STATE_IBI_ACKNACK Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK (MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_ACKNACK << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_ACKNACK Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_RX ((uint32_t)0x7UL) /**< CONT_STATUS_STATE_IBI_RX Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_STATE_IBI_RX (MXC_V_I3C_REVA_CONT_STATUS_STATE_IBI_RX << MXC_F_I3C_REVA_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_RX Setting */ + +#define MXC_F_I3C_REVA_CONT_STATUS_WAIT_POS 4 /**< CONT_STATUS_WAIT Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_WAIT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_WAIT_POS)) /**< CONT_STATUS_WAIT Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_NACK_POS 5 /**< CONT_STATUS_NACK Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_NACK_POS)) /**< CONT_STATUS_NACK Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS 6 /**< CONT_STATUS_IBITYPE Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_IBITYPE ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS)) /**< CONT_STATUS_IBITYPE Mask */ +#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE ((uint32_t)0x0UL) /**< CONT_STATUS_IBITYPE_NONE Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_NONE (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_NONE << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_NONE Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_IBI Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_IBI (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_IBI << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_IBI Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x2UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_CONT_REQ << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_CONT_REQ Setting */ +#define MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x3UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */ +#define MXC_S_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ (MXC_V_I3C_REVA_CONT_STATUS_IBITYPE_HOTJOIN_REQ << MXC_F_I3C_REVA_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Setting */ + +#define MXC_F_I3C_REVA_CONT_STATUS_TARG_START_POS 8 /**< CONT_STATUS_TARG_START Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_TARG_START_POS)) /**< CONT_STATUS_TARG_START Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE_POS 9 /**< CONT_STATUS_REQ_DONE Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_REQ_DONE_POS)) /**< CONT_STATUS_REQ_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_DONE_POS 10 /**< CONT_STATUS_DONE Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_DONE_POS)) /**< CONT_STATUS_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_RX_RDY_POS 11 /**< CONT_STATUS_RX_RDY Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_RX_RDY_POS)) /**< CONT_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL_POS 12 /**< CONT_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_TX_NFULL_POS)) /**< CONT_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_IBI_WON_POS 13 /**< CONT_STATUS_IBI_WON Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_IBI_WON_POS)) /**< CONT_STATUS_IBI_WON Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_ERRWARN_POS 15 /**< CONT_STATUS_ERRWARN Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_ERRWARN_POS)) /**< CONT_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS_POS 19 /**< CONT_STATUS_CONT_TRANS Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_STATUS_CONT_TRANS_POS)) /**< CONT_STATUS_CONT_TRANS Mask */ + +#define MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR_POS 24 /**< CONT_STATUS_IBI_ADDR Position */ +#define MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_STATUS_IBI_ADDR_POS)) /**< CONT_STATUS_IBI_ADDR Mask */ + +/**@} end of group I3C_REVA_CONT_STATUS_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_IBIRULES I3C_REVA_CONT_IBIRULES + * @brief Controller IBI Registry and Rules Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0_POS 0 /**< CONT_IBIRULES_ADDR0 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR0_POS)) /**< CONT_IBIRULES_ADDR0 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1_POS 6 /**< CONT_IBIRULES_ADDR1 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR1_POS)) /**< CONT_IBIRULES_ADDR1 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2_POS 12 /**< CONT_IBIRULES_ADDR2 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR2_POS)) /**< CONT_IBIRULES_ADDR2 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3_POS 18 /**< CONT_IBIRULES_ADDR3 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR3_POS)) /**< CONT_IBIRULES_ADDR3 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4_POS 24 /**< CONT_IBIRULES_ADDR4 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4 ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_IBIRULES_ADDR4_POS)) /**< CONT_IBIRULES_ADDR4 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_MSB0_POS 30 /**< CONT_IBIRULES_MSB0 Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_MSB0 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_IBIRULES_MSB0_POS)) /**< CONT_IBIRULES_MSB0 Mask */ + +#define MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE_POS 31 /**< CONT_IBIRULES_NOBYTE Position */ +#define MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_IBIRULES_NOBYTE_POS)) /**< CONT_IBIRULES_NOBYTE Mask */ + +/**@} end of group I3C_REVA_CONT_IBIRULES_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_INTEN I3C_REVA_CONT_INTEN + * @brief Controller Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_INTEN_TARG_START_POS 8 /**< CONT_INTEN_TARG_START Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_TARG_START_POS)) /**< CONT_INTEN_TARG_START Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE_POS 9 /**< CONT_INTEN_REQ_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_REQ_DONE_POS)) /**< CONT_INTEN_REQ_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_DONE_POS 10 /**< CONT_INTEN_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_DONE_POS)) /**< CONT_INTEN_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_RX_RDY_POS 11 /**< CONT_INTEN_RX_RDY Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_RX_RDY_POS)) /**< CONT_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL_POS 12 /**< CONT_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_TX_NFULL_POS)) /**< CONT_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_IBI_WON_POS 13 /**< CONT_INTEN_IBI_WON Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_IBI_WON_POS)) /**< CONT_INTEN_IBI_WON Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_ERRWARN_POS 15 /**< CONT_INTEN_ERRWARN Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_ERRWARN_POS)) /**< CONT_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT_POS 19 /**< CONT_INTEN_NOW_CONT Position */ +#define MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTEN_NOW_CONT_POS)) /**< CONT_INTEN_NOW_CONT Mask */ + +/**@} end of group I3C_REVA_CONT_INTEN_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_INTCLR I3C_REVA_CONT_INTCLR + * @brief Controller Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_INTCLR_TARG_START_POS 8 /**< CONT_INTCLR_TARG_START Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_TARG_START_POS)) /**< CONT_INTCLR_TARG_START Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE_POS 9 /**< CONT_INTCLR_REQ_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_REQ_DONE_POS)) /**< CONT_INTCLR_REQ_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_DONE_POS 10 /**< CONT_INTCLR_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_DONE_POS)) /**< CONT_INTCLR_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY_POS 11 /**< CONT_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_RX_RDY_POS)) /**< CONT_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL_POS 12 /**< CONT_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_TX_NFULL_POS)) /**< CONT_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON_POS 13 /**< CONT_INTCLR_IBI_WON Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_IBI_WON_POS)) /**< CONT_INTCLR_IBI_WON Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN_POS 15 /**< CONT_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_ERRWARN_POS)) /**< CONT_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT_POS 19 /**< CONT_INTCLR_NOW_CONT Position */ +#define MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTCLR_NOW_CONT_POS)) /**< CONT_INTCLR_NOW_CONT Mask */ + +/**@} end of group I3C_REVA_CONT_INTCLR_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_INTFL I3C_REVA_CONT_INTFL + * @brief Controller Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_INTFL_TARG_START_POS 8 /**< CONT_INTFL_TARG_START Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_TARG_START_POS)) /**< CONT_INTFL_TARG_START Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE_POS 9 /**< CONT_INTFL_REQ_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_REQ_DONE_POS)) /**< CONT_INTFL_REQ_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_DONE_POS 10 /**< CONT_INTFL_DONE Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_DONE_POS)) /**< CONT_INTFL_DONE Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_RX_RDY_POS 11 /**< CONT_INTFL_RX_RDY Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_RX_RDY_POS)) /**< CONT_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL_POS 12 /**< CONT_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_TX_NFULL_POS)) /**< CONT_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_IBI_WON_POS 13 /**< CONT_INTFL_IBI_WON Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_IBI_WON_POS)) /**< CONT_INTFL_IBI_WON Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_ERRWARN_POS 15 /**< CONT_INTFL_ERRWARN Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_ERRWARN_POS)) /**< CONT_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT_POS 19 /**< CONT_INTFL_NOW_CONT Position */ +#define MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_INTFL_NOW_CONT_POS)) /**< CONT_INTFL_NOW_CONT Mask */ + +/**@} end of group I3C_REVA_CONT_INTFL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_ERRWARN I3C_REVA_CONT_ERRWARN + * @brief Controller Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_NACK_POS 2 /**< CONT_ERRWARN_NACK Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_NACK_POS)) /**< CONT_ERRWARN_NACK Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT_POS 3 /**< CONT_ERRWARN_TX_ABT Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TX_ABT_POS)) /**< CONT_ERRWARN_TX_ABT Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM_POS 4 /**< CONT_ERRWARN_RX_TERM Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_RX_TERM_POS)) /**< CONT_ERRWARN_RX_TERM Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR_POS 9 /**< CONT_ERRWARN_HDR_PAR Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_HDR_PAR_POS)) /**< CONT_ERRWARN_HDR_PAR Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC_POS 10 /**< CONT_ERRWARN_HDR_CRC Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_HDR_CRC_POS)) /**< CONT_ERRWARN_HDR_CRC Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR_POS 16 /**< CONT_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_RX_UNR_POS)) /**< CONT_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR_POS 17 /**< CONT_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TX_OVR_POS)) /**< CONT_ERRWARN_TX_OVR Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_MSG_POS 18 /**< CONT_ERRWARN_MSG Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_MSG ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_MSG_POS)) /**< CONT_ERRWARN_MSG Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ_POS 19 /**< CONT_ERRWARN_INV_REQ Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_INV_REQ_POS)) /**< CONT_ERRWARN_INV_REQ Mask */ + +#define MXC_F_I3C_REVA_CONT_ERRWARN_TO_POS 20 /**< CONT_ERRWARN_TO Position */ +#define MXC_F_I3C_REVA_CONT_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_ERRWARN_TO_POS)) /**< CONT_ERRWARN_TO Mask */ + +/**@} end of group I3C_REVA_CONT_ERRWARN_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_DMACTRL I3C_REVA_CONT_DMACTRL + * @brief Controller DMA Control Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS 0 /**< CONT_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS)) /**< CONT_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_DIS (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_DIS << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_RX_EN_EN (MXC_V_I3C_REVA_CONT_DMACTRL_RX_EN_EN << MXC_F_I3C_REVA_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS 2 /**< CONT_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS)) /**< CONT_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_DIS (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_DIS << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_TX_EN_EN (MXC_V_I3C_REVA_CONT_DMACTRL_TX_EN_EN << MXC_F_I3C_REVA_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS 4 /**< CONT_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS)) /**< CONT_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< CONT_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE (MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_BYTE << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< CONT_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_REVA_CONT_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_REVA_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_REVA_CONT_DMACTRL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_FIFOCTRL I3C_REVA_CONT_FIFOCTRL + * @brief Controller FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH_POS 0 /**< CONT_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FLUSH_POS)) /**< CONT_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH_POS 1 /**< CONT_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_FLUSH_POS)) /**< CONT_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK_POS 3 /**< CONT_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_UNLOCK_POS)) /**< CONT_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS 4 /**< CONT_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS)) /**< CONT_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS 6 /**< CONT_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS)) /**< CONT_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS 16 /**< CONT_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_LVL_POS)) /**< CONT_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS 24 /**< CONT_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_LVL_POS)) /**< CONT_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL_POS 30 /**< CONT_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_TX_FULL_POS)) /**< CONT_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM_POS 31 /**< CONT_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_FIFOCTRL_RX_EM_POS)) /**< CONT_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_REVA_CONT_FIFOCTRL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXFIFO8 I3C_REVA_CONT_TXFIFO8 + * @brief Controller Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8_DATA_POS 0 /**< CONT_TXFIFO8_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8_DATA_POS)) /**< CONT_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_REVA_CONT_TXFIFO8_END_POS 8 /**< CONT_TXFIFO8_END Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO8_END_POS)) /**< CONT_TXFIFO8_END Mask */ + +#define MXC_F_I3C_REVA_CONT_TXFIFO8_END2_POS 16 /**< CONT_TXFIFO8_END2 Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO8_END2_POS)) /**< CONT_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_REVA_CONT_TXFIFO8_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXFIFO8E I3C_REVA_CONT_TXFIFO8E + * @brief Controller Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA_POS 0 /**< CONT_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8E_DATA_POS)) /**< CONT_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_TXFIFO8E_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXFIFO16 I3C_REVA_CONT_TXFIFO16 + * @brief Controller Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXFIFO16_DATA_POS 0 /**< CONT_TXFIFO16_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXFIFO16_DATA_POS)) /**< CONT_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_REVA_CONT_TXFIFO16_END_POS 16 /**< CONT_TXFIFO16_END Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXFIFO16_END_POS)) /**< CONT_TXFIFO16_END Mask */ + +/**@} end of group I3C_REVA_CONT_TXFIFO16_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXFIFO16E I3C_REVA_CONT_TXFIFO16E + * @brief Controller Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA_POS 0 /**< CONT_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXFIFO16E_DATA_POS)) /**< CONT_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_TXFIFO16E_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_RXFIFO8 I3C_REVA_CONT_RXFIFO8 + * @brief Controller Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_RXFIFO8_DATA_POS 0 /**< CONT_RXFIFO8_DATA Position */ +#define MXC_F_I3C_REVA_CONT_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_RXFIFO8_DATA_POS)) /**< CONT_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_RXFIFO8_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_RXFIFO16 I3C_REVA_CONT_RXFIFO16 + * @brief Controller Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_RXFIFO16_DATA_POS 0 /**< CONT_RXFIFO16_DATA Position */ +#define MXC_F_I3C_REVA_CONT_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXFIFO16_DATA_POS)) /**< CONT_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_RXFIFO16_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXFIFO8O I3C_REVA_CONT_TXFIFO8O + * @brief Controller Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA_POS 0 /**< CONT_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_REVA_CONT_TXFIFO8O_DATA_POS)) /**< CONT_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_TXFIFO8O_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXSDRMSG_CTRL I3C_REVA_CONT_TXSDRMSG_CTRL + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS 0 /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS)) /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Mask */ + +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR_POS 1 /**< CONT_TXSDRMSG_CTRL_ADDR Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_ADDR_POS)) /**< CONT_TXSDRMSG_CTRL_ADDR Mask */ + +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END_POS 8 /**< CONT_TXSDRMSG_CTRL_END Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_END_POS)) /**< CONT_TXSDRMSG_CTRL_END Mask */ + +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN_POS 10 /**< CONT_TXSDRMSG_CTRL_I2C_EN Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_I2C_EN_POS)) /**< CONT_TXSDRMSG_CTRL_I2C_EN Mask */ + +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN_POS 11 /**< CONT_TXSDRMSG_CTRL_LEN Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN ((uint32_t)(0x1FUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_CTRL_LEN_POS)) /**< CONT_TXSDRMSG_CTRL_LEN Mask */ + +/**@} end of group I3C_REVA_CONT_TXSDRMSG_CTRL_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXSDRMSG_FIFO I3C_REVA_CONT_TXSDRMSG_FIFO + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA_POS 0 /**< CONT_TXSDRMSG_FIFO_DATA Position */ +#define MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXSDRMSG_FIFO_DATA_POS)) /**< CONT_TXSDRMSG_FIFO_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_TXSDRMSG_FIFO_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_RXSDRMSG I3C_REVA_CONT_RXSDRMSG + * @brief Controller Read SDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA_POS 0 /**< CONT_RXSDRMSG_DATA Position */ +#define MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXSDRMSG_DATA_POS)) /**< CONT_RXSDRMSG_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_RXSDRMSG_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_TXDDRMSG I3C_REVA_CONT_TXDDRMSG + * @brief Controller Start or Continue DDR Message Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG_POS 0 /**< CONT_TXDDRMSG_MSG Position */ +#define MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_TXDDRMSG_MSG_POS)) /**< CONT_TXDDRMSG_MSG Mask */ + +/**@} end of group I3C_REVA_CONT_TXDDRMSG_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_RXDDR16 I3C_REVA_CONT_RXDDR16 + * @brief Controller Read DDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_RXDDR16_DATA_POS 0 /**< CONT_RXDDR16_DATA Position */ +#define MXC_F_I3C_REVA_CONT_RXDDR16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_REVA_CONT_RXDDR16_DATA_POS)) /**< CONT_RXDDR16_DATA Mask */ + +/**@} end of group I3C_REVA_CONT_RXDDR16_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_CONT_DYNADDR I3C_REVA_CONT_DYNADDR + * @brief Controller Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_REVA_CONT_DYNADDR_ADDR_POS 1 /**< CONT_DYNADDR_ADDR Position */ +#define MXC_F_I3C_REVA_CONT_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_CONT_DYNADDR_ADDR_POS)) /**< CONT_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_REVA_CONT_DYNADDR_VALID_POS 8 /**< CONT_DYNADDR_VALID Position */ +#define MXC_F_I3C_REVA_CONT_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_REVA_CONT_DYNADDR_VALID_POS)) /**< CONT_DYNADDR_VALID Mask */ + +/**@} end of group I3C_REVA_CONT_DYNADDR_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_GROUPDEF I3C_REVA_TARG_GROUPDEF + * @brief Target Group Definition Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN_POS 0 /**< TARG_GROUPDEF_ADDR_EN Position */ +#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_EN_POS)) /**< TARG_GROUPDEF_ADDR_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_POS 1 /**< TARG_GROUPDEF_ADDR Position */ +#define MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_GROUPDEF_ADDR_POS)) /**< TARG_GROUPDEF_ADDR Mask */ + +/**@} end of group I3C_REVA_TARG_GROUPDEF_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_MAPCTRL0 I3C_REVA_TARG_MAPCTRL0 + * @brief Target Primary Map Control Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN_POS 0 /**< TARG_MAPCTRL0_DYNADDR_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_EN_POS)) /**< TARG_MAPCTRL0_DYNADDR_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_POS 1 /**< TARG_MAPCTRL0_DYNADDR Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL0_DYNADDR_POS)) /**< TARG_MAPCTRL0_DYNADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE_POS 8 /**< TARG_MAPCTRL0_CAUSE Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_MAPCTRL0_CAUSE_POS)) /**< TARG_MAPCTRL0_CAUSE Mask */ + +/**@} end of group I3C_REVA_TARG_MAPCTRL0_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_MAPCTRL1 I3C_REVA_TARG_MAPCTRL1 + * @brief Target Map Control 1 Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_EN_POS 0 /**< TARG_MAPCTRL1_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_EN_POS)) /**< TARG_MAPCTRL1_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR_POS 1 /**< TARG_MAPCTRL1_ADDR Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL1_ADDR_POS)) /**< TARG_MAPCTRL1_ADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN_POS 8 /**< TARG_MAPCTRL1_STATADDR_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_EN_POS)) /**< TARG_MAPCTRL1_STATADDR_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B_POS 9 /**< TARG_MAPCTRL1_STATADDR_10B Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B ((uint32_t)(0x7UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_STATADDR_10B_POS)) /**< TARG_MAPCTRL1_STATADDR_10B Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK_POS 12 /**< TARG_MAPCTRL1_NACK Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL1_NACK_POS)) /**< TARG_MAPCTRL1_NACK Mask */ + +/**@} end of group I3C_REVA_TARG_MAPCTRL1_Register */ + +/** + * @ingroup i3c_reva_registers + * @defgroup I3C_REVA_TARG_MAPCTRL2 I3C_REVA_TARG_MAPCTRL2 + * @brief Target Map Control 2 Register. + * @{ + */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_EN_POS 0 /**< TARG_MAPCTRL2_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_EN_POS)) /**< TARG_MAPCTRL2_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR_POS 1 /**< TARG_MAPCTRL2_ADDR Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_REVA_TARG_MAPCTRL2_ADDR_POS)) /**< TARG_MAPCTRL2_ADDR Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN_POS 8 /**< TARG_MAPCTRL2_STATADDR_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_STATADDR_EN_POS)) /**< TARG_MAPCTRL2_STATADDR_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK_POS 12 /**< TARG_MAPCTRL2_NACK Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_NACK_POS)) /**< TARG_MAPCTRL2_NACK Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN_POS 13 /**< TARG_MAPCTRL2_AUTO_EN Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN ((uint32_t)(0x1UL << MXC_F_I3C_REVA_TARG_MAPCTRL2_AUTO_EN_POS)) /**< TARG_MAPCTRL2_AUTO_EN Mask */ + +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_PID_POS 14 /**< TARG_MAPCTRL2_PID Position */ +#define MXC_F_I3C_REVA_TARG_MAPCTRL2_PID ((uint32_t)(0x3FFFFUL << MXC_F_I3C_REVA_TARG_MAPCTRL2_PID_POS)) /**< TARG_MAPCTRL2_PID Mask */ + +/**@} end of group I3C_REVA_TARG_MAPCTRL2_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_SOURCE_I3C_I3C_REVA_REGS_H_ diff --git a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c new file mode 100644 index 00000000..cace41e7 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva.h" +#include "icc_common.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ****************************************************************************** +Maxim Internal Use + * ****************************************************************************** */ + +int MXC_ICC_ID(mxc_icc_info_t cid) +{ + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid); +} + +void MXC_ICC_Enable(void) +{ + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC); +} + +void MXC_ICC_Disable(void) +{ + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC); +} + +void MXC_ICC_Flush(void) +{ + MXC_ICC_Com_Flush(); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd new file mode 100644 index 00000000..b2e331cf --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd @@ -0,0 +1,244 @@ + + + + ICC + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x1000 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + 32 + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + 32 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + 32 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + WAY + Cache Way Control Register. + 0x0200 + 32 + + + WAY + Number of cache way, default is always 2. Allowed values are 1,2,4. + 0 + 3 + + + 1 + 1 + 1 + + + 2 + 2 + 2 + + + 4 + 4 + 4 + + + + + + + REGCTRL + Regional Control Register. + 0x0204 + 32 + + + EN + Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. + 0 + 8 + + + EXC + Cache the data only if the TAG content is excluded in the high and low bound. + 8 + 8 + + + + + 4 + 8 + REGION[%s] + Regional Low and High Bound Registers. + icc_reg + 0x0208 + 64 + read-write + + LBOUND + Regional Low Bound Register. + 0x0000 + reg + 32 + + + BOUND + Low Bound. + 0 + 32 + + + + + HBOUND + DMA Channel Status Register. + 0x004 + reg + 32 + + + BOUND + High Bound. + 0 + 32 + + + + + + PFMCTRL + Performance Control Register. + 0x0300 + 32 + + + EN + Enable performance counter. Clear to 0 when AHB access counter reach 0. + 0 + 1 + + + + + PFMCNT + Performance Counter Register. + 0x0304 + 32 + + + CNT + Write the total AHB access counter. Read the current performance hit count. + 0 + 32 + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + 32 + + + INVALID + Invalidate. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c index 3b2c9a93..ead2ecec 100644 --- a/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me12.c @@ -58,7 +58,7 @@ void MXC_LP_EnterBackupMode(void) // Should never reach this line - device will jump to backup vector on exit from background mode. } -void MXC_LP_EnterPowerDownMode(void) +void MXC_LP_EnterShutDownMode(void) { MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; MXC_GCR->pm |= MXC_S_GCR_PM_MODE_SHUTDOWN; diff --git a/MAX/Libraries/PeriphDrivers/Source/LP/lp_me30.c b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me30.c new file mode 100644 index 00000000..e900eba3 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/LP/lp_me30.c @@ -0,0 +1,162 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "gcr_regs.h" +#include "mcr_regs.h" +#include "lp.h" + +/* ARM */ +#define SET_SLEEPDEEP(X) (SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk) +#define CLR_SLEEPDEEP(X) (SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk) + +// TODO(SW): Update this. + +void MXC_LP_EnterSleepMode(void) +{ + MXC_LP_ClearWakeStatus(); + + /* Clear SLEEPDEEP bit */ + CLR_SLEEPDEEP(); + + /* Go into Sleep mode and wait for an interrupt to wake the processor */ + __WFI(); +} + +void MXC_LP_EnterLowPowerMode(void) +{ + return; +} + +void MXC_LP_EnterMicroPowerMode(void) +{ + return; +} + +void MXC_LP_EnterStandbyMode(void) +{ + return; +} + +void MXC_LP_EnterBackupMode(void) +{ + MXC_LP_ClearWakeStatus(); + + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; + + while (1) {} + // Should never reach this line - device will jump to backup vector on exit from background mode. +} + +void MXC_LP_EnterPowerDownMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_V_GCR_PM_MODE_PDM; + + while (1) {} + // Should never reach this line - device will reset on exit from shutdown mode. +} + +void MXC_LP_SetOVR(mxc_lp_ovr_t ovr) +{ + //not supported yet +} + +void MXC_LP_BandgapOn(void) +{ + MXC_PWRSEQ->lpctrl &= ~MXC_F_PWRSEQ_LPCTRL_BG_DIS; +} + +void MXC_LP_BandgapOff(void) +{ + MXC_PWRSEQ->lpctrl |= MXC_F_PWRSEQ_LPCTRL_BG_DIS; +} + +int MXC_LP_BandgapIsOn(void) +{ + return (MXC_PWRSEQ->lpctrl & MXC_F_PWRSEQ_LPCTRL_BG_DIS); +} + +void MXC_LP_ClearWakeStatus(void) +{ + /* Write 1 to clear */ + MXC_PWRSEQ->lpwkfl0 = 0xFFFFFFFF; + MXC_PWRSEQ->lppwst = 0xFFFFFFFF; +} + +void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_GPIO_WE; + + switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + case MXC_GPIO_PORT_0: + MXC_PWRSEQ->lpwken0 |= wu_pins->mask; + break; + } +} + +void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +{ + switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + case MXC_GPIO_PORT_0: + MXC_PWRSEQ->lpwken0 &= ~wu_pins->mask; + break; + } + + if (MXC_PWRSEQ->lpwken0 == 0) { + MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIO_WE; + } +} + +void MXC_LP_EnableRTCAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_RTC_WE; +} + +void MXC_LP_DisableRTCAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_RTC_WE; +} + +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr) +{ + return; +} + +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr) +{ + return; +} + +void MXC_LP_EnableWUTAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_WUT_WE; +} + +void MXC_LP_DisableWUTAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_WUT_WE; +} + +int MXC_LP_ConfigDeepSleepClocks(uint32_t mask) +{ + MXC_GCR->pm |= mask; + return E_NO_ERROR; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd b/MAX/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd new file mode 100644 index 00000000..92fcda23 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd @@ -0,0 +1,144 @@ + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x400 + registers + + + + LPCTRL + Low Power Control Register. + 0x00 + + + SRAMRET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 5 + + + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + RETLDO_EN + Retention LDO Enable. + 12 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + LDO_EN_DLY + Core LDO Enable Delay. + 13 + 1 + + + dis + Disable. + 0 + + + en + Enable delay LDO power up to smooth LDO voltage drop. + 1 + + + + + LPWKFL_CLR + LP wakeup flag register clear. + 31 + 1 + + + + + LPWKFL0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + PINS + Wakeup Flags. + 0 + 12 + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + PINS + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 12 + + + + + LPPWST + Low Power Peripheral Wakeup Status Register. + 0x30 + + + BACKUP + BACKUP Wakeful Flag. + 16 + 1 + + + RESET + Reset Detected Wakeup Flag. + 17 + 1 + + + + + GP0 + General Purpose Register 0 + 0x48 + + + GP1 + General Purpose Register 1 + 0x4C + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd b/MAX/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd index 9cbabd3b..0e085606 100644 --- a/MAX/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd +++ b/MAX/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd @@ -35,7 +35,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -47,7 +47,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 diff --git a/MAX/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd b/MAX/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd new file mode 100644 index 00000000..2e8615b2 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/RSTZ/rstz_reva.svd @@ -0,0 +1,139 @@ + + + + + RSTZ + RSTZ Controller + 0x40004800 + + 0x00 + 0x400 + registers + + + + CTRL + RSTZ Control Register. + 0x000 + 32 + + + EN + Enable channels. + [0:0] + read-write + + + SVC_EN + Enable the SVC. + [1:1] + read-write + + + CH_SEL + Channel Select. + [4:2] + read-write + + + CAL_EN + Calibration mode enable. + [5:5] + read-write + + + DMEASURE_EN + Direct Measure mode enable. + [6:6] + read-write + + + OFFTR_P + Offset Trim for positive comparator. + [11:7] + read-write + + + OFFTR_N + Offset Trim for negative comparator. + [16:12] + read-write + + + DOUT + Comparator Result. + [17:17] + read-write + + + CAL_DOUT_POL + Calibration DOUT Polarity. + [18:18] + read-write + + + NUM_SAMP + Number of captures per sample. + [27:24] + read-write + + + TRIP_TOL + Number of failed DOUT captures (tolerance) before corresponding RSTZ signal is tripped. + [31:28] + read-write + + + + + BOOST_CLKCTRL + Boost Clock Control Register. + 0x004 + + + EXIT_NUM_SAMP + Defines how many samples needed of boost output channel to perform when exiting low-power mode before returning to normal active operation. + [1:0] + read-write + + + CH_SEL + Select when channel the output of the boost converter is monitored on. + [4:2] + read-write + + + + + 8 + 4 + STATUS_CH[%s] + Channel X Status Register. + 0x028 + 32 + read-write + + + RSTZ + Result of most recent sample result. + [0:0] + read-only + + + DOUT + Store the most recent DOUT capture for a given channel. + [1:1] + read-only + + + RSTZ_FL + RSTZ Flag indicates the RSTZ was tripped at some point since the last time being cleared. + [31:31] + read-write + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c new file mode 100644 index 00000000..313a1012 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -0,0 +1,281 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "rtc_regs.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gpio_regs.h" +#include "mxc_errors.h" +#include "mcr_regs.h" +#include "rtc_reva.h" +#include "tmr.h" +#include "trimsir_regs.h" + +#define SUBSECOND_MSEC_0 200 +#define SEARCH_STEPS 7 +#define SEARCH_TARGET 0x30d400 /* 1/2 of 32 MHz periods in 32.768 kHz */ + +#define RTCX1x_MASK 0x1F /* 5 bits */ +#define RTCX2x_MASK 0x1F /* 5 bits */ + +#define NOM_32K_FREQ 32768 +#define TICKS_PER_RTC 122 + +/* Converts a time in milleseconds to the equivalent RSSA register value. */ +#define MSEC_TO_RSSA(x) (unsigned int)(0x100000000ULL - ((x * 4096) / 1000)) + +/********************************************/ +/* Maxim Function Mapping */ +/********************************************/ + +int MXC_RTC_EnableInt(uint32_t mask) +{ + return MXC_RTC_RevA_EnableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); +} + +int MXC_RTC_DisableInt(uint32_t mask) +{ + return MXC_RTC_RevA_DisableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); +} + +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras) +{ + return MXC_RTC_RevA_SetTimeofdayAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, ras); +} + +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa) +{ + return MXC_RTC_RevA_SetSubsecondAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, rssa); +} + +int MXC_RTC_Start(void) +{ + return MXC_RTC_RevA_Start((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_Stop(void) +{ + return MXC_RTC_RevA_Stop((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_Init(uint32_t sec, uint16_t ssec) +{ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + + return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_SSEC)); +} + +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t ft) +{ + // TODO(RTC): Use MCR registers for GPIO Port 1 configuration. + + MXC_MCR->outen |= MXC_F_MCR_OUTEN_SQWOUT_EN; + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, + ft); +} + +int MXC_RTC_SquareWaveStop(void) +{ + MXC_MCR->outen &= ~(MXC_F_MCR_OUTEN_SQWOUT_EN); + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, + MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0); +} + +int MXC_RTC_Trim(int8_t trm) +{ + return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm); +} + +int MXC_RTC_GetFlags(void) +{ + return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_ClearFlags(int flags) +{ + return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags); +} + +int MXC_RTC_GetSubSecond(void) +{ + return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_GetSecond(void) +{ + return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_GetSubSeconds(uint32_t *ssec) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSubSeconds((mxc_rtc_reva_regs_t *)MXC_RTC, ssec); +} + +int MXC_RTC_GetSeconds(uint32_t *sec) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSeconds((mxc_rtc_reva_regs_t *)MXC_RTC, sec); +} + +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec) +{ + return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec); +} + +int MXC_RTC_GetBusyFlag(void) +{ + return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +// TODO(SW): TRIMSIR RTC X1/X2 register descriptions were updated due to design changes. +// CAP vs TRIM value differences unknown, and this function has not been tested. +int MXC_RTC_TrimCrystal(void) +{ + unsigned int search_step, elapsed; + unsigned int upper, lower, trim, oldtrim, bestTrim, bestElapsed, bestElapsedDiff; + unsigned int freq = NOM_32K_FREQ; + int retval; + + /* Determine starting point for internal load capacitors */ + upper = RTCX1x_MASK; + lower = 0; + trim = (upper + lower) / 2; + + /* Initialize best trim variables */ + bestTrim = trim; + bestElapsed = bestElapsedDiff = SEARCH_TARGET; + + /* Init timer to count 32 MHz periods */ + mxc_tmr_cfg_t tmr_cfg; + tmr_cfg.pres = MXC_TMR_PRES_1; + tmr_cfg.mode = MXC_TMR_MODE_CONTINUOUS; + tmr_cfg.bitMode = MXC_TMR_BIT_MODE_32; + tmr_cfg.clock = MXC_TMR_APB_CLK; + tmr_cfg.cmp_cnt = 0xFFFFFFFF; + tmr_cfg.pol = 0; + MXC_TMR_Init(MXC_TMR3, &tmr_cfg, FALSE); + + /* Clear out any previous configuration */ + MXC_RTC_DisableInt(MXC_F_RTC_CTRL_TOD_ALARM_IE | MXC_F_RTC_CTRL_SSEC_ALARM_IE | + MXC_F_RTC_CTRL_RDY_IE); + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + + MXC_RTC->oscctrl &= ~(MXC_F_RTC_OSCCTRL_BYPASS | MXC_F_RTC_OSCCTRL_SQW_32K); + + /* Setup SSEC Alarm */ + MXC_RTC_DisableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE); + retval = MXC_RTC_SetSubsecondAlarm(MSEC_TO_RSSA(SUBSECOND_MSEC_0)); + if (retval != E_NO_ERROR) { + return retval; + } + MXC_RTC_EnableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE); + + /* Trim loop */ + search_step = 0; + while (search_step < SEARCH_STEPS) { + /* Set new trim point */ + oldtrim = trim; + trim = (lower + upper) / 2; + if ((search_step > 0) && (trim == oldtrim)) { + /* Found trim value */ + break; + } + + /* Set the trim values */ + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (trim << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (trim << MXC_F_TRIMSIR_RTCX2_CAP_POS)); + + /* Sleep to settle new caps */ + MXC_Delay(MXC_DELAY_MSEC(10)); + + /* Start 200 msec sampling window */ + MXC_TMR_Stop(MXC_TMR3); + MXC_TMR_SetCount(MXC_TMR3, 0); + + /* Wait for an RTC edge */ + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} + + MXC_TMR_Start(MXC_TMR3); + + /* Wait for an RTC edge */ + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} + + /* Capture the TMR count and adjust for processing delay */ + elapsed = MXC_TMR_GetCount(MXC_TMR3); + MXC_TMR_Stop(MXC_TMR3); + elapsed += 810; + + /* Binary search for optimal trim value */ + if (elapsed > SEARCH_TARGET) { + /* Too slow */ + upper = trim; + + /* Record best setting */ + if ((elapsed - SEARCH_TARGET) <= bestElapsedDiff) { + bestElapsedDiff = elapsed - SEARCH_TARGET; + bestElapsed = elapsed; + bestTrim = trim; + } + } else { + /* Too fast */ + lower = trim; + + /* Record best setting */ + if ((SEARCH_TARGET - elapsed) <= bestElapsedDiff) { + bestElapsedDiff = SEARCH_TARGET - elapsed; + bestElapsed = elapsed; + bestTrim = trim; + } + } + + search_step++; + } + + /* Apply the closest trim setting */ + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (bestTrim << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (bestTrim << MXC_F_TRIMSIR_RTCX2_CAP_POS)); + + /* Adjust 32K freq if we can't get close enough to 32768 Hz */ + if (bestElapsed >= SEARCH_TARGET) { + freq -= (((bestElapsed - SEARCH_TARGET) + (TICKS_PER_RTC / 2 - 1)) / TICKS_PER_RTC); + } else { + freq += (((SEARCH_TARGET - bestElapsed) + (TICKS_PER_RTC / 2 - 1)) / TICKS_PER_RTC); + } + + /* Clear hardware state */ + MXC_TMR_Stop(MXC_TMR3); + MXC_TMR_Shutdown(MXC_TMR3); + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + + return freq; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd new file mode 100644 index 00000000..bc42bc5c --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd @@ -0,0 +1,410 @@ + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + Sub-Seconds Counter (12-bit). + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDY_IE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SSEC_ALARM_IF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SQW_EN + Square Wave Output Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + + + RD_EN + Asynchronous Counter Read Enable. + 14 + 1 + + + sync + Synchronous. + 0 + + + async + Asynchronous. + 1 + + + + + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + ignore + Ignored. + 0 + + + allow + Allowed. + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBAT_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enable Filter. + 0 + 1 + + + IBIAS_SEL + IBIAS Select. + 1 + 1 + + + 2x + 2x + 0 + + + 4x + 4x + 1 + + + + + HYST_EN + RTC Hysteresis Enable. + 2 + 1 + + + IBIAS_EN + RTC IBIAS Enable. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_32K + RTC 32kHz Square Wave Output + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c index aed74ee5..45e710c7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_ai87.c @@ -46,6 +46,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the IPO clock if it's not on already @@ -62,6 +63,7 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds0 |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c index a50a1597..a7b54a61 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me10.c @@ -37,6 +37,7 @@ /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SDHC); MXC_GPIO_Config(&gpio_cfg_sdhc_0); @@ -44,6 +45,7 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio_cfg_sdhc_1.port->vssel |= gpio_cfg_sdhc_1.mask; gpio_cfg_sdhc_0.port->ds_sel0 |= gpio_cfg_sdhc_0.mask; gpio_cfg_sdhc_1.port->ds_sel0 |= gpio_cfg_sdhc_1.mask; +#endif return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c index 96c1d99a..4b4cd58b 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me13.c @@ -45,6 +45,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the HIRC96M clock if it's not on already @@ -61,6 +62,8 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif + return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c index fb96f3fa..41332259 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/SDHC/sdhc_me14.c @@ -46,6 +46,7 @@ unsigned int MXC_SDHC_Get_Clock_Config(void) /* ************************************************************************** */ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) { +#ifndef MSDK_NO_GPIO_CLK_INIT mxc_gpio_regs_t *gpio = gpio_cfg_sdhc.port; // Startup the HIRC96M clock if it's not on already @@ -62,6 +63,8 @@ int MXC_SDHC_Init(const mxc_sdhc_cfg_t *cfg) gpio->ds0 |= gpio_cfg_sdhc.mask; MXC_GPIO_Config(&gpio_cfg_sdhc); +#endif + return MXC_SDHC_RevA_Init((mxc_sdhc_reva_regs_t *)MXC_SDHC, cfg); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c index 9d1ce7b3..3105f9c7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_ai87.c @@ -403,34 +403,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -457,36 +442,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - break; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c index f4b82cc5..de0f94b9 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_es17.c @@ -252,35 +252,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - default: - return E_BAD_PARAM; - } - } - - //tx - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -307,34 +291,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c index 6315e4bc..927f94c3 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me11.c @@ -250,34 +250,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSTX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSRX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPIMSSTX; + reqselRx = MXC_DMA_REQUEST_SPIMSSRX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -304,34 +289,19 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPIMSSTX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPIMSSTX; + reqselRx = MXC_DMA_REQUEST_SPIMSSRX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPIMSSRX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c index ee08ebdc..be7dbc52 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me12.c @@ -359,34 +359,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -413,36 +398,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c index f5544910..76bcdc18 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me13.c @@ -283,42 +283,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -344,42 +326,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c index a1f742e9..70eeb41e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me14.c @@ -348,42 +348,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); @@ -413,42 +395,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c index 78edd791..f82cee59 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me15.c @@ -264,42 +264,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -326,42 +308,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c index a2e09344..5be9927d 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me16.c @@ -260,44 +260,26 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3TX; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2TX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3TX; + break; } return MXC_SPI_RevA1_MasterTransactionDMA(req, reqselTx, reqselRx); @@ -323,44 +305,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2TX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3TX; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2TX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3TX; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA(req, reqselTx, reqselRx); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c index 21a546d6..a796c315 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me17.c @@ -417,34 +417,19 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -471,36 +456,20 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - default: - return E_BAD_PARAM; - break; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - default: - return E_BAD_PARAM; - break; - } + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c index bb6ed9b4..9d6c3b21 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18.c @@ -34,11 +34,18 @@ /* **** Definitions **** */ /* ************************************************************************** */ -int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, - unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins) +int MXC_SPI_Init(mxc_spi_regs_t *spi, mxc_spi_type_t controller_target, mxc_spi_interface_t if_mode, + int numTargets, uint8_t ts_active_pol_mask, uint32_t freq, mxc_spi_pins_t pins) { int spi_num; + // Remap input parameters for v1 implementation. + int masterMode = controller_target; + int quadModeUsed = if_mode; + int numSlaves = numTargets; + int ssPolarity = ts_active_pol_mask; + int hz = freq; + spi_num = MXC_SPI_GET_IDX(spi); MXC_ASSERT(spi_num >= 0); @@ -383,48 +390,29 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4TX; - break; - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - case 4: - reqselRx = MXC_DMA_REQUEST_SPI4RX; - break; - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + case 4: + reqselTx = MXC_DMA_REQUEST_SPI4TX; + reqselRx = MXC_DMA_REQUEST_SPI4RX; + break; + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -451,50 +439,30 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0TX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1TX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4TX; - break; - default: - return E_BAD_PARAM; - break; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2RX; - break; - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3RX; - break; - case 4: - reqselTx = MXC_DMA_REQUEST_SPI4RX; - break; - default: - return E_BAD_PARAM; - break; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + case 4: + reqselTx = MXC_DMA_REQUEST_SPI4TX; + reqselRx = MXC_DMA_REQUEST_SPI4RX; + break; + default: + return E_BAD_PARAM; + break; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18_v2.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18_v2.c new file mode 100644 index 00000000..0d7bf5a6 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me18_v2.c @@ -0,0 +1,1075 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spi_reva2.h" +#include "spi.h" +#include "dma.h" +#include "gpio.h" + +/* **** Definitions **** */ + +/* ************************************************************************** */ + +// Max 3 Possible Target Select Options per SPI instance +#define MXC_SPI_TS0_MASK_POS (0) +#define MXC_SPI_TS1_MASK_POS (1) +#define MXC_SPI_TS2_MASK_POS (2) + +int MXC_SPI_Init(mxc_spi_regs_t *spi, mxc_spi_type_t controller_target, mxc_spi_interface_t if_mode, + int numTargets, uint8_t ts_active_pol_mask, uint32_t freq, mxc_spi_pins_t pins) +{ + int error; + int8_t spi_num; + mxc_spi_tscontrol_t ts_control; + mxc_gpio_cfg_t temp_ts_cfg; // TS pins. + mxc_gpio_vssel_t vssel; + + spi_num = MXC_SPI_GET_IDX(spi); + if (spi_num < 0 || spi_num >= MXC_SPI_INSTANCES) { + return E_BAD_PARAM; + } + + // Check if frequency is too high + if ((spi_num == 0) && (freq > MXC_SPI_GetPeripheralClock(spi))) { + return E_BAD_PARAM; + } + + if ((spi_num == 1) && (freq > SystemCoreClock)) { + return E_BAD_PARAM; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + if (pins.vddioh) { + vssel = MXC_GPIO_VSSEL_VDDIOH; + } else { + vssel = MXC_GPIO_VSSEL_VDDIO; + } + + // SPI Target mode only supports HW_AUTO. + if (pins.ss0 || pins.ss1 || pins.ss2 || (controller_target == MXC_SPI_TYPE_TARGET)) { + ts_control = MXC_SPI_TSCONTROL_HW_AUTO; + } else { + ts_control = MXC_SPI_TSCONTROL_SW_APP; + } + + error = MXC_SPI_RevA2_SetTSControl((mxc_spi_reva_regs_t *)spi, ts_control); + if (error != E_NO_ERROR) { + return error; + } + + // Configure SPI peripheral and pins. + if (spi == MXC_SPI0) { // <--------------------------------------- SPI0 + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + error = MXC_GPIO_Config(&gpio_cfg_spi0_standard); + break; + + case MXC_SPI_INTERFACE_QUAD: + error = MXC_GPIO_Config(&gpio_cfg_spi0_quad); + break; + + case MXC_SPI_INTERFACE_3WIRE: + error = MXC_GPIO_Config(&gpio_cfg_spi0_3wire); + break; + + case MXC_SPI_INTERFACE_DUAL: + error = MXC_GPIO_Config(&gpio_cfg_spi1_dual); + break; + + default: + return E_BAD_PARAM; + } + + if (error != E_NO_ERROR) { + return error; + } + + // Set up HW TS pins (if HW_AUTO TS control scheme was selected). + // Voltage and drive strength settings will match the SPI pins. + if (ts_control == MXC_SPI_TSCONTROL_HW_AUTO) { + // Target Select 0 - TS0 (L. SS0 pin) + if (pins.ss0 == true) { + temp_ts_cfg = gpio_cfg_spi0_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 1 - TS1 (L. SS1 pin) + if (pins.ss1 == true) { + temp_ts_cfg = gpio_cfg_spi0_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + } + + } else if (spi == MXC_SPI1) { // <--------------------------------------- SPI1 + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + error = MXC_GPIO_Config(&gpio_cfg_spi1_standard); + break; + + case MXC_SPI_INTERFACE_QUAD: + error = MXC_GPIO_Config(&gpio_cfg_spi1_quad_0); + error |= MXC_GPIO_Config(&gpio_cfg_spi1_quad_1); + if (error != E_NO_ERROR) { + error = E_FAIL; + } + + break; + + case MXC_SPI_INTERFACE_3WIRE: + error = MXC_GPIO_Config(&gpio_cfg_spi1_3wire); + break; + + case MXC_SPI_INTERFACE_DUAL: + error = MXC_GPIO_Config(&gpio_cfg_spi1_dual); + break; + + default: + return E_BAD_PARAM; + } + + if (error != E_NO_ERROR) { + return error; + } + + // Set up HW TS pins (if HW_AUTO TS control scheme was selected). + // Voltage and drive strength settings will match the SPI pins. + if (ts_control == MXC_SPI_TSCONTROL_HW_AUTO) { + // Target Select 0 - TS0 (L. SS0 pin) + if (pins.ss0 == true) { + temp_ts_cfg = gpio_cfg_spi1_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 1 - TS1 (L. SS1 pin) + if (pins.ss1 == true) { + temp_ts_cfg = gpio_cfg_spi1_ts1; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 2 - TS1 (L. SS2 pin) + if (pins.ss2 == true) { + temp_ts_cfg = gpio_cfg_spi1_ts2; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + } + + } else if (spi == MXC_SPI2) { // <--------------------------------------- SPI2 + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI2); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI2); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + error = MXC_GPIO_Config(&gpio_cfg_spi2_standard); + break; + + case MXC_SPI_INTERFACE_QUAD: + error = MXC_GPIO_Config(&gpio_cfg_spi2_quad_0); + error |= MXC_GPIO_Config(&gpio_cfg_spi2_quad_1); + if (error != E_NO_ERROR) { + error = E_FAIL; + } + + break; + + case MXC_SPI_INTERFACE_3WIRE: + error = MXC_GPIO_Config(&gpio_cfg_spi2_3wire); + break; + + case MXC_SPI_INTERFACE_DUAL: + error = MXC_GPIO_Config(&gpio_cfg_spi2_dual); + break; + + default: + return E_BAD_PARAM; + } + + if (error != E_NO_ERROR) { + return error; + } + + // Set up HW TS pins (if HW_AUTO TS control scheme was selected). + // Voltage and drive strength settings will match the SPI pins. + if (ts_control == MXC_SPI_TSCONTROL_HW_AUTO) { + // Target Select 0 - TS0 (L. SS0 pin) + if (pins.ss0 == true) { + temp_ts_cfg = gpio_cfg_spi2_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 1 - TS1 (L. SS1 pin) + if (pins.ss1 == true) { + temp_ts_cfg = gpio_cfg_spi2_ts1; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 2 - TS1 (L. SS2 pin) + if (pins.ss2 == true) { + temp_ts_cfg = gpio_cfg_spi2_ts2; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + } + +#ifndef __riscv + } else if (spi == MXC_SPI3) { // <--------------------------------------- SPI3 + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_SPI3); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI3); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + error = MXC_GPIO_Config(&gpio_cfg_spi3_standard); + break; + + case MXC_SPI_INTERFACE_QUAD: + error = MXC_GPIO_Config(&gpio_cfg_spi3_quad); + break; + + case MXC_SPI_INTERFACE_3WIRE: + error = MXC_GPIO_Config(&gpio_cfg_spi3_3wire); + break; + + case MXC_SPI_INTERFACE_DUAL: + error = MXC_GPIO_Config(&gpio_cfg_spi3_dual); + break; + + default: + return E_BAD_PARAM; + } + + if (error != E_NO_ERROR) { + return error; + } + + // Set up HW TS pins (if HW_AUTO TS control scheme was selected). + // Voltage and drive strength settings will match the SPI pins. + if (ts_control == MXC_SPI_TSCONTROL_HW_AUTO) { + // Target Select 0 - TS0 (L. SS0 pin) + if (pins.ss0 == true) { + temp_ts_cfg = gpio_cfg_spi3_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 1 - TS1 (L. SS1 pin) + if (pins.ss1 == true) { + temp_ts_cfg = gpio_cfg_spi3_ts1; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 2 - TS1 (L. SS2 pin) + if (pins.ss2 == true) { + temp_ts_cfg = gpio_cfg_spi3_ts2; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + } + + } else if (spi == MXC_SPI4) { // <--------------------------------------- SPI4 + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_SPI4); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI4); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + error = MXC_GPIO_Config(&gpio_cfg_spi4_standard); + break; + + case MXC_SPI_INTERFACE_QUAD: + error = MXC_GPIO_Config(&gpio_cfg_spi4_quad); + break; + + case MXC_SPI_INTERFACE_3WIRE: + error = MXC_GPIO_Config(&gpio_cfg_spi4_3wire); + break; + + case MXC_SPI_INTERFACE_DUAL: + error = MXC_GPIO_Config(&gpio_cfg_spi4_dual); + break; + + default: + return E_BAD_PARAM; + } + + if (error != E_NO_ERROR) { + return error; + } + + // Set up HW TS pins (if HW_AUTO TS control scheme was selected). + // Voltage and drive strength settings will match the SPI pins. + if (ts_control == MXC_SPI_TSCONTROL_HW_AUTO) { + // Target Select 0 - TS0 (L. SS0 pin) + if (pins.ss0 == true) { + temp_ts_cfg = gpio_cfg_spi4_ts0; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 1 - TS1 (L. SS1 pin) + if (pins.ss1 == true) { + temp_ts_cfg = gpio_cfg_spi4_ts1; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + + // Target Select 2 - TS1 (L. SS2 pin) + if (pins.ss2 == true) { + temp_ts_cfg = gpio_cfg_spi4_ts2; + temp_ts_cfg.vssel = vssel; + temp_ts_cfg.drvstr = pins.drvstr; + + error = MXC_GPIO_Config(&temp_ts_cfg); + if (error != E_NO_ERROR) { + return error; + } + } + } +#endif // __riscv + } else { + return E_NO_DEVICE; + } +#else + (void)pins; +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_SPI_RevA2_Init((mxc_spi_reva_regs_t *)spi, controller_target, if_mode, freq, + ts_active_pol_mask); +} + +int MXC_SPI_Config(mxc_spi_cfg_t *cfg) +{ + return MXC_SPI_RevA2_Config(cfg); +} + +int MXC_SPI_ConfigStruct(mxc_spi_cfg_t *cfg, bool use_dma_tx, bool use_dma_rx) +{ + if (cfg == NULL) { + return E_BAD_PARAM; + } + + cfg->spi = MXC_SPI0; // SPI1 is available on both the ARM and RISCV core. + cfg->clk_mode = MXC_SPI_CLKMODE_0; // 0 - CPOL :: 0 - CPHA + + if (use_dma_tx || use_dma_rx) { + cfg->use_dma_tx = use_dma_tx; + cfg->use_dma_rx = use_dma_rx; + cfg->dma = MXC_DMA; + } else { + cfg->use_dma_tx = false; + cfg->use_dma_rx = false; + cfg->dma = NULL; + } + + return E_SUCCESS; +} + +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) +{ + int8_t spi_num; + + spi_num = MXC_SPI_GET_IDX(spi); + if (spi_num < 0 || spi_num >= MXC_SPI_INSTANCES) { + return E_BAD_PARAM; + } + + MXC_SPI_RevA2_Shutdown((mxc_spi_reva_regs_t *)spi); + + if (spi == MXC_SPI0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); + } else if (spi == MXC_SPI1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); + } else if (spi == MXC_SPI2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI2); +#ifndef __riscv + } else if (spi == MXC_SPI3) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI3); + } else if (spi == MXC_SPI4) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI4); +#endif //__riscv + } else { + return E_NO_DEVICE; + } + + return E_NO_ERROR; +} + +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi) +{ + return (unsigned int)MXC_SPI_RevA2_GetFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_ClearFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn) +{ + MXC_SPI_RevA2_EnableInt((mxc_spi_reva_regs_t *)spi, (uint32_t)intEn); +} + +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis) +{ + MXC_SPI_RevA2_DisableInt((mxc_spi_reva_regs_t *)spi, (uint32_t)intDis); +} + +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) +{ + int clk_freq = 0; + + if (MXC_SPI_GET_IDX(spi) >= 0 && MXC_SPI_GET_IDX(spi) < 3) { + clk_freq = PeripheralClock; + } else if (MXC_SPI_GET_IDX(spi) >= 3) { + uint32_t clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + switch (clk_src) { + case MXC_SYS_CLOCK_IPO: + clk_freq = IPO_FREQ; + break; + case MXC_SYS_CLOCK_ERFO: + clk_freq = ERFO_FREQ; + break; + case MXC_SYS_CLOCK_IBRO: + clk_freq = IBRO_FREQ; + break; + case MXC_SYS_CLOCK_ISO: + clk_freq = ISO_FREQ; + break; + case MXC_SYS_CLOCK_INRO: + clk_freq = INRO_FREQ; + break; + case MXC_SYS_CLOCK_ERTCO: + clk_freq = ERTCO_FREQ; + break; + case MXC_SYS_CLOCK_EXTCLK: + clk_freq = EXTCLK_FREQ; + break; + default: + return E_BAD_PARAM; + } + } else { + return E_BAD_PARAM; + } + + return (clk_freq / 2); +} + +int MXC_SPI_SetTSControl(mxc_spi_regs_t *spi, mxc_spi_tscontrol_t ts_control) +{ + return MXC_SPI_RevA2_SetTSControl((mxc_spi_reva_regs_t *)spi, ts_control); +} + +mxc_spi_tscontrol_t MXC_SPI_GetTSControl(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetTSControl((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz) +{ + return MXC_SPI_RevA2_SetFrequency((mxc_spi_reva_regs_t *)spi, hz); +} + +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetFrequency((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetFrameSize(mxc_spi_regs_t *spi, int frame_size) +{ + return MXC_SPI_RevA2_SetFrameSize((mxc_spi_reva_regs_t *)spi, frame_size); +} + +int MXC_SPI_GetFrameSize(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetFrameSize((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetInterface(mxc_spi_regs_t *spi, mxc_spi_interface_t mode) +{ + return MXC_SPI_RevA2_SetInterface((mxc_spi_reva_regs_t *)spi, mode); +} + +mxc_spi_interface_t MXC_SPI_GetInterface(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetInterface((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetClkMode(mxc_spi_regs_t *spi, mxc_spi_clkmode_t clk_mode) +{ + return MXC_SPI_RevA2_SetClkMode((mxc_spi_reva_regs_t *)spi, clk_mode); +} + +mxc_spi_clkmode_t MXC_SPI_GetClkMode(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetClkMode((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetCallback(mxc_spi_regs_t *spi, mxc_spi_callback_t completeCB, void *data) +{ + return MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)spi, completeCB, data); +} + +int MXC_SPI_GetActive(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetActive((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_ReadyForSleep((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetDummyTX(mxc_spi_regs_t *spi, uint16_t tx_value) +{ + return MXC_SPI_RevA2_SetDummyTX((mxc_spi_reva_regs_t *)spi, tx_value); +} + +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_StartTransmission((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_AbortTransmission((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_ClearTXFIFO((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_ClearRXFIFO((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return (int)MXC_SPI_RevA2_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return (int)MXC_SPI_RevA2_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi) +{ + return (unsigned int)MXC_SPI_RevA2_GetTXThreshold((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi) +{ + return (unsigned int)MXC_SPI_RevA2_GetRXThreshold((mxc_spi_reva_regs_t *)spi); +} + +/* ** DMA-Specific Functions ** */ + +int MXC_SPI_DMA_Init(mxc_spi_regs_t *spi, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx) +{ + return MXC_SPI_RevA2_DMA_Init((mxc_spi_reva_regs_t *)spi, (mxc_dma_reva_regs_t *)dma, + use_dma_tx, use_dma_rx); +} + +bool MXC_SPI_DMA_GetInitialized(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_DMA_GetInitialized((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_DMA_GetTXChannel(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_DMA_GetTXChannel((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_DMA_GetRXChannel(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_DMA_GetRXChannel((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_DMA_SetRequestSelect(mxc_spi_regs_t *spi, bool use_dma_tx, bool use_dma_rx) +{ + int8_t spi_num; + int tx_reqsel = -1; + int rx_reqsel = -1; + + spi_num = MXC_SPI_GET_IDX(spi); + if (spi_num < 0 || spi_num >= MXC_SPI_INSTANCES) { + return E_INVALID; + } + + if (use_dma_tx) { + switch (spi_num) { + case 0: + tx_reqsel = MXC_DMA_REQUEST_SPI0TX; + break; + + case 1: + tx_reqsel = MXC_DMA_REQUEST_SPI1TX; + break; + + case 2: + tx_reqsel = MXC_DMA_REQUEST_SPI2TX; + break; + + case 3: + tx_reqsel = MXC_DMA_REQUEST_SPI3TX; + break; + + case 4: + tx_reqsel = MXC_DMA_REQUEST_SPI4TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if (use_dma_rx) { + switch (spi_num) { + case 0: + rx_reqsel = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + rx_reqsel = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + rx_reqsel = MXC_DMA_REQUEST_SPI2RX; + break; + + case 3: + rx_reqsel = MXC_DMA_REQUEST_SPI3RX; + break; + + case 4: + rx_reqsel = MXC_DMA_REQUEST_SPI4RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_SPI_RevA2_DMA_SetRequestSelect((mxc_spi_reva_regs_t *)spi, tx_reqsel, rx_reqsel); +} + +/* ** Transaction Functions ** */ + +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA2_ControllerTransaction((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, req->ssDeassert, + req->ssIdx); +} + +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_ControllerTransactionAsync((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + req->ssDeassert, req->ssIdx); +} + +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_ControllerTransactionDMA((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + req->ssDeassert, req->ssIdx, + (mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_SPI_ControllerTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA2_ControllerTransaction((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, req->ssDeassert, + req->ssIdx); +} + +int MXC_SPI_ControllerTransactionAsync(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_ControllerTransactionAsync((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + req->ssDeassert, req->ssIdx); +} + +int MXC_SPI_ControllerTransactionDMA(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_ControllerTransactionDMA((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + req->ssDeassert, req->ssIdx, + (mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA2_TargetTransaction((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen); +} + +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_TargetTransactionAsync((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen); +} + +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) +{ + int error; + + // Users can set their own callback and pass in their own data if they choose to. + if (req->completeCB != NULL) { + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + } + + return MXC_SPI_RevA2_TargetTransactionDMA((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + (mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_SPI_TargetTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA2_TargetTransaction((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen); +} + +int MXC_SPI_TargetTransactionAsync(mxc_spi_req_t *req) +{ + int error; + + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + + return MXC_SPI_RevA2_TargetTransactionAsync((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen); +} + +int MXC_SPI_TargetTransactionDMA(mxc_spi_req_t *req) +{ + int error; + + error = MXC_SPI_RevA2_SetCallback((mxc_spi_reva_regs_t *)(req->spi), req->completeCB, req); + if (error != E_NO_ERROR) { + return error; + } + + return MXC_SPI_RevA2_TargetTransactionDMA((mxc_spi_reva_regs_t *)(req->spi), req->txData, + req->txLen, req->rxData, req->rxLen, + (mxc_dma_reva_regs_t *)MXC_DMA); +} + +/* ** Handler Functions ** */ + +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_Handler((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_Handler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_Handler((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_DMA_TX_Handler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_DMA_TX_Handler((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_DMA_RX_Handler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA2_DMA_RX_Handler((mxc_spi_reva_regs_t *)spi); +} + +/* ** Unsupported-Legacy Functions from Previous Implementation ** */ + +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize) +{ + return MXC_SPI_RevA2_SetFrameSize((mxc_spi_reva_regs_t *)spi, dataSize); +} + +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA2_GetFrameSize((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth) +{ + switch (spiWidth) { + case SPI_WIDTH_3WIRE: + return MXC_SPI_SetInterface(spi, MXC_SPI_INTERFACE_3WIRE); + + case SPI_WIDTH_STANDARD: + return MXC_SPI_SetInterface(spi, MXC_SPI_INTERFACE_STANDARD); + + case SPI_WIDTH_DUAL: + return MXC_SPI_SetInterface(spi, MXC_SPI_INTERFACE_DUAL); + break; + + case SPI_WIDTH_QUAD: + return MXC_SPI_SetInterface(spi, MXC_SPI_INTERFACE_QUAD); + + default: + return E_BAD_PARAM; + } +} + +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi) +{ + mxc_spi_interface_t if_mode; + + if_mode = MXC_SPI_GetInterface(spi); + + switch (if_mode) { + case MXC_SPI_INTERFACE_STANDARD: + return SPI_WIDTH_STANDARD; + + case MXC_SPI_INTERFACE_QUAD: + return SPI_WIDTH_QUAD; + + case MXC_SPI_INTERFACE_DUAL: + return SPI_WIDTH_DUAL; + + case MXC_SPI_INTERFACE_3WIRE: + return SPI_WIDTH_3WIRE; + + default: + return SPI_WIDTH_STANDARD; + } +} + +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi) +{ + MXC_SPI_AbortTransmission(spi); +} + +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx) +{ + return E_NOT_SUPPORTED; +} + +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi) +{ + return E_NOT_SUPPORTED; +} + +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode) +{ + switch (spiMode) { + case SPI_MODE_0: + return MXC_SPI_SetClkMode(spi, MXC_SPI_CLKMODE_0); + + case SPI_MODE_1: + return MXC_SPI_SetClkMode(spi, MXC_SPI_CLKMODE_1); + + case SPI_MODE_2: + return MXC_SPI_SetClkMode(spi, MXC_SPI_CLKMODE_2); + + case SPI_MODE_3: + return MXC_SPI_SetClkMode(spi, MXC_SPI_CLKMODE_3); + + default: + return E_BAD_PARAM; + } +} + +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi) +{ + mxc_spi_clkmode_t clk_mode; + + clk_mode = MXC_SPI_GetClkMode(spi); + + switch (clk_mode) { + case MXC_SPI_CLKMODE_0: + return SPI_MODE_0; + + case MXC_SPI_CLKMODE_1: + return SPI_MODE_1; + + case MXC_SPI_CLKMODE_2: + return SPI_MODE_2; + + case MXC_SPI_CLKMODE_3: + return SPI_MODE_3; + + default: + return SPI_MODE_0; + } +} + +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) +{ + return MXC_SPI_RevA2_SetDummyTX((mxc_spi_reva_regs_t *)spi, defaultTXData); +} + +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state) +{ + MXC_ASSERT(0); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c index 35aec655..738c0652 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me21.c @@ -281,42 +281,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -343,43 +325,26 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - case 2: - reqselTx = MXC_DMA_REQUEST_SPI2TX; - break; + case 2: + reqselTx = MXC_DMA_REQUEST_SPI2TX; + reqselRx = MXC_DMA_REQUEST_SPI2RX; + break; - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 2: - reqselRx = MXC_DMA_REQUEST_SPI2RX; - break; - - default: - return E_BAD_PARAM; - } - } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, MXC_DMA); } diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c new file mode 100644 index 00000000..ac48b4f2 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -0,0 +1,440 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spi_reva1.h" +#include "dma.h" + +/* **** Definitions **** */ + +/* ************************************************************************** */ +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins) +{ + int spi_num; + + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + if (numSlaves > MXC_SPI_SS_INSTANCES) { + return E_BAD_PARAM; + } + + // Check if frequency is too high + if ((spi_num == 0) && (hz > PeripheralClock)) { + return E_BAD_PARAM; + } + + if ((spi_num == 1) && (hz > SystemCoreClock)) { + return E_BAD_PARAM; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + mxc_gpio_cfg_t gpio_cfg_spi; + gpio_cfg_spi.pad = MXC_GPIO_PAD_NONE; + gpio_cfg_spi.port = MXC_GPIO0; + + // Set VDDIO level + if (pins.vddioh) { + gpio_cfg_spi.vssel = MXC_GPIO_VSSEL_VDDIOH; + } else { + gpio_cfg_spi.vssel = MXC_GPIO_VSSEL_VDDIO; + } + + // Configure GPIO for spi + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI); + +#if (TARGET != MAX78000 || TARGET_NUM == 32655) + + //Define pins + if (pins.ss1) { + gpio_cfg_spi.mask = MXC_GPIO_PIN_26; + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + MXC_GPIO_Config(&gpio_cfg_spi); + } + + if (pins.ss2) { + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + gpio_cfg_spi.mask = MXC_GPIO_PIN_27; + MXC_GPIO_Config(&gpio_cfg_spi); + } + +#endif + //clear mask + gpio_cfg_spi.mask = 0; + + // TODO(ME30): Validate pin assignments + // check rest of the pins + if (pins.clock) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; + } + + if (pins.miso) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; + } + + if (pins.mosi) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; + } + + if (pins.sdio2) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; + } + + if (pins.sdio3) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; + } + + if (pins.ss0) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; + } + + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; + + MXC_GPIO_Config(&gpio_cfg_spi); +#else + (void)pins; +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_SPI_RevA1_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, + ssPolarity, hz); +} + +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + (void)spi_num; + + MXC_SPI_RevA1_Shutdown((mxc_spi_reva_regs_t *)spi); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI); + + return E_NO_ERROR; +} + +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_ReadyForSleep((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) +{ + int retval; + + // TODO(ME30): Validate this logic + int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + switch (sys_clk) { + case MXC_SYS_CLOCK_IPO: + retval = IPO_FREQ; + break; + case MXC_SYS_CLOCK_IBRO: + retval = IBRO_FREQ; + break; + case MXC_SYS_CLOCK_INRO: + retval = INRO_FREQ; + break; + case MXC_SYS_CLOCK_ERTCO: + retval = ERTCO_FREQ; + break; + // TODO(ME30): EXTCLK definition is missing from registers + // case MXC_SYS_CLOCK_EXTCLK: + // retval = EXTCLK_FREQ; + // break; +#if TARGET_NUM == 32655 || TARGET_NUM == 32680 + case MXC_SYS_CLOCK_ERFO: + retval = ERFO_FREQ; + break; +#endif + default: + return E_BAD_STATE; + } + + retval /= 2; + + return retval; +} + +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz) +{ + return MXC_SPI_RevA1_SetFrequency((mxc_spi_reva_regs_t *)spi, hz); +} + +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetFrequency((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize) +{ + return MXC_SPI_RevA1_SetDataSize((mxc_spi_reva_regs_t *)spi, dataSize); +} + +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetDataSize((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx) +{ + return MXC_SPI_RevA1_SetSlave((mxc_spi_reva_regs_t *)spi, ssIdx); +} + +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetSlave((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth) +{ + return MXC_SPI_RevA1_SetWidth((mxc_spi_reva_regs_t *)spi, spiWidth); +} + +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetWidth((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetMTMode(mxc_spi_regs_t *spi, int mtMode) +{ + return MXC_SPI_RevA1_SetMTMode((mxc_spi_reva_regs_t *)spi, mtMode); +} + +int MXC_SPI_GetMTMode(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetMTMode((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode) +{ + return MXC_SPI_RevA1_SetMode((mxc_spi_reva_regs_t *)spi, spiMode); +} + +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetMode((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_StartTransmission((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_GetActive(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetActive((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_AbortTransmission((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) +{ + return MXC_SPI_RevA1_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); +} + +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) +{ + return MXC_SPI_RevA1_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); +} + +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearRXFIFO((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearTXFIFO((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return MXC_SPI_RevA1_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetRXThreshold((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return MXC_SPI_RevA1_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetTXThreshold((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn) +{ + MXC_SPI_RevA1_EnableInt((mxc_spi_reva_regs_t *)spi, intEn); +} + +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis) +{ + MXC_SPI_RevA1_DisableInt((mxc_spi_reva_regs_t *)spi, intDis); +} + +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_MasterTransaction((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_MasterTransactionAsync((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if (req->txData != NULL) { + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPITX; + break; + + default: + return E_BAD_PARAM; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPIRX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); +} + +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_SlaveTransaction((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if (req->txData != NULL) { + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPITX; + break; + + default: + return E_BAD_PARAM; + break; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPIRX; + break; + + default: + return E_BAD_PARAM; + break; + } + } + + return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); +} + +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) +{ + return MXC_SPI_RevA1_SetDefaultTXData((mxc_spi_reva_regs_t *)spi, defaultTXData); +} + +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_AbortAsync((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_AsyncHandler((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state) +{ + MXC_SPI_RevA1_HWSSControl((mxc_spi_reva_regs_t *)spi, state); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c index 4254d262..338de200 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_me55.c @@ -279,42 +279,24 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; - - default: - return E_BAD_PARAM; - } - } - - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - - default: - return E_BAD_PARAM; - } + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; + + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, @@ -340,42 +322,24 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) spi_num = MXC_SPI_GET_IDX(req->spi); MXC_ASSERT(spi_num >= 0); - if (req->txData != NULL) { - switch (spi_num) { - case 0: - reqselTx = MXC_DMA_REQUEST_SPI0TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 3: - reqselTx = MXC_DMA_REQUEST_SPI3TX; - break; + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; - default: - return E_BAD_PARAM; - } - } + case 1: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; - if (req->rxData != NULL) { - switch (spi_num) { - case 0: - reqselRx = MXC_DMA_REQUEST_SPI0RX; - break; + case 3: + reqselTx = MXC_DMA_REQUEST_SPI3TX; + reqselRx = MXC_DMA_REQUEST_SPI3RX; + break; - case 1: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 3: - reqselRx = MXC_DMA_REQUEST_SPI3RX; - break; - - default: - return E_BAD_PARAM; - } + default: + return E_BAD_PARAM; } return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c index 4c7fd64e..fbe87887 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c @@ -952,7 +952,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1007,9 +1007,15 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } //tx - if (req->txData != NULL && !tx_is_complete) { + if (req->txData != NULL && req->txLen && !tx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselTx; config.ch = states[spi_num].channelTx; advConfig.ch = states[spi_num].channelTx; @@ -1047,9 +1053,15 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } // rx - if (req->rxData != NULL && !rx_is_complete) { + if (req->rxData != NULL && req->rxLen && !rx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselRx; config.ch = states[spi_num].channelRx; config.srcinc_en = 0; @@ -1095,11 +1107,11 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in } // Manually run TX/RX callbacks if the FIFO pre-load already completed that portion of the transaction - if (tx_is_complete) { + if (req->txData != NULL && req->txLen && tx_is_complete) { MXC_SPI_RevA1_DMACallback(states[spi_num].channelTx, E_NO_ERROR); } - if (rx_is_complete) { + if (req->rxData != NULL && req->rxLen && rx_is_complete) { MXC_SPI_RevA1_DMACallback(states[spi_num].channelRx, E_NO_ERROR); } @@ -1160,7 +1172,7 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1180,8 +1192,14 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif } bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd new file mode 100644 index 00000000..d8917410 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -0,0 +1,1227 @@ + + + + SPI + SPI peripheral. + 0x400BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + FIFO32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + FIFO16[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + FIFO8[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + CONT_MODE + Controller Mode Enable. + 1 + 1 + + + dis + SPI is Target mode. + 0 + + + en + SPI is Controller mode. + 1 + + + + + TS_IO + Target Select 0, IO direction, to support Multi-Controller mode,Target Select 0 can be input in Controller mode. This bit has no effect in target mode. + 4 + 1 + + + output + Target select 0 is output. + 0 + + + input + Target Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Controller Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Controller halts, if a transaction completes, and the TX FIFO is not empty, the Controller initiates another transaction. + 1 + + + + + TS_CTRL + Start Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Target Select at the end of a transaction. + 0 + + + ATSERT + SPI leaves Target Select asserted at the end of a transaction. + 1 + + + + + TS_ACTIVE + Target Select, when in Controller mode selects which Target devices are selected. More than one Target device can be selected. + 16 + 4 + + + TS0 + TS0 is selected. + 0x1 + + + TS1 + TS1 is selected. + 0x2 + + + TS2 + TS2 is selected. + 0x4 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLKPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLKPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_FB_INV + Clock Polarity. + 4 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 16 + 16 bits per character. + 0 + + + 1 + 1 bits per character. + 1 + + + 2 + 2 bits per character. + 2 + + + 3 + 3 bits per character. + 3 + + + 4 + 4 bits per character. + 4 + + + 5 + 5 bits per character. + 5 + + + 6 + 6 bits per character. + 6 + + + 7 + 7 bits per character. + 7 + + + 8 + 8 bits per character. + 8 + + + 9 + 9 bits per character. + 9 + + + 10 + 10 bits per character. + 10 + + + 11 + 11 bits per character. + 11 + + + 12 + 12 bits per character. + 12 + + + 13 + 13 bits per character. + 13 + + + 14 + 14 bits per character. + 14 + + + 15 + 15 bits per character. + 15 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + TSPOL + Target Select Polarity, each Target Select can have unique polarity. + 16 + 3 + + + TS0_high + TS0 active high. + 0x1 + + + TS1_high + TS1 active high. + 0x2 + + + TS2_high + TS2 active high. + 0x4 + + + + + + + TSTIME + Register for controlling SPI peripheral/Target Select Timing. + 0x10 + read-write + + + PRE + Target Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between TS active and first serial clock edge. + 0 + + + + + POST + Target Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and TS inactive. + 0 + + + + + INACT + Target Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLKCTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + CLKDIV + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_THD_VAL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FLUSH + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_LVL + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_THD_VAL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FLUSH + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_LVL + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INTFL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THD + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TSA + Target Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TSD + Target Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Controller Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Target Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + CONT_DONE + Controller Done, set when SPI Controller has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OV + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UN + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OV + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UN + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INTEN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THD + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EM + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TSA + Target Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TSD + Target Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Controller Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Target Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + CONT_DONE + Controller Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OV + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UN + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OV + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UN + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WKFL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WKEN + Register for wake up enable. + 0x2C + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EM + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STATUS + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Controller mode, set when transaction starts, cleared when last bit of last character is acted upon and Target Select de-assertion would occur. In Target mode, set when Target Select is asserted, cleared when Target Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd new file mode 100644 index 00000000..844c25a7 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd @@ -0,0 +1,29 @@ + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd new file mode 100644 index 00000000..a290bd93 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd @@ -0,0 +1,293 @@ + + + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 12 + + + + + GPIO1 + Secure GPIO1 Configuration Register. + 0x0184 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 2 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd new file mode 100644 index 00000000..005effeb --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -0,0 +1,399 @@ + + + + FCR + Function Control Register. + 0x40000800 + + 0x00 + 0x400 + registers + + + + CTRL + Function Control 0 Register. + 0x00 + read-write + + + BTLELDO_RF + BTLE LDO RF Trim. + 0 + 5 + + + BTLELDO_BB + BTLE LDO BB Trim. + 8 + 5 + + + I3CDGEN0 + I3C SDA Glitch Filter Enable. + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I3CDGEN1 + I3C SCL Glitch Filter Enable. + 21 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + + + AUTOCAL0 + Automatic Calibration 0 Register. + 0x04 + read-write + + + EN + Auto-calibration Enable. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + RUN + Autocalibration Run. + 1 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + LOAD_TRIM + Load Trim. + 2 + 1 + + + GAIN_INV + Invert Gain. + 3 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + ATOMIC + Atomic mode. + 4 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + MU + MU value. + 8 + 12 + + + TRIM_OUT + IPO Auto Calibration Trim + 23 + 9 + + + + + AUTOCAL1 + Automatic Calibration 1 Register. + 0x08 + read-write + + + INIT_TRIM + IPO Trim Automatic Calibration Initial Trim. + 0 + 9 + + + + + AUTOCAL2 + Automatic Calibration 2 Register. + 0x0C + read-write + + + RUNTIME + IPO Trim Autocal Run Time + 0 + 8 + + + DIV + IPO Trim Automatic Calibration Divide Factor. + 8 + 13 + + + + + ERFOKS + ERFO Kick Start Register. + 0x18 + read-write + + + CNT + Kick Start ERFO Counter. + 0 + 7 + + + EN + Kick Start ERFO Enable. + 7 + 1 + + + DRVSTR + Kick Start ERFO Drive Strength. + 8 + 3 + + + X2_PLEN + ERFO Kick Start Enable Double Pulse Length. + 11 + 1 + + + CLKSEL + Kick Start Clock Select for ERFO + 12 + 2 + + + NO_CLK + No kick start clock. + 0 + + + IPO + IPO. + 3 + + + + + + + INTFL + Interrupt Flag Register. + 0x1C + read-write + + + ERTOC_RDY + ERTCO 32K Ready. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Flag. + 1 + 1 + + + + + INTEN + Interrupt Enable Register. + 0x20 + read-write + + + ERTOC_RDY + ERTCO 32K Ready Interrupt Enable. + 0 + 1 + + + FRQCNT + Frequency Counter Interrupt Enable. + 1 + 1 + + + + + ERFOCTRL + ERFO Control Register. + 0x24 + read-write + + + CAP_X1 + Load capacitor tuning bit for X1. + 0 + 7 + + + CAP_X2 + Load capacitor tuning bit for X2. + 7 + 7 + + + CAP_BYPASS + Bypass (disable) load capacitors. + 14 + 1 + + + + + FRQCNTCTRL + Frequency Counter Control Register. + 0x28 + read-write + + + START + Start Compare. + 0 + 1 + + + CMP_CLKSEL + Compared Clock Select. + 1 + 2 + + + RTC + RTC. + 0 + + + EXT_GPIO + External GPIO. + 2 + + + INRO + INRO. + 3 + + + + + + + FRQCNTCMP + Frequency Counter Compared Target Register. + 0x2C + read-write + + + TARGET + Compared Clock Target. + 0 + 14 + + + + + REFCLK + Reference Clock Result Register. + 0x30 + read-only + + + RESULT + Reference Clock Result. + 0 + 20 + + + + + CMPCLK + Compared Clock Result Register. + 0x34 + read-only + + + RESULT + Compared Clock Result. + 0 + 14 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd index 018778fd..f147d782 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd @@ -1865,8 +1865,8 @@ 0x74 - LDOTXEN - LDOTX Enable + LDORXEN + LDORX Enable 0 1 @@ -1883,8 +1883,8 @@ - LDOTXOPULLD - LDOTX PULL Disable + LDORXOPULLD + LDORX PULL Disable 1 1 @@ -1901,24 +1901,24 @@ - LDOTXVSEL - LDOTX Voltage Setting + LDORXVSEL + LDORX Voltage Setting 2 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -1929,8 +1929,8 @@ - LDORXEN - LDORX Enable + LDOTXEN + LDOTX Enable 4 1 @@ -1947,8 +1947,8 @@ - LDORXPULLD - LDORX Pulldown + LDOTXPULLD + LDOTX Pulldown 5 1 @@ -1965,24 +1965,24 @@ - LDORXVSEL - LDORX Output Voltage Setting + LDOTXVSEL + LDOTX Output Voltage Setting 6 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -1993,8 +1993,8 @@ - LDORXBYP - LDORX Bypass Enable + LDOTXBYP + LDOTX Bypass Enable 8 1 @@ -2011,8 +2011,8 @@ - LDORXDISCH - LDORX Discharge + LDOTXDISCH + LDOTX Discharge 9 1 @@ -2029,8 +2029,8 @@ - LDOTXBYP - LDOTX Bypass Enable + LDORXBYP + LDORX Bypass Enable 10 1 @@ -2047,8 +2047,8 @@ - LDOTXDISCH - LDOTX Discharge + LDORXDISCH + LDORX Discharge 11 1 @@ -2065,8 +2065,8 @@ - LDOTXENDLY - LDOTX Enable Delay + LDORXENDLY + LDORX Enable Delay 12 1 @@ -2083,8 +2083,8 @@ - LDORXENDLY - LDORX Enable Delay + LDOTXENDLY + LDOTX Enable Delay 13 1 @@ -2101,13 +2101,13 @@ - LDORXBYPENENDLY + LDOTXBYPENENDLY LDOTX Bypass Enable Delay 14 1 - LDOTXBYPENENDLY + LDORXBYPENENDLY LDORX Bypass Enable Delay 15 1 @@ -2126,14 +2126,14 @@ 8 - LDORXDLYCNT - LDORX Delay Count. Count delay base on PCLK/128. + LDOTXDLYCNT + LDOTX Delay Count. Count delay base on PCLK/128. 8 9 - LDOTXDLYCNT - LDOTX Delay Count. Count delay base on PCLK/128. + LDORXDLYCNT + LDORX Delay Count. Count delay base on PCLK/128. 20 9 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd new file mode 100644 index 00000000..a580c6ad --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -0,0 +1,1000 @@ + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE + + + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CHKRES + ROM Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + OVR + Operating Voltage Range. + 16 + 2 + + + + + RST0 + Reset. + 0x04 + + + DMA0 + DMA Reset. + 0 + 1 + + + WDT + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + TMR0 + Timer0 Reset. + 5 + 1 + + + TMR1 + Timer1 Reset. + 6 + 1 + + + TMR2 + Timer2 Reset. + 7 + 1 + + + TMR3 + Timer3 Reset. + 8 + 1 + + + TMR4 + Timer4 Reset. + 9 + 1 + + + TMR5 + Timer5 Reset. + 10 + 1 + + + UART + UART Reset. + 11 + 1 + + + SPI + SPI Reset. + 13 + 1 + + + I3C + I3C Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + TRNG + TRNG Reset. + 24 + 1 + + + DMA1 + DMA1 Reset. + 27 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + + + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + IPO + The internal Primary oscillator is used for the system clock. + 0 + + + ERFO + 27MHz Crystal is used for the system clock. + 2 + + + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + + EXTCLK + External Clock. + 7 + + + + + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + IPO_EN + 50MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 + 1 + + + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + + + IPO_RDY + Internal Primary Oscillator Ready. + 26 + 1 + + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 + 1 + + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 4 + + + ACTIVE + Active Mode. + 0 + + + BACKUP + Backup Mode. + 4 + + + PDM + DeepSleep Mode. + 10 + + + + + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + WUT_WE + Enable Wakeup Timer as wakeup source. + 7 + 1 + + + ERFO_BP + XTAL Bypass + 20 + 1 + + + normal + Normal + 0 + + + bypass + Bypass + 1 + + + + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + + + CLKDIV + Clock Divide Value. + 0 + 32 + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + DMA0 + DMA0 Disable. + 5 + 1 + + + SPI + SPI Disable. + 6 + 1 + + + UART + UART Disable. + 9 + 1 + + + I3C + I3C Disable. + 13 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + TMR4 + Timer 4 Disable. + 19 + 1 + + + TMR5 + Timer 5 Disable. + 20 + 1 + + + + + MEMCTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + + + MEMZ + Memory Zeroize Control. + 0x2C + + + SRAM0 + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + SRAM1 + System RAM Block 1. + 1 + 1 + + + SRAM2 + System RAM Block 2. + 2 + 1 + + + SRAM3 + System RAM Block 3. + 3 + 1 + + + SRAM4 + System RAM Block 4. + 4 + 1 + + + ICC + Internal Cache. + 5 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 + 1 + + + AUTOCAL + Auto calibration Reset. + 12 + 1 + + + BTLE + BTLE Reset. + 18 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + TRNG + TRNG Clock Disable. + 2 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + CRC + CRC Disable. + 14 + 1 + + + AES + AES Clock Disable + 15 + 1 + + + DMA1 + DMA1 Clock Disable + 21 + 1 + + + WDT + WDT Clock Disable + 27 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA0 + Enable DMA0 event. When this bit is set, a DMA0 event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + DMA1 + Enable DMA1 event. When this bit is set, a DMA1 event will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSINTEN + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + ECCERR + ECC Error Register + 0x64 + + + FLASH + ECC Flash Error Flag. Write 1 to clear. + 0 + 1 + + + + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + + + ECCINTEN + ECC Interrupt Enable Register + 0x6C + + + FLASH + ECC Flash0 Interrupt Enable. + 0 + 1 + + + + + ECCADDR + ECC Error Address Register + 0x70 + + + DADDR + Address of Error in Data RAM. + 0 + 14 + + + DB + Data Bank, + 14 + 1 + + + DE + Data Error Flag. + 15 + 1 + + + TADDR + Address of Error in Tag RAM. + 16 + 14 + + + TB + Tag Bank. + 30 + 1 + + + TE + Tag Error Flag. + 31 + 1 + + + + + BTLELDOCTRL + BTLE LDO Control Register + 0x74 + + + BB_EN + LDO BB enable. + 0 + 1 + + + BB_PD_EN + LDO BB Pull Down. + 1 + 1 + + + BB_VSEL + Voltage Selection for BB LDO. + 2 + 2 + + + RF_EN + LDO RF enable. + 4 + 1 + + + RF_PD_EN + LDO RF Pull DOwn. + 5 + 1 + + + RF_VSEL + LDO RF Voltage Setting. + 6 + 2 + + + RF_BP_EN + LDO RF Bypass Enable. + 8 + 1 + + + RF_DISCH + LDO RF Discharge. + 9 + 1 + + + BB_BP_EN + LDO BB Bypass Enable. + 10 + 1 + + + BB_DISCH + LDO BB Discharge. + 11 + 1 + + + BB_EN_DLY + LDO BB Enable Delay. + 12 + 1 + + + RF_EN_DLY + LDO RF Enable Delay. + 13 + 1 + + + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. + 14 + 1 + + + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. + 15 + 1 + + + + + BTLELDODLY + BTLE LDO Delay Register + 0x78 + + + BP_CNT + Bypass delay count. + 0 + 8 + + + BB_CNT + BB delay count. + 8 + 9 + + + RF_CNT + RF delay count. + 20 + 9 + + + + + GPR + General Purpose Register 0. + 0x80 + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd new file mode 100644 index 00000000..814c4e73 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -0,0 +1,104 @@ + + + + MCR + Misc Control. + 0x40006C00 + + 0x00 + 0x400 + registers + + + + RST + Reset Register. + 0x04 + + + BOOST + Reset BOOST Controller. + 0 + 1 + + + + + OUTEN + Output Enable Register. + 0x08 + + + SQWOUT_EN + Square Wave Output Enable. + 0 + 1 + + + + + CTRL + Control Register + 0x10 + + + CLKSEL + Clcok Select for the RTC, System, WUT, and Timer. + 0 + 2 + + + ERTCO + ERTCO as clock source. + 0 + + + INRO_DIV4 + INRO as clock source. + 1 + + + RTC_IN_DIV8 + P0.12 div 8 as clock source. + 2 + + + + + ERTCO32K_EN + Enable the 32KHz ERTCO. + 3 + 1 + + + ERTCO_EN + Enable the ERTCO. + 5 + 1 + + + + + BYPASS0 + This register is used by firmware to bypass chain of trust on a Warm Boot. + 0x30 + + + BYPASS1 + This register is used by firmware to bypass chain of trust on a Warm Boot. + 0x34 + + + DATA0 + Battery Back Data0 Register. Retains value in all modes. + 0x40 + + + DATA1 + Battery Back Data1 Register. Retains value in all modes. + 0x44 + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd new file mode 100644 index 00000000..330f128c --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd @@ -0,0 +1,124 @@ + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x000 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x004 + read-only + + + ERRADDR + 0 + 32 + + + + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + + + SFSTAT + Security function status register. + 0x104 + read-only + + + SECBOOT_EN + Security Boot. + 0 + 1 + + + SECEXT_EN + M33 SecExt Function Enable. + 1 + 1 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd new file mode 100644 index 00000000..c834decf --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd @@ -0,0 +1,42 @@ + + + + TRIMSIR + Trim System Initilazation Registers. + 0x40005400 + + 0x00 + 0x400 + registers + + + + RTCX1 + RTC X1 Capacitor Setting. + 0x3C + + + CAP + RTC X1 Load Capacitor Setting. + 0 + 5 + + + + + RTCX2 + RTC X2 Capacitor Setting. + 0x44 + + + CAP + RTC X2 Load Capacitor Setting. + 0 + 5 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c b/MAX/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c index 1c1034c6..b2afc940 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/mxc_lock.c @@ -52,13 +52,23 @@ void MXC_FreeLock(uint32_t *lock) /* ************************************************************************** */ int MXC_GetLock(uint32_t *lock, uint32_t value) { -#warning "Unimplemented for RISCV" + __disable_irq(); + if (*lock) { + __enable_irq(); + return E_BUSY; + } + + *lock = value; + + __asm volatile("fence rw, rw"); + __enable_irq(); return E_NO_ERROR; } /* ************************************************************************** */ void MXC_FreeLock(uint32_t *lock) { -#warning "Unimplemented for RISCV" + __asm volatile("fence" ::: "memory"); + *lock = 0; } #endif diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/nvic_table.c b/MAX/Libraries/PeriphDrivers/Source/SYS/nvic_table.c index 783f8ce7..2b2a792f 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/nvic_table.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/nvic_table.c @@ -1,6 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), * Copyright (C) 2023-2024 Analog Devices, Inc. * @@ -35,15 +35,15 @@ __attribute__((aligned(512))) #endif static void (*ramVectorTable[MXC_IRQ_COUNT])(void); -void NVIC_SetRAM(void) -{ #if defined(__ICCARM__) - extern void (*const __isr_vector[])(void); +extern void (*const __isr_vector[])(void); #else - /* should be defined in starup_.S */ - extern uint32_t __isr_vector[MXC_IRQ_COUNT]; +/* should be defined in starup_.S */ +extern uint32_t __isr_vector[MXC_IRQ_COUNT]; #endif +void NVIC_SetRAM(void) +{ memcpy(&ramVectorTable, &__isr_vector, sizeof(ramVectorTable)); SCB->VTOR = (uint32_t)&ramVectorTable; } diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me16.c b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me16.c index 3dadfd04..5a897c98 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me16.c @@ -47,14 +47,27 @@ const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_G MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// NOTE: UART1 pins inaccessible -const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, +// NOTE: UART1 pins inaccessible on RevA. +const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT2, +const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_IN, +const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO1, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO1, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// NOTE: UART3 pins inaccessible on RevA. +const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO0, (MXC_GPIO_PIN_26 | MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart3_flow = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// NOTE: UART3 pins inaccessible const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; @@ -62,19 +75,20 @@ const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO0, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN // NOTE: SPI1 definied here with SS0 only const mxc_gpio_cfg_t gpio_cfg_spi1 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// NOTE: SPI2 defined here with SS0 only, and NOT SS1 and SS2 +// NOTE: SPI2 defined here with SS0 only const mxc_gpio_cfg_t gpio_cfg_spi2 = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // Timers are only defined once, depending on package, each timer could be mapped to other pins const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT3, +const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT3, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// TMR 4 and 5 pins not available on Rev B. const mxc_gpio_cfg_t gpio_cfg_tmr4 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_tmr5 = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT1, @@ -89,22 +103,21 @@ const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_11, MXC_GPI const mxc_gpio_cfg_t gpio_cfg_chrg_lc1 = { MXC_GPIO1, MXC_GPIO_PIN_12, MXC_GPIO_FUNC_ALT4, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_31, MXC_GPIO_FUNC_ALT4, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_mon_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT4, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmd_rs_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT4, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_chrg_lc2 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT4, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - // SPI v2 Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi1_standard = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi1_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_15 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // MXC_SPI1 does not support Dual or Quad modes. +const mxc_gpio_cfg_t gpio_cfg_spi2_standard = { MXC_GPIO1, (MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi2_3wire = { MXC_GPIO1, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// MXC_SPI2 does not support Dual or Quad modes. // SPI v2 Target Selects Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi1_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_spi2_ts0 = { MXC_GPIO1, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me18.c b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me18.c index 2f1bf5f8..af79fc85 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me18.c @@ -56,36 +56,36 @@ const mxc_gpio_cfg_t gpio_cfg_i2c2c = { MXC_GPIO0, (MXC_GPIO_PIN_13 | MXC_GPIO_P MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO2, (MXC_GPIO_PIN_11 | MXC_GPIO_PIN_12), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO2, (MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO2, (MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO2, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_16), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO2, (MXC_GPIO_PIN_13 | MXC_GPIO_PIN_15), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO2, (MXC_GPIO_PIN_13 | MXC_GPIO_PIN_15), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_9 | MXC_GPIO_PIN_10), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO1, (MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO1, (MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO3, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart3_flow = { MXC_GPIO3, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart3_flow_disable = { MXC_GPIO3, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_PULL_UP, + MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO2, (MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT2, @@ -266,7 +266,7 @@ const mxc_gpio_cfg_t gpio_cfg_can1 = { MXC_GPIO2, (MXC_GPIO_PIN_24 | MXC_GPIO_PI // SPI v2 Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi0_standard = { MXC_GPIO2, (MXC_GPIO_PIN_27 | MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_3wire = { MXC_GPIO2, (MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_dual = { MXC_GPIO2, (MXC_GPIO_PIN_27 | MXC_GPIO_PIN_28 | MXC_GPIO_PIN_29), MXC_GPIO_FUNC_ALT1, diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me30.c new file mode 100644 index 00000000..b7fd798d --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -0,0 +1,81 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "gpio.h" +#include "mxc_device.h" + +/***** Definitions *****/ + +/***** Global Variables *****/ + +// clang-format off +// P0.0 - I3C SCL +// P0.1 - I3C SDA +const mxc_gpio_cfg_t gpio_cfg_i3c = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// P0.5 - UART RX +// P0.9 - UART TX +const mxc_gpio_cfg_t gpio_cfg_uart = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_0), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_10), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO0, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr4 = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr4b = { MXC_GPIO0, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr5 = { MXC_GPIO0, (MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr5b = { MXC_GPIO0, (MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// SPI v2 Pin Definitions +// P0.2 - SPI SDO (COTI) +// P0.4 - SPI SDI (CITO) +// P0.6 - SPI CLK +const mxc_gpio_cfg_t gpio_cfg_spi_standard = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_6), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi_dual = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// TODO(SPI): Is quad mode supported? +const mxc_gpio_cfg_t gpio_cfg_spi_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// SPI v2 Target Selects Pin Definitions +const mxc_gpio_cfg_t gpio_cfg_spi_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_8, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai85.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai85.c index da47775a..b58d1eb1 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai85.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai85.c @@ -75,7 +75,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) uint32_t _usn_32[MXC_SYS_USN_CHECKSUM_LEN / 4]; // ^ Declare as uint32_t to preserve mem alignment uint8_t *_usn_8 = (uint8_t *)_usn_32; - memset(_usn_8, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(_usn_8, 0, MXC_SYS_USN_LEN); _usn_8[0] = (infoblock[0] & 0x007F8000) >> 15; _usn_8[1] = (infoblock[0] & 0x7F800000) >> 23; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai87.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai87.c index fdb03567..808705d1 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_ai87.c @@ -75,7 +75,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) uint32_t _usn_32[MXC_SYS_USN_CHECKSUM_LEN / 4]; // ^ Declare as uint32_t to preserve mem alignment uint8_t *_usn_8 = (uint8_t *)_usn_32; - memset(_usn_8, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(_usn_8, 0, MXC_SYS_USN_LEN); _usn_8[0] = (infoblock[0] & 0x007F8000) >> 15; _usn_8[1] = (infoblock[0] & 0x7F800000) >> 23; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me12.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me12.c index f2881904..d7db012f 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me12.c @@ -70,7 +70,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; @@ -103,10 +103,12 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Set NULL Key MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + uint8_t usn_copy[MXC_SYS_USN_LEN] = { 0 }; + memcpy(usn_copy, usn, MXC_SYS_USN_LEN); // Compute Checksum mxc_aes_req_t aes_req; aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; - aes_req.inputData = (uint32_t *)usn; + aes_req.inputData = (uint32_t *)usn_copy; aes_req.resultData = (uint32_t *)check_csum; aes_req.keySize = MXC_AES_128BITS; aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me14.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me14.c index 520f5bf9..d22d481b 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me14.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me14.c @@ -64,7 +64,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me15.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me15.c index 6ffab731..dd4ad687 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me15.c @@ -76,7 +76,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; @@ -110,10 +110,13 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Set NULL Key MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + uint8_t usn_copy[MXC_SYS_USN_LEN] = { 0 }; + memcpy(usn_copy, usn, MXC_SYS_USN_LEN); + // Compute Checksum mxc_aes_req_t aes_req; aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; - aes_req.inputData = (uint32_t *)usn; + aes_req.inputData = (uint32_t *)usn_copy; aes_req.resultData = (uint32_t *)check_csum; aes_req.keySize = MXC_AES_128BITS; aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me16.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me16.c index b9268fc2..bb597468 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me16.c @@ -62,7 +62,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c index 9f2b06d8..cb9ad432 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c @@ -72,7 +72,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; @@ -105,10 +105,13 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Set NULL Key MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + uint8_t usn_copy[MXC_SYS_USN_LEN] = { 0 }; + memcpy(usn_copy, usn, MXC_SYS_USN_LEN); + // Compute Checksum mxc_aes_req_t aes_req; aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; - aes_req.inputData = (uint32_t *)usn; + aes_req.inputData = (uint32_t *)usn_copy; aes_req.resultData = (uint32_t *)check_csum; aes_req.keySize = MXC_AES_128BITS; aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c index d8305fa9..89c2386c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c @@ -71,7 +71,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; @@ -97,9 +97,9 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Initialize key and plaintext */ memset(key, 0, MXC_SYS_USN_CHECKSUM_LEN); memset(pt32, 0, MXC_SYS_USN_CHECKSUM_LEN); - memcpy(pt32, usn, MXC_SYS_USN_CHECKSUM_LEN); + memcpy(pt32, usn, MXC_SYS_USN_LEN); - /* Read the checksum from the info block */ + /* Read the checksum from the inspfo block */ checksum[1] = ((infoblock[3] & 0x7F800000) >> 23); checksum[0] = ((infoblock[4] & 0x007F8000) >> 15); diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me21.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me21.c index da04b656..f84de585 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me21.c @@ -68,7 +68,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) /* Read the USN from the info block */ MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); - memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + memset(usn, 0, MXC_SYS_USN_LEN); usn[0] = (infoblock[0] & 0x007F8000) >> 15; usn[1] = (infoblock[0] & 0x7F800000) >> 23; @@ -102,10 +102,13 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Set NULL Key MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + uint8_t usn_copy[MXC_SYS_USN_LEN] = { 0 }; + memcpy(usn_copy, usn, MXC_SYS_USN_LEN); + // Compute Checksum mxc_aes_req_t aes_req; aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; - aes_req.inputData = (uint32_t *)usn; + aes_req.inputData = (uint32_t *)usn_copy; aes_req.resultData = (uint32_t *)check_csum; aes_req.keySize = MXC_AES_128BITS; aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c new file mode 100644 index 00000000..b6b28689 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -0,0 +1,548 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mxc_sys.c + * @brief System layer driver. + * @details This driver is used to control the system layer of the device. + */ + +/* **** Includes **** */ +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gcr_regs.h" +#include "fcr_regs.h" +#include "mcr_regs.h" +#include "pwrseq_regs.h" +#include "aes.h" +#include "flc.h" + +/** + * @ingroup mxc_sys + * @{ + */ + +/* **** Definitions **** */ +#define MXC_SYS_CLOCK_TIMEOUT MSEC(1) + +// DAP Lock macros +#define INFOBLOCK_DAP_LOCK_OFFSET 0x30 +#define DAP_LOCK_SEQUENCE_01 0x5A5AA5A5 +#define DAP_LOCK_SEQUENCE_23 0xFFFFFFFF + +/* **** Globals **** */ + +/* Symbol defined when loading RISCV image */ +extern uint32_t _binary_riscv_bin_start; + +/* **** Functions **** */ + +/* ************************************************************************** */ +#if CONFIG_TRUSTED_EXECUTION_SECURE +int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) +{ + int err = E_NO_ERROR; + uint32_t *infoblock = (uint32_t *)MXC_INFO_MEM_BASE; + + if (usn == NULL) { + return E_NULL_PTR; + } + + /* Read the USN from the info block */ + MXC_FLC_UnlockInfoBlock(MXC_INFO_MEM_BASE); + + memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + + usn[0] = (infoblock[0] & 0x007F8000) >> 15; + usn[1] = (infoblock[0] & 0x7F800000) >> 23; + usn[2] = (infoblock[1] & 0x0000007F) << 1; + usn[2] |= (infoblock[0] & 0x80000000) >> 31; + usn[3] = (infoblock[1] & 0x00007F80) >> 7; + usn[4] = (infoblock[1] & 0x007F8000) >> 15; + usn[5] = (infoblock[1] & 0x7F800000) >> 23; + usn[6] = (infoblock[2] & 0x007F8000) >> 15; + usn[7] = (infoblock[2] & 0x7F800000) >> 23; + usn[8] = (infoblock[3] & 0x0000007F) << 1; + usn[8] |= (infoblock[2] & 0x80000000) >> 31; + usn[9] = (infoblock[3] & 0x00007F80) >> 7; + usn[10] = (infoblock[3] & 0x007F8000) >> 15; + + /* If requested, verify and return the checksum */ + if (checksum != NULL) { + uint8_t check_csum[MXC_SYS_USN_CHECKSUM_LEN]; + uint8_t aes_key[MXC_SYS_USN_CHECKSUM_LEN] = { 0 }; // NULL Key (per checksum spec) + + checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); + checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); + + // Info block only accessible from secure code. + // Use Secure DMA1. + err = MXC_AES_Init(MXC_DMA1); + if (err) { + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + return err; + } + + // Set NULL Key + MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + + // Compute Checksum + mxc_aes_req_t aes_req; + aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; + aes_req.inputData = (uint32_t *)usn; + aes_req.resultData = (uint32_t *)check_csum; + aes_req.keySize = MXC_AES_128BITS; + aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; + aes_req.callback = NULL; + + err = MXC_AES_Generic(&aes_req); + if (err) { + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + return err; + } + + MXC_AES_Shutdown(); + + // Verify Checksum + if (check_csum[0] != checksum[1] || check_csum[1] != checksum[0]) { + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + return E_INVALID; + } + } + + /* Add the info block checksum to the USN */ + usn[11] = ((infoblock[3] & 0x7F800000) >> 23); + usn[12] = ((infoblock[4] & 0x007F8000) >> 15); + + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); + + return err; +} +#endif + +/* ************************************************************************** */ +int MXC_SYS_GetRevision(void) +{ + return MXC_GCR->revision; +} + +/* ************************************************************************** */ +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 31) { + clock -= 32; + return !(MXC_GCR->pclkdis1 & (0x1 << clock)); + } else { + return !(MXC_GCR->pclkdis0 & (0x1 << clock)); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 31) { + clock -= 32; + MXC_GCR->pclkdis1 |= (0x1 << clock); + } else { + MXC_GCR->pclkdis0 |= (0x1 << clock); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 31) { + clock -= 32; + MXC_GCR->pclkdis1 &= ~(0x1 << clock); + } else { + MXC_GCR->pclkdis0 &= ~(0x1 << clock); + } +} +/* ************************************************************************** */ +void MXC_SYS_RTCClockEnable() +{ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; +} + +/* ************************************************************************** */ +int MXC_SYS_RTCClockDisable(void) +{ + /* Check that the RTC is not the system clock source */ + if ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) != MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO) { + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; + return E_NO_ERROR; + } else { + return E_BAD_STATE; + } +} + +#if TARGET_NUM == 32655 +/******************************************************************************/ +void MXC_SYS_RTCClockPowerDownEn(void) +{ + MXC_MCR->ctrl |= MXC_F_MCR_CTRL_32KOSC_EN; +} + +/******************************************************************************/ +void MXC_SYS_RTCClockPowerDownDis(void) +{ + MXC_MCR->ctrl &= ~MXC_F_MCR_CTRL_32KOSC_EN; +} +#endif //TARGET_NUM == 32655 + +/******************************************************************************/ +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) +{ + switch (clock) { + case MXC_SYS_CLOCK_IPO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY); + break; + + case MXC_SYS_CLOCK_IBRO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); + break; + + // TODO(ME30): EXTCLK is missing from register definitions + // case MXC_SYS_CLOCK_EXTCLK: + // // No "RDY" bit to monitor, so just configure the GPIO + // return MXC_GPIO_Config(&gpio_cfg_extclk); + // break; + + case MXC_SYS_CLOCK_INRO: + // The 80k clock is always enabled + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_INRO_RDY); + break; + + case MXC_SYS_CLOCK_ERFO: + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_RF_EN | MXC_F_GCR_BTLELDOCTRL_BB_EN; + + /* Initialize kickstart circuit + Select Kick start circuit clock source- IPO/ISO + */ + // TODO(ME30): MXC_FCR missing ERFOKS definition + // MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) + // /* Set Drive strengh - 0x1,0x2,0x3 */ + // | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) + // /* Set kick count 1-127 */ + // | (0x8) + // /* Set double pulse length On/Off*/ + // | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) + // /* Enable On/Off */ + // | (MXC_F_FCR_ERFOKS_KSERFO_EN)); + + /* Enable ERFO */ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY); + break; + + case MXC_SYS_CLOCK_ERTCO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY); + break; + + default: + return E_BAD_PARAM; + break; + } +} + +/******************************************************************************/ +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + + current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; + + // Don't turn off the clock we're running on + if (clock == current_clock) { + return E_BAD_PARAM; + } + + switch (clock) { + case MXC_SYS_CLOCK_IPO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IPO_EN; + break; + + case MXC_SYS_CLOCK_IBRO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; + break; + + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not a great way to disable the external clock. + // Deinitializing the GPIO here may have unintended consequences + // for application code. + // Selecting a different system clock source is sufficient + // to "disable" the EXT_CLK source. + // */ + // break; + + case MXC_SYS_CLOCK_INRO: + // The 80k clock is always enabled + break; + + case MXC_SYS_CLOCK_ERFO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERFO_EN; + break; + + case MXC_SYS_CLOCK_ERTCO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SYS_Clock_Timeout(uint32_t ready) +{ +#ifdef __riscv + // The current RISC-V implementation is to block until the clock is ready. + // We do not have access to a system tick in the RV core. + while (!(MXC_GCR->clkctrl & ready)) {} + return E_NO_ERROR; +#else +#ifndef BOARD_ME17_TESTER + // Start timeout, wait for ready + MXC_DelayAsync(MXC_SYS_CLOCK_TIMEOUT, NULL); + + do { + if (MXC_GCR->clkctrl & ready) { + MXC_DelayAbort(); + return E_NO_ERROR; + } + } while (MXC_DelayCheck() == E_BUSY); + + return E_TIME_OUT; +#else + + return E_NO_ERROR; +#endif + +#endif // __riscv +} +/* ************************************************************************** */ +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + + // Save the current system clock + current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; + + switch (clock) { + case MXC_SYS_CLOCK_IPO: + + // Enable IPO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; + + // Check if IPO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set IPO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO); + + break; + + case MXC_SYS_CLOCK_IBRO: + + // Enable IBRO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IBRO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; + + // Check if IBRO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set IBRO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO); + + break; + + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not "EXT_CLK RDY" bit for the ME17, so we'll + // blindly enable (configure GPIO) the external clock every time. + // */ + // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); + // if (err) + // return err; + + // // Set EXT clock as System Clock + // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + + // break; + + case MXC_SYS_CLOCK_ERFO: + + // Enable ERFO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; + + // Check if ERFO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set ERFO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO); + + break; + + case MXC_SYS_CLOCK_INRO: + // Set INRO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO); + + break; + + case MXC_SYS_CLOCK_ERTCO: + + // Enable ERTCO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERTCO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + + // Check if ERTCO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set ERTCO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO); + + break; + + default: + return E_BAD_PARAM; + } + + // Wait for system clock to be ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_SYSCLK_RDY) != E_NO_ERROR) { + // Restore the old system clock if timeout + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, current_clock); + + return E_TIME_OUT; + } + + // Update the system core clock + SystemCoreClockUpdate(); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div) +{ + /* Return if this setting is already current */ + if (div == MXC_SYS_GetClockDiv()) { + return; + } + + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_DIV, div); + + SystemCoreClockUpdate(); +} + +/* ************************************************************************** */ +mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void) +{ + return (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV); +} + +/* ************************************************************************** */ +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) +{ + /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 and 64 for the rst register. */ + if (reset > 31) { + reset -= 32; + MXC_GCR->rst1 = (0x1 << reset); + while (MXC_GCR->rst1 & (0x1 << reset)) {} + } else { + MXC_GCR->rst0 = (0x1 << reset); + while (MXC_GCR->rst0 & (0x1 << reset)) {} + } +} + +#if CONFIG_TRUSTED_EXECUTION_SECURE +/* ************************************************************************** */ +int MXC_SYS_LockDAP_Permanent(void) +{ +#ifdef DEBUG + // Locking the DAP is not supported while in DEBUG. + // To use this function, build for release ("make release") + // or set DEBUG = 0 + // (see https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-tables) + return E_NOT_SUPPORTED; +#else + int err; + uint32_t info_blk_addr; + uint32_t lock_sequence[4]; + + // Infoblock address to write lock sequence to + info_blk_addr = MXC_INFO_MEM_BASE + INFOBLOCK_DAP_LOCK_OFFSET; + + // Set lock sequence + lock_sequence[0] = DAP_LOCK_SEQUENCE_01; + lock_sequence[1] = DAP_LOCK_SEQUENCE_01; + lock_sequence[2] = DAP_LOCK_SEQUENCE_23; + lock_sequence[3] = DAP_LOCK_SEQUENCE_23; + + // Initialize FLC + MXC_FLC_Init(); + + // Unlock infoblock + MXC_FLC_UnlockInfoBlock(info_blk_addr); + + // Write DAP lock sequence to infoblock + err = MXC_FLC_Write128(info_blk_addr, lock_sequence); + + // Re-lock infoblock + MXC_FLC_LockInfoBlock(info_blk_addr); + + return err; +#endif +} +#endif + +/**@} end of mxc_sys */ diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me16.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me16.c index 901344e3..b91427f2 100644 --- a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me16.c @@ -32,6 +32,7 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) return E_NULL_PTR; } + tmr_id = MXC_TMR_GET_IDX(tmr); MXC_ASSERT(tmr_id >= 0); switch (cfg->clock) { diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c new file mode 100644 index 00000000..6b1c80e0 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -0,0 +1,367 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "tmr.h" +#include "tmr_revb.h" +#include "tmr_common.h" +#include "stdbool.h" + +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) +{ + int tmr_id = MXC_TMR_GET_IDX(tmr); + uint8_t clockSource = MXC_TMR_CLK0; + + if (cfg == NULL) { + return E_NULL_PTR; + } + + MXC_ASSERT(tmr_id >= 0); + + switch (cfg->clock) { + case MXC_TMR_IBRO_CLK: + if (tmr_id > 3) { // Timers 4-5 do not support this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK2; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ); + break; + + case MXC_TMR_IBRO_DIV8_CLK: + if (tmr_id != 5) { // Only timer 5 supports this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK1; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8)); + break; + + case MXC_TMR_ERTCO_CLK: + if (tmr_id == 4) { + clockSource = MXC_TMR_CLK1; + } else if (tmr_id < 4) { + clockSource = MXC_TMR_CLK3; + } else { // Timers 5 do not support this clock source + return E_NOT_SUPPORTED; + } + + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ); + break; + + case MXC_TMR_INRO_CLK: + if (tmr_id < 4) { // Timers 0-3 do not support this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK2; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ); + break; + + default: + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock); + break; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + //enable peripheral clock and configure gpio pins + switch (tmr_id) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr0); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr0b); + } + } + + break; + + case 1: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr1); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr1b); + } + } + + break; + + case 2: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr2); + } + } + + break; + + case 3: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr3); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr3b); + } + } + + break; + + case 4: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR4); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4); + break; + + case 5: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR5); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5); + break; + } +#else + (void)init_pins; +#endif + + return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource); +} + +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) +{ + MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0); + + MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr); + + // System settigns + //diasble peripheral clock + if (tmr == MXC_TMR0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); + } + + if (tmr == MXC_TMR1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); + } + + if (tmr == MXC_TMR2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); + } + + if (tmr == MXC_TMR3) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3); + } + + if (tmr == MXC_TMR4) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4); + } + + if (tmr == MXC_TMR5) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5); + } +} + +void MXC_TMR_Start(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr); +} + +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm) +{ + return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm); +} + +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency) +{ + uint32_t clockFrequency = PeripheralClock; + int tmr_id = MXC_TMR_GET_IDX(tmr); + + MXC_ASSERT(tmr_id >= 0); + + if (tmr_id > 3) { + switch (clock) { + case MXC_TMR_APB_CLK: + clockFrequency = IBRO_FREQ; + break; + +#if (TARGET_NUM != 32680) + case MXC_TMR_ERTCO_CLK: + clockFrequency = ERTCO_FREQ; + break; +#endif + + case MXC_TMR_INRO_CLK: + clockFrequency = INRO_FREQ; + break; + + case MXC_TMR_IBRO_DIV8_CLK: + clockFrequency = IBRO_FREQ / 8; + break; + + default: + break; + } + } else { + switch (clock) { + case MXC_TMR_APB_CLK: + clockFrequency = PeripheralClock; + break; + + case MXC_TMR_IBRO_CLK: + clockFrequency = IBRO_FREQ; + break; + + case MXC_TMR_ERTCO_CLK: + clockFrequency = ERTCO_FREQ; + break; + + default: + break; + } + } + + return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency); +} + +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) +{ + MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); +} + +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) +{ + MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); +} + +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) +{ + MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt); +} + +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) +{ + MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt); +} + +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us) +{ + MXC_TMR_Common_Delay(tmr, us); +} + +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us) +{ + MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us); +} + +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Check(tmr); +} + +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Stop(tmr); +} + +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Clear(tmr); +} + +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Elapsed(tmr); +} + +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Remaining(tmr); +} + +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_SW_Start(tmr); +} + +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_SW_Stop(tmr); +} + +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +{ + return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units); +} + +int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks) +{ + return MXC_TMR_RevB_GetTicks((mxc_tmr_revb_regs_t *)tmr, time, units, ticks); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c index dbb50679..1d9e0476 100644 --- a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_reva.c @@ -37,64 +37,72 @@ void MXC_TMR_RevA_Init(mxc_tmr_reva_regs_t *tmr, mxc_tmr_cfg_t *cfg) // Set the prescaler switch (cfg->pres) { case MXC_TMR_PRES_1: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV1); break; case MXC_TMR_PRES_2: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV2); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV2); break; case MXC_TMR_PRES_4: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV4); break; case MXC_TMR_PRES_8: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV8); break; case MXC_TMR_PRES_16: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV16); break; case MXC_TMR_PRES_32: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV32); break; case MXC_TMR_PRES_64: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV64); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV64); break; case MXC_TMR_PRES_128: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV128); + tmr->cn &= ~(MXC_F_TMR_REVA_CN_PRES3); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV128); break; case MXC_TMR_PRES_256: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn &= ~(MXC_S_TMR_REVA_CN_PRES_DIV1); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV1); break; case MXC_TMR_PRES_512: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV4); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV2); break; case MXC_TMR_PRES_1024: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV8); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV4); break; case MXC_TMR_PRES_2048: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV16); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV8); break; case MXC_TMR_PRES_4096: tmr->cn |= (MXC_F_TMR_REVA_CN_PRES3); - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV32); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV16); break; default: - tmr->cn |= (MXC_S_TMR_REVA_CN_PRES_DIV1); + MXC_SETFIELD(tmr->cn, 0b111 << MXC_F_TMR_REVA_CN_PRES_POS, MXC_S_TMR_REVA_CN_PRES_DIV1); break; } diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c index 18a81332..46786062 100644 --- a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c @@ -192,7 +192,8 @@ void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) while (!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))) {} tmr->cmp = (cfg->cmp_cnt << timerOffset); -#if TARGET_NUM == 32655 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 +#if TARGET_NUM == 32655 || TARGET_NUM == 32657 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || \ + TARGET_NUM == 78002 tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #else tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd new file mode 100644 index 00000000..5bb17764 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd @@ -0,0 +1,662 @@ + + + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + diff --git a/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c b/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c new file mode 100644 index 00000000..9d9725e5 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c @@ -0,0 +1,89 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "trng_revb.h" +#include "trng.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/********************************************************/ + +int MXC_TRNG_Init(void) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); +#endif + + MXC_TRNG_RevB_Init(); + + return E_NO_ERROR; +} + +void MXC_TRNG_EnableInt(void) +{ + MXC_TRNG_RevB_EnableInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +void MXC_TRNG_DisableInt(void) +{ + MXC_TRNG_RevB_DisableInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +int MXC_TRNG_Shutdown(void) +{ + int error = MXC_TRNG_RevB_Shutdown(); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TRNG); + + return error; +} + +void MXC_TRNG_Handler(void) +{ + MXC_TRNG_RevB_Handler((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +/* ************************************************************************* */ +/* True Random Number Generator (TRNG) functions */ +/* ************************************************************************* */ + +int MXC_TRNG_RandomInt(void) +{ + return MXC_TRNG_RevB_RandomInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +int MXC_TRNG_Random(uint8_t *data, uint32_t len) +{ + return MXC_TRNG_RevB_Random(data, len); +} + +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback) +{ + MXC_TRNG_RevB_RandomAsync((mxc_trng_revb_regs_t *)MXC_TRNG, data, len, callback); +} + +int MXC_TRNG_HealthTest(void) +{ + return MXC_TRNG_RevB_HealthTest((mxc_trng_revb_regs_t *)MXC_TRNG); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd b/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd new file mode 100644 index 00000000..e7184d78 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd @@ -0,0 +1,349 @@ + + + + TRNG + Random Number Generator. + 0x4004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CTRL + TRNG Control Register. + 0x00 + 0x00000003 + + + OD_HEALTH + Start On-Demand health test. + 0 + 1 + + + RND_IE + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_IE + Enable IRQ generation when a health test fails. + 2 + 1 + + + AESKG_MEU + Generate and transfer 256 bit MEU key to AES Key storage. + 3 + 1 + + + AESKG_MEMPROT_XIP + Generate and transfer 128 bit MEMPROT_XIP key to AES key storage. + 4 + 1 + + + AESKG_MEMPROT_DIP + Generate and transfer 128 bit MEMPROT_DIP key to AES key storage. + 5 + 1 + + + OD_ROMON + Start ring oscillator monitor on demand test. + 6 + 1 + + + OD_EE + Start entropy estimator on demand test. + 7 + 1 + + + ROMON_EE_FOE + Ring Oscillator Monitors and Entropy Estimator Freeze on Error. + 8 + 1 + + + ROMON_EE_FOD + Ring Oscillator Monitors and Entropy Estimator Freeze on Done. + 9 + 1 + + + EBLS + Entropy Bit Load Select. + 10 + 1 + + + KEYWIPE + To wipe the Battery Backed key. + 15 + 1 + + + GET_TERO_CNT + Get Tero Count. + 16 + 1 + + + EE_DONE_IE + Entropy Estimator Done Interrupt Enable. + 23 + 1 + + + ROMON_DIS + Ring Oscillator Disable. + 24 + 3 + + + RO_0 + Ring Oscillator 0. + 1 + + + RO_1 + Ring Oscillator 1. + 2 + + + RO_2 + Ring Oscillator 2. + 4 + + + + + ROMON_DIV2 + Divide ring by 2. + 28 + 3 + + + RO_0 + Ring Oscillator 0. + 0 + + + RO_1 + Ring Oscillator 1. + 1 + + + RO_2 + Ring Oscillator 2. + 2 + + + + + + + STATUS + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + + + RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + OD_HEALTH + On-Demand health test status. + 1 + 1 + + + HEALTH + Health test status. + 2 + 1 + + + SRCFAIL + Entropy source has failed. + 3 + 1 + + + AES_KEYGEN + AESKGD. + 4 + 1 + + + OD_ROMON + On demand ring oscillator test status. + 6 + 1 + + + OD_EE + On demand entropy estimator status. + 7 + 1 + + + PP_ERR + Post process error. + 8 + 1 + + + ROMON_0_ERR + Ring Oscillator 0 Monitor Error. + 9 + 1 + + + ROMON_1_ERR + Ring Oscillator 1 Monitor Error. + 10 + 1 + + + ROMON_2_ERR + Ring Oscillator 2 Monitor Error. + 11 + 1 + + + EE_ERR_THR + Entropy Estimator Threshold Error. + 12 + 1 + + + EE_ERR_OOB + Entropy Estimator Out of Bounds Error.. + 13 + 1 + + + EE_ERR_LOCK + Entropy Estimator Lock Error. + 14 + 1 + + + TERO_CNT_RDY + TERO Count Ready. + 16 + 1 + + + RC_ERR + Repetition Count Error. + 17 + 1 + + + AP_ERR + Adaptive Proportion Error. + 18 + 1 + + + DATA_DONE + Data register has been loaded with at least 32 new entropy bits. + 19 + 1 + + + DATA_NIST_DONE + Data NIST register has been loaded with at least 32 new entropy bits. + 20 + 1 + + + HEALTH_DONE + Health Test Done. + 21 + 1 + + + ROMON_DONE + Ring Oscillator Monitor Test Done. + 22 + 1 + + + EE_DONE + Entropy Estimator Test Done. + 23 + 1 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + DATA_NIST + Data NIST Register. + 0x38 + + + DATA + Ring Oscillator 1 Monitor Last Ring Oscillator Count. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c b/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c new file mode 100644 index 00000000..b0e79a1e --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.c @@ -0,0 +1,255 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mpc_me30.c + * @brief Memory Protection Controller (MPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the security policy of each + * memory region (SRAM0-4 and Flash). + */ + +// TODO(MPC): Add Interrupt functionality. + +/** + * The MPC is only accessible from Secure World. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 1 + +/**** Includes ****/ + +#include +#include "mxc_device.h" +#include "mpc.h" +#include "spc.h" + +/**** Definitions ****/ +// Enumeration for security policy. +typedef enum { MXC_MPC_STATE_SECURE = 0, MXC_MPC_STATE_NONSECURE = 1 } mxc_mpc_state_t; + +/**** Globals ****/ + +/**** Functions ****/ + +static int MXC_MPC_SetBlockSecurity(int start_addr, int end_addr, mxc_mpc_state_t state) +{ + int error; + uint32_t phy_start_addr, phy_end_addr; + + int i, j; + uint32_t curr_addr, start_mpc_region_addr, end_mpc_region_addr; + uint32_t start_block_idx; + uint32_t end_block_idx; + mxc_mpc_regs_t *start_mpc; + mxc_mpc_regs_t *end_mpc; + mxc_mpc_regs_t *curr_mpc; + + // Check for supported address ranges. + if (start_addr > end_addr) { + return E_BAD_PARAM; + } + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of address. + phy_start_addr = start_addr & ~(1 << 28); + phy_end_addr = end_addr & ~(1 << 28); + + // Ensure the start address is not past the end address. + if (phy_start_addr > phy_end_addr) { + return E_BAD_PARAM; + } + + // Check addresses are within usable memory regions. + error = MXC_MPC_CheckPhyBoundaries(phy_start_addr, phy_end_addr); + if (error != E_NO_ERROR) { + return error; + } + + // Set all blocks within each MPC of the given memory regions to Secure. + start_mpc = MXC_MPC_GetInstance(phy_start_addr); + end_mpc = MXC_MPC_GetInstance(phy_end_addr); + + if (start_mpc == NULL || end_mpc == NULL) { + // Given addresses are in memory space that doesn't support MPC. + return E_BAD_PARAM; + } + + curr_addr = phy_start_addr; + for (i = MXC_MPC_GET_IDX(start_mpc); i <= MXC_MPC_GET_IDX(end_mpc); i++) { + // Get current MPC, whether in Flash or SRAM. + curr_mpc = MXC_MPC_SRAM_GET_BASE(i); + if (curr_mpc == NULL) { + curr_mpc = MXC_MPC_FLASH_GET_BASE(i); + } + + // Get the address range of the current MPC region. + start_mpc_region_addr = curr_addr; + + // NOTE: Project Owner/Developer must be aware of the memory settings for Secure and Non-Secure + // boundaries do not share an MPC block. An MPC block can only be set to one security + // policy (Secure or Non-Secure). + if (i == MXC_MPC_GET_IDX(end_mpc)) { + // The physical ending address is within the final MPC region - stop there. + end_mpc_region_addr = phy_end_addr; + } else { + // -1 to get the last address of the current region. + end_mpc_region_addr = + MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc) - 1; + } + + start_block_idx = MXC_MPC_GetBlockIdx(curr_mpc, start_mpc_region_addr); + end_block_idx = MXC_MPC_GetBlockIdx(curr_mpc, end_mpc_region_addr); + + // TODO(SW): Precautionary measure that needs to be confirmed - prevents the MPC_BLK_LUT[n] + // register from auto-incrementing after a full word read/write occurs. + // There is only 1 available index (n) (in MPC_BLK_IDX register) for the ME30 because memory + // size does not exceed a single full word length of the MPC_BLK_LUT[n] register. Each bit + // in the MPC_BLK_LUT[n] corresponds to a block of memory with the block size given by the + // MPC_BLK_CFG register. + // For example: + // - FLASH => 1MB; MPC_FLASH Block size => 32KB. + // 32KB * 32 (bits in MPC_BLK_LUT[n] register) = 1MB. + curr_mpc->ctrl &= ~MXC_F_MPC_CTRL_AUTO_INC; + + // Set the security state of each block. + for (j = start_block_idx; j <= end_block_idx; j++) { + if (state == MXC_MPC_STATE_NONSECURE) { + curr_mpc->blk_lut |= (1 << j); + } else { + curr_mpc->blk_lut &= ~(1 << j); + } + } + + // Update curr_addr to start at the beginning of the next MPC region for the next iteration of this for loop. + curr_addr = MXC_MPC_GET_PHY_MEM_BASE(curr_mpc) + MXC_MPC_GET_PHY_MEM_SIZE(curr_mpc); + } + + return E_NO_ERROR; +} + +int MXC_MPC_CheckPhyBoundaries(uint32_t start_addr, uint32_t end_addr) +{ + uint32_t phy_start_addr, phy_end_addr; + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of the address. + phy_start_addr = start_addr & ~(1 << 28); + phy_end_addr = end_addr & ~(1 << 28); + + // Check Flash Boundaries. + if ((phy_start_addr >= MXC_PHY_FLASH_MEM_BASE) && + (phy_end_addr < (MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE))) { + return E_NO_ERROR; + } + + // Check SRAM Boundaries. + if ((phy_start_addr >= MXC_PHY_SRAM_MEM_BASE) && + (phy_end_addr < (MXC_PHY_SRAM_MEM_BASE + MXC_PHY_SRAM_MEM_SIZE))) { + return E_NO_ERROR; + } + + // Addresses are located outside of available/usable memory spaces. + return E_BAD_PARAM; +} + +mxc_mpc_regs_t *MXC_MPC_GetInstance(uint32_t addr) +{ + uint32_t phy_addr; + + // Get physical addresses from virtual secure/nonsecure addresses + // by clearing bit 28 - indicates the security state of the address. + phy_addr = addr & ~(1 << 28); + + if ((phy_addr >= MXC_PHY_FLASH_MEM_BASE) && + (phy_addr < MXC_PHY_FLASH_MEM_BASE + MXC_PHY_FLASH_MEM_SIZE)) { + return MXC_MPC_FLASH; + } else if ((phy_addr >= MXC_PHY_SRAM0_MEM_BASE) && + (phy_addr < MXC_PHY_SRAM0_MEM_BASE + MXC_PHY_SRAM0_MEM_SIZE)) { + return MXC_MPC_SRAM0; + } else if ((phy_addr >= MXC_PHY_SRAM1_MEM_BASE) && + (phy_addr < MXC_PHY_SRAM1_MEM_BASE + MXC_PHY_SRAM1_MEM_SIZE)) { + return MXC_MPC_SRAM1; + } else if ((phy_addr >= MXC_PHY_SRAM2_MEM_BASE) && + (phy_addr < MXC_PHY_SRAM2_MEM_BASE + MXC_PHY_SRAM2_MEM_SIZE)) { + return MXC_MPC_SRAM2; + } else if ((phy_addr >= MXC_PHY_SRAM3_MEM_BASE) && + (phy_addr < MXC_PHY_SRAM3_MEM_BASE + MXC_PHY_SRAM3_MEM_SIZE)) { + return MXC_MPC_SRAM3; + } else if ((phy_addr >= MXC_PHY_SRAM4_MEM_BASE) && + (phy_addr < MXC_PHY_SRAM4_MEM_BASE + MXC_PHY_SRAM4_MEM_SIZE)) { + return MXC_MPC_SRAM4; + } else { + // Addresses are located outside of memory spaces that don't have an + // associated MPC. + return NULL; + } +} + +int MXC_MPC_GetBlockIdx(mxc_mpc_regs_t *mpc, uint32_t addr) +{ + uint32_t physical_addr; + uint32_t block_size; + uint32_t start_mpc_region_addr, mpc_region_size; + int base, block, remainder; + + if (mpc == NULL) { + return E_NO_DEVICE; + } + + start_mpc_region_addr = MXC_MPC_GET_PHY_MEM_BASE(mpc); + mpc_region_size = MXC_MPC_GET_PHY_MEM_SIZE(mpc); + if (!((addr >= start_mpc_region_addr) && (addr < start_mpc_region_addr + mpc_region_size))) { + // Given address is not within the MPC region. + return E_BAD_PARAM; + } + + // Block size = 1 << (BLK_CFG.size + 5) + block_size = 1 << ((mpc->blk_cfg & MXC_F_MPC_BLK_CFG_SIZE) + 5); + + // Clear bit 28 (Security State of Region) to get the physical memory address. + physical_addr &= ~(1 << 28); + + base = addr - start_mpc_region_addr; + block = base / block_size; + remainder = base % block_size; + + // Get the current block if the address does not start at the beginning of a whole block. + if (remainder != 0) { + block += 1; + } + + return block; +} + +int MXC_MPC_SetSecure(uint32_t start_addr, uint32_t end_addr) +{ + return MXC_MPC_SetBlockSecurity(start_addr, end_addr, MXC_MPC_STATE_SECURE); +} + +int MXC_MPC_SetNonSecure(uint32_t start_addr, uint32_t end_addr) +{ + return MXC_MPC_SetBlockSecurity(start_addr, end_addr, MXC_MPC_STATE_NONSECURE); +} + +int MXC_MPC_Lock(mxc_mpc_regs_t *mpc) +{ + mpc->ctrl |= MXC_F_MPC_CTRL_SEC_LOCKDOWN; + + return E_NO_ERROR; +} + +#endif diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd b/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd new file mode 100644 index 00000000..f06322f9 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/mpc_me30.svd @@ -0,0 +1,283 @@ + + + + MPC + Memory Protection Controller. + 0x50091000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + 32 + + + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. + 0 + 32 + + + + + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only + + + SIZE + Block Size. + 0 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 + + + + + BLK_IDX + Block Index Register. + 0x0018 + + + IDX + Index value for accessing block-based lookup table. + 0 + 32 + + + + + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C + + + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. + 0 + 32 + + + + + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only + + + MPC_IRQ + MPC IRQ triggered. + 0 + 1 + + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + + + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 + 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR5 + Peripheral ID 5 Register. + 0x0FD4 + read-only + + + PIDR6 + Peripheral ID 6 Register. + 0x0FD8 + read-only + + + PIDR7 + Peripheral ID 6 Register. + 0x0FDC + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + CIDR0 + Component ID register. + 0x0FF0 + read-only + + + CIDR1 + Component ID register. + 0x0FF4 + read-only + + + CIDR2 + Component ID register. + 0x0FF8 + read-only + + + CIDR3 + Component ID register. + 0x0FFC + read-only + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c b/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c new file mode 100644 index 00000000..bc654e5d --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.c @@ -0,0 +1,63 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file nspc_me30.c + * @brief Non-Secure Privilege Controller (NSPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the privilege policy of data + * flowing to/from peripherals though the APB Peripheral Proection + * Controllers (PPC). + * The NSPC is only readable via Non-Secure Privileged access. + */ + +/** + * NSPC can only be accessed from the non-secure world. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 0 + +/**** Includes ****/ +#include +#include +#include "mxc_device.h" +#include "nspc.h" +#include "nspc_regs.h" + +/**** Definitions ****/ + +/**** Globals ****/ + +void MXC_NSPC_SetPrivAccess(mxc_nspc_periph_t periph, mxc_nspc_priv_t priv) +{ + if (priv == MXC_NSPC_UNPRIVILEGED) { + MXC_NSPC->apbpriv |= periph; + } else { + MXC_NSPC->apbpriv &= ~periph; + } +} + +// TODO(SW): Check function name. +void MXC_NSPC_DMA_SetPrivAccess(mxc_nspc_priv_t priv) +{ + if (priv == MXC_NSPC_UNPRIVILEGED) { + MXC_NSPC->ahbmpriv |= MXC_F_NSPC_AHBMPRIV_DMA; + } else { + MXC_NSPC->ahbmpriv &= ~MXC_F_NSPC_AHBMPRIV_DMA; + } +} + +#endif diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd b/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd new file mode 100644 index 00000000..aa3ae3d6 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/nspc_me30.svd @@ -0,0 +1,189 @@ + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.c b/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.c new file mode 100644 index 00000000..bfc5def1 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.c @@ -0,0 +1,184 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file spc_me30.c + * @brief Secure Privilege Controller (SPC) Driver for the MAX32657 (ME30). + * @details This driver is used to control the security and privilege policy of data + * flowing to/from peripherals though the APB Peripheral Proection + * Controllers (PPC). + * The SPC is only readable via Secure Privileged access. + */ + +/** + * SPC can only be accessed from the secure world. + */ +#if CONFIG_TRUSTED_EXECUTION_SECURE == 1 + +/**** Includes ****/ +#include +#include +#include "mxc_device.h" +#include "mxc_errors.h" +#include "spc.h" +#include "spc_regs.h" +#include "gpio.h" + +/**** Definitions ****/ + +/**** Globals ****/ + +/**** Functions ****/ + +void MXC_SPC_Lock(void) +{ + // Note: Cannot unlock SPC registers except via a reset. + MXC_SPC->ctrl |= MXC_F_SPC_CTRL_LOCK; +} + +// TODO(SW): Need to verify if this prevents the Non-Secure world from +// accessing the VTOR register. Note: the suffix '_NS' means that +// the secure world is accessing a non-secure register +void MXC_SPC_Core_Lock(void) +{ + // Locks the Cortex-M33 Core Registers (VTOR, SAU, MPU, etc). + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_AIRCR_VTOR_S; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_VTOR_NS; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_MPU_S; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_MPU_NS; + MXC_SPC->m33lock |= MXC_F_SPC_M33LOCK_SAU; +} + +void MXC_SPC_Core_UnLock(void) +{ + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_AIRCR_VTOR_S; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_VTOR_NS; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_MPU_S; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_MPU_NS; + MXC_SPC->m33lock &= ~MXC_F_SPC_M33LOCK_SAU; +} + +void MXC_SPC_SetPrivAccess(mxc_spc_periph_t periph, mxc_spc_priv_t priv) +{ + if (priv == MXC_SPC_UNPRIVILEGED) { + MXC_SPC->apbpriv |= periph; + } else { + MXC_SPC->apbpriv &= ~periph; + } +} + +// TODO(SW): Check names. +void MXC_SPC_SetSecure(mxc_spc_periph_t periph) +{ + MXC_SPC->apbsec &= ~periph; +} + +void MXC_SPC_SetNonSecure(mxc_spc_periph_t periph) +{ + MXC_SPC->apbsec |= periph; +} + +// TODO(SW): Check function name. +void MXC_SPC_DMA_SetPrivAccess(mxc_spc_priv_t priv) +{ + if (priv == MXC_SPC_UNPRIVILEGED) { + MXC_SPC->ahbmpriv |= MXC_F_SPC_AHBMPRIV_DMA; + } else { + MXC_SPC->ahbmpriv &= ~MXC_F_SPC_AHBMPRIV_DMA; + } +} + +int MXC_SPC_GPIO_SetSecure(mxc_gpio_regs_t *gpio, uint32_t pins) +{ + // Added GPIO instance as a parameter to follow convention of future devices that could + // potentially have more than one GPIO port. + if (gpio == MXC_GPIO0) { + MXC_SPC->gpio0 &= ~pins; + return E_NO_ERROR; + } else { + return E_BAD_PARAM; + } +} + +int MXC_SPC_GPIO_SetNonSecure(mxc_gpio_regs_t *gpio, uint32_t pins) +{ + // Added GPIO instance as a parameter to follow convention of future devices that could + // potentially have more than one GPIO port. + if (gpio == MXC_GPIO0) { + MXC_SPC->gpio0 |= pins; + return E_NO_ERROR; + } else { + return E_BAD_PARAM; + } +} + +void MXC_SPC_MPC_EnableInt(uint32_t intr) +{ + MXC_SPC->mpc_inten |= intr; +} + +void MXC_SPC_MPC_DisableInt(uint32_t intr) +{ + MXC_SPC->mpc_inten &= ~intr; +} + +uint32_t MXC_SPC_MPC_GetFlags(void) +{ + return MXC_SPC->mpc_status; +} + +void MXC_SPC_PPC_EnableInt(uint32_t intr) +{ + MXC_SPC->ppc_inten |= intr; +} + +void MXC_SPC_PPC_DisableInt(uint32_t intr) +{ + MXC_SPC->ppc_inten &= ~intr; +} + +uint32_t MXC_SPC_PPC_GetFlags(void) +{ + return MXC_SPC->ppc_status; +} + +void MXC_SPC_PPC_ClearFlags(uint32_t flags) +{ + MXC_SPC->ppc_intclr |= flags; +} + +// TODO(SW): This requires testing. ICODE +void MXC_SPC_SetCode_NSC(bool isNSC) +{ + if (isNSC) { + MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_CODE; + } else { + MXC_SPC->nscidau &= ~MXC_F_SPC_NSCIDAU_CODE; + } +} + +void MXC_SPC_SetSRAM_NSC(bool isNSC) +{ + if (isNSC) { + MXC_SPC->nscidau |= MXC_F_SPC_NSCIDAU_SRAM; + } else { + MXC_SPC->nscidau &= ~MXC_F_SPC_NSCIDAU_SRAM; + } +} + +#endif diff --git a/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd b/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd new file mode 100644 index 00000000..a2cbc615 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/TZ/spc_me30.svd @@ -0,0 +1,575 @@ + + + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 4 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Security Access for GCR. + 0x01 + + + SIR + Security Access for SIR. + 0x02 + + + FCR + Security Access for FCR. + 0x04 + + + WDT + Security Access for WDT. + 0x08 + + + AES + Security Access for AES. + 0x010 + + + AESKEYS + Security Access for AESKEYS. + 0x020 + + + CRC + Security Access for CRC. + 0x040 + + + GPIO0 + Security Access for GPIO0. + 0x080 + + + TMR0 + Security Access for TMR0. + 0x0100 + + + TMR1 + Security Access for TMR1. + 0x0200 + + + TMR2 + Security Access for TMR2. + 0x0400 + + + TMR3 + Security Access for TMR3. + 0x0800 + + + TMR4 + Security Access for TMR4. + 0x01000 + + + TMR5 + Security Access for TMR5. + 0x02000 + + + I3C + Security Access for I3C. + 0x04000 + + + UART + Security Access for UART. + 0x08000 + + + SPI + Security Access for SPI. + 0x010000 + + + TRNG + Security Access for TRNG. + 0x020000 + + + BTLE_DBB + Security Access for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Security Access for BTLE RFFE. + 0x080000 + + + RSTZ + Security Access for RSTZ. + 0x0100000 + + + BOOST + Security Access for Boost Controller. + 0x0200000 + + + TRIMSIR + Security Access for TRIMSIR. + 0x0400000 + + + RTC + Security Access for RTC. + 0x01000000 + + + WUT0 + Security Access for WUT0. + 0x02000000 + + + WUT1 + Security Access for WUT1. + 0x04000000 + + + PWRSEQ + Security Access for Power Sequencer. + 0x08000000 + + + MCR + Security Access for MCR. + 0x10000000 + + + ALL + Security Access for all peripherals. + 0x1F7FFFFF + + + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + GCR + Privilege setting for GCR. + 0x01 + + + SIR + Privilege setting for SIR. + 0x02 + + + FCR + Privilege setting for FCR. + 0x04 + + + WDT + Privilege setting for WDT. + 0x08 + + + AES + Privilege setting for AES. + 0x010 + + + AESKEYS + Privilege setting for AESKEYS. + 0x020 + + + CRC + Privilege setting for CRC. + 0x040 + + + GPIO0 + Privilege setting for GPIO0. + 0x080 + + + TMR0 + Privilege setting for TMR0. + 0x0100 + + + TMR1 + Privilege setting for TMR1. + 0x0200 + + + TMR2 + Privilege setting for TMR2. + 0x0400 + + + TMR3 + Privilege setting for TMR3. + 0x0800 + + + TMR4 + Privilege setting for TMR4. + 0x01000 + + + TMR5 + Privilege setting for TMR5. + 0x02000 + + + I3C + Privilege setting for I3C. + 0x04000 + + + UART + Privilege setting for UART. + 0x08000 + + + SPI + Privilege setting for SPI. + 0x010000 + + + TRNG + Privilege setting for TRNG. + 0x020000 + + + BTLE_DBB + Privilege setting for BTLE DBB. + 0x040000 + + + BTLE_RFFE + Privilege setting for BTLE RFFE. + 0x080000 + + + RSTZ + Privilege setting for RSTZ. + 0x0100000 + + + BOOST + Privilege setting for Boost Controller. + 0x0200000 + + + TRIMSIR + Privilege setting for TRIMSIR. + 0x0400000 + + + RTC + Privilege setting for RTC. + 0x01000000 + + + WUT0 + Privilege setting for WUT0. + 0x02000000 + + + WUT1 + Privilege setting for WUT1. + 0x04000000 + + + PWRSEQ + Privilege setting for Power Sequencer. + 0x08000000 + + + MCR + Privilege setting for MCR. + 0x10000000 + + + ALL + Privilege setting for all peripherals. + 0x1F7FFFFF + + + + + + + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 + + + DMA + Controls access of transactions coming from the Secure DMA. + 0 + 1 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secure or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 14 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai85.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai85.c index 361a7e13..8a10a826 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai85.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai85.c @@ -328,7 +328,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -371,7 +372,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -446,7 +448,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai87.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai87.c index 51f31363..b75fbdf1 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai87.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_ai87.c @@ -343,7 +343,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -382,7 +383,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -457,7 +459,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me12.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me12.c index 4f3b33da..d010911b 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me12.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me12.c @@ -259,7 +259,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -291,7 +292,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -366,7 +368,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me15.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me15.c index 3a89341f..ec12f579 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me15.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me15.c @@ -398,7 +398,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -437,7 +438,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -514,7 +516,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me16.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me16.c index ec1ff462..03903628 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me16.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me16.c @@ -179,7 +179,8 @@ int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clo freq = MXC_UART_GetFrequency(uart); } else { - freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); + freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, + (mxc_uart_revb_clock_t)clock); } if (freq > 0) { @@ -338,7 +339,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -373,7 +375,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -450,7 +453,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me17.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me17.c index 7d9a4343..3344a6e2 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me17.c @@ -364,7 +364,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -406,7 +407,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -481,7 +483,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me18.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me18.c index 7539ab30..cae32b5e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me18.c @@ -404,7 +404,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -446,7 +447,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -521,7 +523,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me21.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me21.c index c6ec59c1..d4bbfc54 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me21.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me21.c @@ -437,7 +437,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -475,7 +476,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigne break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -552,7 +554,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me30.c new file mode 100644 index 00000000..93725f41 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -0,0 +1,375 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "uart.h" +#include "mxc_device.h" +#include "mxc_pins.h" +#include "mxc_assert.h" +#include "uart_revb.h" +#include "uart_common.h" +#include "dma.h" +#include "dma_regs.h" + +void MXC_UART_DMACallback(int ch, int error) +{ + MXC_UART_RevB_DMACallback(ch, error); +} + +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); +} + +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + int retval; + + retval = MXC_UART_Shutdown(uart); + + if (retval) { + return retval; + } + + switch (clock) { + case MXC_UART_ERTCO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + break; + + case MXC_UART_IBRO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + break; + + default: + break; + } + + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_GPIO_Config(&gpio_cfg_uart); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); + break; + + default: + return E_BAD_PARAM; + } +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); +} + +int MXC_UART_Shutdown(mxc_uart_regs_t *uart) +{ + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART); + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +{ + int freq; + + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + if (clock == MXC_UART_ERTCO_CLK) { + return E_BAD_PARAM; + } + + freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); + + if (freq > 0) { + // Enable baud clock and wait for it to become ready. + uart->ctrl |= MXC_F_UART_CTRL_CLK_EN; + while (((uart->ctrl & MXC_F_UART_CTRL_CLK_RDY) >> MXC_F_UART_CTRL_CLK_RDY_POS) == 0) {} + } + + return freq; +} + +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) +{ + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) +{ + return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); +} + +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) +{ + return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); +} + +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) +{ + return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); +} + +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +{ + return E_NOT_SUPPORTED; +} + +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) +{ + return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); +} + +int MXC_UART_GetActive(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) +{ + return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); +} + +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) +{ + return MXC_UART_Common_ReadCharacter(uart); +} + +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) +{ + return MXC_UART_Common_WriteCharacter(uart, character); +} + +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) +{ + return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); +} + +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) +{ + return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); +} + +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) +{ + return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); +} + +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX(uart); + + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UARTRX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, + config); +} + +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); +} + +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len) +{ + return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); +} + +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX(uart); + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UARTTX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, + config); +} + +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) +{ + return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); +} + +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) +{ + return E_NOT_SUPPORTED; +} + +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) +{ + return E_NOT_SUPPORTED; +} + +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) +{ + return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); +} + +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int intEn) +{ + return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, intEn); +} + +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int intDis) +{ + return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, intDis); +} + +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_Transaction(mxc_uart_req_t *req) +{ + return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); +} + +int MXC_UART_TransactionAsync(mxc_uart_req_t *req) +{ + return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); +} + +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma) +{ + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, dma); +} + +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); +} + +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) +{ + return req->txCnt; +} + +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) +{ + return req->rxCnt; +} + +int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable) +{ + return MXC_UART_RevB_SetAutoDMAHandlers((mxc_uart_revb_regs_t *)uart, enable); +} + +int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) +{ + return MXC_UART_RevB_SetTXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); +} + +int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) +{ + return MXC_UART_RevB_SetRXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); +} + +int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); +} diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me55.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me55.c index 463e315f..de15b76f 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_me55.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_me55.c @@ -298,7 +298,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -340,7 +341,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -415,7 +417,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 2256afe3..35f3b8c6 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -28,6 +28,8 @@ #include "nvic_table.h" #endif +// TODO(DMA): Fix multiple DMA instance handling. + /* **** Definitions **** */ #define MXC_UART_REVA_ERRINT_EN \ (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ @@ -48,9 +50,20 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_reva_req_state_t; -uart_reva_req_state_t states[MXC_UART_INSTANCES]; +// clang-format off +uart_reva_req_state_t states[MXC_UART_INSTANCES] = { + [0 ... MXC_UART_INSTANCES - 1] = { + .tx_req = NULL, + .rx_req = NULL, + .channelTx = -1, + .channelRx = -1, + .auto_dma_handlers = false + } +}; +// clang-format on /* **** Function Prototypes **** */ @@ -99,6 +112,7 @@ int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud) states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -502,7 +516,7 @@ unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char return read; } -#if MXC_DMA_INSTANCES > 1 +#if (MXC_DMA_INSTANCES > 1) void MXC_UART_RevA_DMA0_Handler(void) { @@ -522,9 +536,9 @@ DMA instance. void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ +#if (MXC_DMA_INSTANCES > 1) NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); -#if MXC_DMA_INSTANCES > 1 /* (JC): This is not the cleanest or most scalable way to do this, but I tried defining default handler's in the system file. Some complications make this the most attractive short-term @@ -535,6 +549,8 @@ void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); } #else + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); #endif // MXC_DMA_INSTANCES > 1 @@ -591,7 +607,9 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -679,7 +697,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -708,7 +726,9 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + MXC_DMA_EnableInt(channel); + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -951,6 +971,9 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -976,7 +999,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -990,7 +1013,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1005,7 +1028,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1029,7 +1052,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1051,7 +1074,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch); diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c index da82f678..d3a55b2e 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -29,6 +29,8 @@ #include "nvic_table.h" #endif +// TOD(DMA): Fix multiple instance handling. + /* **** Definitions **** */ #define MXC_UART_REVB_ERRINT_EN \ (MXC_F_UART_REVB_INT_EN_RX_FERR | MXC_F_UART_REVB_INT_EN_RX_PAR | MXC_F_UART_REVB_INT_EN_RX_OV) @@ -36,6 +38,25 @@ #define MXC_UART_REVB_ERRINT_FL \ (MXC_F_UART_REVB_INT_FL_RX_FERR | MXC_F_UART_REVB_INT_FL_RX_PAR | MXC_F_UART_REVB_INT_FL_RX_OV) +#if CONFIG_TRUSTED_EXECUTION_SECURE +#ifndef MXC_DMA0 +// TrustZone support to keep up with naming convention. +// For ME30, non-secure DMA (DMA0) is accessible from Secure code using non-secure mapping. +// Undecorated MXC_DMA0 definition for secure code is not defined as the undecorated +// definitions corresponds with the security attribution of an address. +// Because there is no secure mapping for DMA0, following ARM naming convention, it's +// recommend that secure code use the definition with '_NS' suffix (MXC_DMA0_NS). +// Placing this here to limit scope of this definition to this file. +#define MXC_DMA0 MXC_DMA0_NS +#endif +#else +#ifndef MXC_DMA1 +// Non-Secure world can not access Secure DMA (DMA1). +// Placing this here to limit scope of this definition to this file. +#define MXC_DMA1 NULL +#endif +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + /* **** Variable Declaration **** */ static void *AsyncTxRequests[MXC_UART_INSTANCES]; static void *AsyncRxRequests[MXC_UART_INSTANCES]; @@ -46,9 +67,20 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_revb_req_state_t; -uart_revb_req_state_t states[MXC_UART_INSTANCES]; +// clang-format off +uart_revb_req_state_t states[MXC_UART_INSTANCES] = { + [0 ... MXC_UART_INSTANCES - 1] = { + .tx_req = NULL, + .rx_req = NULL, + .channelTx = -1, + .channelRx = -1, + .auto_dma_handlers = false + } +}; +// clang-format on /* **** Function Prototypes **** */ @@ -93,6 +125,7 @@ int MXC_UART_RevB_Init(mxc_uart_revb_regs_t *uart, unsigned int baud, mxc_uart_r states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -824,14 +857,50 @@ int MXC_UART_RevB_SetAutoDMAHandlers(mxc_uart_revb_regs_t *uart, bool enable) return E_NO_ERROR; } -void MXC_UART_RevB_DMA_SetupAutoHandlers(unsigned int channel) +#if (TARGET_NUM == 32657) + +void MXC_UART_RevA_DMA0_Handler(void) { + MXC_DMA_Handler(MXC_DMA0); +} + +#if CONFIG_TRUSTED_EXECUTION_SECURE +void MXC_UART_RevA_DMA1_Handler(void) +{ + MXC_DMA_Handler(MXC_DMA1); +} +#endif + +#endif + +/* "Auto" handlers just need to call MXC_DMA_Handler with the correct +DMA instance. +*/ +void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) +{ +// Add RISCV support here for future parts with more than one DMA instance. #ifdef __arm__ - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); +#if (TARGET_NUM == 32657) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); + + /* (JC): This is not the cleanest or most scalable way to do this, + but I tried defining default handler's in the system file. + Some complications make this the most attractive short-term + option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ + if (dma_instance == MXC_DMA0) { + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); +#if CONFIG_TRUSTED_EXECUTION_SECURE + // Only secure code has access to Secure DMA (DMA1). + } else if (dma_instance == MXC_DMA1) { + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); +#endif // CONFIG_TRUSTED_EXECUTION_SECURE + } #else - // TODO(JC): RISC-V + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + // Only one DMA instance, we can point direct to MXC_DMA_Handler + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); +#endif // MXC_DMA_INSTANCES > 1 #endif // __arm__ } @@ -867,7 +936,8 @@ int MXC_UART_RevB_GetRXDMAChannel(mxc_uart_revb_regs_t *uart) return states[n].channelRx; } -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; @@ -881,9 +951,13 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ +#if (TARGET_NUM == 32657) + channel = MXC_DMA_AcquireChannel(dma); +#else channel = MXC_DMA_AcquireChannel(); +#endif MXC_UART_RevB_SetRXDMAChannel(uart, channel); - MXC_UART_RevB_DMA_SetupAutoHandlers(channel); + MXC_UART_RevB_DMA_SetupAutoHandlers(dma, channel); } else { if (states[uart_num].channelRx < 0) return E_BAD_STATE; @@ -905,7 +979,13 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes states[uart_num].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -914,9 +994,9 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes return E_NO_ERROR; } -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, - mxc_dma_config_t config) +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; @@ -929,9 +1009,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ +#if (TARGET_NUM == 32657) + channel = MXC_DMA_AcquireChannel(dma); +#else channel = MXC_DMA_AcquireChannel(); +#endif MXC_UART_RevB_SetTXDMAChannel(uart, channel); - MXC_UART_RevB_DMA_SetupAutoHandlers(channel); + MXC_UART_RevB_DMA_SetupAutoHandlers(dma, channel); } else { if (states[uart_num].channelTx < 0) return E_BAD_STATE; @@ -953,7 +1037,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char states[uart_num].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -962,10 +1052,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char return E_NO_ERROR; } -int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -990,7 +1083,11 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) (req->uart)->dma |= (1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS); (req->uart)->dma |= (2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS); +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); +#else MXC_DMA_Init(); +#endif // Reset rx/tx counters, req->rxCnt = 0; @@ -1000,8 +1097,13 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; +#if (TARGET_NUM == 32657) + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, + NULL) != E_NO_ERROR) { +#else if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen, NULL) != E_NO_ERROR) { +#endif return E_BAD_PARAM; } } @@ -1009,8 +1111,13 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) //rx if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; +#if (TARGET_NUM == 32657) + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, + NULL) != E_NO_ERROR) { +#else if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) { +#endif return E_BAD_PARAM; } } @@ -1026,7 +1133,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1048,7 +1155,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch); diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.h b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.h index 5bf47655..07178392 100644 --- a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.h +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb.h @@ -74,14 +74,15 @@ int MXC_UART_RevB_Read(mxc_uart_revb_regs_t *uart, uint8_t *buffer, int *len); int MXC_UART_RevB_Write(mxc_uart_revb_regs_t *uart, const uint8_t *byte, int *len); unsigned int MXC_UART_RevB_ReadRXFIFO(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetRXFIFOAvailable(mxc_uart_revb_regs_t *uart); unsigned int MXC_UART_RevB_WriteTXFIFO(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, - mxc_dma_config_t config); +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetTXFIFOAvailable(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_ClearRXFIFO(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_ClearTXFIFO(mxc_uart_revb_regs_t *uart); @@ -97,7 +98,7 @@ unsigned int MXC_UART_RevB_GetStatus(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_Busy(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_Transaction(mxc_uart_revb_req_t *req); int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req); -int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req); +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma); int MXC_UART_RevB_AbortAsync(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_AsyncHandler(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_AsyncStop(mxc_uart_revb_regs_t *uart); diff --git a/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd new file mode 100644 index 00000000..d88279c5 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd @@ -0,0 +1,472 @@ + + + + UART + UART Low Power Registers + 0x40042000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control register + 0x0000 + + + RX_THD_VAL + This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) + 0 + 4 + + + PAR_EN + Parity Enable + 4 + 1 + + + PAR_EO + when PAREN=1 selects odd or even parity odd is 1 even is 0 + 5 + 1 + + + PAR_MD + Selects parity based on 1s or 0s count (when PAREN=1) + 6 + 1 + + + CTS_DIS + CTS Sampling Disable + 7 + 1 + + + TX_FLUSH + Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 8 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 9 + 1 + + + CHAR_SIZE + Selects UART character size + 10 + 2 + + + 5bits + 5 bits + 0 + + + 6bits + 6 bits + 1 + + + 7bits + 7 bits + 2 + + + 8bits + 8 bits + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated + 12 + 1 + + + HFC_EN + Enables/disables hardware flow control + 13 + 1 + + + RTS_NEG + The condition to negate RTS in HFC mode. + 14 + 1 + + + CLK_EN + Baud clock enable + 15 + 1 + + + CLK_SEL + To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. + 16 + 2 + + + PERIPHERAL_CLOCK + APB Clock. + 0 + + + CLK1 + IBRO clock. + 1 + + + + + CLK_RDY + Baud clock Ready read only bit + 19 + 1 + + + CLK_GATE + UART Clock Auto Gating mode + 20 + 1 + + + + + STATUS + Status register + 0x0004 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status + 0 + 1 + + + RX_BUSY + Read-only flag indicating the UART receiver status + 1 + 1 + + + RX_EM + Read-only flag indicating the RX FIFO state + 4 + 1 + + + RX_FULL + Read-only flag indicating the RX FIFO state + 5 + 1 + + + TX_EM + Read-only flag indicating the TX FIFO state + 6 + 1 + + + TX_FULL + Read-only flag indicating the TX FIFO state + 7 + 1 + + + RX_LVL + Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) + 8 + 4 + + + TX_LVL + Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) + 12 + 4 + + + + + INTEN + Interrupt Enable control register + 0x0008 + + + RX_FERR + Enable Interrupt For RX Frame Error + 0 + 1 + + + RX_PAR + Enable Interrupt For RX Parity Error + 1 + 1 + + + CTS_EV + Enable Interrupt For CTS signal change Error + 2 + 1 + + + RX_OV + Enable Interrupt For RX FIFO Overrun Error + 3 + 1 + + + RX_THD + Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD + 4 + 1 + + + TX_OB + Enable Interrupt For TX FIFO when only one byte is remaining. + 5 + 1 + + + TX_THD + Enable Interrupt for when TX FIFO meets or passes the threshold level. + 6 + 1 + + + RX_FULL + Enable for RX FIFO Full interrupt. + 7 + 1 + + + + + INTFL + Interrupt status flags Control register + 0x000C + + + RX_FERR + Flag for RX Frame Error Interrupt. + 0 + 1 + + + RX_PAR + Flag for RX Parity Error interrupt + 1 + 1 + + + CTS_EV + Flag for CTS signal change interrupt (hardware flow control disabled) + 2 + 1 + + + RX_OV + Flag for RX FIFO Overrun interrupt + 3 + 1 + + + RX_THD + Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field + 4 + 1 + + + TX_OB + Flag for interrupt when TX FIFO has only one byte is remaining. + 5 + 1 + + + TX_THD + Flag for interrupt when TX FIFO meets or passes the threshold level. + 6 + 1 + + + RX_FULL + Flag for full RX FIFO. + 7 + 1 + + + + + CLKDIV + Clock Divider register + 0x0010 + + + CLKDIV + Baud rate divisor value + 0 + 20 + + + + + OSR + Over Sampling Rate register + 0x0014 + + + OSR + OSR + 0 + 3 + + + + + TXPEEK + TX FIFO Output Peek register + 0x0018 + + + DATA + Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. + 0 + 8 + + + + + PIN + Pin register + 0x001C + + + CTS + Current sampled value of CTS IO + 0 + 1 + read-only + + + RTS + This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. + 1 + 1 + + + + + FIFO + FIFO Read/Write register + 0x0020 + + + DATA + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + RX_PAR + Parity error flag for next byte to be read from FIFO. + 8 + 1 + + + + + DMA + DMA Configuration register + 0x0030 + + + TX_THD_VAL + TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. + 0 + 4 + + + TX_EN + TX DMA channel enable + 4 + 1 + + + RX_THD_VAL + Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. + 5 + 4 + + + RX_EN + RX DMA channel enable + 9 + 1 + + + + + WKEN + Wake up enable Control register + 0x0034 + + + RX_NE + Wake-Up Enable for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Enable for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Enable for RX FIFO Threshold Met + 2 + 1 + + + + + WKFL + Wake up Flags register + 0x0038 + + + RX_NE + Wake-Up Flag for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Flag for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Flag for RX FIFO Threshold Met + 2 + 1 + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c b/MAX/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c new file mode 100644 index 00000000..00ba3952 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c @@ -0,0 +1,143 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" +#include "wdt_revb.h" + +/* **** Functions **** */ + +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + if (wdt == MXC_WDT) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT); + } else { + return E_BAD_PARAM; + } +#endif + + return MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); +} + +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) +{ + if (wdt == MXC_WDT) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ + MXC_WDT_RevB_SetIntPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); +} + +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ + MXC_WDT_RevB_SetResetPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); +} + +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_Enable((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_Disable((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); +} + +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); +} + +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); +} + +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); +} + +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ResetTimer((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt) +{ + return MXC_WDT_RevB_GetResetFlag((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ClearResetFlag((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt) +{ + return MXC_WDT_RevB_GetIntFlag((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ClearIntFlag((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source) +{ + const uint8_t clock_source_num = 8; + uint8_t idx = 0; + uint8_t instance = 0; + + mxc_wdt_clock_t clock_sources[1][8] = { + { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + }; + + if (wdt == MXC_WDT) { + instance = 0; + } else { + return E_BAD_PARAM; + } + + for (idx = 0; idx < clock_source_num; idx++) { + if (clock_sources[instance][idx] == clock_source) { + break; + } + } + + MXC_WDT_RevB_SetClockSource((mxc_wdt_revb_regs_t *)wdt, idx); + + return E_NO_ERROR; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/WUT/wut_me30.c b/MAX/Libraries/PeriphDrivers/Source/WUT/wut_me30.c new file mode 100644 index 00000000..2d51c4d2 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/WUT/wut_me30.c @@ -0,0 +1,372 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "wut.h" +#include "wut_reva.h" +#include "trimsir_regs.h" + +/* **** Definitions **** */ + +/* Clock rate the BLE DBB counter */ +#ifndef BB_CLK_RATE_HZ +#define BB_CLK_RATE_HZ 1000000 +#endif + +/* Higher values will produce a more accurate measurement, but will consume more power */ +#define WUT_TRIM_TICKS 0x1000 + +/* **** Globals **** */ + +/* **** Local Variables **** */ + +/* Used for the asynchronous trim procedure */ +static uint32_t wutCnt0_async, snapshot0_async, bestTrim_async, bestDiff_async; +static int capAdded_async; +static int trimPending; +static mxc_wut_complete_cb_t cb_async; + +/* **** Functions **** */ + +/* ************************************************************************** */ +void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); +#endif + MXC_WUT_RevA_Init((mxc_wut_reva_regs_t *)wut, pres); +} + +void MXC_WUT_Shutdown(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Shutdown((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Enable(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Enable((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Disable(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Disable((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg) +{ + MXC_WUT_RevA_Config((mxc_wut_reva_regs_t *)wut, (mxc_wut_reva_cfg_t *)cfg); +} + +/* ************************************************************************** */ +uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetCompare((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetCount((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +void MXC_WUT_IntClear(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt) +{ + MXC_WUT_RevA_SetCompare((mxc_wut_reva_regs_t *)wut, cmp_cnt); +} + +/* ************************************************************************* */ +void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt) +{ + MXC_WUT_RevA_SetCount((mxc_wut_reva_regs_t *)wut, cnt); +} + +/* ************************************************************************* */ +int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks) +{ + return MXC_WUT_RevA_GetTicks((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, time, units, ticks); +} + +/* ************************************************************************* */ +int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units) +{ + return MXC_WUT_RevA_GetTime((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, ticks, time, + (mxc_wut_reva_unit_t *)units); +} + +/* ************************************************************************** */ +void MXC_WUT_Edge(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Store(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq) +{ + MXC_WUT_RevA_RestoreBBClock((mxc_wut_reva_regs_t *)wut, dbbFreq, ERTCO_FREQ); +} + +/* ************************************************************************** */ +uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetSleepTicks((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs) +{ + MXC_WUT_RevA_Delay_MS((mxc_wut_reva_regs_t *)wut, waitMs, ERTCO_FREQ); +} + +/* ************************************************************************** */ +static void MXC_WUT_GetWUTSync(mxc_wut_regs_t *wut, uint32_t *wutCnt, uint32_t *snapshot) +{ + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); + *wutCnt = wut->cnt; + *snapshot = wut->snapshot; +} + +/* ************************************************************************** */ +static void MXC_WUT_SetTrim(uint32_t trimValue) +{ + MXC_SETFIELD(MXC_TRIMSIR->rtcx1, MXC_F_TRIMSIR_RTCX1_CAP, + (trimValue << MXC_F_TRIMSIR_RTCX1_CAP_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtcx2, MXC_F_TRIMSIR_RTCX2_CAP, + (trimValue << MXC_F_TRIMSIR_RTCX2_CAP_POS)); +} + +/* ************************************************************************** */ +// TODO(SW): TRIMSIR RTC X1/X2 register descriptions were updated due to design changes. +// CAP vs TRIM value differences unknown, and this function has not been tested. +static int MXC_WUT_StartTrim(mxc_wut_regs_t *wut) +{ + uint32_t wutCnt0, wutCnt1; + uint32_t snapshot0, snapshot1; + uint32_t trimValue; + + /* Make sure the WUT is running in compare mode */ + if (!(wut->ctrl & MXC_F_WUT_REVA_CTRL_TEN)) { + return E_UNINITIALIZED; + } + + /* Make sure that DBB counter is running */ + MXC_WUT_GetWUTSync(wut, &wutCnt0, &snapshot0); + MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1); + if (snapshot0 == snapshot1) { + return E_UNINITIALIZED; + } + + /* Start with existing trim value */ + trimValue = (MXC_TRIMSIR->rtcx1 & MXC_F_TRIMSIR_RTCX1_CAP) >> MXC_F_TRIMSIR_RTCX1_CAP_POS; + MXC_WUT_SetTrim(trimValue); + + /* Initialize the variables */ + bestTrim_async = trimValue; + bestDiff_async = 0xFFFF; + + /* Get the initial snapshot */ + MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async); + + trimPending = 1; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_Handler(mxc_wut_regs_t *wut) +{ + uint32_t wutCnt1; + uint32_t snapshot1; + uint32_t trimValue; + uint32_t snapTicks, wutTicks; + uint64_t calcTicks; + int trimComplete; + mxc_wut_complete_cb_t cbTemp; + + /* Clear the interrupt flags */ + MXC_WUT_IntClear(wut); + + if (!trimPending) { + return E_NO_ERROR; + } + + /* Store the snapshot */ + MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1); + snapTicks = snapshot1 - snapshot0_async; + wutTicks = wutCnt1 - wutCnt0_async; + + /* Calculate the ideal number of DBB ticks in WUT_TRIM_TICKS */ + calcTicks = ((uint64_t)wutTicks * (uint64_t)BB_CLK_RATE_HZ) / (uint64_t)32768; + + trimComplete = 0; + trimValue = (MXC_TRIMSIR->rtcx1 & MXC_F_TRIMSIR_RTCX1_CAP) >> MXC_F_TRIMSIR_RTCX1_CAP_POS; + + if (snapTicks > calcTicks) { + /* See if we're closer to the calculated value */ + if ((snapTicks - calcTicks) <= bestDiff_async) { + bestDiff_async = snapTicks - calcTicks; + bestTrim_async = trimValue; + } + + /* Running slow, reduce cap */ + if (trimValue == 0) { + /* We're maxed out on trim range */ + trimComplete = 1; + } + trimValue--; + + if (capAdded_async == 1) { + /* We've hit an inflection point */ + trimComplete = 1; + } + capAdded_async = -1; + + } else if (snapTicks < calcTicks) { + /* See if we're closer to the calculated value */ + if ((calcTicks - snapTicks) <= bestDiff_async) { + bestDiff_async = calcTicks - snapTicks; + bestTrim_async = trimValue; + } + + /* Running fast, increase cap */ + if (trimValue == 0x1f) { + /* We're maxed out on trim range */ + trimComplete = 1; + } + trimValue++; + + if (capAdded_async == -1) { + /* We've hit an inflection point */ + trimComplete = 1; + } + capAdded_async = 1; + + } else { + /* Just right */ + bestTrim_async = trimValue; + trimComplete = 1; + } + + if (trimComplete) { + /* Apply the best trim value */ + MXC_WUT_SetTrim(bestTrim_async); + + trimPending = 0; + + /* Call the callback */ + if (cb_async != NULL) { + cbTemp = cb_async; + cb_async = NULL; + cbTemp(E_NO_ERROR); + } + + return E_NO_ERROR; + } + + /* Start the next step */ + MXC_WUT_SetTrim(trimValue); + MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async); + + if (cb_async != NULL) { + /* Prime the compare interrupt */ + wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1; + } + + /* Return E_BUSY to indicate the trim procedure is still running */ + return E_BUSY; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut) +{ + int err, i; + + /* Clear the async callback pointer */ + cb_async = NULL; + + /* Start the trim procedure */ + err = MXC_WUT_StartTrim(wut); + if (err != E_NO_ERROR) { + return err; + } + do { + for (i = 0; i < (WUT_TRIM_TICKS - 1); i++) { + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); + } + } while (MXC_WUT_Handler(wut) != E_NO_ERROR); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb) +{ + int err; + + if (cb == NULL) { + return E_NULL_PTR; + } + + /* Save the callback */ + cb_async = cb; + + /* Start the trim procedure */ + err = MXC_WUT_StartTrim(wut); + if (err != E_NO_ERROR) { + return err; + } + + /* Prime the compare interrupt */ + wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimPending(mxc_wut_regs_t *wut) +{ + if (trimPending) { + return E_BUSY; + } + + return E_NO_ERROR; +} diff --git a/MAX/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd new file mode 100644 index 00000000..509e6696 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd @@ -0,0 +1,261 @@ + + + + WUT + 32-bit reloadable timer that can be used for timing and wakeup. + 0x40006400 + + 0x00 + 0x400 + registers + + + WUT + WUT IRQ + 1 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Timer Count Value. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Timer Compare Value. + 0 + 32 + + + + + INTFL + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + CLR + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOL_LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOL_HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + PRESET + Preset register. + 0x18 + + + PRESET + Preset Value. + 0 + 32 + + + + + RELOAD + Reload register. + 0x1C + + + RELOAD + Rerload Value. + 0 + 32 + + + + + SNAPSHOT + Snapshot register. + 0x20 + + + SNAPSHOT + Snapshot Value. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/MAX/Source/MAX32655/CMakeLists.txt b/MAX/Source/MAX32655/CMakeLists.txt index cdc901c7..c78155ea 100644 --- a/MAX/Source/MAX32655/CMakeLists.txt +++ b/MAX/Source/MAX32655/CMakeLists.txt @@ -48,14 +48,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32655.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32655.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32655.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me17.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me17.c diff --git a/MAX/Source/MAX32657/CMakeLists.txt b/MAX/Source/MAX32657/CMakeLists.txt new file mode 100644 index 00000000..9077c239 --- /dev/null +++ b/MAX/Source/MAX32657/CMakeLists.txt @@ -0,0 +1,153 @@ +############################################################################## +# +# Copyright (C) 2024 Analog Devices, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################## + + +if(NOT TARGET_REV) + # Default version A1, not actively use in driver but requires to be defined. + zephyr_compile_definitions(-DTARGET_REV=0x4131) +endif() + +math(EXPR __MXC_FLASH_MEM_SIZE "${CONFIG_FLASH_SIZE} * 1024") +math(EXPR __MXC_SRAM_MEM_SIZE "${CONFIG_SRAM_SIZE} * 1024") + +zephyr_compile_definitions( + -D__MXC_FLASH_MEM_BASE=${CONFIG_FLASH_BASE_ADDRESS} + -D__MXC_FLASH_MEM_SIZE=${__MXC_FLASH_MEM_SIZE} + -D__MXC_SRAM_MEM_BASE=${CONFIG_SRAM_BASE_ADDRESS} + -D__MXC_SRAM_MEM_SIZE=${__MXC_SRAM_MEM_SIZE} +) + +zephyr_include_directories( + ${MSDK_PERIPH_SRC_DIR}/SYS + ${MSDK_PERIPH_SRC_DIR}/AES + ${MSDK_PERIPH_SRC_DIR}/CRC + ${MSDK_PERIPH_SRC_DIR}/DMA + ${MSDK_PERIPH_SRC_DIR}/FLC + ${MSDK_PERIPH_SRC_DIR}/GPIO + ${MSDK_PERIPH_SRC_DIR}/I2C + ${MSDK_PERIPH_SRC_DIR}/ICC + ${MSDK_PERIPH_SRC_DIR}/LP + ${MSDK_PERIPH_SRC_DIR}/RTC + ${MSDK_PERIPH_SRC_DIR}/SPI + ${MSDK_PERIPH_SRC_DIR}/TRNG + ${MSDK_PERIPH_SRC_DIR}/TMR + ${MSDK_PERIPH_SRC_DIR}/UART + ${MSDK_PERIPH_SRC_DIR}/WDT + ${MSDK_PERIPH_SRC_DIR}/WUT +) + +zephyr_library_sources( + ./max32xxx_system.c + + ${MSDK_CMSIS_DIR}/Source/system_max32657.c + + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c + ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me30.c + + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${MSDK_PERIPH_SRC_DIR}/LP/lp_me30.c + + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_me30.c + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_reva.c + + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_reva.c +) + +if (CONFIG_UART_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/UART/uart_common.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_me30.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_revb.c +) +endif() + +if (CONFIG_GPIO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_reva.c +) +endif() + +if (CONFIG_SPI_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_me30.c + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_reva1.c +) +endif() + +if (CONFIG_I2C_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_me30.c + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_reva.c +) +endif() + +if (CONFIG_WDT_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_common.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_me30.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_revb.c +) +endif() + +if (CONFIG_RTC_MAX32 OR CONFIG_COUNTER_RTC_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_me30.c + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_reva.c +) +endif() + +if (CONFIG_SOC_FLASH_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_reva.c +) +endif() + +if (CONFIG_PWM_MAX32 OR CONFIG_TIMER_MAX32 OR CONFIG_COUNTER_TIMER_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_common.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_me30.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_revb.c +) +endif() + +if (CONFIG_ENTROPY_MAX32_TRNG) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_me30.c + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c +) +endif() + +if (CONFIG_CRYPTO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/AES/aes_me30.c + ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c + + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_me30.c + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c +) +endif() diff --git a/MAX/Source/MAX32657/max32xxx_system.c b/MAX/Source/MAX32657/max32xxx_system.c new file mode 100644 index 00000000..9998ccfb --- /dev/null +++ b/MAX/Source/MAX32657/max32xxx_system.c @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "max32657.h" + +/* + * This function is called during boot up. + */ +void max32xx_system_init(void) {} diff --git a/MAX/Source/MAX32657/partition_max32657.h b/MAX/Source/MAX32657/partition_max32657.h new file mode 100644 index 00000000..1f55ac96 --- /dev/null +++ b/MAX/Source/MAX32657/partition_max32657.h @@ -0,0 +1,27 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_ZEPHYR_MAX_SOURCE_MAX32657_PARTITION_MAX32657_H_ +#define LIBRARIES_ZEPHYR_MAX_SOURCE_MAX32657_PARTITION_MAX32657_H_ + +void TZ_SAU_Setup(void) +{ + /* Added empty function to use MSDK file as it is */ +} + +#endif // LIBRARIES_ZEPHYR_MAX_SOURCE_MAX32657_PARTITION_MAX32657_H_ diff --git a/MAX/Source/MAX32680/CMakeLists.txt b/MAX/Source/MAX32680/CMakeLists.txt index bcdfad4f..03458b6a 100644 --- a/MAX/Source/MAX32680/CMakeLists.txt +++ b/MAX/Source/MAX32680/CMakeLists.txt @@ -48,14 +48,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32680.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32680.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32680.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me20.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me17.c diff --git a/MAX/Source/MAX32690/CMakeLists.txt b/MAX/Source/MAX32690/CMakeLists.txt index add3ddc5..53afa9fe 100644 --- a/MAX/Source/MAX32690/CMakeLists.txt +++ b/MAX/Source/MAX32690/CMakeLists.txt @@ -51,14 +51,18 @@ zephyr_include_directories( ${MSDK_PERIPH_SRC_DIR}/WUT ) +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max32690.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max32690.c) +endif() + zephyr_library_sources( ./max32xxx_system.c - ${MSDK_CMSIS_DIR}/Source/system_max32690.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c - ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me18.c ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me18.c diff --git a/MAX/Source/MAX78002/CMakeLists.txt b/MAX/Source/MAX78002/CMakeLists.txt new file mode 100644 index 00000000..11839a85 --- /dev/null +++ b/MAX/Source/MAX78002/CMakeLists.txt @@ -0,0 +1,183 @@ +############################################################################## +# +# Copyright (C) 2024 Analog Devices, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################## + + +if(NOT TARGET_REV) + # Default version A1, not actively use in driver but requires to be defined. + zephyr_compile_definitions(-DTARGET_REV=0x4131) +endif() + +zephyr_include_directories( + ${MSDK_PERIPH_SRC_DIR}/ADC + ${MSDK_PERIPH_SRC_DIR}/AES + ${MSDK_PERIPH_SRC_DIR}/CRC + ${MSDK_PERIPH_SRC_DIR}/DMA + ${MSDK_PERIPH_SRC_DIR}/FLC + ${MSDK_PERIPH_SRC_DIR}/GPIO + ${MSDK_PERIPH_SRC_DIR}/I2C + ${MSDK_PERIPH_SRC_DIR}/I2S + ${MSDK_PERIPH_SRC_DIR}/ICC + ${MSDK_PERIPH_SRC_DIR}/LP + ${MSDK_PERIPH_SRC_DIR}/LPCMP + ${MSDK_PERIPH_SRC_DIR}/OWM + ${MSDK_PERIPH_SRC_DIR}/PT + ${MSDK_PERIPH_SRC_DIR}/RTC + ${MSDK_PERIPH_SRC_DIR}/SPI + ${MSDK_PERIPH_SRC_DIR}/SDHC + ${MSDK_PERIPH_SRC_DIR}/SYS + ${MSDK_PERIPH_SRC_DIR}/TMR + ${MSDK_PERIPH_SRC_DIR}/TRNG + ${MSDK_PERIPH_SRC_DIR}/UART + ${MSDK_PERIPH_SRC_DIR}/WDT + ${MSDK_PERIPH_SRC_DIR}/WUT +) + +if(CONFIG_ARM) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_max78002.c) + zephyr_library_sources(${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c) +elseif(CONFIG_RISCV) + zephyr_library_sources(${MSDK_CMSIS_DIR}/Source/system_riscv_max78002.c) +endif() + +zephyr_library_sources( + ./max78xxx_system.c + + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${MSDK_PERIPH_SRC_DIR}/LP/lp_ai87.c + + ${MSDK_PERIPH_SRC_DIR}/LPCMP/lpcmp_ai87.c + ${MSDK_PERIPH_SRC_DIR}/LPCMP/lpcmp_reva.c + + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${MSDK_PERIPH_SRC_DIR}/SYS/pins_ai87.c + ${MSDK_PERIPH_SRC_DIR}/SYS/sys_ai87.c + + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_ai87.c + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_reva.c + + ${MSDK_PERIPH_SRC_DIR}/PT/pt_ai87.c + ${MSDK_PERIPH_SRC_DIR}/PT/pt_reva.c + + ${MSDK_PERIPH_SRC_DIR}/SDHC/sdhc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/SDHC/sdhc_reva.c + + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_ai87.c + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_reva.c +) + +if (CONFIG_ADC_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/ADC/adc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/ADC/adc_revb.c +) +endif() + +if (CONFIG_UART_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/UART/uart_common.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_ai87.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_revb.c +) +endif() + +if (CONFIG_GPIO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_ai87.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_reva.c +) +endif() + +if (CONFIG_SPI_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_ai87.c + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_reva1.c +) +endif() + +if (CONFIG_I2C_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_ai87.c + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_reva.c +) +endif() + +if (CONFIG_I2S_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/I2S/i2s_ai87.c + ${MSDK_PERIPH_SRC_DIR}/I2S/i2s_reva.c +) +endif() + +if (CONFIG_WDT_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_common.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_ai87.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_revb.c +) +endif() + +if (CONFIG_RTC_MAX32 OR CONFIG_COUNTER_RTC_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_reva.c +) +endif() + +if (CONFIG_SOC_FLASH_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_reva.c +) +endif() + +if (CONFIG_PWM_MAX32 OR CONFIG_TIMER_MAX32 OR CONFIG_COUNTER_TIMER_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_common.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_ai87.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_revb.c +) +endif() + +if (CONFIG_ENTROPY_MAX32_TRNG) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_ai87.c + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c +) +endif() + +if (CONFIG_CRYPTO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/AES/aes_ai87.c + ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c + + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_ai87.c + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c +) +endif() + +if (CONFIG_W1_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/OWM/owm_ai87.c + ${MSDK_PERIPH_SRC_DIR}/OWM/owm_reva.c +) +endif() diff --git a/MAX/Source/MAX78002/max78xxx_system.c b/MAX/Source/MAX78002/max78xxx_system.c new file mode 100644 index 00000000..ac79d2af --- /dev/null +++ b/MAX/Source/MAX78002/max78xxx_system.c @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "max78002.h" + +/* + * This function is called during boot up. + */ +void max32xx_system_init(void) {} diff --git a/MAX/msdk_sha b/MAX/msdk_sha new file mode 100644 index 00000000..68b67c4f --- /dev/null +++ b/MAX/msdk_sha @@ -0,0 +1 @@ +1ee96f58a0d9635530b01686c5e2a3691232b6cd