How .sdc is related to synthesis? #788
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This may be a "stupid" question to ask, however, My professor and I are doing research that involves the OpenROAD flow. I have little experience with general ASIC/IC RTL-to-GDS flows. How does the synopsys design constraints file (.sdc) relate to synthesis? How does the .sdc file affect the flow in general? |
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Replies: 2 comments
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Synthesis will get information about the clock and i/o timings. Its primarily used during techmapping and optimization which is done by abc from within yosys. |
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In the rest of the flow in OpenRoad it is used to drive clock tree synthesis and timing optimization throughout the flow. |
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Synthesis will get information about the clock and i/o timings. Its primarily used during techmapping and optimization which is done by abc from within yosys.