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@QuantumHD are you using this plugin? |
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I have installed the yosys-uhdm plugin so that I could read SystemVerilog source files directly during synthesis.
I am using the ORFS and I use -m systemverilog to load the systemverilog plugin during Yosys startup.
I have the following lines in my design/config.mk file
I have also modified the file scripts/synth_preamble.tcl to look like this:
I don't know if this is an issue with the way the variable $::env(VERILOG_FILES) is passed to read_systemverilog or something else
but:
for trial 1) above, the script complains that the file 'all_the_files_names_together_separated_with_a_blank' cannot be found for read
For trial 2) the lower level modules (module1.sv and module2.sv) are not elaborated/compiled and I also get the message [ERR:EL0528] undefined package "my_desf_pkg" which indicates that the package was not read properly.
Trial 3 works but it is not exactly what I am looking for since I am hard coding the file names in the synthesis script.
Could someone shed some light on what is going on here?
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