Are there plans to support System Verilog?

[yurivict]

Currently System Verilog designs fail in yosys, for example:

ERROR: input/output/inout ports cannot have unpacked dimensions.

or

ERROR: syntax error, unexpected OP_CAST

yosys supports Verilog-2005 plus a small subset of System Verilog features.

Are there plans for OpenRoad to fully support System Verilog?

[maliberty]

That is a yosys issue more than an OpenROAD one. I believe there is a path via surelog (see https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/)

@mithro any comments?

[mithro]

FYI - @kgugala

[kgugala]

@maliberty check this note https://antmicro.com/blog/2021/10/openlane-asic-build-flow-with-systemverliog-support/ it links to Surelog/UHDM/Yosys example with OpenLane.

[yurivict]

What is the difference between this repository and OpenLane? They seem to do the same. Is OpenLane superseding this repository?

[maliberty]

ORFS is maintained by the OpenROAD team and is the primary test bed for OR. OpenLane is part of eFabless and the MPW shuttle program. They are quite similar and there has been discussion of moving to OL but there are a number of technical issues to work through. Until then they continue to co-exist.

Also https://github.com/siliconcompiler/siliconcompiler is another similar flow and there has been discussion with https://chipyard.readthedocs.io/en/latest/ as well.