The question of "SYNTH_HIERARCHICAL = 1"

[tylpk1216]

I am not sure my understanding of SYNTH_HIERARCHICAL is wrong?

When we set SYNTH_HIERARCHICAL = 1, the synthesis does two things.

1. run synth_hier_report.tcl
2. run synth.tcl

In step 2, we run mark_hier_stop_modules.tcl to invoke "setattr -mod -set keep_hierarchy 1" to individual modules.

It seems that the step 2 doesn't use the result of step 1 to speed up the action.

In step 2, we still need to do "synth" or "abc" from the original verilog code(RTL).

Is my understanding wrong? Thanks.

[maliberty]

The goal is not to speed up synthesis but to keep the large modules in the hierarchy while flattening the small ones. Flattening the small modules enable more optimization. Keeping the large modules helps macro placement and the GUI (and in the future hierarchical timing constraints).

[tylpk1216]

Thanks for your reply. Because I want to speed up the synthesis time and don't set MAX_UNGROUP_SIZE, I know I can do something to satisfy my goal now.

Many thanks.