how to solve Insufficient width problem during floorplanning for my design please help

[velmuruganvmtor]

while designing my circuit using nangate45 the error pop up in floorplanning section saying that [ERROR PDN-0185] Insufficient width (6.27 um) to add straps on layer metal4 in grid "grid" with total strap width 28.48 um and offset 2.0 um.
Error: grid_strategy-M1-M4-M7.tcl, 19 PDN-0185
Command exited with non-zero status 1
Elapsed time: 0:00.17[h:]min:sec. CPU time: user 0.16 sys 0.01 (99%). Peak memory: 96124KB.
make[1]: *** [Makefile:627: do-2_6_floorplan_pdn] Error 1
make: *** [Makefile:627: results/nangate45/samplea/base/2_6_floorplan_pdn.odb] Error 2
I have tried to make many chages in config.mk file i found no improvement to reduce the error please mail answer also mail to me at [email protected] it would be useful

also please find my attached file of terminal output
[
error message while executing make DESIGN_CONFIG.txt

[maliberty]

Please see the discussion in #1839

[velmuruganvmtor]

sir i have done modifications in config.mk
sir i have tried thoes methord you have said and my design is small i am learning from this

could you review the config.mk file

export PLATFORM = nangate45

export DESIGN_NAME = samplea

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

#export CORE_UTILIZATION ?= 0.10
#export PLACE_DENSITY_LB_ADDON = 0.20
export DIE_AREA = 50 50 50 50
export CORE_AREA = 50 50 50 50

error after making changes
Using 2 tracks default min distance between IO pins.
[ERROR PPL-0021] Horizontal routing tracks not found for layer metal5.
Error: io_placement_random.tcl, 14 PPL-0021
Command exited with non-zero status 1

and tell me where is the error please also tell me other methords also

this is my samplea .v code :
module samplea (
input clk, // Clock input
input reset, // Reset input
input a, // First input
input b, // Second input
input cin, // Carry input
output reg sum, // Sum output
output reg cout // Carry output
);

// Internal signals
reg [1:0] s;
reg [1:0] c;

always @(posedge clk or posedge reset) begin
if (reset) begin
// Reset the registers
s <= 2'b0;
c <= 2'b0;
end else begin
// Calculate sum and carry
s <= a ^ b ^ c;
c <= (a & b) | (b & c) | (a & c);
end
end

// Output assignments
assign sum = s[0];
assign cout = c[1];

endmodule
please consider helping also teach me how it works

[velmuruganvmtor]

#using this config.mk file for short verilog files:
export PLATFORM = nangate45

export DESIGN_NAME = samplea

export VERILOG_FILES = $(sort $(wildcard ./designs/src/$(DESIGN_NICKNAME)/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export CORE_UTILIZATION ?= 0.30
export PLACE_DENSITY_LB_ADDON = 0.40
export DIE_AREA = 30 30 30 30
export CORE_AREA = 30 30 30 30
#for my code also please note that everytime changes done to config.mk file need to update using vi constraint.sdc in the project folder
#by simply enter the command in terminal and use :wq command

[maliberty]

Please do make pdn_issue and attached the resulting tar file which will make it easier to reproduce your problem.

[velmuruganvmtor]

done sir

[velmuruganvmtor]

pdn issue_samplea.zip

[maliberty]

I had to rename the path to not contain a space but after that it runs without error:

[maliberty]

Fwiw I used OR commit 64b9d673c

[velmuruganvmtor]

Sir could you elaborate the steps that you have perform to not contain space also the previous config.mk also runs without error (but I didn't do testing part) could you tell me any error is obtained in my config.mk part

🙏 Thanks in advance

[maliberty]

I just changed 'pdn issue_samplea/' to 'pdn_issue_samplea/'

[velmuruganvmtor]

so my config.mk works fine ??

[maliberty]

Yes as shown above.