How to get standard cell data (size, pin count, logic function) from the gates of a design?

[gudeh]

Hi everyone! I would like to build a TCL script to get the standard cell data of each logic gate in the design. I wonder if it is even possible to extract these from ORFS TCL commands.

I was trying to at least print the names of the logic gates, it runs without errors, although it seems that "get_lib_cells" is always empty. I added this code to the end of "gui_final" script:

    set cell_names [get_lib_cells]
    set csv_file "cell_names.csv"
    set csv_handle [open $csv_file "w"]
    foreach cell $cell_names {
        puts $csv_handle $cell
    }
    close $csv_handle

[maliberty]

You need an argument, eg

>>> llength [get_lib_cells *]
135

[maliberty]

In sdc instances are called cells. What information are you trying to query? The timing info will be available through sdc but not physical info

[gudeh]

The cell area, number of input and output pins, and the string logic function, if possible.

[gudeh]

Well, obviously this can be achieved by reading the liberty file myself. I did with python and it is working fine.

I wanted to do this via OpenROAD because I assume it would be safer and also to learn a little more about the tool. Unfortunately the documentation does not include a lot about TCL commands.

I also attempted to do so with Yosys RTLIL, but I was not successful. It seems to not be possible to get standard cell data from RTLIL.

Either way, I am just replying here to wrap up this question.

[maliberty]

Have you looked at https://github.com/The-OpenROAD-Project/OpenSTA/blob/master/doc/OpenSTA.pdf ?

[maliberty]

I don't think the function is exposed but the others are easy to get from the odb APIs and possible from sta.