Transforming sequential circuits into combinational

[gudeh]

TL;DR - Does anyone know how to transform a sequential circuit into a combinational one? Perhaps there is a way to remove the clock entirely during synthesis in OpenROAD?

Hello everyone. I am using OpenROAD to generate a dataset. In this dataset, I would like to include the logic depth of each logic gate. However, I'm facing an issue with the sequential parts of the circuit, as they introduce loops when represented as a graph. If there was a way to remove all sequential elements from the circuit, the logic depth calculation would be straightforward.

To generate the data, I am using the final Verilog file (6_final.v) located in the results directory. I made modifications to Yosys to transform the circuits into CSV representations and then represent them as graphs. I reached out to the Yosys developers on their Slack channel, and they informed me about built-in functions that can identify sequential cells. However, these functions only work if the built-in sequential cells from Yosys are used. They don't work when the flow utilizes sequential cells from the PDK library of cells, making it impossible to identify sequential cells within Yosys.

I attempted a naive approach of removing logic gates based on their names after the flow. I used regex name matching based on the sequential elements I found in the NanGate library of cells. However, this approach did not work, and I still ended up with graphs containing loops.

My ultimate goal is to calculate the logic depth of each logic gate. This would be straightforward if the graph representation of the circuit had no loops.

Does anyone know how to transform a sequential circuit into a combinational one? Perhaps there is a way to remove the clock entirely during synthesis?

[maliberty]

I don't think this is possible (even theoretically)

[rovinski]

In a general case, I don't think this is possible (or at least practical). For some extremely targeted use cases I could see this being possible.

I think you are working at the wrong level of abstraction to accomplish this. It sounds kind of similar to loop unrolling in high-level synthesis tools which allow manipulating the RTL before implementing into a netlist.

My ultimate goal is to calculate the logic depth of each logic gate. This would be straightforward if the graph representation of the circuit had no loops.

This does not seem like the right approach to this problem. Also I am unsure what definition of "logic depth" you are using here.

[gudeh]

By logic depth I mean the maximum number of logic gates going from any input to a logic gate. The inverse, starting from the outputs, is also possible.

When you say I am working on the wrong level of abstraction you mean representing the circuit as a graph? Indeed, I wish I was able to solve this during the logic synthesis, not after the flow has run already.

I was thinking about removing the clock from the RTL description, although I am not sure if the openroad flow would work without it.

Also I have a question, during logic synthesis, will the tool synthesize sequential elements using simple combinational cells?

[rovinski]

By logic depth I mean the maximum number of logic gates going from any input to a logic gate.

In my experience "logic depth" refers to the number of gates between inputs, outputs, or sequential elements. Is there a particular reason your analysis needs to ignore sequential elements in the logic depth calculation? I don't see when that would make sense because sequential elements are meant to hold state - trying to "flatten" them by any means would cause a combinatorial explosion in your graph analysis.

will the tool synthesize sequential elements using simple combinational cells?

No, sequential elements are fundamentally not representable by combinational elements. The whole purpose of sequential elements is to hold state, and combinational elements do not hold state. Could you connect combinational elements together in a manner that holds state? Yes, but then you have just taken a roundabout way to creating a sequential element, and your netlist will still contain loops.

Maybe if you describe what you are trying to do from a high-level view it might be possible to give better feedback?