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"value": 11, + "value": 10, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -20.31, + "value": -13.78, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/intel16/aes/constraint.sdc b/flow/designs/intel16/aes/constraint.sdc index c25b8b64cf..b90ac2d10e 100644 --- a/flow/designs/intel16/aes/constraint.sdc +++ b/flow/designs/intel16/aes/constraint.sdc @@ -1,5 +1,5 @@ set clk_name clk -set clk_period 2600 +set clk_period 2100 # create_clock -name $clk_name -period $clk_period [get_ports clk] # diff --git a/flow/designs/intel16/aes/metadata-base-ok.json b/flow/designs/intel16/aes/metadata-base-ok.json index 6856df82aa..f66d1ae305 100644 --- a/flow/designs/intel16/aes/metadata-base-ok.json +++ b/flow/designs/intel16/aes/metadata-base-ok.json @@ -1,69 +1,69 @@ { "constraints__clocks__count": 1, "constraints__clocks__details": [ - "clk: 2600.0000" + "clk: 2100.0000" ], - "cts__clock__skew__hold": 610.9531, - "cts__clock__skew__hold__post_repair": 582.0911, - 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"placeopt__design__instance__area__stdcell": 148.541, + "placeopt__design__instance__area__stdcell": 151.5154, "placeopt__design__instance__area__stdcell__pre_opt": 137.5186, "placeopt__design__instance__count": 323, "placeopt__design__instance__count__macros": 0, @@ -232,13 +235,13 @@ "placeopt__design__instance__count__pre_opt": 270, "placeopt__design__instance__count__stdcell": 323, "placeopt__design__instance__count__stdcell__pre_opt": 270, - "placeopt__design__instance__utilization": 0.3286, + "placeopt__design__instance__utilization": 0.3352, "placeopt__design__instance__utilization__pre_opt": 0.3042, - "placeopt__design__instance__utilization__stdcell": 0.3286, + "placeopt__design__instance__utilization__stdcell": 0.3352, "placeopt__design__instance__utilization__stdcell__pre_opt": 0.3042, "placeopt__design__io": 54, "placeopt__design__io__pre_opt": 54, - "placeopt__mem__peak": 202204.0, + "placeopt__mem__peak": 231320.0, "placeopt__power__internal__total": 0.0001, "placeopt__power__internal__total__pre_opt": 0.0001, "placeopt__power__leakage__total": 0.0, @@ -247,24 +250,24 @@ "placeopt__power__switching__total__pre_opt": 0.0, "placeopt__power__total": 0.0001, "placeopt__power__total__pre_opt": 0.0001, - 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"value": -383.32, + "value": -204.75, "compare": ">=" }, "globalroute__timing__setup__ws": { - "value": -383.32, + "value": -204.76, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 2262, + "value": 2218, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -276.82, + "value": -99.22, "compare": ">=" }, "finish__design__instance__area": { @@ -80,11 +80,11 @@ "compare": "<=" }, "finish__timing__drv__hold_violation_count": { - "value": 11, + "value": 10, "compare": "<=" }, "finish__timing__wns_percent_delay": { - "value": -25.68, + "value": -13.55, "compare": ">=" } } \ No newline at end of file diff --git a/flow/designs/intel22/aes/constraint.sdc b/flow/designs/intel22/aes/constraint.sdc index c25b8b64cf..be212dcfa9 100644 --- a/flow/designs/intel22/aes/constraint.sdc +++ b/flow/designs/intel22/aes/constraint.sdc @@ -1,5 +1,5 @@ set clk_name clk -set clk_period 2600 +set clk_period 1360 # create_clock -name $clk_name -period $clk_period [get_ports clk] # diff --git a/flow/designs/intel22/aes/metadata-base-ok.json b/flow/designs/intel22/aes/metadata-base-ok.json index fe10072c8b..b44a916577 100644 --- a/flow/designs/intel22/aes/metadata-base-ok.json +++ b/flow/designs/intel22/aes/metadata-base-ok.json @@ -1,69 +1,69 @@ { "constraints__clocks__count": 1, "constraints__clocks__details": [ - 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"placeopt__timing__setup__ws__pre_opt": -15431.0801, + "placeopt__timing__drv__max_slew_limit": 0.2161, + "placeopt__timing__drv__setup_violation_count": 1, + "placeopt__timing__setup__tns": -3430009.5, + "placeopt__timing__setup__tns__pre_opt": -38784240.0, + "placeopt__timing__setup__ws": -2608.28, + "placeopt__timing__setup__ws__pre_opt": -19801.5293, "run__flow__design": "ibex", - "run__flow__generate_date": "2022-12-12 14:36", + "run__flow__generate_date": "2022-12-29 17:27", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-6071-g5cc4fa644", + "run__flow__openroad_version": "v2.0-6190-g4f1108b6f", "run__flow__platform": "intel22", "run__flow__platform__capacitance_units": "1fF", "run__flow__platform__current_units": "1mA", @@ -305,14 +300,14 @@ "run__flow__platform__resistance_units": "1ohm", "run__flow__platform__time_units": "1ps", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "d88be9a4f007c5f3a72d22a2aff36fad8b717eae", - "run__flow__scripts_commit": "b03d9e081aa35f977aca64fac7586bb01f1a9abc", - "run__flow__uuid": "073aaa87-56ea-4e94-9cc1-35dc9c42cd26", + "run__flow__platform_commit": "edcdbdb80fc4e37a2f79567fa40becf24410f069", + "run__flow__scripts_commit": "2b93d1f5f60a7e1fd2b55823379a1a485e865cec", + "run__flow__uuid": "791a5c34-3fc1-4ee3-b0d1-523944530212", "run__flow__variant": "base", - "synth__cpu__total": 133.31, + "synth__cpu__total": 134.59, "synth__design__instance__area__stdcell": 9184.3794, "synth__design__instance__count__stdcell": 16702.0, - "synth__mem__peak": 319932.0, - "synth__runtime__total": "2:20.27", - "total_time": "0:04:05.870000" + "synth__mem__peak": 331912.0, + "synth__runtime__total": "2:17.78", + "total_time": "0:04:03.370000" } \ No newline at end of file diff --git a/flow/designs/intel22/ibex/rules-base.json b/flow/designs/intel22/ibex/rules-base.json index 4fa9b9b726..0e28c70426 100644 --- a/flow/designs/intel22/ibex/rules-base.json +++ b/flow/designs/intel22/ibex/rules-base.json @@ -20,19 +20,19 @@ "compare": "==" }, "cts__timing__setup__ws": { - "value": -978.69, + "value": -2017.06, "compare": ">=" }, "cts__timing__setup__ws__pre_repair": { - "value": -1023.65, + "value": -4255.06, "compare": ">=" }, "cts__timing__setup__ws__post_repair": { - "value": -1023.65, + "value": -4255.06, "compare": ">=" }, "cts__design__instance__count__setup_buffer": { - "value": 783, + "value": 900, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { @@ -40,11 +40,11 @@ "compare": "<=" }, "globalroute__timing__clock__slack": { - "value": -40.2, + "value": -1922.6, "compare": ">=" }, "globalroute__timing__setup__ws": { - "value": -40.2, + "value": -1922.61, "compare": ">=" }, "detailedroute__route__wirelength": { @@ -56,11 +56,11 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -259.77, "compare": ">=" }, "finish__design__instance__area": { - "value": 15512, + "value": 18349, "compare": "<=" }, "finish__timing__drv__max_slew_limit": { diff --git a/flow/designs/nangate45/black_parrot/config.mk b/flow/designs/nangate45/black_parrot/config.mk index c41c2927b3..aa4ef2cfd9 100644 --- a/flow/designs/nangate45/black_parrot/config.mk +++ b/flow/designs/nangate45/black_parrot/config.mk @@ -24,10 +24,12 @@ export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NAME)/ # These values must be multiples of placement site # x=0.19 y=1.4 -export DIE_AREA = 0 0 2200.01 2199.4 -export CORE_AREA = 10.07 11.2 2189.94 2189.6 +export DIE_AREA = 0 0 1500 1400 +export CORE_AREA = 10.07 11.2 1490 1390 -export PLACE_DENSITY = 0.15 +export PLACE_PINS_ARGS = -exclude left:* -exclude right:* -exclude top:* -exclude bottom:0-50 -exclude bottom:1500-1600 -export MACRO_PLACE_HALO = 5 5 -export MACRO_PLACE_CHANNEL = 10 10 +export PLACE_DENSITY_LB_ADDON = 0.10 + +export MACRO_PLACE_HALO = 10 10 +export MACRO_PLACE_CHANNEL = 20 20 diff --git a/flow/designs/nangate45/bp_be_top/config.mk b/flow/designs/nangate45/bp_be_top/config.mk index 7fb46a5b26..2dc7831c15 100644 --- a/flow/designs/nangate45/bp_be_top/config.mk +++ b/flow/designs/nangate45/bp_be_top/config.mk @@ -3,7 +3,6 @@ export DESIGN_NAME = bp_be_top export PLATFORM = nangate45 export SYNTH_HIERARCHICAL = 1 -export RTLMP_FLOW = True # # RTL_MP Settings export RTLMP_MAX_INST = 30000 @@ -25,7 +24,4 @@ export ADDITIONAL_LIBS = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NAME)/ export DIE_AREA = 0 0 1000 800 export CORE_AREA = 10.07 11.2 990 790 -export MACRO_PLACE_HALO = 5 5 -export MACRO_PLACE_CHANNEL = 10 10 - -export PLACE_DENSITY = 0.15 +export PLACE_DENSITY = 0.25 diff --git a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json b/flow/designs/nangate45/bp_be_top/metadata-base-ok.json index 4bb57c8b3c..2b1f1cce0d 100644 --- a/flow/designs/nangate45/bp_be_top/metadata-base-ok.json +++ b/flow/designs/nangate45/bp_be_top/metadata-base-ok.json @@ -3,67 +3,67 @@ "constraints__clocks__details": [ "CLK: 5.4000" ], - "cts__clock__skew__hold": 0.0959, - "cts__clock__skew__hold__post_repair": 0.0945, - "cts__clock__skew__hold__pre_repair": 0.0945, - "cts__clock__skew__setup": 0.0959, - "cts__clock__skew__setup__post_repair": 0.0945, - "cts__clock__skew__setup__pre_repair": 0.0945, - "cts__design__instance__area": 255371.9688, + "cts__clock__skew__hold": 0.0914, + "cts__clock__skew__hold__post_repair": 0.0915, + "cts__clock__skew__hold__pre_repair": 0.0915, + "cts__clock__skew__setup": 0.0914, + "cts__clock__skew__setup__post_repair": 0.0915, + "cts__clock__skew__setup__pre_repair": 0.0915, + "cts__design__instance__area": 247285.0312, "cts__design__instance__area__macros": 143269.4688, "cts__design__instance__area__macros__post_repair": 143269.4688, "cts__design__instance__area__macros__pre_repair": 143269.4688, - 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"value": 262506, + "value": 46692, "compare": "<=" }, "constraints__clocks__count": { @@ -8,11 +8,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 289861, + "value": 283620, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 62732, + "value": 55913, "compare": "<=" }, "detailedplace__design__violations": { @@ -32,11 +32,11 @@ "compare": ">=" }, "cts__design__instance__count__setup_buffer": { - "value": 2733, + "value": 2431, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 2733, + "value": 2431, "compare": "<=" }, "globalroute__timing__clock__slack": { @@ -48,7 +48,7 @@ "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 3132128, + "value": 2351207, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -60,7 +60,7 @@ "compare": ">=" }, "finish__design__instance__area": { - "value": 290857, + "value": 284378, "compare": "<=" }, "finish__timing__drv__max_slew_limit": { @@ -72,7 +72,7 @@ "compare": ">=" }, "finish__timing__drv__max_cap_limit": { - "value": -0.79, + "value": -0.46, "compare": ">=" }, "finish__timing__drv__setup_violation_count": { diff --git a/flow/designs/tsmc65lp/aes/constraint.sdc b/flow/designs/tsmc65lp/aes/constraint.sdc index 0ad4c64b4b..3986c9cf36 100644 --- a/flow/designs/tsmc65lp/aes/constraint.sdc +++ b/flow/designs/tsmc65lp/aes/constraint.sdc @@ -2,7 +2,7 @@ current_design aes_cipher_top set clk_name clk set clk_port_name clk -set clk_period 2.3 +set clk_period 1.8 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/tsmc65lp/aes/metadata-base-ok.json b/flow/designs/tsmc65lp/aes/metadata-base-ok.json index 9c4f6a0eef..4e32abaf43 100644 --- a/flow/designs/tsmc65lp/aes/metadata-base-ok.json +++ b/flow/designs/tsmc65lp/aes/metadata-base-ok.json @@ -1,69 +1,69 @@ { "constraints__clocks__count": 1, "constraints__clocks__details": [ - "clk: 2.3000" + "clk: 1.8000" ], - "cts__clock__skew__hold": 0.32, - "cts__clock__skew__hold__post_repair": 0.3273, - "cts__clock__skew__hold__pre_repair": 0.3273, - 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"value": 126516, + "value": 126322, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -40,11 +40,11 @@ "compare": "<=" }, "globalroute__timing__clock__slack": { - "value": -0.18, + "value": -0.38, "compare": ">=" }, "globalroute__timing__setup__ws": { - "value": -0.18, + "value": -0.39, "compare": ">=" }, "detailedroute__route__wirelength": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.14, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/tsmc65lp/gcd/constraint.sdc b/flow/designs/tsmc65lp/gcd/constraint.sdc index 82620ed752..98ab807b4d 100644 --- a/flow/designs/tsmc65lp/gcd/constraint.sdc +++ b/flow/designs/tsmc65lp/gcd/constraint.sdc @@ -2,7 +2,7 @@ current_design gcd set clk_name core_clock set clk_port_name clk -set clk_period 1.28 +set clk_period 1.20 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/tsmc65lp/gcd/metadata-base-ok.json b/flow/designs/tsmc65lp/gcd/metadata-base-ok.json index 4f942d095c..3bb922cb7a 100644 --- a/flow/designs/tsmc65lp/gcd/metadata-base-ok.json +++ b/flow/designs/tsmc65lp/gcd/metadata-base-ok.json @@ -1,69 +1,69 @@ { "constraints__clocks__count": 1, "constraints__clocks__details": [ - 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"run__flow__generate_date": "2022-09-29 20:20", + "run__flow__generate_date": "2022-12-29 16:17", "run__flow__metrics_version": "Metrics_2.1.2", "run__flow__openroad_commit": "N/A", - "run__flow__openroad_version": "v2.0-5083-ga783d1b9c", + "run__flow__openroad_version": "v2.0-6190-g4f1108b6f", "run__flow__platform": "tsmc65lp", "run__flow__platform__capacitance_units": "1pF", "run__flow__platform__current_units": "1mA", @@ -275,14 +276,14 @@ "run__flow__platform__resistance_units": "1kohm", "run__flow__platform__time_units": "1ns", "run__flow__platform__voltage_units": "1v", - "run__flow__platform_commit": "b25f2daf0825d34d8053a13141d30ac3424479e7", - "run__flow__scripts_commit": "97d54ba50c9e1213757524d9bd4e1a40d26c1a17", - "run__flow__uuid": "8ca6516a-28ec-40ce-b29b-07c25fbbd97b", + "run__flow__platform_commit": "5cb1fac1f980bb0c2fdb7fbcbf294a8d6c2cc02e", + "run__flow__scripts_commit": "2b93d1f5f60a7e1fd2b55823379a1a485e865cec", + "run__flow__uuid": "e2e4c94b-7891-4381-acc3-d428704f09b6", "run__flow__variant": "base", - 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"value": -0.44, + "value": -1.04, "compare": ">=" }, "globalroute__timing__setup__ws": { - "value": -0.44, + "value": -1.04, "compare": ">=" }, "detailedroute__route__wirelength": { @@ -56,7 +56,7 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": 0.0, + "value": -0.29, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/tsmc65lp/jpeg/constraint.sdc b/flow/designs/tsmc65lp/jpeg/constraint.sdc index 56391c205d..ba4cb6213a 100644 --- a/flow/designs/tsmc65lp/jpeg/constraint.sdc +++ b/flow/designs/tsmc65lp/jpeg/constraint.sdc @@ -2,7 +2,7 @@ current_design jpeg_encoder set clk_name clk set clk_port_name clk -set clk_period 5.0 +set clk_period 3.2 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] diff --git a/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json b/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json index 2f3d0f7ed5..08425e7280 100644 --- a/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json +++ b/flow/designs/tsmc65lp/jpeg/metadata-base-ok.json @@ -1,69 +1,69 @@ { "constraints__clocks__count": 1, "constraints__clocks__details": [ - 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