From bc7e99d0cbf5a62720b0910e5c65c6093de5e490 Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:22:21 -0400 Subject: [PATCH 1/6] Removed unsupported instructions from code. --- src/parser/parser_assembler_main.rs | 16 ---------------- src/parser/parser_structs_and_enums.rs | 5 +---- 2 files changed, 1 insertion(+), 20 deletions(-) diff --git a/src/parser/parser_assembler_main.rs b/src/parser/parser_assembler_main.rs index 161ea968a..6b5c75995 100644 --- a/src/parser/parser_assembler_main.rs +++ b/src/parser/parser_assembler_main.rs @@ -2606,22 +2606,6 @@ pub fn read_instructions_riscv( monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); } } - "fence.i" => { - // fence.i instruction encoding does not change - instruction.binary = 0b00000000000000000001000000001111; - - //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb - if monaco_line_info[instruction.line_number] - .mouse_hover_string - .is_empty() - { - let info = InstructionDescription{ - syntax: "fence.i".to_string(), - description: "Provides explicit synchronization between writes to instruction memory and instruction fetches on the same hart.".to_string(), - }; - monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); - } - } "lui" => { read_operands_riscv( instruction, diff --git a/src/parser/parser_structs_and_enums.rs b/src/parser/parser_structs_and_enums.rs index 9498ccf52..1816d3725 100644 --- a/src/parser/parser_structs_and_enums.rs +++ b/src/parser/parser_structs_and_enums.rs @@ -269,7 +269,7 @@ pub const SUPPORTED_INSTRUCTIONS_MIPS: [&str; 64] = [ "sll", "slt", "sltu", "sub", "sub.d", "sub.s", "sw", "swc1", ]; -pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 131] = [ +pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 128] = [ // RV32I "lui", "auipc", @@ -291,8 +291,6 @@ pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 131] = [ "sra", "or", "and", - "fence", - "fence.i", "csrrw", "csrrs", "csrrc", @@ -305,7 +303,6 @@ pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 131] = [ "sret", "mret", "wfi", - "sfence.vma", "lb", "lh", "lw", From 1e3241920d072166b779c9532470c5a81cae2029 Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:23:46 -0400 Subject: [PATCH 2/6] Removed unsupported instructions from readme. --- README.md | 3 --- 1 file changed, 3 deletions(-) diff --git a/README.md b/README.md index 4ca1a95e1..a0592041b 100644 --- a/README.md +++ b/README.md @@ -147,8 +147,6 @@ The RISC-V core supports the RV32I, RV64I, RV32M, RV64M, RV32F, and RV64F extens - sra - or - and - - fence - - fence.i - csrrw - csrrs - csrrc @@ -161,7 +159,6 @@ The RISC-V core supports the RV32I, RV64I, RV32M, RV64M, RV32F, and RV64F extens - sret - mret - wfi - - sfence.vma - lb - lh - lw From 68b40c2267e61f6db1d5d8f82ab83ddc08c39f44 Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:28:29 -0400 Subject: [PATCH 3/6] Fixed parser tests. --- src/tests/parser/parser_assembler_main.rs | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/src/tests/parser/parser_assembler_main.rs b/src/tests/parser/parser_assembler_main.rs index a38a24224..a04664c30 100644 --- a/src/tests/parser/parser_assembler_main.rs +++ b/src/tests/parser/parser_assembler_main.rs @@ -523,18 +523,6 @@ mod read_riscv_instructions_tests { ); } - #[test] - fn read_instructions_fencei() { - let file_string = "fence.i".to_string(); - - let instruction_list = instruction_parser_riscv(file_string); - - assert_eq!( - instruction_list[0].binary, - 0b00000000000000000001000000001111 - ); - } - #[test] fn read_instructions_lui() { let file_string = "lui x16, 4096".to_string(); From 7f7d4a89a1ba0f3175b6d672736f5d8200786ed3 Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:34:46 -0400 Subject: [PATCH 4/6] Removed more unsupported instructions. --- src/parser/parser_structs_and_enums.rs | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/src/parser/parser_structs_and_enums.rs b/src/parser/parser_structs_and_enums.rs index 1816d3725..e3ca298ee 100644 --- a/src/parser/parser_structs_and_enums.rs +++ b/src/parser/parser_structs_and_enums.rs @@ -269,7 +269,7 @@ pub const SUPPORTED_INSTRUCTIONS_MIPS: [&str; 64] = [ "sll", "slt", "sltu", "sub", "sub.d", "sub.s", "sw", "swc1", ]; -pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 128] = [ +pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 123] = [ // RV32I "lui", "auipc", @@ -286,7 +286,6 @@ pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 128] = [ "sll", "slt", "sltu", - "cor", "srl", "sra", "or", @@ -299,10 +298,6 @@ pub const SUPPORTED_INSTRUCTIONS_RISCV: [&str; 128] = [ "csrrci", "ecall", "ebreak", - "uret", - "sret", - "mret", - "wfi", "lb", "lh", "lw", @@ -817,7 +812,11 @@ pub const UNSUPPORTED_INSTRUCTIONS_MIPS: [&str; 408] = [ "xori", ]; -pub const UNSUPPORTED_INSTRUCTIONS_RISCV: [&str; 69] = [ +pub const UNSUPPORTED_INSTRUCTIONS_RISCV: [&str; 73] = [ + "fence", + "fence.i", + "sfence.vma", + "uret", "lr.w", "sc.w", "amoswap.w", From edbc68555dc43acd218b23fa98856b91f2ffab60 Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:38:21 -0400 Subject: [PATCH 5/6] Removed more unsupported code. --- src/parser/parser_assembler_main.rs | 64 ----------------------- src/tests/parser/parser_assembler_main.rs | 48 ----------------- 2 files changed, 112 deletions(-) diff --git a/src/parser/parser_assembler_main.rs b/src/parser/parser_assembler_main.rs index 6b5c75995..7e0ea0052 100644 --- a/src/parser/parser_assembler_main.rs +++ b/src/parser/parser_assembler_main.rs @@ -2542,70 +2542,6 @@ pub fn read_instructions_riscv( monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); } } - "uret" => { - // uret instruction encoding does not change - instruction.binary = 0b00000000001000000000000001110011; - - //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb - if monaco_line_info[instruction.line_number] - .mouse_hover_string - .is_empty() - { - let info = InstructionDescription{ - syntax: "uret".to_string(), - description: "Return from traps in U-mode, and URET copies UPIE into UIE, then sets UPIE.".to_string(), - }; - monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); - } - } - "sret" => { - // uret instruction encoding does not change - instruction.binary = 0b00010000001000000000000001110011; - - //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb - if monaco_line_info[instruction.line_number] - .mouse_hover_string - .is_empty() - { - let info = InstructionDescription{ - syntax: "uret".to_string(), - description: "Return from traps in U-mode, and URET copies UPIE into UIE, then sets UPIE.".to_string(), - }; - monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); - } - } - "mret" => { - // uret instruction encoding does not change - instruction.binary = 0b00110000001000000000000001110011; - - //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb - if monaco_line_info[instruction.line_number] - .mouse_hover_string - .is_empty() - { - let info = InstructionDescription{ - syntax: "mret".to_string(), - description: "Return from traps in M-mode, and MRET copies MPIE into MIE, then sets MPIE.".to_string(), - }; - monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); - } - } - "wfi" => { - // uret instruction encoding does not change - instruction.binary = 0b00010000010100000000000001110011; - - //Pseudo-instructions already have text in mouse_hover_string so we check if there's text there already before adding in the blurb - if monaco_line_info[instruction.line_number] - .mouse_hover_string - .is_empty() - { - let info = InstructionDescription{ - syntax: "wfi".to_string(), - description: "Provides a hint to the implementation that the current hart can be stalled until an interrupt might need servicing.\n\nExecution of the WFI instruction can also be used to inform the hardware platform that suitable interrupts should preferentially be routed to this hart.\n\nWFI is available in all privileged modes, and optionally available to U-mode.\n\nThis instruction may raise an illegal instruction exception when TW=1 in mstatus.".to_string(), - }; - monaco_line_info[instruction.line_number].mouse_hover_string = info.to_string(); - } - } "lui" => { read_operands_riscv( instruction, diff --git a/src/tests/parser/parser_assembler_main.rs b/src/tests/parser/parser_assembler_main.rs index a04664c30..6bf102195 100644 --- a/src/tests/parser/parser_assembler_main.rs +++ b/src/tests/parser/parser_assembler_main.rs @@ -475,54 +475,6 @@ mod read_riscv_instructions_tests { ); } - #[test] - fn read_instructions_uret() { - let file_string = "uret".to_string(); - - let instruction_list = instruction_parser_riscv(file_string); - - assert_eq!( - instruction_list[0].binary, - 0b00000000001000000000000001110011 - ); - } - - #[test] - fn read_instructions_sret() { - let file_string = "sret".to_string(); - - let instruction_list = instruction_parser_riscv(file_string); - - assert_eq!( - instruction_list[0].binary, - 0b00010000001000000000000001110011 - ); - } - - #[test] - fn read_instructions_mret() { - let file_string = "mret".to_string(); - - let instruction_list = instruction_parser_riscv(file_string); - - assert_eq!( - instruction_list[0].binary, - 0b00110000001000000000000001110011 - ); - } - - #[test] - fn read_instructions_wfi() { - let file_string = "wfi".to_string(); - - let instruction_list = instruction_parser_riscv(file_string); - - assert_eq!( - instruction_list[0].binary, - 0b00010000010100000000000001110011 - ); - } - #[test] fn read_instructions_lui() { let file_string = "lui x16, 4096".to_string(); From 16d273d2e220acd7d310b9596eeada8b38c66ddb Mon Sep 17 00:00:00 2001 From: rharding8 Date: Fri, 19 Apr 2024 21:40:50 -0400 Subject: [PATCH 6/6] Fixed README --- README.md | 5 ----- 1 file changed, 5 deletions(-) diff --git a/README.md b/README.md index a0592041b..6d2cbcc4e 100644 --- a/README.md +++ b/README.md @@ -142,7 +142,6 @@ The RISC-V core supports the RV32I, RV64I, RV32M, RV64M, RV32F, and RV64F extens - sll - slt - sltu - - cor - srl - sra - or @@ -155,10 +154,6 @@ The RISC-V core supports the RV32I, RV64I, RV32M, RV64M, RV32F, and RV64F extens - csrrci - ecall - ebreak - - uret - - sret - - mret - - wfi - lb - lh - lw