The implementation of a Feed Forward Equalizer (FFE) using only one adder and one multiplier. The specifications include an input data frequency of 1 MHz and an FFE clock frequency of 4 MHz. The output data is assumed to be a 12-bit signed value. The output is available after every 4 cycles of the FFE clock. This paper details the proposed design, provides pseudo code to represent the design, includes Verilog code to mimic the design behavior, and presents the netlist of the Verilog code.