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lissajous_vhdl.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2016 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel MegaCore Function License Agreement, or other
# applicable license agreement, including, without limitation,
# that your use is for the sole purpose of programming logic
# devices manufactured by Intel and sold by Intel or its
# authorized distributors. Please refer to the applicable
# agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 16.1.0 Build 196 10/24/2016 SJ Lite Edition
# Date created = 00:50:52 November 27, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# lissajous_vhdl_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M50DAF484C7G
set_global_assignment -name TOP_LEVEL_ENTITY lissajous_curves
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 16.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:50:52 NOVEMBER 27, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "16.1.0 Lite Edition"
set_global_assignment -name VHDL_FILE lissajous_curves.vhd
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE SPEED
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_location_assignment PIN_N5 -to clk
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_AA8 -to x_out[7]
set_location_assignment PIN_W5 -to x_out[0]
set_location_assignment PIN_AA14 -to x_out[1]
set_location_assignment PIN_W12 -to x_out[2]
set_location_assignment PIN_AB12 -to x_out[3]
set_location_assignment PIN_AB11 -to x_out[4]
set_location_assignment PIN_AB10 -to x_out[5]
set_location_assignment PIN_AA9 -to x_out[6]
set_location_assignment PIN_Y7 -to y_out[7]
set_location_assignment PIN_Y8 -to y_out[6]
set_location_assignment PIN_AA10 -to y_out[5]
set_location_assignment PIN_W11 -to y_out[4]
set_location_assignment PIN_Y11 -to y_out[3]
set_location_assignment PIN_AB13 -to y_out[2]
set_location_assignment PIN_W13 -to y_out[1]
set_location_assignment PIN_AA15 -to y_out[0]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top