From 3c355ec439dcf821c50fb4660ef0e50d19ae2b63 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?K=C3=A9vin=20Petit?= <kevin.petit@arm.com>
Date: Wed, 10 Jul 2024 16:43:24 +0100
Subject: [PATCH] Reserve 4 memory operands bits for Arm (#436)

Change-Id: I3b19b7ab42ba7bd5a87776fb21cb62451bb61683
---
 include/spirv/spir-v.xml | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/spirv/spir-v.xml b/include/spirv/spir-v.xml
index f9b23ac41..332f41148 100644
--- a/include/spirv/spir-v.xml
+++ b/include/spirv/spir-v.xml
@@ -272,7 +272,8 @@
     <!-- Reserved memory operand bits -->
     <ids type="MemoryOperand" start="0" end="15" vendor="Khronos" comment="Reserved MemoryOperand bits, not available to vendors - see the SPIR-V Specification"/>
     <ids type="MemoryOperand" start="16" end="18" vendor="Intel" comment="Contact michael.kinsner@intel.com"/>
-    <ids type="MemoryOperand" start="19" end="30" comment="Unreserved bits reservable for use by vendors"/>
+    <ids type="MemoryOperand" start="19" end="22" vendor="Arm" comment="Contact kevin.petit@arm.com"/>
+    <ids type="MemoryOperand" start="23" end="30" comment="Unreserved bits reservable for use by vendors"/>
     <ids type="MemoryOperand" start="31" end="31" vendor="Khronos" comment="Reserved MemoryOperand bit, not available to vendors"/>
 
     <!-- SECTION: SPIR-V Image Operand Bit Reservations -->