axi4_2x2_ic.icd

{
  "interconnects": [
  	{
  		"name": "main_ic", 
  		"protocol": "axi4", 
  		"data-width": "32", 
  		"addr-width": "32",
  		"id-width": "4",
  		"n-targets": "2",
  		"n-initiators": "2",
	    "addrmap": [
	      {"port": "t[0]", "base": "0x00000000", "limit": "0x00001FFF"}
	    ]
  	},
  	{
  		"name": "periph_ic", 
  		"protocol": "axi4", 
  		"data-width": "32", 
  		"addr-width": "32",
  		"id-width": "4",
  		"n-targets": "2",
  		"n-initiators": "4",
    	"addrmap": [
    	  {"port": "i[0]", "base": "0x00000000", "limit": "0x00001FFF"}
    	]
    }
  ],
  "bridges": [
  	{ 
  		"name": "main2reg", 
	    "target": {
	      "protocol": "axi4", "data-width": "32", "addr-width": "32"
	    },
	    "initiator": {
	      "protocol": "wb", "data-width": "64", "addr-width": "32"
	    }
	}
  ],
  "portmap": [
    ["export", "main_ic.t[0]", "axi0"],
    ["bind", "main_ic.i[0]", "main2reg.t"],
    ["export", "main2reg.t[0]", "axi1"]
  ]
}