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aarch64.h
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/* Copyright 2024 Dual Tachyon
* https://github.com/DualTachyon
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef AARCH64_COMMON_CORE_H
#define AARCH64_COMMON_CORE_H
#include <stdint.h>
#define CORE_BIT_MASK(s, w) ((((2ULL) << ((w) - 1)) - 1LLU) << (s))
// CurrentEL SHIFT
#define CORE_CurrentEL_SHIFT_EL (2)
// CurrentEL WIDTH
#define CORE_CurrentEL_WIDTH_EL (2)
// CurrentEL MASK
#define CORE_CurrentEL_MASK_EL CORE_BIT_MASK(CORE_CurrentEL_SHIFT_EL, CORE_CurrentEL_WIDTH_EL)
// CurrentEL GET
#define CORE_CurrentEL_GET_EL(v) (((v) >> CORE_CurrentEL_SHIFT_EL) & CORE_BIT_MASK(0, CORE_CurrentEL_WIDTH_EL))
// CurrentEL BITS
#define CORE_CurrentEL_BITS_EL(v) (((v) & CORE_BIT_MASK(0, CORE_CurrentEL_WIDTH_EL)) << CORE_CurrentEL_SHIFT_EL)
// CurrentEL VALUE
#define CORE_CurrentEL_VALUE_EL_EL3 (3U)
#define CORE_CurrentEL_VALUE_EL_EL2 (2U)
#define CORE_CurrentEL_VALUE_EL_EL1 (1U)
#define CORE_CurrentEL_VALUE_EL_EL0 (0U)
// ELR_EL3 SHIFT
#define CORE_ELR_EL3_SHIFT_ADDRESS (0)
// ELR_EL3 WIDTH
#define CORE_ELR_EL3_WIDTH_ADDRESS (64)
// ELR_EL3 MASK
#define CORE_ELR_EL3_MASK_ADDRESS CORE_BIT_MASK(CORE_ELR_EL3_SHIFT_ADDRESS, CORE_ELR_EL3_WIDTH_ADDRESS)
// ELR_EL3 GET
#define CORE_ELR_EL3_GET_ADDRESS(v) (((v) >> CORE_ELR_EL3_SHIFT_ADDRESS) & CORE_BIT_MASK(0, CORE_ELR_EL3_WIDTH_ADDRESS))
// ELR_EL3 BITS
#define CORE_ELR_EL3_BITS_ADDRESS(v) (((v) & CORE_BIT_MASK(0, CORE_ELR_EL3_WIDTH_ADDRESS)) << CORE_ELR_EL3_SHIFT_ADDRESS)
// ESR_EL3 SHIFT
#define CORE_ESR_EL3_SHIFT_EC (26)
#define CORE_ESR_EL3_SHIFT_IL (25)
#define CORE_ESR_EL3_SHIFT_ISS (0)
// ESR_EL3 WIDTH
#define CORE_ESR_EL3_WIDTH_EC (6)
#define CORE_ESR_EL3_WIDTH_IL (1)
#define CORE_ESR_EL3_WIDTH_ISS (25)
// ESR_EL3 MASK
#define CORE_ESR_EL3_MASK_EC CORE_BIT_MASK(CORE_ESR_EL3_SHIFT_EC, CORE_ESR_EL3_WIDTH_EC)
#define CORE_ESR_EL3_MASK_IL CORE_BIT_MASK(CORE_ESR_EL3_SHIFT_IL, CORE_ESR_EL3_WIDTH_IL)
#define CORE_ESR_EL3_MASK_ISS CORE_BIT_MASK(CORE_ESR_EL3_SHIFT_ISS, CORE_ESR_EL3_WIDTH_ISS)
// ESR_EL3 GET
#define CORE_ESR_EL3_GET_EC(v) (((v) >> CORE_ESR_EL3_SHIFT_EC) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_EC))
#define CORE_ESR_EL3_GET_IL(v) (((v) >> CORE_ESR_EL3_SHIFT_IL) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_IL))
#define CORE_ESR_EL3_GET_ISS(v) (((v) >> CORE_ESR_EL3_SHIFT_ISS) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_ISS))
// ESR_EL3 BITS
#define CORE_ESR_EL3_BITS_EC(v) (((v) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_EC)) << CORE_ESR_EL3_SHIFT_EC)
#define CORE_ESR_EL3_BITS_IL(v) (((v) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_IL)) << CORE_ESR_EL3_SHIFT_IL)
#define CORE_ESR_EL3_BITS_ISS(v) (((v) & CORE_BIT_MASK(0, CORE_ESR_EL3_WIDTH_ISS)) << CORE_ESR_EL3_SHIFT_ISS)
// ESR_EL3 VALUE
#define CORE_ESR_EL3_VALUE_EC_UNKNOWN (0U)
#define CORE_ESR_EL3_VALUE_EC_WFE_WFI (1U)
#define CORE_ESR_EL3_VALUE_EC_MCR_MRC_C15 (3U)
#define CORE_ESR_EL3_VALUE_EC_MCRR_MRRC_C15 (4U)
#define CORE_ESR_EL3_VALUE_EC_MCR_MRC_C14 (5U)
#define CORE_ESR_EL3_VALUE_EC_LDC_STC (6U)
#define CORE_ESR_EL3_VALUE_EC_ILLEGAL (14U)
#define CORE_ESR_EL3_VALUE_EC_A64_SVC (21U)
#define CORE_ESR_EL3_VALUE_EC_A64_HVC (22U)
#define CORE_ESR_EL3_VALUE_EC_A64_SMC (23U)
#define CORE_ESR_EL3_VALUE_EC_MSR_MRS_SYS (24U)
#define CORE_ESR_EL3_VALUE_EC_INSN_ABORT_T (32U)
#define CORE_ESR_EL3_VALUE_EC_INSN_ABORT_H (33U)
#define CORE_ESR_EL3_VALUE_EC_PC_ALIGNMENT (34U)
#define CORE_ESR_EL3_VALUE_EC_DATA_ABORT_T (36U)
#define CORE_ESR_EL3_VALUE_EC_DATA_ABORT_H (37U)
#define CORE_ESR_EL3_VALUE_EC_STACK_ALIGN (38U)
#define CORE_ESR_EL3_VALUE_EC_SERROR (47U)
#define CORE_ESR_EL3_VALUE_EC_BRK (60U)
// FAR_EL3 SHIFT
#define CORE_FAR_EL3_SHIFT_ADDRESS (0)
// FAR_EL3 WIDTH
#define CORE_FAR_EL3_WIDTH_ADDRESS (64)
// FAR_EL3 MASK
#define CORE_FAR_EL3_MASK_ADDRESS CORE_BIT_MASK(CORE_FAR_EL3_SHIFT_ADDRESS, CORE_FAR_EL3_WIDTH_ADDRESS)
// FAR_EL3 GET
#define CORE_FAR_EL3_GET_ADDRESS(v) (((v) >> CORE_FAR_EL3_SHIFT_ADDRESS) & CORE_BIT_MASK(0, CORE_FAR_EL3_WIDTH_ADDRESS))
// FAR_EL3 BITS
#define CORE_FAR_EL3_BITS_ADDRESS(v) (((v) & CORE_BIT_MASK(0, CORE_FAR_EL3_WIDTH_ADDRESS)) << CORE_FAR_EL3_SHIFT_ADDRESS)
// MPIDR_EL1 SHIFT
#define CORE_MPIDR_EL1_SHIFT_AFF3 (32)
#define CORE_MPIDR_EL1_SHIFT_U (30)
#define CORE_MPIDR_EL1_SHIFT_MT (24)
#define CORE_MPIDR_EL1_SHIFT_AFF2 (16)
#define CORE_MPIDR_EL1_SHIFT_AFF1 (8)
#define CORE_MPIDR_EL1_SHIFT_AFF0 (0)
// MPIDR_EL1 WIDTH
#define CORE_MPIDR_EL1_WIDTH_AFF3 (8)
#define CORE_MPIDR_EL1_WIDTH_U (1)
#define CORE_MPIDR_EL1_WIDTH_MT (1)
#define CORE_MPIDR_EL1_WIDTH_AFF2 (8)
#define CORE_MPIDR_EL1_WIDTH_AFF1 (8)
#define CORE_MPIDR_EL1_WIDTH_AFF0 (8)
// MPIDR_EL1 MASK
#define CORE_MPIDR_EL1_MASK_AFF3 CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_AFF3, CORE_MPIDR_EL1_WIDTH_AFF3)
#define CORE_MPIDR_EL1_MASK_U CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_U, CORE_MPIDR_EL1_WIDTH_U)
#define CORE_MPIDR_EL1_MASK_MT CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_MT, CORE_MPIDR_EL1_WIDTH_MT)
#define CORE_MPIDR_EL1_MASK_AFF2 CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_AFF2, CORE_MPIDR_EL1_WIDTH_AFF2)
#define CORE_MPIDR_EL1_MASK_AFF1 CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_AFF1, CORE_MPIDR_EL1_WIDTH_AFF1)
#define CORE_MPIDR_EL1_MASK_AFF0 CORE_BIT_MASK(CORE_MPIDR_EL1_SHIFT_AFF0, CORE_MPIDR_EL1_WIDTH_AFF0)
// MPIDR_EL1 GET
#define CORE_MPIDR_EL1_GET_AFF3(v) (((v) >> CORE_MPIDR_EL1_SHIFT_AFF3) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF3))
#define CORE_MPIDR_EL1_GET_U(v) (((v) >> CORE_MPIDR_EL1_SHIFT_U) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_U))
#define CORE_MPIDR_EL1_GET_MT(v) (((v) >> CORE_MPIDR_EL1_SHIFT_MT) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_MT))
#define CORE_MPIDR_EL1_GET_AFF2(v) (((v) >> CORE_MPIDR_EL1_SHIFT_AFF2) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF2))
#define CORE_MPIDR_EL1_GET_AFF1(v) (((v) >> CORE_MPIDR_EL1_SHIFT_AFF1) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF1))
#define CORE_MPIDR_EL1_GET_AFF0(v) (((v) >> CORE_MPIDR_EL1_SHIFT_AFF0) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF0))
// MPIDR_EL1 BITS
#define CORE_MPIDR_EL1_BITS_AFF3(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF3)) << CORE_MPIDR_EL1_SHIFT_AFF3)
#define CORE_MPIDR_EL1_BITS_U(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_U)) << CORE_MPIDR_EL1_SHIFT_U)
#define CORE_MPIDR_EL1_BITS_MT(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_MT)) << CORE_MPIDR_EL1_SHIFT_MT)
#define CORE_MPIDR_EL1_BITS_AFF2(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF2)) << CORE_MPIDR_EL1_SHIFT_AFF2)
#define CORE_MPIDR_EL1_BITS_AFF1(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF1)) << CORE_MPIDR_EL1_SHIFT_AFF1)
#define CORE_MPIDR_EL1_BITS_AFF0(v) (((v) & CORE_BIT_MASK(0, CORE_MPIDR_EL1_WIDTH_AFF0)) << CORE_MPIDR_EL1_SHIFT_AFF0)
// SPSEL SHIFT
#define CORE_SPSEL_SHIFT_SP (0)
// SPSEL WIDTH
#define CORE_SPSEL_WIDTH_SP (1)
// SPSEL MASK
#define CORE_SPSEL_MASK_SP CORE_BIT_MASK(CORE_SPSEL_SHIFT_SP, CORE_SPSEL_WIDTH_SP)
// SPSEL GET
#define CORE_SPSEL_GET_SP(v) (((v) >> CORE_SPSEL_SHIFT_SP) & CORE_BIT_MASK(0, CORE_SPSEL_WIDTH_SP))
// SPSEL BITS
#define CORE_SPSEL_BITS_SP(v) (((v) & CORE_BIT_MASK(0, CORE_SPSEL_WIDTH_SP)) << CORE_SPSEL_SHIFT_SP)
// SPSR_EL3 SHIFT
#define CORE_SPSR_EL3_SHIFT_A64_N (31)
#define CORE_SPSR_EL3_SHIFT_A64_Z (30)
#define CORE_SPSR_EL3_SHIFT_A64_C (29)
#define CORE_SPSR_EL3_SHIFT_A64_V (28)
#define CORE_SPSR_EL3_SHIFT_A64_SS (21)
#define CORE_SPSR_EL3_SHIFT_A64_IL (20)
#define CORE_SPSR_EL3_SHIFT_A64_D (9)
#define CORE_SPSR_EL3_SHIFT_A64_A (8)
#define CORE_SPSR_EL3_SHIFT_A64_I (7)
#define CORE_SPSR_EL3_SHIFT_A64_F (6)
#define CORE_SPSR_EL3_SHIFT_A64_MODE (4)
#define CORE_SPSR_EL3_SHIFT_A64_M (2)
#define CORE_SPSR_EL3_SHIFT_A64_SP (0)
#define CORE_SPSR_EL3_SHIFT_A32_N (31)
#define CORE_SPSR_EL3_SHIFT_A32_Z (30)
#define CORE_SPSR_EL3_SHIFT_A32_C (29)
#define CORE_SPSR_EL3_SHIFT_A32_V (28)
#define CORE_SPSR_EL3_SHIFT_A32_Q (27)
#define CORE_SPSR_EL3_SHIFT_A32_IT_LOW (25)
#define CORE_SPSR_EL3_SHIFT_A32_J (24)
#define CORE_SPSR_EL3_SHIFT_A32_SS (21)
#define CORE_SPSR_EL3_SHIFT_A32_IL (20)
#define CORE_SPSR_EL3_SHIFT_A32_GE (16)
#define CORE_SPSR_EL3_SHIFT_A32_IT_HIGH (10)
#define CORE_SPSR_EL3_SHIFT_A32_E (9)
#define CORE_SPSR_EL3_SHIFT_A32_A (8)
#define CORE_SPSR_EL3_SHIFT_A32_I (7)
#define CORE_SPSR_EL3_SHIFT_A32_F (6)
#define CORE_SPSR_EL3_SHIFT_A32_T (5)
#define CORE_SPSR_EL3_SHIFT_A32_MODE (4)
#define CORE_SPSR_EL3_SHIFT_A32_M (0)
// SPSR_EL3 WIDTH
#define CORE_SPSR_EL3_WIDTH_A64_N (1)
#define CORE_SPSR_EL3_WIDTH_A64_Z (1)
#define CORE_SPSR_EL3_WIDTH_A64_C (1)
#define CORE_SPSR_EL3_WIDTH_A64_V (1)
#define CORE_SPSR_EL3_WIDTH_A64_SS (1)
#define CORE_SPSR_EL3_WIDTH_A64_IL (1)
#define CORE_SPSR_EL3_WIDTH_A64_D (1)
#define CORE_SPSR_EL3_WIDTH_A64_A (1)
#define CORE_SPSR_EL3_WIDTH_A64_I (1)
#define CORE_SPSR_EL3_WIDTH_A64_F (1)
#define CORE_SPSR_EL3_WIDTH_A64_MODE (1)
#define CORE_SPSR_EL3_WIDTH_A64_M (2)
#define CORE_SPSR_EL3_WIDTH_A64_SP (1)
#define CORE_SPSR_EL3_WIDTH_A32_N (1)
#define CORE_SPSR_EL3_WIDTH_A32_Z (1)
#define CORE_SPSR_EL3_WIDTH_A32_C (1)
#define CORE_SPSR_EL3_WIDTH_A32_V (1)
#define CORE_SPSR_EL3_WIDTH_A32_Q (1)
#define CORE_SPSR_EL3_WIDTH_A32_IT_LOW (2)
#define CORE_SPSR_EL3_WIDTH_A32_J (1)
#define CORE_SPSR_EL3_WIDTH_A32_SS (1)
#define CORE_SPSR_EL3_WIDTH_A32_IL (1)
#define CORE_SPSR_EL3_WIDTH_A32_GE (4)
#define CORE_SPSR_EL3_WIDTH_A32_IT_HIGH (6)
#define CORE_SPSR_EL3_WIDTH_A32_E (1)
#define CORE_SPSR_EL3_WIDTH_A32_A (1)
#define CORE_SPSR_EL3_WIDTH_A32_I (1)
#define CORE_SPSR_EL3_WIDTH_A32_F (1)
#define CORE_SPSR_EL3_WIDTH_A32_T (1)
#define CORE_SPSR_EL3_WIDTH_A32_MODE (1)
#define CORE_SPSR_EL3_WIDTH_A32_M (4)
// SPSR_EL3 MASK
#define CORE_SPSR_EL3_MASK_A64_N CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_N, CORE_SPSR_EL3_WIDTH_A64_N)
#define CORE_SPSR_EL3_MASK_A64_Z CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_Z, CORE_SPSR_EL3_WIDTH_A64_Z)
#define CORE_SPSR_EL3_MASK_A64_C CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_C, CORE_SPSR_EL3_WIDTH_A64_C)
#define CORE_SPSR_EL3_MASK_A64_V CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_V, CORE_SPSR_EL3_WIDTH_A64_V)
#define CORE_SPSR_EL3_MASK_A64_SS CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_SS, CORE_SPSR_EL3_WIDTH_A64_SS)
#define CORE_SPSR_EL3_MASK_A64_IL CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_IL, CORE_SPSR_EL3_WIDTH_A64_IL)
#define CORE_SPSR_EL3_MASK_A64_D CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_D, CORE_SPSR_EL3_WIDTH_A64_D)
#define CORE_SPSR_EL3_MASK_A64_A CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_A, CORE_SPSR_EL3_WIDTH_A64_A)
#define CORE_SPSR_EL3_MASK_A64_I CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_I, CORE_SPSR_EL3_WIDTH_A64_I)
#define CORE_SPSR_EL3_MASK_A64_F CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_F, CORE_SPSR_EL3_WIDTH_A64_F)
#define CORE_SPSR_EL3_MASK_A64_MODE CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_MODE, CORE_SPSR_EL3_WIDTH_A64_MODE)
#define CORE_SPSR_EL3_MASK_A64_M CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_M, CORE_SPSR_EL3_WIDTH_A64_M)
#define CORE_SPSR_EL3_MASK_A64_SP CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A64_SP, CORE_SPSR_EL3_WIDTH_A64_SP)
#define CORE_SPSR_EL3_MASK_A32_N CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_N, CORE_SPSR_EL3_WIDTH_A32_N)
#define CORE_SPSR_EL3_MASK_A32_Z CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_Z, CORE_SPSR_EL3_WIDTH_A32_Z)
#define CORE_SPSR_EL3_MASK_A32_C CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_C, CORE_SPSR_EL3_WIDTH_A32_C)
#define CORE_SPSR_EL3_MASK_A32_V CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_V, CORE_SPSR_EL3_WIDTH_A32_V)
#define CORE_SPSR_EL3_MASK_A32_Q CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_Q, CORE_SPSR_EL3_WIDTH_A32_Q)
#define CORE_SPSR_EL3_MASK_A32_IT_LOW CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_IT_LOW, CORE_SPSR_EL3_WIDTH_A32_IT_LOW)
#define CORE_SPSR_EL3_MASK_A32_J CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_J, CORE_SPSR_EL3_WIDTH_A32_J)
#define CORE_SPSR_EL3_MASK_A32_SS CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_SS, CORE_SPSR_EL3_WIDTH_A32_SS)
#define CORE_SPSR_EL3_MASK_A32_IL CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_IL, CORE_SPSR_EL3_WIDTH_A32_IL)
#define CORE_SPSR_EL3_MASK_A32_GE CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_GE, CORE_SPSR_EL3_WIDTH_A32_GE)
#define CORE_SPSR_EL3_MASK_A32_IT_HIGH CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_IT_HIGH, CORE_SPSR_EL3_WIDTH_A32_IT_HIGH)
#define CORE_SPSR_EL3_MASK_A32_E CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_E, CORE_SPSR_EL3_WIDTH_A32_E)
#define CORE_SPSR_EL3_MASK_A32_A CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_A, CORE_SPSR_EL3_WIDTH_A32_A)
#define CORE_SPSR_EL3_MASK_A32_I CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_I, CORE_SPSR_EL3_WIDTH_A32_I)
#define CORE_SPSR_EL3_MASK_A32_F CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_F, CORE_SPSR_EL3_WIDTH_A32_F)
#define CORE_SPSR_EL3_MASK_A32_T CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_T, CORE_SPSR_EL3_WIDTH_A32_T)
#define CORE_SPSR_EL3_MASK_A32_MODE CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_MODE, CORE_SPSR_EL3_WIDTH_A32_MODE)
#define CORE_SPSR_EL3_MASK_A32_M CORE_BIT_MASK(CORE_SPSR_EL3_SHIFT_A32_M, CORE_SPSR_EL3_WIDTH_A32_M)
// SPSR_EL3 GET
#define CORE_SPSR_EL3_GET_A64_N(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_N) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_N))
#define CORE_SPSR_EL3_GET_A64_Z(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_Z) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_Z))
#define CORE_SPSR_EL3_GET_A64_C(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_C) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_C))
#define CORE_SPSR_EL3_GET_A64_V(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_V) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_V))
#define CORE_SPSR_EL3_GET_A64_SS(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_SS) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_SS))
#define CORE_SPSR_EL3_GET_A64_IL(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_IL) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_IL))
#define CORE_SPSR_EL3_GET_A64_D(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_D) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_D))
#define CORE_SPSR_EL3_GET_A64_A(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_A) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_A))
#define CORE_SPSR_EL3_GET_A64_I(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_I) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_I))
#define CORE_SPSR_EL3_GET_A64_F(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_F) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_F))
#define CORE_SPSR_EL3_GET_A64_MODE(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_MODE) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_MODE))
#define CORE_SPSR_EL3_GET_A64_M(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_M) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_M))
#define CORE_SPSR_EL3_GET_A64_SP(v) (((v) >> CORE_SPSR_EL3_SHIFT_A64_SP) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_SP))
#define CORE_SPSR_EL3_GET_A32_N(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_N) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_N))
#define CORE_SPSR_EL3_GET_A32_Z(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_Z) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_Z))
#define CORE_SPSR_EL3_GET_A32_C(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_C) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_C))
#define CORE_SPSR_EL3_GET_A32_V(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_V) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_V))
#define CORE_SPSR_EL3_GET_A32_Q(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_Q) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_Q))
#define CORE_SPSR_EL3_GET_A32_IT_LOW(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_IT_LOW) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IT_LOW))
#define CORE_SPSR_EL3_GET_A32_J(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_J) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_J))
#define CORE_SPSR_EL3_GET_A32_SS(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_SS) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_SS))
#define CORE_SPSR_EL3_GET_A32_IL(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_IL) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IL))
#define CORE_SPSR_EL3_GET_A32_GE(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_GE) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_GE))
#define CORE_SPSR_EL3_GET_A32_IT_HIGH(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_IT_HIGH) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IT_HIGH))
#define CORE_SPSR_EL3_GET_A32_E(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_E) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_E))
#define CORE_SPSR_EL3_GET_A32_A(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_A) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_A))
#define CORE_SPSR_EL3_GET_A32_I(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_I) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_I))
#define CORE_SPSR_EL3_GET_A32_F(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_F) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_F))
#define CORE_SPSR_EL3_GET_A32_T(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_T) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_T))
#define CORE_SPSR_EL3_GET_A32_MODE(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_MODE) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_MODE))
#define CORE_SPSR_EL3_GET_A32_M(v) (((v) >> CORE_SPSR_EL3_SHIFT_A32_M) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_M))
// SPSR_EL3 BITS
#define CORE_SPSR_EL3_BITS_A64_N(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_N)) << CORE_SPSR_EL3_SHIFT_A64_N)
#define CORE_SPSR_EL3_BITS_A64_Z(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_Z)) << CORE_SPSR_EL3_SHIFT_A64_Z)
#define CORE_SPSR_EL3_BITS_A64_C(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_C)) << CORE_SPSR_EL3_SHIFT_A64_C)
#define CORE_SPSR_EL3_BITS_A64_V(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_V)) << CORE_SPSR_EL3_SHIFT_A64_V)
#define CORE_SPSR_EL3_BITS_A64_SS(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_SS)) << CORE_SPSR_EL3_SHIFT_A64_SS)
#define CORE_SPSR_EL3_BITS_A64_IL(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_IL)) << CORE_SPSR_EL3_SHIFT_A64_IL)
#define CORE_SPSR_EL3_BITS_A64_D(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_D)) << CORE_SPSR_EL3_SHIFT_A64_D)
#define CORE_SPSR_EL3_BITS_A64_A(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_A)) << CORE_SPSR_EL3_SHIFT_A64_A)
#define CORE_SPSR_EL3_BITS_A64_I(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_I)) << CORE_SPSR_EL3_SHIFT_A64_I)
#define CORE_SPSR_EL3_BITS_A64_F(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_F)) << CORE_SPSR_EL3_SHIFT_A64_F)
#define CORE_SPSR_EL3_BITS_A64_MODE(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_MODE)) << CORE_SPSR_EL3_SHIFT_A64_MODE)
#define CORE_SPSR_EL3_BITS_A64_M(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_M)) << CORE_SPSR_EL3_SHIFT_A64_M)
#define CORE_SPSR_EL3_BITS_A64_SP(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A64_SP)) << CORE_SPSR_EL3_SHIFT_A64_SP)
#define CORE_SPSR_EL3_BITS_A32_N(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_N)) << CORE_SPSR_EL3_SHIFT_A32_N)
#define CORE_SPSR_EL3_BITS_A32_Z(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_Z)) << CORE_SPSR_EL3_SHIFT_A32_Z)
#define CORE_SPSR_EL3_BITS_A32_C(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_C)) << CORE_SPSR_EL3_SHIFT_A32_C)
#define CORE_SPSR_EL3_BITS_A32_V(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_V)) << CORE_SPSR_EL3_SHIFT_A32_V)
#define CORE_SPSR_EL3_BITS_A32_Q(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_Q)) << CORE_SPSR_EL3_SHIFT_A32_Q)
#define CORE_SPSR_EL3_BITS_A32_IT_LOW(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IT_LOW)) << CORE_SPSR_EL3_SHIFT_A32_IT_LOW)
#define CORE_SPSR_EL3_BITS_A32_J(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_J)) << CORE_SPSR_EL3_SHIFT_A32_J)
#define CORE_SPSR_EL3_BITS_A32_SS(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_SS)) << CORE_SPSR_EL3_SHIFT_A32_SS)
#define CORE_SPSR_EL3_BITS_A32_IL(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IL)) << CORE_SPSR_EL3_SHIFT_A32_IL)
#define CORE_SPSR_EL3_BITS_A32_GE(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_GE)) << CORE_SPSR_EL3_SHIFT_A32_GE)
#define CORE_SPSR_EL3_BITS_A32_IT_HIGH(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_IT_HIGH)) << CORE_SPSR_EL3_SHIFT_A32_IT_HIGH)
#define CORE_SPSR_EL3_BITS_A32_E(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_E)) << CORE_SPSR_EL3_SHIFT_A32_E)
#define CORE_SPSR_EL3_BITS_A32_A(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_A)) << CORE_SPSR_EL3_SHIFT_A32_A)
#define CORE_SPSR_EL3_BITS_A32_I(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_I)) << CORE_SPSR_EL3_SHIFT_A32_I)
#define CORE_SPSR_EL3_BITS_A32_F(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_F)) << CORE_SPSR_EL3_SHIFT_A32_F)
#define CORE_SPSR_EL3_BITS_A32_T(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_T)) << CORE_SPSR_EL3_SHIFT_A32_T)
#define CORE_SPSR_EL3_BITS_A32_MODE(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_MODE)) << CORE_SPSR_EL3_SHIFT_A32_MODE)
#define CORE_SPSR_EL3_BITS_A32_M(v) (((v) & CORE_BIT_MASK(0, CORE_SPSR_EL3_WIDTH_A32_M)) << CORE_SPSR_EL3_SHIFT_A32_M)
// SPSR_EL3 VALUE
#define CORE_SPSR_EL3_VALUE_A64_MODE_A32 (1U)
#define CORE_SPSR_EL3_VALUE_A64_MODE_A64 (0U)
#define CORE_SPSR_EL3_VALUE_A64_M_EL3 (3U)
#define CORE_SPSR_EL3_VALUE_A64_M_EL2 (2U)
#define CORE_SPSR_EL3_VALUE_A64_M_EL1 (1U)
#define CORE_SPSR_EL3_VALUE_A64_M_EL0 (0U)
#define CORE_SPSR_EL3_VALUE_A64_SP_H (1U)
#define CORE_SPSR_EL3_VALUE_A64_SP_T (0U)
#define CORE_SPSR_EL3_VALUE_A32_MODE_32 (1U)
#define CORE_SPSR_EL3_VALUE_A32_MODE_64 (0U)
#define CORE_SPSR_EL3_VALUE_A32_M_SYSTEM (15U)
#define CORE_SPSR_EL3_VALUE_A32_M_UNDEFINED (11U)
#define CORE_SPSR_EL3_VALUE_A32_M_HYP (10U)
#define CORE_SPSR_EL3_VALUE_A32_M_ABORT (7U)
#define CORE_SPSR_EL3_VALUE_A32_M_SUPERVISOR (3U)
#define CORE_SPSR_EL3_VALUE_A32_M_IRQ (2U)
#define CORE_SPSR_EL3_VALUE_A32_M_FIQ (1U)
#define CORE_SPSR_EL3_VALUE_A32_M_USER (0U)
// SP_EL3 SHIFT
#define CORE_SP_EL3_SHIFT_ADDRESS (0)
// SP_EL3 WIDTH
#define CORE_SP_EL3_WIDTH_ADDRESS (64)
// SP_EL3 MASK
#define CORE_SP_EL3_MASK_ADDRESS CORE_BIT_MASK(CORE_SP_EL3_SHIFT_ADDRESS, CORE_SP_EL3_WIDTH_ADDRESS)
// SP_EL3 GET
#define CORE_SP_EL3_GET_ADDRESS(v) (((v) >> CORE_SP_EL3_SHIFT_ADDRESS) & CORE_BIT_MASK(0, CORE_SP_EL3_WIDTH_ADDRESS))
// SP_EL3 BITS
#define CORE_SP_EL3_BITS_ADDRESS(v) (((v) & CORE_BIT_MASK(0, CORE_SP_EL3_WIDTH_ADDRESS)) << CORE_SP_EL3_SHIFT_ADDRESS)
// VBAR_EL3 SHIFT
#define CORE_VBAR_EL3_SHIFT_ADDRESS (11)
// VBAR_EL3 WIDTH
#define CORE_VBAR_EL3_WIDTH_ADDRESS (53)
// VBAR_EL3 MASK
#define CORE_VBAR_EL3_MASK_ADDRESS CORE_BIT_MASK(CORE_VBAR_EL3_SHIFT_ADDRESS, CORE_VBAR_EL3_WIDTH_ADDRESS)
// VBAR_EL3 GET
#define CORE_VBAR_EL3_GET_ADDRESS(v) (((v) >> CORE_VBAR_EL3_SHIFT_ADDRESS) & CORE_BIT_MASK(0, CORE_VBAR_EL3_WIDTH_ADDRESS))
// VBAR_EL3 BITS
#define CORE_VBAR_EL3_BITS_ADDRESS(v) (((v) & CORE_BIT_MASK(0, CORE_VBAR_EL3_WIDTH_ADDRESS)) << CORE_VBAR_EL3_SHIFT_ADDRESS)
#define CORE_REGISTER_SET_IMMEDIATE(name, width) \
static inline void coreSet_##name(width Value) \
{ \
__asm__ __volatile__("msr " #name ", %0" : : "i" (Value)); \
}
#define CORE_REGISTER_SET(name, width) \
static inline void coreSet_##name(width Value) \
{ \
uint64_t V = (uint64_t)Value; \
__asm__ __volatile__("msr " #name ", %0" : : "r" (V)); \
}
#define CORE_REGISTER_GET(name, width) \
static inline width coreGet_##name(void) \
{ \
uint64_t Value; \
__asm__ __volatile__("mrs %0, " #name : "=r" (Value) : ); \
return (width)Value; \
}
#define CORE_TYPE_CurrentEL uint32_t
CORE_REGISTER_GET(CurrentEL, uint32_t)
CORE_REGISTER_SET(CurrentEL, uint32_t)
#define CORE_TYPE_ELR_EL3 uint64_t
CORE_REGISTER_GET(ELR_EL3, uint64_t)
CORE_REGISTER_SET(ELR_EL3, uint64_t)
#define CORE_TYPE_ESR_EL3 uint32_t
CORE_REGISTER_GET(ESR_EL3, uint32_t)
CORE_REGISTER_SET(ESR_EL3, uint32_t)
#define CORE_TYPE_FAR_EL3 uint64_t
CORE_REGISTER_GET(FAR_EL3, uint64_t)
CORE_REGISTER_SET(FAR_EL3, uint64_t)
#define CORE_TYPE_MPIDR_EL1 uint64_t
CORE_REGISTER_GET(MPIDR_EL1, uint64_t)
CORE_REGISTER_SET(MPIDR_EL1, uint64_t)
#define CORE_TYPE_SPSEL uint32_t
CORE_REGISTER_GET(SPSEL, uint32_t)
CORE_REGISTER_SET(SPSEL, uint32_t)
#define CORE_TYPE_SPSR_EL3 uint32_t
CORE_REGISTER_GET(SPSR_EL3, uint32_t)
CORE_REGISTER_SET(SPSR_EL3, uint32_t)
#define CORE_TYPE_SP_EL3 uint64_t
CORE_REGISTER_GET(SP_EL3, uint64_t)
CORE_REGISTER_SET(SP_EL3, uint64_t)
#define CORE_TYPE_VBAR_EL3 uint64_t
CORE_REGISTER_GET(VBAR_EL3, uint64_t)
CORE_REGISTER_SET(VBAR_EL3, uint64_t)
#define coreInstructionSyncBarrier() __asm__ volatile("isb" : : : "memory")
#define coreDataMemoryBarrier() __asm__ volatile("dmb sy" : : : "memory")
#define coreDataSyncBarrier() __asm__ volatile("dsb sy" : : : "memory")
#endif