disassembler.cc

/*-
 * Copyright (c) 2015 David T. Chisnall
 *
 * All rights reserved.
 *
 * This software was developed by SRI International and the University of
 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
 * ("CTSRD"), as part of the DARPA CRASH research programme.
 *
 * This software was developed by SRI International and the University of
 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-11-C-0249
 * ("MRC2"), as part of the DARPA MRC research programme.
 *
 * @BERI_LICENSE_HEADER_START@
 *
 * Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor
 * license agreements.  See the NOTICE file distributed with this work for
 * additional information regarding copyright ownership.  BERI licenses this
 * file to you under the BERI Hardware-Software License, Version 1.0 (the
 * "License"); you may not use this file except in compliance with the
 * License.  You may obtain a copy of the License at:
 *
 *   http://www.beri-open-systems.org/legal/license-1-0.txt
 *
 * Unless required by applicable law or agreed to in writing, Work distributed
 * under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
 * CONDITIONS OF ANY KIND, either express or implied.  See the License for the
 * specific language governing permissions and limitations under the License.
 *
 * @BERI_LICENSE_HEADER_END@
 */

#include "cheri.hh"
#include "disassembler.hh"
#include "llvm/Support/MemoryBuffer.h"
#include "llvm/Support/TargetRegistry.h"
#include "llvm/Support/SMLoc.h"
#include "llvm/Object/ObjectFile.h"
#include "llvm/Support/Format.h"
#include "llvm/Support/TargetSelect.h"
#include "llvm/Support/SourceMgr.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstrAnalysis.h"
#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCObjectFileInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCTargetOptions.h"
#include "llvm/MC/MCAsmBackend.h"
#include "llvm/MC/MCCodeEmitter.h"
#include "llvm/MC/MCStreamer.h"
#include "llvm/MC/MCParser/MCAsmParser.h"
#include "llvm/MC/MCParser/MCTargetAsmParser.h"

#include <mutex>
#include <assert.h>

using namespace cheri::disassembler;

namespace llvm {
	extern const MCInstrDesc MipsInsts[];
}
using llvm::MipsInsts;

namespace {
int registerIndexForString(const char *str)
{
	if (str[0] == '$')
	{
		str++;
	}
	char *end;
	if (strcmp(str, "cnull") == 0)
	{
		// same as C0
		return 64;
	}
	if (strcmp(str, "ddc") == 0)
	{
		// special case, this is the same as chwr_ddc
		return 96;
	}
	if (str[0] == 'c' && str[1] != 'h')
	{
		// GP capability register, not a capability hardware register
		str++;
		long idx = strtol(str, &end, 10);
		if (str == end)
		{
			return -1;
		}
		return idx + 64;
	}
	if (str[0] == 'f' && str[1] != 'p')
	{
		// float register, not frame pointer
		str++;
		long idx = strtol(str, &end, 10);
		if (str == end)
		{
			return -1;
		}
		return idx + 32;
	}
	long idx = strtol(str, &end, 10);
	if (str != end)
	{
		return (int)idx;
	}
	for (size_t i=0 ; i<(sizeof(MipsRegisterNames) / sizeof(*MipsRegisterNames)) ; i++)
	{
		// other register name or hardware capability register
		if (strcmp(str, MipsRegisterNames[i]) == 0)
		{
			return (int)i;
		}
	}
	return -1;
}
} // Anonymous namespace

namespace cheri {
namespace disassembler{

static std::unique_ptr<const llvm::MCRegisterInfo> mri;
static std::unique_ptr<llvm::MCSubtargetInfo> sti;

struct disassembler_impl
{
	/**
	 * LLVM machine code context.
	 */
	std::unique_ptr<llvm::MCContext> mccontext;
	/**
	 * LLVM disassembler.
	 */
	std::unique_ptr<llvm::MCDisassembler> disAsm;
	/**
	 * LLVM instruction printer.
	 */
	std::unique_ptr<llvm::MCInstPrinter> instrPrinter;
	/**
	 * Map from LLVM's notion of registers to something stable.
	 */
	int registerIndexForLLVMRegNo(unsigned regNo);
	disassembler_impl();
};
}
} // cheri::disassembler

int disassembler_impl::registerIndexForLLVMRegNo(unsigned regNo)
{
	std::string regName;
	llvm::raw_string_ostream regStream(regName);
	instrPrinter->printRegName(regStream, regNo);
	int idx = registerIndexForString(regStream.str().c_str());
	return idx;
}

disassembler::disassembler()
{
	pimpl = new disassembler_impl();
}

disassembler::~disassembler()
{
	delete pimpl;
}
disassembler_impl::disassembler_impl()
{
	static std::once_flag flag;
	static const llvm::Target *target;
	static std::unique_ptr<const llvm::MCAsmInfo> asmInfo;
	static std::unique_ptr<const llvm::MCInstrInfo> mii;
	static std::unique_ptr<const llvm::MCInstrAnalysis> mia;
	static llvm::Triple targetTriple;
	static llvm::MCTargetOptions MCOptions;

	LLVMInitializeMipsTargetInfo();
	LLVMInitializeMipsTargetMC();
	LLVMInitializeMipsAsmParser();
	LLVMInitializeMipsDisassembler();

	std::call_once(flag, [this](){
		std::string cheriTriple("cheri-unknown-freebsd");
		std::string mipsTriple("mips64-unknown-freebsd");
		std::string triple = cheriTriple;
		std::string features("");
		const llvm::MCRegisterInfo *MRI = nullptr;

		std::string Error;

		target = llvm::TargetRegistry::lookupTarget(triple, Error);
		if (target)
		{
			MRI = target->createMCRegInfo(triple);
		}
		// First try to set up the target for CHERI, if it doesn't work then fall back to MIPS
		if (MRI == 0)
		{
			triple = mipsTriple;
			target = llvm::TargetRegistry::lookupTarget(triple, Error);
			if (target)
			{
				MRI = target->createMCRegInfo(triple);
			}
		}
		targetTriple = llvm::Triple(triple);
		assert(MRI != 0);
		mri.reset(MRI);
		assert(mri && "Failed to create MCRegisterInfo");
		asmInfo.reset(target->createMCAsmInfo(*mri, triple, MCOptions));
		assert(asmInfo && "Failed to create MCAsmInfo");
		sti.reset(target->createMCSubtargetInfo(triple, "", features));
		assert(sti && "Failed to create MCSubtargetInfo");
		mii.reset(target->createMCInstrInfo());
		assert(mii && "Failed to create MCInstrInfo");
		mia.reset(new llvm::MCInstrAnalysis(mii.get()));
		assert(mia && "Failed to create MCInstrAnalysis");
	});
	assert(mri);
	mccontext.reset(new llvm::MCContext(asmInfo.get(), mri.get(), nullptr));
	disAsm.reset(target->createMCDisassembler(*sti, *mccontext));
	assert(disAsm && "Failed to create MCDisassembler");
	instrPrinter.reset(target->createMCInstPrinter(targetTriple,
		asmInfo->getAssemblerDialect(), *asmInfo, *mii, *mri));
	assert(instrPrinter && "Failed to create MCInstPrinter");
}


instruction_info disassembler::disassemble(uint32_t anInstruction)
{
	assert(pimpl->mccontext->getAsmInfo());
	instruction_info info;
	uint8_t instbytes[4];
	std::memcpy(instbytes, &anInstruction, sizeof(anInstruction));
	static_assert(sizeof(anInstruction) == sizeof(instbytes),
			"Instruction size is wrong!");
	llvm::MCInst inst;
	uint64_t size;
	auto status = pimpl->disAsm->getInstruction(inst, size, instbytes, 0,
			llvm::errs());
	if (status != llvm::MCDisassembler::Success)
	{
		info.name = "<Unable to disassemble>";
		return info;
	}
	llvm::raw_string_ostream os(info.name);
	pimpl->instrPrinter->printInst(&inst, 0, "", *sti, os);
	os.str();
	auto &desc = MipsInsts[inst.getOpcode()];
	if (desc.isBranch() || desc.isCall() || desc.isReturn())
	{
		info.type = instruction_info::flow_control;
	}
	else if (desc.mayLoad() || desc.mayStore())
	{
		info.type = instruction_info::memory_access;
	}
	info.has_delay_slot = desc.hasDelaySlot();
	// The MIPS back end currently uses a pseudo for returns and so the
	// disassembled instruction is not identifiable as a return.
	info.is_return = (anInstruction == 0x03e00008) || desc.isReturn();
	info.is_call = desc.isCall();
	const uint16_t *implicitDefs = desc.getImplicitDefs();
	unsigned numImplicitDefs = desc.getNumImplicitDefs();
	for (unsigned i = 0; i < numImplicitDefs; i++)
	{
		int regNo = pimpl->registerIndexForLLVMRegNo(implicitDefs[i]);
		if (regNo >= 0)
		{
			info.destination_register = regNo;
			break;
		}
	}
	if ((info.destination_register == -1) && (inst.getNumOperands() > 0))
	{
		llvm::MCOperand op0 = inst.getOperand(0);
		if (op0.isReg())
		{
			if (desc.hasDefOfPhysReg(inst, op0.getReg(), *mri.get()))
			{
				int regNo = pimpl->registerIndexForLLVMRegNo(op0.getReg());
				if (regNo >= 0)
					info.destination_register = regNo;
			}
			// else if (info.name.find("cwritehwr") != std::string::npos) {
			// 	/*
			// 	 * XXX-AM: Handle this case specially because cwritehwr
			// 	 * in LLVM does not have a valid output register description.
			// 	 */
			// 	int regNo = pimpl->registerIndexForLLVMRegNo(inst.getOperand(1).getReg());
			// 	if (regNo >= 0)
			// 		info.destination_register = regNo;
			// }
		}
	}
	if ((info.destination_register == -1) && desc.mayStore())
	{
		int regNo = pimpl->registerIndexForLLVMRegNo(inst.getOperand(0).getReg());
		if (regNo >= 0)
			info.destination_register = regNo;
	}

	/* Extract operands of the instruction */
	for (unsigned i=0; i<inst.getNumOperands(); i++)
	{
		operand_info op_info;
		llvm::MCOperand op = inst.getOperand(i);
		op_info.is_valid = op.isValid();
		op_info.is_register = op.isReg();
		op_info.is_immediate = op.isImm();
		op_info.is_fp_immediate = op.isFPImm();
		op_info.is_expr = op.isExpr();
		op_info.is_inst = op.isInst();
		if (op.isReg())
		{
			op_info.register_number = pimpl->registerIndexForLLVMRegNo(op.getReg());
		}
		else if (op.isImm())
		{
			op_info.immediate = op.getImm();
		}
		else if (op.isFPImm())
		{
			op_info.fp_immediate = op.getFPImm();
		}
		info.operands.push_back(op_info);
	}
	return info;
}

namespace cheri {
namespace disassembler{

  using namespace llvm;

struct assembler_impl
{
	const std::string cheriTriple;
	const llvm::Triple targetTriple;
	const llvm::Target *target;
	std::unique_ptr<llvm::MCRegisterInfo> MRI;
	std::unique_ptr<llvm::MCAsmInfo> MAI;
	std::unique_ptr<llvm::MCInstrInfo> MCII;
	std::unique_ptr<llvm::MCSubtargetInfo> STI;
	llvm::MCObjectFileInfo MOFI;
	llvm::MCTargetOptions MCOptions;
	assembler_impl();
};

class MCInstEncodingStreamer final : public llvm::MCStreamer
{
	llvm::raw_ostream &OS;
	std::unique_ptr<llvm::MCCodeEmitter> Emitter;
public:
	MCInstEncodingStreamer(llvm::MCContext &Context, llvm::raw_ostream &os, llvm::MCCodeEmitter *emitter)
		: MCStreamer(Context), OS(os), Emitter(emitter)
	{
		assert(Emitter);
	}

	void emitInstruction(const llvm::MCInst &Inst, const llvm::MCSubtargetInfo &STI) override;
	void emitZerofill(llvm::MCSection *Section, llvm::MCSymbol *Symbol,
			  uint64_t Size, unsigned ByteAlignment, llvm::TailPaddingAmount TailPadding,
			  llvm::SMLoc Loc = llvm::SMLoc()) override;
	bool emitSymbolAttribute(llvm::MCSymbol *Symbol, llvm::MCSymbolAttr Attribute) override;
	void emitCommonSymbol(llvm::MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment,
			      llvm::TailPaddingAmount TailPadding) override;
};
}
}

void MCInstEncodingStreamer::emitZerofill(llvm::MCSection *Section, llvm::MCSymbol *Symbol, uint64_t Size,
    unsigned ByteAlignment, llvm::TailPaddingAmount TailPadding, llvm::SMLoc Loc)
{
	assert(false && "Not implemented");
}

bool MCInstEncodingStreamer::emitSymbolAttribute(llvm::MCSymbol *Symbol, llvm::MCSymbolAttr Attribute)
{
	assert(false && "Not implemented");
	return false;
}
void MCInstEncodingStreamer::emitCommonSymbol(llvm::MCSymbol *Symbol, uint64_t Size, unsigned ByteAlignment,
    llvm::TailPaddingAmount TailPadding)
{
	assert(false && "Not implemented");
}

void MCInstEncodingStreamer::emitInstruction(const llvm::MCInst &Inst, const llvm::MCSubtargetInfo &STI)
{
	llvm::SmallVector<llvm::MCFixup, 4> Fixups;
	Emitter->encodeInstruction(Inst, OS, Fixups, STI);
	assert(Fixups.size() == 0 && "Instruction requires fixups");
}

assembler::assembler()
{
	pimpl.reset(new assembler_impl);
}

assembler::~assembler() = default;

assembler_impl::assembler_impl()
	: cheriTriple("cheri-unknown-freebsd"), targetTriple(llvm::Triple(cheriTriple))
{
	std::string MCPU("");
	std::string FeatureStr("");
	LLVMInitializeMipsTargetInfo();
	LLVMInitializeMipsTargetMC();
	LLVMInitializeMipsAsmParser();
	LLVMInitializeMipsDisassembler();
	/* require the cheri target */
	std::string Error;
	target = llvm::TargetRegistry::lookupTarget(cheriTriple, Error);
	assert(target);
	/* make machine register info mri */
	MRI.reset(target->createMCRegInfo(cheriTriple));
	assert(MRI && "Unable to create target register info");
	/* make asm info asmInfo */
	MAI.reset(target->createMCAsmInfo(*MRI, cheriTriple, MCOptions));
	assert(MAI && "Failed to create MCAsmInfo");
	/* create mc instr info mcii */
	MCII.reset(target->createMCInstrInfo());
	assert(MCII && "Failed to create MCInstrInfo");
	/* create mc subtarget info sti */
	STI.reset(target->createMCSubtargetInfo(cheriTriple, MCPU, FeatureStr));
	assert(STI && "Failed to create MCSubtargetInfo");
}

uint32_t assembler::assemble(const std::string &asmexpr)
{
	auto& MRI = pimpl->MRI;
	auto& MAI = pimpl->MAI;
	auto& MOFI = pimpl->MOFI;
	auto& MCII = pimpl->MCII;
	auto& STI = pimpl->STI;
	auto& MCOptions = pimpl->MCOptions;
	auto& targetTriple = pimpl->targetTriple;
	auto target = pimpl->target;
	llvm::ErrorOr<std::unique_ptr<llvm::MemoryBuffer>> BufferPtr =
		llvm::MemoryBuffer::getMemBuffer(asmexpr);
	assert(!BufferPtr.getError() && "Can not create input buffer");

	llvm::SourceMgr SrcMgr;
	SrcMgr.AddNewSourceBuffer(std::move(*BufferPtr), llvm::SMLoc());

	/* make context */
	llvm::MCContext Ctx(MAI.get(), MRI.get(), &MOFI, &SrcMgr);
	assert(Ctx.getRegisterInfo() && "Register info is NULL");
	MOFI.InitMCObjectFileInfo(targetTriple, /*PIC*/ false, Ctx);

	llvm::SmallString<256> instrBuffer;
	llvm::raw_svector_ostream OS(instrBuffer);
	llvm::MCCodeEmitter *CE = target->createMCCodeEmitter(*MCII, *MRI, Ctx);

	std::unique_ptr<MCInstEncodingStreamer> Str(new MCInstEncodingStreamer(Ctx, OS, CE));
	/* ownership of the target streamer is taken by the MCInstEncodingStreamer */
	target->createNullTargetStreamer(*Str);

	std::unique_ptr<llvm::MCAsmParser> Parser(llvm::createMCAsmParser(SrcMgr, Ctx, *Str, *MAI));
	std::unique_ptr<llvm::MCTargetAsmParser> TAP(target->createMCAsmParser(*STI, *Parser, *MCII, MCOptions));
	assert(TAP && "Failed to create MCTargetAsmParser");
	Parser->setTargetParser(*TAP);

	int Res = Parser->Run(/*NoInitialTextSection*/ false);
	assert(Res == 0 && "Failed to run MCAsmParser");
	uint32_t opcode;
	memcpy((void *)&opcode, instrBuffer.data(), sizeof(opcode));
	return opcode;
}