diff --git a/Binary2BCD.v b/Binary2BCD.v index 5227a09..9ae7e63 100644 --- a/Binary2BCD.v +++ b/Binary2BCD.v @@ -1,26 +1,80 @@ -module CondAdd3(input[3:0]in,output[3:0]out); - - assign out = in >= 5 ? in + 3 : in; +module CondAdd3(in, out); + input [3:0] in; + output [3:0] out; + assign out = in >= 5 ? in + 3:in; endmodule - - -module Binary2BCD(in , out); +module Binary2BCD(in, out); input [7:0] in; output [11:0] out; - wire [28 : 1] temp; + wire [28:1] temp; + + CondAdd3 c1({0,in[7:5]}, temp[4:1]); + CondAdd3 c2({temp[3:1], in[4]}, temp[8:5]); + CondAdd3 c3({temp[7:5], in[3]}, temp[12:9]); + CondAdd3 c4({temp[11:9], in[2]}, temp[16:13]); + CondAdd3 c5({temp[15:13], in[1]}, temp[20:17]); + CondAdd3 c6({0, temp[4], temp[8], temp[12]}, temp[24:21]); + CondAdd3 c7({temp[23:21], temp[16]}, temp[28:25]); + + assign out = {0, 0, temp[24], temp[28:25], temp[20:17], in[0]}; +endmodule - CondAdd3 c1( {0,in[7:5]}, temp[4 : 1] ); - CondAdd3 c2( {temp[3:1] , in[4]}, temp[8 : 5] ); - CondAdd3 c3( {temp[7:5] , in[3]}, temp[12 : 9] ); - CondAdd3 c4( {temp[11:9] , in[2]}, temp[16 : 13] ); - CondAdd3 c5( {temp[15:13] , in[1]}, temp[20 : 17] ); - CondAdd3 c6( {0 , temp[4] , temp[8] , temp[12] }, temp[24 : 21] ); - CondAdd3 c7( {temp[23:21] , temp[16] }, temp[28 : 25] ); +module Binary2BCD_DUT(); + reg [7:0] in; + wire [11:0] out; - assign out = { 0 , 0 , temp[24] , temp[28:25] , temp[20:17] , in[0]}; + Binary2BCD b2b(in, out); + initial begin + in = 1; + #10; + in = 112; + #10; + in = 251; + #10; + in = 0; + #10; + in = 156; + #10; + in = 045; + #10; + in = 255; + #10; + in = 100; + #10; + in = 124; + #10; + in = 235; + #10; + in = 050; + end + initial begin + $display("Binary2BCD_DUT"); + $display("=================================="); + $monitor("Expected: 000000000001, Actual: %h\n",out); + #10; + $monitor("Expected: 000000011100, Actual: %h\n",out); + #10; + $monitor("Expected: 000010010011, Actual: %h\n",out); + #10; + $monitor("Expected: 000000000000, Actual: %h\n",out); + #10; + $monitor("Expected: 000000010110, Actual: %h\n",out); + #10; + $monitor("Expected: 000000010101, Actual: %h\n",out); + #10; + $monitor("Expected: 000000111111, Actual: %h\n",out); + #10; + $monitor("Expected: 000000011001, Actual: %h\n",out); + #10; + $monitor("Expected: 000000011100, Actual: %h\n",out); + #10; + $monitor("Expected: 000000111011, Actual: %h\n",out); + #10; + $monitor("Expected: 000000010010, Actual: %h\n",out); + end endmodule \ No newline at end of file diff --git a/Binary2BCD_tb.v b/Binary2BCD_tb.v deleted file mode 100644 index 82e5a28..0000000 --- a/Binary2BCD_tb.v +++ /dev/null @@ -1,48 +0,0 @@ -module Binary2BCD_tb(); - - reg [7:0] in; - wire [11:0] out; - - Binary2BCD Binary2BCD_dut( - .in(in), - .out(out) -); - - - - initial begin - in = 1; - # 50; - in = 112; - # 50; - in = 251; - # 50; - in = 0; - # 50; - in = 156; - # 50; - in = 045; - # 50; - in = 255; - # 50; - in = 100; - # 50; - in = 124; - # 50; - in = 235; - # 50; - in = 050; - - - - end - - always @ (in) begin - $display("\nin = %d", in); - - $display("\nout = %b", out); - - - end - -endmodule \ No newline at end of file diff --git a/DisplayDecoder.v b/DisplayDecoder.v index 504cfbb..757eaa8 100644 --- a/DisplayDecoder.v +++ b/DisplayDecoder.v @@ -1,6 +1,10 @@ -module DisplayDecoder(in,display7); - input [3:0]in; - output [6:0]display7; +module DisplayDecoder(in, out); + input [3:0] in; + output [6:0] out; + + reg [6:0] display7; + + assign out = display7; always @(in) case(in) @@ -16,5 +20,4 @@ module DisplayDecoder(in,display7); 9 : display7 = 7'b0000100; default : display7 = 7'b1111111; endcase - endmodule diff --git a/InvMixColumns.v b/InvMixColumns.v index 6d524be..56ec0d5 100644 --- a/InvMixColumns.v +++ b/InvMixColumns.v @@ -1,9 +1,9 @@ -module InvMixColumns (stateIn,stateOut); - input[127:0] stateIn; - output[127:0] stateOut; +module InvMixColumns(stateIn, stateOut); + input [127:0] stateIn; + output [127:0] stateOut; - //mul2 function that multiply x by 2^n and fixes the overflow - function [7:0] mul2(input [7:0]in,input integer n); + // Function to multiply by 2 and fix the overflow + function [7:0] mul2(input [7:0] in, input integer n); integer i; begin for(i = 0; i < n; i = i + 1)begin @@ -14,28 +14,28 @@ module InvMixColumns (stateIn,stateOut); end endfunction - function [7:0] mb0e; //Multiply by 0e + function [7:0] mb0e; // Multiply by 0e input [7:0] x; begin mb0e = mul2(x,3) ^ mul2(x,2)^ mul2(x,1); end endfunction - function [7:0] mb0d; //Multiply by 0d + function [7:0] mb0d; // Multiply by 0d input [7:0] x; begin mb0d = mul2(x,3) ^ mul2(x,2) ^ x; end endfunction - function [7:0] mb0b; //Multiply by 0b + function [7:0] mb0b; // Multiply by 0b input [7:0] x; begin mb0b = mul2(x,3) ^ mul2(x,1) ^ x; end endfunction - function [7:0] mb09; //Multiply by 09 + function [7:0] mb09; // Multiply by 09 input [7:0] x; begin mb09 = mul2(x,3) ^ x; @@ -44,7 +44,7 @@ module InvMixColumns (stateIn,stateOut); genvar i; generate - for(i = 0; i < 4; i = i + 1)begin: InvMixColumnsLoop + for(i = 0; i < 4; i = i + 1) begin: InvMixColumnsLoop //state[0,c] = 0e*state[0,c] + 0b*state[1,c] + 0d*state[2,c] + 09*state[3,c] assign stateOut[32*i+24+:8] = mb0e(stateIn[32*i+24+:8]) ^ mb0b(stateIn[32*i+16+:8]) ^ mb0d(stateIn[32*i+8 +:8]) ^ mb09(stateIn[32*i +:8]); @@ -58,6 +58,29 @@ module InvMixColumns (stateIn,stateOut); assign stateOut[32*i +:8] = mb0e(stateIn[32*i +:8]) ^ mb0b(stateIn[32*i+24+:8]) ^ mb0d(stateIn[32*i+16+:8]) ^ mb09(stateIn[32*i+8 +:8]); end endgenerate +endmodule +module InvMixColumns_DUT(); + reg [127:0] stateIn; + wire [127:0] stateOut; -endmodule + InvMixColumns imc(stateIn, stateOut); + + initial begin + stateIn = 128'hbd6e7c3df2b5779e0b61216e8b10b689; + #10 + stateIn = 128'hfde3bad205e5d0d73547964ef1fe37f1; + #10 + stateIn = 128'hd1876c0f79c4300ab45594add66ff41f; + end + + initial begin + $display("InvMixColumns_DUT"); + $display("=================================="); + $monitor("Expected: 4773b91ff72f354361cb018ea1e6cf2c, Actual: %h\n", stateOut); + #10 + $monitor("Expected: 2d7e86a339d9393ee6570a1101904e16, Actual: %h\n", stateOut); + #10 + $monitor("Expected: 39daee38f4f1a82aaf432410c36d45b9, Actual: %h\n", stateOut); + end +endmodule \ No newline at end of file diff --git a/InvMixColumns_tb.v b/InvMixColumns_tb.v deleted file mode 100644 index 3c7d532..0000000 --- a/InvMixColumns_tb.v +++ /dev/null @@ -1,21 +0,0 @@ -module InvMixColumns_tb(); - - reg [127:0] stateIn; - wire [127:0] stateOut; - - InvMixColumns mix(stateIn,stateOut); - - initial begin - stateIn = 128'hbd6e7c3df2b5779e0b61216e8b10b689; - $monitor("expected: 4773b91ff72f354361cb018ea1e6cf2c actual: %h\n",stateOut); - #2 - stateIn = 128'hfde3bad205e5d0d73547964ef1fe37f1; - $monitor("expected: 2d7e86a339d9393ee6570a1101904e16 actual: %h\n",stateOut); - #2 - stateIn = 128'hd1876c0f79c4300ab45594add66ff41f; - $monitor("expected: 39daee38f4f1a82aaf432410c36d45b9 actual: %h\n",stateOut); - - - end - -endmodule \ No newline at end of file diff --git a/InvShiftRows .v b/InvShiftRows .v deleted file mode 100644 index 899d24a..0000000 --- a/InvShiftRows .v +++ /dev/null @@ -1,53 +0,0 @@ -module InvShiftRows( in , out ); -input [127 : 0 ] in; -output [127 : 0 ] out ; -// S(0,0) in[127:120] -// S(0,1) in[95:88] -// S(0,2) in[63:56] -// S(0,3) in[31:24] -//-------------------- -// S(1,0) in[119:112] -// S(1,1) in[87:80] -// S(1,2) in[55:48] -// S(1,3) in[23:16] -//-------------------- -// S(2,0) in[111:104] -// S(2,1) in[79:72] -// S(2,2) in[47:40] -// S(2,3) in[15:8] -//-------------------- -// S(3,0) in[103:96] -// S(3,1) in[71:64] -// S(3,2) in[39:32] -// S(3,3) in[7:0] -//-------------------- - - - -//1st row no shift -assign out[127:120] = in[127:120]; -assign out[95:88] = in[95:88]; -assign out[63:56] = in[63:56]; -assign out[31:24] = in[31:24]; -//2nd row shift 1 -assign out[119:112] = in[23:16]; -assign out[87:80] = in[119:112]; -assign out[55:48] = in[87:80]; -assign out[23:16] = in[55:48]; -//3rd row shift 2 -assign out[111:104] = in[47:40]; -assign out[79:72] = in[15:8]; -assign out[47:40] = in[111:104]; -assign out[15:8] = in[79:72]; -//4th row shift 3 -assign out[103:96] = in[71:64]; -assign out[71:64] = in[39:32]; -assign out[39:32] = in[7:0]; -assign out[7:0] = in[103:96]; - - - - - - -endmodule \ No newline at end of file diff --git a/InvShiftRows.v b/InvShiftRows.v new file mode 100644 index 0000000..1965599 --- /dev/null +++ b/InvShiftRows.v @@ -0,0 +1,69 @@ +module InvShiftRows(in, out); + input [127:0] in; + output [127:0] out; + + //-------------------- + // S(0,0) in[127:120] + // S(0,1) in[95:88] + // S(0,2) in[63:56] + // S(0,3) in[31:24] + //-------------------- + // S(1,0) in[119:112] + // S(1,1) in[87:80] + // S(1,2) in[55:48] + // S(1,3) in[23:16] + //-------------------- + // S(2,0) in[111:104] + // S(2,1) in[79:72] + // S(2,2) in[47:40] + // S(2,3) in[15:8] + //-------------------- + // S(3,0) in[103:96] + // S(3,1) in[71:64] + // S(3,2) in[39:32] + // S(3,3) in[7:0] + //-------------------- + + // 1st row no shift + assign out[127:120] = in[127:120]; + assign out[95:88] = in[95:88]; + assign out[63:56] = in[63:56]; + assign out[31:24] = in[31:24]; + + // 2nd row shift 1 + assign out[119:112] = in[23:16]; + assign out[87:80] = in[119:112]; + assign out[55:48] = in[87:80]; + assign out[23:16] = in[55:48]; + + // 3rd row shift 2 + assign out[111:104] = in[47:40]; + assign out[79:72] = in[15:8]; + assign out[47:40] = in[111:104]; + assign out[15:8] = in[79:72]; + + // 4th row shift 3 + assign out[103:96] = in[71:64]; + assign out[71:64] = in[39:32]; + assign out[39:32] = in[7:0]; + assign out[7:0] = in[103:96]; +endmodule + +module InvShiftRows_DUT(); + reg [127:0] in; + wire [127:0] out; + + InvShiftRows isr(in, out); + + initial begin + in = 128'h_aa5ece06ee6e3c56dde68bac2621bebf; + #10; + in = 128'h_d1ed44fd1a0f3f2afa4ff27b7c332a69; + end + + initial begin + $display("InvShiftRows_DUT"); + $display("=================================="); + $monitor("in = %h, out = %h", in, out); + end +endmodule \ No newline at end of file diff --git a/InvShiftRows_tb.v b/InvShiftRows_tb.v deleted file mode 100644 index d89a327..0000000 --- a/InvShiftRows_tb.v +++ /dev/null @@ -1,24 +0,0 @@ -module InvShiftRows_tb(); - reg [127 : 0 ] in; - wire [127 : 0 ] out ; - -initial begin -in = 128'h_aa5ece06ee6e3c56dde68bac2621bebf; -# 50; -in = 128'h_d1ed44fd1a0f3f2afa4ff27b7c332a69; -end - - - -InvShiftRows InvShiftRows_dut( - .in(in), - .out(out) -); - -always @ (in) begin - $display("in = %h", in); - $display("out = %h", out); - -end - -endmodule \ No newline at end of file diff --git a/SBox.v b/SBox.v index 6931047..1494319 100644 --- a/SBox.v +++ b/SBox.v @@ -1,5 +1,5 @@ module SBox(in, out); - input [7:0] in; + input [7:0] in; output [7:0] out; reg [7:0] tmp; diff --git a/ShiftRows.v b/ShiftRows.v index 31433b7..2b86ba5 100644 --- a/ShiftRows.v +++ b/ShiftRows.v @@ -1,53 +1,69 @@ -module ShiftRows( in , out ); -input [127 : 0 ] in; -output [127 : 0 ] out ; -// S(0,0) in[127:120] -// S(0,1) in[95:88] -// S(0,2) in[63:56] -// S(0,3) in[31:24] -//-------------------- -// S(1,0) in[119:112] -// S(1,1) in[87:80] -// S(1,2) in[55:48] -// S(1,3) in[23:16] -//-------------------- -// S(2,0) in[111:104] -// S(2,1) in[79:72] -// S(2,2) in[47:40] -// S(2,3) in[15:8] -//-------------------- -// S(3,0) in[103:96] -// S(3,1) in[71:64] -// S(3,2) in[39:32] -// S(3,3) in[7:0] -//-------------------- - - - -//1st row no shift -assign out[127:120] = in[127:120]; -assign out[95:88] = in[95:88]; -assign out[63:56] = in[63:56]; -assign out[31:24] = in[31:24]; -//2nd row shift 1 -assign out[119:112] = in[87:80]; -assign out[87:80] = in[55:48]; -assign out[55:48] = in[23:16]; -assign out[23:16] = in[119:112]; -//3rd row shift 2 -assign out[111:104] = in[47:40]; -assign out[79:72] = in[15:8]; -assign out[47:40] = in[111:104]; -assign out[15:8] = in[79:72]; -//4th row shift 3 -assign out[103:96] = in[7:0]; -assign out[71:64] = in[103:96]; -assign out[39:32] = in[71:64]; -assign out[7:0] = in[39:32]; +module ShiftRows(in, out); + input [127:0] in; + output [127:0] out; + //-------------------- + // S(0,0) in[127:120] + // S(0,1) in[95:88] + // S(0,2) in[63:56] + // S(0,3) in[31:24] + //-------------------- + // S(1,0) in[119:112] + // S(1,1) in[87:80] + // S(1,2) in[55:48] + // S(1,3) in[23:16] + //-------------------- + // S(2,0) in[111:104] + // S(2,1) in[79:72] + // S(2,2) in[47:40] + // S(2,3) in[15:8] + //-------------------- + // S(3,0) in[103:96] + // S(3,1) in[71:64] + // S(3,2) in[39:32] + // S(3,3) in[7:0] + //-------------------- + // 1st row no shift + assign out[127:120] = in[127:120]; + assign out[95:88] = in[95:88]; + assign out[63:56] = in[63:56]; + assign out[31:24] = in[31:24]; + // 2nd row shift 1 + assign out[119:112] = in[87:80]; + assign out[87:80] = in[55:48]; + assign out[55:48] = in[23:16]; + assign out[23:16] = in[119:112]; + // 3rd row shift 2 + assign out[111:104] = in[47:40]; + assign out[79:72] = in[15:8]; + assign out[47:40] = in[111:104]; + assign out[15:8] = in[79:72]; + // 4th row shift 3 + assign out[103:96] = in[7:0]; + assign out[71:64] = in[103:96]; + assign out[39:32] = in[71:64]; + assign out[7:0] = in[39:32]; +endmodule +module ShiftRows_DUT(); + reg [127:0] in; + wire [127:0] out; + + initial begin + in = 128'h_adcb0f257e9c63e0bc557e951c15ef01; + #10; + in = 128'h_884a33781fdb75c2d380349e19f876fb; + end + + ShiftRows sr(in, out); + + initial begin + $display("ShiftRows_DUT"); + $display("=================================="); + $monitor("In = %h, Out = %h", in, out); + end endmodule \ No newline at end of file diff --git a/ShiftRows_tb.v b/ShiftRows_tb.v deleted file mode 100644 index 5f18234..0000000 --- a/ShiftRows_tb.v +++ /dev/null @@ -1,24 +0,0 @@ -module ShiftRows_tb(); - reg [127 : 0 ] in; - wire [127 : 0 ] out ; - -initial begin -in = 128'h_adcb0f257e9c63e0bc557e951c15ef01; -# 50; -in = 128'h_884a33781fdb75c2d380349e19f876fb; -end - - - -ShiftRows ShiftRows_dut( - .in(in), - .out(out) -); - -always @ (in) begin - $display("in = %h", in); - $display("out = %h", out); - -end - -endmodule \ No newline at end of file diff --git a/mixColumns.v b/mixColumns.v index c539c86..a228cf7 100644 --- a/mixColumns.v +++ b/mixColumns.v @@ -1,33 +1,54 @@ -module MixColumns (stateIn,stateOut); - input[127:0] stateIn; - output[127:0] stateOut; +module MixColumns(stateIn, stateOut); + input [127:0] stateIn; + output [127:0] stateOut; - - - //xtime function that multiply x by 2 and fixes the overflow + // Function to multiply by 2 and fix the overflow function [7:0] xtime; - input [7:0]in; + input [7:0] in; if(in[7] == 1) xtime = (in << 1) ^ 8'h1B; else xtime = in << 1; endfunction - + genvar i; generate for(i = 0; i < 4; i = i + 1)begin: mixColumnsLoop - //state[0,c] = 2*state[0,c] + (2 * state[1,c] + state[1,c]) + state[2,c] + state[3,c] + // state[0,c] = 2*state[0,c] + (2 * state[1,c] + state[1,c]) + state[2,c] + state[3,c] assign stateOut[32*i+24+:8] = xtime(stateIn[32*i+24+:8]) ^ (xtime(stateIn[32*i+16+:8]) ^ stateIn[32*i+16+:8]) ^ stateIn[32*i+8 +:8] ^ stateIn[32*i +:8]; - //state[1,c] = 2*state[1,c] + (2 * state[2,c] + state[2,c]) + state[3,c] + state[0,c] + // state[1,c] = 2*state[1,c] + (2 * state[2,c] + state[2,c]) + state[3,c] + state[0,c] assign stateOut[32*i+16+:8] = xtime(stateIn[32*i+16+:8]) ^ (xtime(stateIn[32*i+8 +:8]) ^ stateIn[32*i+8 +:8]) ^ stateIn[32*i +:8] ^ stateIn[32*i+24+:8]; - //state[2,c] = 2*state[2,c] + (2 * state[3,c] + state[3,c]) + state[0,c] + state[1,c] + // state[2,c] = 2*state[2,c] + (2 * state[3,c] + state[3,c]) + state[0,c] + state[1,c] assign stateOut[32*i+8 +:8] = xtime(stateIn[32*i+8 +:8]) ^ (xtime(stateIn[32*i +:8]) ^ stateIn[32*i +:8]) ^ stateIn[32*i+24+:8] ^ stateIn[32*i+16+:8]; - //state[3,c] = 2*state[3,c] + (2 * state[0,c] + state[0,c]) + state[1,c] + state[2,c] + // state[3,c] = 2*state[3,c] + (2 * state[0,c] + state[0,c]) + state[1,c] + state[2,c] assign stateOut[32*i +:8] = xtime(stateIn[32*i +:8]) ^ (xtime(stateIn[32*i+24+:8]) ^ stateIn[32*i+24+:8]) ^ stateIn[32*i+16+:8] ^ stateIn[32*i+8 +:8]; end endgenerate +endmodule +module MixColumns_DUT(); + reg [127:0] stateIn; + wire [127:0] stateOut; -endmodule + MixColumns mc(stateIn, stateOut); + + initial begin + stateIn = 128'h6353e08c0960e104cd70b751bacad0e7; + #10 + stateIn = 128'h84e1dd691a41d76f792d389783fbac70; + #10 + stateIn = 128'h1fb5430ef0accf64aa370cde3d77792c; + end + + initial begin + $display("MixColumns_DUT"); + $display("=================================="); + $monitor("Expected: 5f72641557f5bc92f7be3b291db9f91a, Actual: %h\n",stateOut); + #10 + $monitor("Expected: 9f487f794f955f662afc86abd7f1ab29, Actual: %h\n",stateOut); + #10 + $monitor("Expected: b7a53ecbbf9d75a0c40efc79b674cc11, Actual: %h\n",stateOut); + end +endmodule \ No newline at end of file diff --git a/mixColumns_tb.v b/mixColumns_tb.v deleted file mode 100644 index 1c122ad..0000000 --- a/mixColumns_tb.v +++ /dev/null @@ -1,21 +0,0 @@ -module MixColumns_tb(); - - reg [127:0] stateIn; - wire [127:0] stateOut; - - MixColumns mix(stateIn,stateOut); - - initial begin - stateIn = 128'h6353e08c0960e104cd70b751bacad0e7; - $monitor("expected: 5f72641557f5bc92f7be3b291db9f91a actual: %h\n",stateOut); - #2 - stateIn = 128'h84e1dd691a41d76f792d389783fbac70; - $monitor("expected: 9f487f794f955f662afc86abd7f1ab29 actual: %h\n",stateOut); - #2 - stateIn = 128'h1fb5430ef0accf64aa370cde3d77792c; - $monitor("expected: b7a53ecbbf9d75a0c40efc79b674cc11 actual: %h\n",stateOut); - - - end - -endmodule \ No newline at end of file