From 267fdfcdb89689038b31e05497208db8390a8bcd Mon Sep 17 00:00:00 2001 From: Ahmed Sobhy Date: Tue, 23 Jul 2024 00:06:46 +0300 Subject: [PATCH] :zap: Updated readme & added license (#16) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Update README.md * Create LICENSE * Update README.md * 💫 Name spelling preferences --------- Co-authored-by: Anas Ibrahem <139391509+anas-ibrahem@users.noreply.github.com> --- LICENSE | 21 +++++++++++ README.md | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 125 insertions(+) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..9675b9b --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2024 Ahmed Sobhy + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md index e69de29..ab62c4f 100644 --- a/README.md +++ b/README.md @@ -0,0 +1,104 @@ +#

AES Encryption using Verilog on FPGA

+ +https://github.com/user-attachments/assets/89a8f95d-6bfe-42bc-836b-53730abd24ab + +## 📝 Project Description + +This project implements the Advanced Encryption Standard (AES) encryption algorithm using Verilog. The design is targeted for the Altera DE1-SoC FPGA board. This project was undertaken as part of the Logic Design course during the first year of our Computer Engineering program. + +The AES algorithm is widely used for securing data and is known for its efficiency and security. In this project, we have implemented the 128-bit, 192-bit, and 256-bit versions of AES. The design includes key expansion, the encryption process, and the decryption process. + +## ✨ Features + +- **AES-128, AES-192, and AES-256 Encryption and Decryption**: Implements the core AES algorithm for 128-bit, 192-bit, and 256-bit keys. +- **Key Expansion**: Dynamically generates the required round keys from the initial key. +- **Hardware Implementation**: Optimized for running on the Altera DE1-SoC FPGA board. + +## 🚀 Getting Started + +### Prerequisites + +- Altera DE1-SoC FPGA board +- Quartus Prime software +- ModelSim for simulation + +### Installation + +1. **Clone the repository** + + ```bash + git clone https://github.com/AhmedSobhy01/AES-Verilog.git + cd AES-Verilog + ``` + +2. **Open Quartus Prime** + + - Open Quartus Prime and create a new project. + - Add all the Verilog files from the repository to the project. + +3. **Compile the Project** + + - Compile the project in Quartus Prime. + - Ensure there are no errors in the compilation. + +4. **Program the FPGA** + - Connect the DE1-SoC board to your computer. + - Use the Quartus Prime Programmer to upload the compiled design to the FPGA. + +### Running the Simulation + +1. **Open ModelSim** + + - Load the project files into ModelSim. + +2. **Run the Simulation** + - Perform functional and timing simulations to verify the design. + - Use the provided testbenches to simulate AES encryption and decryption. + +## 📁 Project Structure + +Root directory contains all Verilog modules, each module file includes a module for the testbench with the convention {moduleName}\_DUT. + +## 🛠️ Usage + +- **Encrypting Data:** Input your plaintext and key to the FPGA design to receive the encrypted ciphertext. +- **Decrypting Data:** Input the ciphertext and the key to the FPGA design to retrieve the original plaintext. + +## 👥 Collaborators + + + + + + + + +
+ + +
+ Ahmed Amr + + 		+ + +
+ Ahmed Sobhy + + 		+ + +
+ Ahmed Waleed + + 		+ + +
+ Anas Ibrahem + +
+ +## 📜 License + +This project is licensed under the MIT License - see [License](LICENSE) for more information.