diff --git a/LICENSE b/LICENSE
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+MIT License
+
+Copyright (c) 2024 Ahmed Sobhy
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/README.md b/README.md
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+# AES Encryption using Verilog on FPGA
+
+https://github.com/user-attachments/assets/89a8f95d-6bfe-42bc-836b-53730abd24ab
+
+## 📝 Project Description
+
+This project implements the Advanced Encryption Standard (AES) encryption algorithm using Verilog. The design is targeted for the Altera DE1-SoC FPGA board. This project was undertaken as part of the Logic Design course during the first year of our Computer Engineering program.
+
+The AES algorithm is widely used for securing data and is known for its efficiency and security. In this project, we have implemented the 128-bit, 192-bit, and 256-bit versions of AES. The design includes key expansion, the encryption process, and the decryption process.
+
+## ✨ Features
+
+- **AES-128, AES-192, and AES-256 Encryption and Decryption**: Implements the core AES algorithm for 128-bit, 192-bit, and 256-bit keys.
+- **Key Expansion**: Dynamically generates the required round keys from the initial key.
+- **Hardware Implementation**: Optimized for running on the Altera DE1-SoC FPGA board.
+
+## 🚀 Getting Started
+
+### Prerequisites
+
+- Altera DE1-SoC FPGA board
+- Quartus Prime software
+- ModelSim for simulation
+
+### Installation
+
+1. **Clone the repository**
+
+ ```bash
+ git clone https://github.com/AhmedSobhy01/AES-Verilog.git
+ cd AES-Verilog
+ ```
+
+2. **Open Quartus Prime**
+
+ - Open Quartus Prime and create a new project.
+ - Add all the Verilog files from the repository to the project.
+
+3. **Compile the Project**
+
+ - Compile the project in Quartus Prime.
+ - Ensure there are no errors in the compilation.
+
+4. **Program the FPGA**
+ - Connect the DE1-SoC board to your computer.
+ - Use the Quartus Prime Programmer to upload the compiled design to the FPGA.
+
+### Running the Simulation
+
+1. **Open ModelSim**
+
+ - Load the project files into ModelSim.
+
+2. **Run the Simulation**
+ - Perform functional and timing simulations to verify the design.
+ - Use the provided testbenches to simulate AES encryption and decryption.
+
+## 📁 Project Structure
+
+Root directory contains all Verilog modules, each module file includes a module for the testbench with the convention {moduleName}\_DUT.
+
+## 🛠️ Usage
+
+- **Encrypting Data:** Input your plaintext and key to the FPGA design to receive the encrypted ciphertext.
+- **Decrypting Data:** Input the ciphertext and the key to the FPGA design to retrieve the original plaintext.
+
+## 👥 Collaborators
+
+
+
+## 📜 License
+
+This project is licensed under the MIT License - see [License](LICENSE) for more information.
+ 
+ 
+ 
+