From 1eaeab6c36fcb129723e345fb646844cac89b86e Mon Sep 17 00:00:00 2001 From: Ahmed Sobhy Date: Fri, 26 Apr 2024 15:18:46 +0300 Subject: [PATCH] :sparkles: Implemented main AES module (#9) * :tada: Implemented main AES module * edits for quartus * running in 11 clocks each * :memo: Modified regs in main module * :hammer: Fixed port size warning * :hammer: Fixed a missing statement --------- Co-authored-by: AhmedAmrNabil --- AES.v | 90 ++++++++++++++++++++++++++++++++++++++++++++++++++ AESDecrypt.v | 56 ++++++++++++++++--------------- AESEncrypt.v | 60 ++++++++++++++++++--------------- Binary2BCD.v | 6 ++-- KeyExpansion.v | 2 +- 5 files changed, 157 insertions(+), 57 deletions(-) create mode 100644 AES.v diff --git a/AES.v b/AES.v new file mode 100644 index 0000000..2cd584b --- /dev/null +++ b/AES.v @@ -0,0 +1,90 @@ +module AES #(parameter Nk = 4, parameter Nr = 10) (encryptedOutputReg, decryptedOutputReg, HEX0, HEX1, HEX2, clk); + input clk; + output [6:0] HEX0; + output [6:0] HEX1; + output [6:0] HEX2; + + output reg [127:0] encryptedOutputReg = 128'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00; + output reg [127:0] decryptedOutputReg = 128'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00; + + // Key + wire [127:0] key = 128'h_000102030405060708090a0b0c0d0e0f; + + // Key Expansion + wire [(11 * 128) - 1:0] allKeys; + KeyExpansion keysGetter(key, allKeys); + + // Data + wire [127:0] data = 128'h_00112233445566778899aabbccddeeff; + + // AES + wire [127:0] tempEncryptedOutput; + wire [127:0] tempDecryptedOutput; + + // Binary to BCD Logic + reg [7:0] bcdInput = 8'b_00000000; + wire [11:0] bcdOutput; + Binary2BCD b2b(bcdInput, bcdOutput); + + // 7-Segment Logic + DisplayDecoder dd1(bcdOutput[3:0], HEX0); + DisplayDecoder dd2(bcdOutput[7:4], HEX1); + DisplayDecoder dd3(bcdOutput[11:8], HEX2); + + // Encrypt + reg AESEncryptEnable = 1'b1; + AESEncrypt AESE(data, allKeys, tempEncryptedOutput, clk, AESEncryptEnable); + + // Decrypt + reg AESDecryptEnable = 1'b0; + AESDecrypt AESD(tempEncryptedOutput, allKeys, tempDecryptedOutput, clk, AESDecryptEnable); + + reg [4:0] count = 0; + always @(posedge clk) begin + if (AESEncryptEnable == 1 || AESDecryptEnable == 1) + count <= count + 1; + end + + always @(count) begin + if (count < Nr + 1) + bcdInput = tempEncryptedOutput[7:0]; + else if (count == Nr + 1) begin + encryptedOutputReg = tempEncryptedOutput; + bcdInput = tempEncryptedOutput[7:0]; + AESEncryptEnable = 1'b0; + AESDecryptEnable = 1'b1; + end + else if (count < ((Nr + 1) * 2)) + bcdInput = tempDecryptedOutput[7:0]; + else if (count == ((Nr + 1) * 2)) begin + decryptedOutputReg = tempDecryptedOutput; + bcdInput = tempDecryptedOutput[7:0]; + AESDecryptEnable = 1'b0; + end + end +endmodule + +module AES_DUT(); + reg clk = 1'b0; + wire [127:0] encrypted; + wire [127:0] decrypted; + wire [6:0] HEX0, HEX1, HEX2; + + AES AES(encrypted, decrypted, HEX0, HEX1, HEX2, clk); + + reg [4:0] count = 5'b00000; + initial begin + clk = 0; + forever begin + #10 clk = ~clk; + if (clk) + count = count + 1; + end + end + + initial begin + $display("AES Encryption and Decryption"); + $display("================================"); + $monitor("Encrypted: %h, Decrypted: %h, Count: %d", encrypted, decrypted, count); + end +endmodule \ No newline at end of file diff --git a/AESDecrypt.v b/AESDecrypt.v index 6375b71..90963b4 100644 --- a/AESDecrypt.v +++ b/AESDecrypt.v @@ -1,56 +1,60 @@ -module AESDecrypt #(parameter Nk = 4,parameter Nr = 10) (data, key, out, clk); +module AESDecrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, out, clk, enable); input [127:0] data; - input [Nk * 32 - 1:0] key; + input [(11 * 128) - 1:0] allKeys; input clk; + input enable; output [127:0] out; reg [127:0] state; reg [127:0] keyReg; - reg [3:0] roundCount = 0; + reg [3:0] roundCount = 1; wire [127:0] stateAfterLastRound; wire [127:0] stateAfterKey; wire [127:0] stateAfterRound; - wire [(11 * 128) - 1:0] allKeys; - - KeyExpansion keysGetter( key , allKeys); AddRoundKey a(state, keyReg , stateAfterKey); DecryptRound round(state , keyReg , stateAfterRound); LastDecryptRound lastRound (state , keyReg , stateAfterLastRound); + always@(data)begin + state = data; + end + + always@(allKeys)begin + keyReg = allKeys[((11 * 128) - 1) -: 128] ; + end + assign out = state; always @(posedge clk) begin - if (roundCount == 0)begin - keyReg = allKeys [((11 * 128) - 1) -: 128 ] ; - state = data; + if (enable == 1) begin + if (roundCount == 1) + state <= stateAfterKey; + else if (roundCount < Nr +1) + state <= stateAfterRound; + else if (roundCount == Nr +1) + state <= stateAfterLastRound; + + if (roundCount > 0 && roundCount < Nr + 1) + keyReg <= allKeys[((11 * 128) - roundCount * 128 - 1) -: 128]; + + if (roundCount < Nr + 2) + roundCount <= roundCount + 1; end - else if (roundCount == 1) - state <= stateAfterKey; - else if (roundCount < Nr +1) - state <= stateAfterRound; - else if (roundCount == Nr +1) - state <= stateAfterLastRound; - - if (roundCount > 0 && roundCount < Nr + 1) - keyReg <= allKeys [((11 * 128) - roundCount * 128 - 1) -: 128 ]; - - if (roundCount < Nr + 2) - roundCount <= roundCount + 1; end endmodule module AESDecrypt_DUT(); - reg [127:0] data; - reg [127:0] key; + wire [127:0] data = 128'h69c4e0d86a7b0430d8cdb78070b4c55a; + wire [127:0] key = 128'h000102030405060708090a0b0c0d0e0f; + wire [(11 * 128) - 1:0] allKeys; wire [127:0] out; reg clk; - AESDecrypt aes(data,key,out,clk); + KeyExpansion ke(key, allKeys); + AESDecrypt aes(data, allKeys, out, clk, 1); initial begin - key = 128'h000102030405060708090a0b0c0d0e0f; - data = 128'h69c4e0d86a7b0430d8cdb78070b4c55a; clk = 0; forever #10 clk = ~clk; end diff --git a/AESEncrypt.v b/AESEncrypt.v index b1cd13a..f47d7a0 100644 --- a/AESEncrypt.v +++ b/AESEncrypt.v @@ -1,56 +1,62 @@ -module AESEncrypt #(parameter Nk = 4,parameter Nr = 10) (data, key, out, clk); +module AESEncrypt #(parameter Nk = 4, parameter Nr = 10) (data, allKeys, out, clk, enable); input [127:0] data; - input [Nk * 32 - 1:0] key; + input [(11 * 128) - 1:0] allKeys; input clk; + input enable; output [127:0] out; reg [127:0] state; reg [127:0] keyReg; - reg [3:0] roundCount = 0; + reg [3:0] roundCount = 1; wire [127:0] stateAfterLastRound; wire [127:0] stateAfterKey; wire [127:0] stateAfterRound; wire [127:0] keyWire; - KeyExpansionRound keyexpround(roundCount,keyReg,keyWire); - AddRoundKey a(state,keyReg,stateAfterKey); - EncryptRound round(state,keyReg,stateAfterRound); - LastEncryptRound lastRound(state,keyReg,stateAfterLastRound); + AddRoundKey a(state, keyReg, stateAfterKey); + EncryptRound round(state, keyReg, stateAfterRound); + LastEncryptRound lastRound(state, keyReg, stateAfterLastRound); + + always @(data) begin + state = data; + end + + always @(allKeys) begin + keyReg = allKeys[127:0]; + end assign out = state; always @(posedge clk) begin - if (roundCount == 0) begin - keyReg = key; - state = data; + if (enable == 1) begin + if (roundCount == 1) + state <= stateAfterKey; + else if (roundCount < Nr + 1) + state <= stateAfterRound; + else if (roundCount == Nr + 1) + state <= stateAfterLastRound; + + if (roundCount > 0 && roundCount < Nr + 1) + keyReg <= allKeys[(128 * (roundCount + 1)) - 1 -: 128]; + + if (roundCount < Nr + 2) + roundCount <= roundCount + 1; end - else if (roundCount == 1) - state <= stateAfterKey; - else if (roundCount < Nr +1) - state <= stateAfterRound; - else if (roundCount == Nr +1) - state <= stateAfterLastRound; - - if (roundCount > 0 && roundCount < Nr + 1) - keyReg <= keyWire; - - if (roundCount < Nr + 2) - roundCount <= roundCount + 1; end endmodule module AESEncrypt_DUT(); - reg [127:0] data; - reg [127:0] key; + wire [127:0] data = 128'h00112233445566778899aabbccddeeff; + wire [127:0] key = 128'h000102030405060708090a0b0c0d0e0f; + wire [(11 * 128) - 1:0] allKeys; wire [127:0] out; reg clk; - AESEncrypt aes(data,key,out,clk); + KeyExpansion ke(key, allKeys); + AESEncrypt aes(data, allKeys, out, clk, 1); initial begin - key = 128'h000102030405060708090a0b0c0d0e0f; - data = 128'h00112233445566778899aabbccddeeff; clk = 0; forever #10 clk = ~clk; end diff --git a/Binary2BCD.v b/Binary2BCD.v index 9ae7e63..b9bdffd 100644 --- a/Binary2BCD.v +++ b/Binary2BCD.v @@ -11,15 +11,15 @@ module Binary2BCD(in, out); output [11:0] out; wire [28:1] temp; - CondAdd3 c1({0,in[7:5]}, temp[4:1]); + CondAdd3 c1({1'b0,in[7:5]}, temp[4:1]); CondAdd3 c2({temp[3:1], in[4]}, temp[8:5]); CondAdd3 c3({temp[7:5], in[3]}, temp[12:9]); CondAdd3 c4({temp[11:9], in[2]}, temp[16:13]); CondAdd3 c5({temp[15:13], in[1]}, temp[20:17]); - CondAdd3 c6({0, temp[4], temp[8], temp[12]}, temp[24:21]); + CondAdd3 c6({1'b0, temp[4], temp[8], temp[12]}, temp[24:21]); CondAdd3 c7({temp[23:21], temp[16]}, temp[28:25]); - assign out = {0, 0, temp[24], temp[28:25], temp[20:17], in[0]}; + assign out = {1'b0, 1'b0, temp[24], temp[28:25], temp[20:17], in[0]}; endmodule module Binary2BCD_DUT(); diff --git a/KeyExpansion.v b/KeyExpansion.v index 96e864f..79a0868 100644 --- a/KeyExpansion.v +++ b/KeyExpansion.v @@ -62,7 +62,7 @@ module KeyExpansion(keyIn, keysOut); genvar i; generate for (i = 0; i < 10; i = i + 1) begin : KeyExpansionLoop - KeyExpansionRound keyExpansionRound(i + 1, keysOut[127 + i * 128 -: 128], keysOut[255 + i * 128 -: 128]); + KeyExpansionRound keyExpansionRound(i[3:0] + 4'b0001, keysOut[127 + i * 128 -: 128], keysOut[255 + i * 128 -: 128]); end endgenerate endmodule