diff --git a/DIO.C b/DIO.C
new file mode 100644
index 0000000..56f95d1
--- /dev/null
+++ b/DIO.C
@@ -0,0 +1,247 @@
+#include "DIO.h" // Include DIO.h file 
+
+
+//**** Definition of DIO.c file ****
+
+//Inizialization function
+void DIO_INIT(int_32 port, int_32 pin, int_32 dir){ 
+
+    SET_BIT(SYSCTL_RCGCGPIO_R, port);
+    while(GET_BIT(SYSCTL_PRGPIO_R, port) == 0){};
+    
+    switch (port){
+        case PORTA:
+        GPIO_PORTA_LOCK_R = 0x4C4F434B;
+        GPIO_PORTA_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTA_DIR_R,pin);
+        SET_BIT(GPIO_PORTA_PUR_R, pin);
+        }
+        SET_BIT(GPIO_PORTA_DEN_R, pin)
+        GPIO_PORTA_CR_R = 0xFF;
+            break;
+
+        case PORTB:
+        GPIO_PORTB_LOCK_R = 0x4C4F434B;
+        GPIO_PORTB_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTB_DIR_R,pin);
+        SET_BIT(GPIO_PORTB_PUR_R, pin);
+        }
+        SET_BIT(GPIO_PORTB_DEN_R, pin)
+        GPIO_PORTB_CR_R = 0xFF;
+
+            break;
+
+        case PORTC:
+        GPIO_PORTC_LOCK_R = 0x4C4F434B;
+        GPIO_PORTC_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTC_DIR_R,pin);
+        SET_BIT(GPIO_PORTC_PUR_R, pin);
+        }
+        SET_BIT(GPIO_PORTC_DEN_R, pin)
+        GPIO_PORTC_CR_R = 0xFF;
+
+            break;
+
+
+        case PORTD:
+        GPIO_PORTD_LOCK_R = 0x4C4F434B;
+         GPIO_PORTD_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTD_DIR_R,pin);
+        SET_BIT(GPIO_PORTD_PUR_R, pin);
+        }
+        SET_BIT(GPIO_PORTD_DEN_R, pin)
+        GPIO_PORTD_CR_R = 0xFF;
+
+            break;
+
+
+        case PORTE:
+        GPIO_PORTE_LOCK_R = 0x4C4F434B;
+        GPIO_PORTE_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTE_DIR_R,pin);
+        SET_BIT(GPIO_PORTE_PUR_R, pin);
+        }
+        SET_BIT(GPIO_PORTE_DEN_R, pin)
+        GPIO_PORTE_CR_R = 0xFF;
+
+            break;
+
+        
+        case PORTF:
+        GPIO_PORTF_LOCK_R = 0x4C4F434B;
+        GPIO_PORTF_DIR_R |= (1<<pin);
+        if(!dir){
+        TOGGLE_BIT(GPIO_PORTF_DIR_R,pin);
+        SET_BIT(GPIO_PORTF_PUR_R, pin);
+        }
+        GPIO_PORTF_CR_R = 0xFF;
+        SET_BIT(GPIO_PORTF_DEN_R, pin)
+            break;
+        default:
+            break;
+        }
+}
+
+// Write value to pin
+void write_pin(int_8 port, int_8 pin, int_8 value)
+{
+  switch (port)
+  {
+  case PORTA: 
+    if (GET_BIT(GPIO_PORTA_DEN_R, pin) && GET_BIT(GPIO_PORTA_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTA_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTA_DATA_R, pin)
+      }
+    }
+    
+    
+  case PORTB: 
+   if (GET_BIT(GPIO_PORTB_DEN_R, pin)&& GET_BIT(GPIO_PORTB_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTB_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTB_DATA_R, pin)
+      }
+    }
+    
+    
+  case PORTC: 
+   if (GET_BIT(GPIO_PORTC_DEN_R, pin) && GET_BIT(GPIO_PORTC_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTC_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTC_DATA_R, pin)
+      }
+    }
+    
+    
+  case PORTD: 
+   if (GET_BIT(GPIO_PORTD_DEN_R, pin) && GET_BIT(GPIO_PORTD_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTD_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTD_DATA_R, pin)
+      }
+    }
+    
+    
+  case PORTE: 
+    if (GET_BIT(GPIO_PORTE_DEN_R, pin) && GET_BIT(GPIO_PORTE_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTE_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTE_DATA_R, pin)
+      }
+    }
+    
+    
+    
+  case PORTF: 
+    if (GET_BIT(GPIO_PORTF_DEN_R, pin) && GET_BIT(GPIO_PORTF_DIR_R, pin))
+    {
+      if (value)
+      {
+        SET_BIT(GPIO_PORTF_DATA_R, pin)
+      }
+      else
+      {
+        CLEAR_BIT(GPIO_PORTF_DATA_R, pin)
+      }
+    }
+    
+  }
+}
+ 
+// Write value to port 
+void write_port(int_8 port, int_8 value) 
+{  
+  for (int i = 0; i < 8; i++)
+  {
+    write_pin(port, i, GET_BIT(value,i));
+  }
+}
+
+// Read value from port            
+int_8 read_port(int_8 port) 
+{  
+  int_8 port_reading = 0x00; 
+  for (int i = 0; i < 8; i++)
+  {
+    port_reading |= DIO_ReadPin(port, i) << i;
+  }
+  return port_reading;
+}
+
+// Read value from pin
+int_8 DIO_ReadPin(int_8 port, int_8 pin)
+{
+  switch (port)
+  {
+  case PORTA: 
+     if (GET_BIT(GPIO_PORTA_DEN_R, pin) && (!GET_BIT(GPIO_PORTA_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTA_DATA_R, pin);
+     }
+    
+  case PORTB: 
+    if (GET_BIT(GPIO_PORTB_DEN_R, pin) && (!GET_BIT(GPIO_PORTB_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTB_DATA_R, pin);
+     }
+    
+    
+  case PORTC: 
+   if (GET_BIT(GPIO_PORTC_DEN_R, pin) && (!GET_BIT(GPIO_PORTC_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTC_DATA_R, pin);
+     }    
+    
+    
+  case PORTD: 
+    if (GET_BIT(GPIO_PORTD_DEN_R, pin) && (!GET_BIT(GPIO_PORTD_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTD_DATA_R, pin);
+     }
+        
+  case PORTE: 
+    if (GET_BIT(GPIO_PORTE_DEN_R, pin) && (!GET_BIT(GPIO_PORTE_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTE_DATA_R, pin);
+     }    
+    
+  case PORTF: 
+   if (GET_BIT(GPIO_PORTF_DEN_R, pin) && (!GET_BIT(GPIO_PORTF_DIR_R, pin)))
+     {
+        return GET_BIT(GPIO_PORTF_DATA_R, pin);
+     }
+   
+  default: return -1;
+  }
+}
\ No newline at end of file
diff --git a/DIO.h b/DIO.h
new file mode 100644
index 0000000..6b620d1
--- /dev/null
+++ b/DIO.h
@@ -0,0 +1,32 @@
+//**** Include files ****
+#include "types.h"
+#include "tm4c123gh6pm.h"
+#include "stdint.h"
+
+//**** Define macros ****
+#define SET_BIT(REG,PIN) {REG|=(1<<PIN);}
+#define CLEAR_BIT(REG,PIN) {REG&= ~(1<<PIN);}
+#define TOGGLE_BIT(REG,PIN) {REG^= (1<<PIN);}
+#define GET_BIT(REG,PIN) (((1<<PIN)&REG)>>PIN)
+#define IN 0
+#define OUT 1
+#define PORTA 0
+#define PORTB 1
+#define PORTC 2
+#define PORTD 3
+#define PORTE 4
+#define PORTF 5
+
+//**** Light code definition ****
+#define GREEN  0
+#define YELLOW 1
+#define RED    2
+
+
+//**** DIO functions definitions ****
+void DIO_INIT(int_32 port, int_32 pin, int_32 dir);
+void write_pin(int_8 port, int_8 pin, int_8 value); 
+void write_port(int_8 port, int_8 value);
+int_8 DIO_ReadPin(int_8 port, int_8 pin);
+int_8 DIO_ReadPort(int_8 port);
+int_8 test_DIO_ReadPin(int_8 port, int_8 pin);
diff --git a/Debug/.ninja_deps b/Debug/.ninja_deps
new file mode 100644
index 0000000..f9769ea
Binary files /dev/null and b/Debug/.ninja_deps differ
diff --git a/Debug/.ninja_log b/Debug/.ninja_log
new file mode 100644
index 0000000..4153b47
--- /dev/null
+++ b/Debug/.ninja_log
@@ -0,0 +1,103 @@
+# ninja log v5
+398	494	6636740791479191	G:/Semester 7/Embedded/FinalProject/CESS_Team4_Trafficlight/Debug/Exe/TrafficLight.out	254d6e9907258244
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diff --git a/Debug/BrowseInfo/.ninja_deps b/Debug/BrowseInfo/.ninja_deps
new file mode 100644
index 0000000..e5675ec
Binary files /dev/null and b/Debug/BrowseInfo/.ninja_deps differ
diff --git a/Debug/BrowseInfo/.ninja_log b/Debug/BrowseInfo/.ninja_log
new file mode 100644
index 0000000..8d6ed6c
--- /dev/null
+++ b/Debug/BrowseInfo/.ninja_log
@@ -0,0 +1,51 @@
+# ninja log v5
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diff --git a/Debug/BrowseInfo/DIO.pbi b/Debug/BrowseInfo/DIO.pbi
new file mode 100644
index 0000000..d5642d1
Binary files /dev/null and b/Debug/BrowseInfo/DIO.pbi differ
diff --git a/Debug/BrowseInfo/DIO.pbi.dep b/Debug/BrowseInfo/DIO.pbi.dep
new file mode 100644
index 0000000..88d4cc5
--- /dev/null
+++ b/Debug/BrowseInfo/DIO.pbi.dep
@@ -0,0 +1,11 @@
+G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi: \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.C \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\types.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\tm4c123gh6pm.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\stdint.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\ycheck.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\yvals.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Defaults.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Config_Normal.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Product.h
diff --git a/Debug/BrowseInfo/DIO.xcl b/Debug/BrowseInfo/DIO.xcl
new file mode 100644
index 0000000..c9db17a
--- /dev/null
+++ b/Debug/BrowseInfo/DIO.xcl
@@ -0,0 +1,368 @@
+"G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.C"
+-std=c11
+-ferror-limit=0
+-fbracket-depth=512
+-funsigned-char
+-MD
+-MF
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi.dep
+-o
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi
+-I
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight
+-I
+C:\ti\TivaWare_C_Series-2.2.0.295
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\aarch32
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c
+-I
+C:\ti\TivaWare_C_Series-2.2.0.295
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diff --git a/Debug/BrowseInfo/TrafficLight.pbd b/Debug/BrowseInfo/TrafficLight.pbd
new file mode 100644
index 0000000..cc5e2de
Binary files /dev/null and b/Debug/BrowseInfo/TrafficLight.pbd differ
diff --git a/Debug/BrowseInfo/TrafficLight.pbd.browse b/Debug/BrowseInfo/TrafficLight.pbd.browse
new file mode 100644
index 0000000..cc5e2de
Binary files /dev/null and b/Debug/BrowseInfo/TrafficLight.pbd.browse differ
diff --git a/Debug/BrowseInfo/TrafficLight.pbw b/Debug/BrowseInfo/TrafficLight.pbw
new file mode 100644
index 0000000..a62ce79
--- /dev/null
+++ b/Debug/BrowseInfo/TrafficLight.pbw
@@ -0,0 +1,142625 @@
+[
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+    "ID": "c:tm4c123gh6pm.h@2033@macro@__TM4C123GH6PM_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__TM4C123GH6PM_H__",
+    "location": {
+      "column": "9",
+      "line": "41",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "__TM4C123GH6PM_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2259@macro@INT_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "48",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2319@macro@INT_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "49",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2379@macro@INT_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "50",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2439@macro@INT_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "51",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2499@macro@INT_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "52",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2559@macro@INT_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART0",
+    "location": {
+      "column": "9",
+      "line": "53",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2613@macro@INT_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART1",
+    "location": {
+      "column": "9",
+      "line": "54",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2667@macro@INT_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_SSI0",
+    "location": {
+      "column": "9",
+      "line": "55",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2720@macro@INT_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_I2C0",
+    "location": {
+      "column": "9",
+      "line": "56",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2773@macro@INT_PWM0_FAULT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_FAULT",
+    "location": {
+      "column": "9",
+      "line": "57",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_PWM0_FAULT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2832@macro@INT_PWM0_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_0",
+    "location": {
+      "column": "9",
+      "line": "58",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_PWM0_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2897@macro@INT_PWM0_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_1",
+    "location": {
+      "column": "9",
+      "line": "59",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_PWM0_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@2962@macro@INT_PWM0_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_2",
+    "location": {
+      "column": "9",
+      "line": "60",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_PWM0_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3027@macro@INT_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_QEI0",
+    "location": {
+      "column": "9",
+      "line": "61",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3080@macro@INT_ADC0SS0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_ADC0SS0",
+    "location": {
+      "column": "9",
+      "line": "62",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC0SS0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3144@macro@INT_ADC0SS1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_ADC0SS1",
+    "location": {
+      "column": "9",
+      "line": "63",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC0SS1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3208@macro@INT_ADC0SS2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_ADC0SS2",
+    "location": {
+      "column": "9",
+      "line": "64",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC0SS2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3272@macro@INT_ADC0SS3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_ADC0SS3",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC0SS3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3336@macro@INT_WATCHDOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WATCHDOG",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WATCHDOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3408@macro@INT_TIMER0A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER0A",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER0A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3475@macro@INT_TIMER0B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER0B",
+    "location": {
+      "column": "9",
+      "line": "68",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER0B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3542@macro@INT_TIMER1A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER1A",
+    "location": {
+      "column": "9",
+      "line": "69",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER1A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@3609@macro@INT_TIMER1B",
+    "What": "MacroDef",
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+    "display": "INT_TIMER1B",
+    "location": {
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+      "line": "70",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+  {
+    "ID": "c:tm4c123gh6pm.h@3676@macro@INT_TIMER2A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER2A",
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+    },
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+    },
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+    },
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+    "scope": null
+  },
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@3946@macro@INT_SYSCTL",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_SYSCTL",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@4009@macro@INT_FLASH",
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+    "defdec": "Def",
+    "display": "INT_FLASH",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_FLASH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4145@macro@INT_GPIOF",
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+    },
+    "name": "INT_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART2",
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+    "scope": null
+  },
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+    },
+    "name": "INT_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
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+    },
+    "name": "INT_TIMER3A",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "INT_TIMER3B",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4489@macro@INT_QEI1",
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+    "defdec": "Def",
+    "display": "INT_QEI1",
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+    },
+    "name": "INT_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4542@macro@INT_CAN0",
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+    "defdec": "Def",
+    "display": "INT_CAN0",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4595@macro@INT_CAN1",
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+    "defdec": "Def",
+    "display": "INT_CAN1",
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+    },
+    "name": "INT_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4648@macro@INT_HIBERNATE",
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+    "defdec": "Def",
+    "display": "INT_HIBERNATE",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_HIBERNATE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4715@macro@INT_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_USB0",
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+      "line": "88",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4767@macro@INT_PWM0_3",
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+    "defdec": "Def",
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+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_PWM0_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4831@macro@INT_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UDMA",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4893@macro@INT_UDMAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UDMAERR",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UDMAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@4952@macro@INT_ADC1SS0",
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+    "defdec": "Def",
+    "display": "INT_ADC1SS0",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC1SS0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_ADC1SS1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5080@macro@INT_ADC1SS2",
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+    },
+    "name": "INT_ADC1SS2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
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+    },
+    "name": "INT_ADC1SS3",
+    "origin": "user_include",
+    "scope": null
+  },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_SSI2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    },
+    "name": "INT_SSI3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART3",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
+    "display": "INT_UART4",
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+      "line": "99",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5422@macro@INT_UART5",
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+    "defdec": "Def",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5476@macro@INT_UART6",
+    "What": "MacroDef",
+    "defdec": "Def",
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+    "location": {
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+      "line": "101",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5530@macro@INT_UART7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART7",
+    "location": {
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+      "line": "102",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_UART7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
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+    "location": {
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+      "line": "103",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_I2C2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5637@macro@INT_I2C3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_I2C3",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_I2C3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER4A",
+    "location": {
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+      "line": "105",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER4A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
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+    "location": {
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+      "line": "106",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER4B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5824@macro@INT_TIMER5A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER5A",
+    "location": {
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+      "line": "107",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER5A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5891@macro@INT_TIMER5B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_TIMER5B",
+    "location": {
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+      "line": "108",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_TIMER5B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@5958@macro@INT_WTIMER0A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER0A",
+    "location": {
+      "column": "9",
+      "line": "109",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER0A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6025@macro@INT_WTIMER0B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER0B",
+    "location": {
+      "column": "9",
+      "line": "110",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER0B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6092@macro@INT_WTIMER1A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER1A",
+    "location": {
+      "column": "9",
+      "line": "111",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER1A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6159@macro@INT_WTIMER1B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER1B",
+    "location": {
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+      "line": "112",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER1B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6226@macro@INT_WTIMER2A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER2A",
+    "location": {
+      "column": "9",
+      "line": "113",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER2A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6293@macro@INT_WTIMER2B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER2B",
+    "location": {
+      "column": "9",
+      "line": "114",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER2B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@6360@macro@INT_WTIMER3A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_WTIMER3A",
+    "location": {
+      "column": "9",
+      "line": "115",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "INT_WTIMER3A",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
+    "name": "GPIO_PORTA_ICR_R",
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+    },
+    "name": "GPIO_PORTA_AFSEL_R",
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+    },
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+  },
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+    },
+    "name": "GPIO_PORTA_DR4R_R",
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+  },
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+    },
+    "name": "GPIO_PORTA_DR8R_R",
+    "origin": "user_include",
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+  },
+  {
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+    },
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+    },
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+  },
+  {
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+    },
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+  },
+  {
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+    },
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+  },
+  {
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@10230@macro@GPIO_PORTA_LOCK_R",
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+    },
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+  },
+  {
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+    },
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+  },
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+    },
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+  },
+  {
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+    },
+    "name": "GPIO_PORTA_PCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@10510@macro@GPIO_PORTA_ADCCTL_R",
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+    },
+    "name": "GPIO_PORTA_ADCCTL_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@10580@macro@GPIO_PORTA_DMACTL_R",
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+    },
+    "name": "GPIO_PORTA_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@10849@macro@GPIO_PORTB_DATA_BITS_R",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@10916@macro@GPIO_PORTB_DATA_R",
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+    "defdec": "Def",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@10986@macro@GPIO_PORTB_DIR_R",
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+    },
+    "name": "GPIO_PORTB_DIR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11056@macro@GPIO_PORTB_IS_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_IS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11126@macro@GPIO_PORTB_IBE_R",
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+    },
+    "name": "GPIO_PORTB_IBE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11196@macro@GPIO_PORTB_IEV_R",
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+    },
+    "name": "GPIO_PORTB_IEV_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11266@macro@GPIO_PORTB_IM_R",
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+    },
+    "name": "GPIO_PORTB_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11336@macro@GPIO_PORTB_RIS_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTB_RIS_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11406@macro@GPIO_PORTB_MIS_R",
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+    },
+    "name": "GPIO_PORTB_MIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11476@macro@GPIO_PORTB_ICR_R",
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+    },
+    "name": "GPIO_PORTB_ICR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11546@macro@GPIO_PORTB_AFSEL_R",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "GPIO_PORTB_DR2R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11686@macro@GPIO_PORTB_DR4R_R",
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+    },
+    "name": "GPIO_PORTB_DR4R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@11756@macro@GPIO_PORTB_DR8R_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_DR8R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_ODR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "GPIO_PORTB_PUR_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_PUR_R",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "GPIO_PORTB_PDR_R",
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+  },
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+    },
+    "name": "GPIO_PORTB_SLR_R",
+    "origin": "user_include",
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+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_DEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "line": "211",
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+    },
+    "name": "GPIO_PORTB_LOCK_R",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "GPIO_PORTB_CR_R",
+    "origin": "user_include",
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+  },
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+    },
+    "name": "GPIO_PORTB_AMSEL_R",
+    "origin": "user_include",
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+    },
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+    "origin": "user_include",
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+  },
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+    "display": "GPIO_PORTB_ADCCTL_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@12526@macro@GPIO_PORTB_DMACTL_R",
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+    "display": "GPIO_PORTB_DMACTL_R",
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+      "line": "216",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@12795@macro@GPIO_PORTC_DATA_BITS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_DATA_BITS_R",
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+      "line": "223",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@12862@macro@GPIO_PORTC_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_DATA_R",
+    "location": {
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+      "line": "224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@12932@macro@GPIO_PORTC_DIR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_DIR_R",
+    "location": {
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+      "line": "225",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_DIR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@13002@macro@GPIO_PORTC_IS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_IS_R",
+    "location": {
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+      "line": "226",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_IS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@13072@macro@GPIO_PORTC_IBE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_IBE_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_IBE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@13142@macro@GPIO_PORTC_IEV_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_IEV_R",
+    "location": {
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+      "line": "228",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+  {
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+    },
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+    },
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+    },
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+  {
+    "ID": "c:tm4c123gh6pm.h@41132@macro@GPIO_PORTE_PDR_R",
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+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41202@macro@GPIO_PORTE_SLR_R",
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+    },
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+  {
+    "ID": "c:tm4c123gh6pm.h@41272@macro@GPIO_PORTE_DEN_R",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41342@macro@GPIO_PORTE_LOCK_R",
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+    },
+    "name": "GPIO_PORTE_LOCK_R",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41412@macro@GPIO_PORTE_CR_R",
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+    },
+    "name": "GPIO_PORTE_CR_R",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@41482@macro@GPIO_PORTE_AMSEL_R",
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+    },
+    "name": "GPIO_PORTE_AMSEL_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41552@macro@GPIO_PORTE_PCTL_R",
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+    },
+    "name": "GPIO_PORTE_PCTL_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41622@macro@GPIO_PORTE_ADCCTL_R",
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+    },
+    "name": "GPIO_PORTE_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@41692@macro@GPIO_PORTE_DMACTL_R",
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+    },
+    "name": "GPIO_PORTE_DMACTL_R",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@41961@macro@GPIO_PORTF_DATA_BITS_R",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@42028@macro@GPIO_PORTF_DATA_R",
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+    },
+    "name": "GPIO_PORTF_DATA_R",
+    "origin": "user_include",
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+  },
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+    },
+    "name": "GPIO_PORTF_DIR_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@42168@macro@GPIO_PORTF_IS_R",
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+    },
+    "name": "GPIO_PORTF_IS_R",
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+  },
+  {
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+    },
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+  {
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+    },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+    },
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+    },
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+    },
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+    },
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+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_DR8R_R",
+    "origin": "user_include",
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+  },
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+    "defdec": "Def",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_ODR_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43008@macro@GPIO_PORTF_PUR_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTF_PUR_R",
+    "location": {
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+      "line": "715",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_PUR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43078@macro@GPIO_PORTF_PDR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_PDR_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_PDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43148@macro@GPIO_PORTF_SLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_SLR_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_SLR_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43218@macro@GPIO_PORTF_DEN_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTF_DEN_R",
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+      "line": "718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_DEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43288@macro@GPIO_PORTF_LOCK_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_LOCK_R",
+    "location": {
+      "column": "9",
+      "line": "719",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_LOCK_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43358@macro@GPIO_PORTF_CR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_CR_R",
+    "location": {
+      "column": "9",
+      "line": "720",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_CR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43428@macro@GPIO_PORTF_AMSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_AMSEL_R",
+    "location": {
+      "column": "9",
+      "line": "721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_AMSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43498@macro@GPIO_PORTF_PCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_PCTL_R",
+    "location": {
+      "column": "9",
+      "line": "722",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_PCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43568@macro@GPIO_PORTF_ADCCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_ADCCTL_R",
+    "location": {
+      "column": "9",
+      "line": "723",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43638@macro@GPIO_PORTF_DMACTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTF_DMACTL_R",
+    "location": {
+      "column": "9",
+      "line": "724",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTF_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43905@macro@PWM0_CTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_CTL_R",
+    "location": {
+      "column": "9",
+      "line": "731",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_CTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@43975@macro@PWM0_SYNC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_SYNC_R",
+    "location": {
+      "column": "9",
+      "line": "732",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_SYNC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44045@macro@PWM0_ENABLE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_ENABLE_R",
+    "location": {
+      "column": "9",
+      "line": "733",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_ENABLE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44115@macro@PWM0_INVERT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_INVERT_R",
+    "location": {
+      "column": "9",
+      "line": "734",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_INVERT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44185@macro@PWM0_FAULT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_FAULT_R",
+    "location": {
+      "column": "9",
+      "line": "735",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_FAULT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44255@macro@PWM0_INTEN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_INTEN_R",
+    "location": {
+      "column": "9",
+      "line": "736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_INTEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44325@macro@PWM0_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "737",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44395@macro@PWM0_ISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_ISC_R",
+    "location": {
+      "column": "9",
+      "line": "738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_ISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44465@macro@PWM0_STATUS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_STATUS_R",
+    "location": {
+      "column": "9",
+      "line": "739",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_STATUS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44535@macro@PWM0_FAULTVAL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_FAULTVAL_R",
+    "location": {
+      "column": "9",
+      "line": "740",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_FAULTVAL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44605@macro@PWM0_ENUPD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_ENUPD_R",
+    "location": {
+      "column": "9",
+      "line": "741",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_ENUPD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44675@macro@PWM0_0_CTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_CTL_R",
+    "location": {
+      "column": "9",
+      "line": "742",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_CTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44745@macro@PWM0_0_INTEN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_INTEN_R",
+    "location": {
+      "column": "9",
+      "line": "743",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_INTEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44815@macro@PWM0_0_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "744",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44885@macro@PWM0_0_ISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_ISC_R",
+    "location": {
+      "column": "9",
+      "line": "745",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_ISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@44955@macro@PWM0_0_LOAD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_LOAD_R",
+    "location": {
+      "column": "9",
+      "line": "746",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_LOAD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45025@macro@PWM0_0_COUNT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_COUNT_R",
+    "location": {
+      "column": "9",
+      "line": "747",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_COUNT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45095@macro@PWM0_0_CMPA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_CMPA_R",
+    "location": {
+      "column": "9",
+      "line": "748",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_CMPA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45165@macro@PWM0_0_CMPB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_CMPB_R",
+    "location": {
+      "column": "9",
+      "line": "749",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_CMPB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45235@macro@PWM0_0_GENA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_GENA_R",
+    "location": {
+      "column": "9",
+      "line": "750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_GENA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45305@macro@PWM0_0_GENB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_GENB_R",
+    "location": {
+      "column": "9",
+      "line": "751",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_GENB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45375@macro@PWM0_0_DBCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_DBCTL_R",
+    "location": {
+      "column": "9",
+      "line": "752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_DBCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45445@macro@PWM0_0_DBRISE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_DBRISE_R",
+    "location": {
+      "column": "9",
+      "line": "753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_DBRISE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45515@macro@PWM0_0_DBFALL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_DBFALL_R",
+    "location": {
+      "column": "9",
+      "line": "754",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_DBFALL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45585@macro@PWM0_0_FLTSRC0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_FLTSRC0_R",
+    "location": {
+      "column": "9",
+      "line": "755",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_FLTSRC0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45655@macro@PWM0_0_FLTSRC1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_FLTSRC1_R",
+    "location": {
+      "column": "9",
+      "line": "756",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_FLTSRC1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45725@macro@PWM0_0_MINFLTPER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_0_MINFLTPER_R",
+    "location": {
+      "column": "9",
+      "line": "757",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_0_MINFLTPER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45795@macro@PWM0_1_CTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_CTL_R",
+    "location": {
+      "column": "9",
+      "line": "758",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_CTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45865@macro@PWM0_1_INTEN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_INTEN_R",
+    "location": {
+      "column": "9",
+      "line": "759",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_INTEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@45935@macro@PWM0_1_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "760",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@46005@macro@PWM0_1_ISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_ISC_R",
+    "location": {
+      "column": "9",
+      "line": "761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_ISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@46075@macro@PWM0_1_LOAD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_LOAD_R",
+    "location": {
+      "column": "9",
+      "line": "762",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_LOAD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@46145@macro@PWM0_1_COUNT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_COUNT_R",
+    "location": {
+      "column": "9",
+      "line": "763",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_COUNT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@46215@macro@PWM0_1_CMPA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_CMPA_R",
+    "location": {
+      "column": "9",
+      "line": "764",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM0_1_CMPA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@46285@macro@PWM0_1_CMPB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM0_1_CMPB_R",
+    "location": {
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
+  {
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+    },
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+  },
+  {
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
+    "name": "ADC0_SSMUX2_R",
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+  },
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+    },
+    "name": "ADC0_SSCTL2_R",
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+  },
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+    },
+    "name": "ADC0_SSFIFO2_R",
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+  },
+  {
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+    "display": "ADC0_SSFSTAT2_R",
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+    },
+    "name": "ADC0_SSFSTAT2_R",
+    "origin": "user_include",
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+  },
+  {
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+    "display": "ADC0_SSOP2_R",
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+    },
+    "name": "ADC0_SSOP2_R",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "ADC0_SSDC2_R",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "ADC0_SSMUX3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77313@macro@ADC0_SSCTL3_R",
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+    "display": "ADC0_SSCTL3_R",
+    "location": {
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+    },
+    "name": "ADC0_SSCTL3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77383@macro@ADC0_SSFIFO3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_SSFIFO3_R",
+    "location": {
+      "column": "9",
+      "line": "1247",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_SSFIFO3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77453@macro@ADC0_SSFSTAT3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_SSFSTAT3_R",
+    "location": {
+      "column": "9",
+      "line": "1248",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_SSFSTAT3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77523@macro@ADC0_SSOP3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_SSOP3_R",
+    "location": {
+      "column": "9",
+      "line": "1249",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_SSOP3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77593@macro@ADC0_SSDC3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_SSDC3_R",
+    "location": {
+      "column": "9",
+      "line": "1250",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_SSDC3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77663@macro@ADC0_DCRIC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCRIC_R",
+    "location": {
+      "column": "9",
+      "line": "1251",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCRIC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77733@macro@ADC0_DCCTL0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL0_R",
+    "location": {
+      "column": "9",
+      "line": "1252",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77803@macro@ADC0_DCCTL1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL1_R",
+    "location": {
+      "column": "9",
+      "line": "1253",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77873@macro@ADC0_DCCTL2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL2_R",
+    "location": {
+      "column": "9",
+      "line": "1254",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@77943@macro@ADC0_DCCTL3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL3_R",
+    "location": {
+      "column": "9",
+      "line": "1255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78013@macro@ADC0_DCCTL4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL4_R",
+    "location": {
+      "column": "9",
+      "line": "1256",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78083@macro@ADC0_DCCTL5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL5_R",
+    "location": {
+      "column": "9",
+      "line": "1257",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78153@macro@ADC0_DCCTL6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL6_R",
+    "location": {
+      "column": "9",
+      "line": "1258",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78223@macro@ADC0_DCCTL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCTL7_R",
+    "location": {
+      "column": "9",
+      "line": "1259",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCTL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78293@macro@ADC0_DCCMP0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP0_R",
+    "location": {
+      "column": "9",
+      "line": "1260",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78363@macro@ADC0_DCCMP1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP1_R",
+    "location": {
+      "column": "9",
+      "line": "1261",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78433@macro@ADC0_DCCMP2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP2_R",
+    "location": {
+      "column": "9",
+      "line": "1262",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78503@macro@ADC0_DCCMP3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP3_R",
+    "location": {
+      "column": "9",
+      "line": "1263",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78573@macro@ADC0_DCCMP4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP4_R",
+    "location": {
+      "column": "9",
+      "line": "1264",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78643@macro@ADC0_DCCMP5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP5_R",
+    "location": {
+      "column": "9",
+      "line": "1265",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78713@macro@ADC0_DCCMP6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP6_R",
+    "location": {
+      "column": "9",
+      "line": "1266",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78783@macro@ADC0_DCCMP7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_DCCMP7_R",
+    "location": {
+      "column": "9",
+      "line": "1267",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_DCCMP7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78853@macro@ADC0_PP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_PP_R",
+    "location": {
+      "column": "9",
+      "line": "1268",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_PP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78923@macro@ADC0_PC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_PC_R",
+    "location": {
+      "column": "9",
+      "line": "1269",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_PC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@78993@macro@ADC0_CC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC0_CC_R",
+    "location": {
+      "column": "9",
+      "line": "1270",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC0_CC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79260@macro@ADC1_ACTSS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_ACTSS_R",
+    "location": {
+      "column": "9",
+      "line": "1277",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_ACTSS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79330@macro@ADC1_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "1278",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79400@macro@ADC1_IM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_IM_R",
+    "location": {
+      "column": "9",
+      "line": "1279",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79470@macro@ADC1_ISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_ISC_R",
+    "location": {
+      "column": "9",
+      "line": "1280",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_ISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79540@macro@ADC1_OSTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_OSTAT_R",
+    "location": {
+      "column": "9",
+      "line": "1281",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_OSTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79610@macro@ADC1_EMUX_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_EMUX_R",
+    "location": {
+      "column": "9",
+      "line": "1282",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_EMUX_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79680@macro@ADC1_USTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_USTAT_R",
+    "location": {
+      "column": "9",
+      "line": "1283",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_USTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79750@macro@ADC1_TSSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_TSSEL_R",
+    "location": {
+      "column": "9",
+      "line": "1284",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_TSSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79820@macro@ADC1_SSPRI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SSPRI_R",
+    "location": {
+      "column": "9",
+      "line": "1285",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SSPRI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79890@macro@ADC1_SPC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SPC_R",
+    "location": {
+      "column": "9",
+      "line": "1286",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SPC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@79960@macro@ADC1_PSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_PSSI_R",
+    "location": {
+      "column": "9",
+      "line": "1287",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_PSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80030@macro@ADC1_SAC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SAC_R",
+    "location": {
+      "column": "9",
+      "line": "1288",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SAC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80100@macro@ADC1_DCISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCISC_R",
+    "location": {
+      "column": "9",
+      "line": "1289",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80170@macro@ADC1_CTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_CTL_R",
+    "location": {
+      "column": "9",
+      "line": "1290",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_CTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80240@macro@ADC1_SSMUX0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SSMUX0_R",
+    "location": {
+      "column": "9",
+      "line": "1291",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SSMUX0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80310@macro@ADC1_SSCTL0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SSCTL0_R",
+    "location": {
+      "column": "9",
+      "line": "1292",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SSCTL0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80380@macro@ADC1_SSFIFO0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SSFIFO0_R",
+    "location": {
+      "column": "9",
+      "line": "1293",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_SSFIFO0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@80450@macro@ADC1_SSFSTAT0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_SSFSTAT0_R",
+    "location": {
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+      "line": "1294",
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
+    "name": "ADC1_SSDC1_R",
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+    "ID": "c:tm4c123gh6pm.h@81080@macro@ADC1_SSMUX2_R",
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+    },
+    "name": "ADC1_SSMUX2_R",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81150@macro@ADC1_SSCTL2_R",
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+    "display": "ADC1_SSCTL2_R",
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+    },
+    "name": "ADC1_SSCTL2_R",
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+  },
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+    },
+    "name": "ADC1_SSFIFO2_R",
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+    "scope": null
+  },
+  {
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+    "display": "ADC1_SSFSTAT2_R",
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+    },
+    "name": "ADC1_SSFSTAT2_R",
+    "origin": "user_include",
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+  },
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+    },
+    "name": "ADC1_SSOP2_R",
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+  {
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+    "display": "ADC1_SSDC2_R",
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+    },
+    "name": "ADC1_SSDC2_R",
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+  },
+  {
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+    "display": "ADC1_SSMUX3_R",
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+    },
+    "name": "ADC1_SSMUX3_R",
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+    "scope": null
+  },
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+    "display": "ADC1_SSCTL3_R",
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+    },
+    "name": "ADC1_SSCTL3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81640@macro@ADC1_SSFIFO3_R",
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+    },
+    "name": "ADC1_SSFIFO3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81710@macro@ADC1_SSFSTAT3_R",
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+    "display": "ADC1_SSFSTAT3_R",
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+    },
+    "name": "ADC1_SSFSTAT3_R",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81780@macro@ADC1_SSOP3_R",
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+    "display": "ADC1_SSOP3_R",
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+    },
+    "name": "ADC1_SSOP3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81850@macro@ADC1_SSDC3_R",
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+    "display": "ADC1_SSDC3_R",
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+    },
+    "name": "ADC1_SSDC3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81920@macro@ADC1_DCRIC_R",
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+    "display": "ADC1_DCRIC_R",
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+      "line": "1315",
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+    },
+    "name": "ADC1_DCRIC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@81990@macro@ADC1_DCCTL0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL0_R",
+    "location": {
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+      "line": "1316",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCTL0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82060@macro@ADC1_DCCTL1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL1_R",
+    "location": {
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+      "line": "1317",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCTL1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82130@macro@ADC1_DCCTL2_R",
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+    "defdec": "Def",
+    "display": "ADC1_DCCTL2_R",
+    "location": {
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+      "line": "1318",
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+    },
+    "name": "ADC1_DCCTL2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82200@macro@ADC1_DCCTL3_R",
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+    "defdec": "Def",
+    "display": "ADC1_DCCTL3_R",
+    "location": {
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+    },
+    "name": "ADC1_DCCTL3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82270@macro@ADC1_DCCTL4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL4_R",
+    "location": {
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+      "line": "1320",
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+    },
+    "name": "ADC1_DCCTL4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82340@macro@ADC1_DCCTL5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL5_R",
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+    },
+    "name": "ADC1_DCCTL5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82410@macro@ADC1_DCCTL6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL6_R",
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+      "line": "1322",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCTL6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82480@macro@ADC1_DCCTL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCTL7_R",
+    "location": {
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+      "line": "1323",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCTL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82550@macro@ADC1_DCCMP0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP0_R",
+    "location": {
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+      "line": "1324",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82620@macro@ADC1_DCCMP1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP1_R",
+    "location": {
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+      "line": "1325",
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+    },
+    "name": "ADC1_DCCMP1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82690@macro@ADC1_DCCMP2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP2_R",
+    "location": {
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+      "line": "1326",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82760@macro@ADC1_DCCMP3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP3_R",
+    "location": {
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+      "line": "1327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82830@macro@ADC1_DCCMP4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP4_R",
+    "location": {
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+      "line": "1328",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82900@macro@ADC1_DCCMP5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP5_R",
+    "location": {
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+      "line": "1329",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@82970@macro@ADC1_DCCMP6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP6_R",
+    "location": {
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+      "line": "1330",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@83040@macro@ADC1_DCCMP7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_DCCMP7_R",
+    "location": {
+      "column": "9",
+      "line": "1331",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_DCCMP7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@83110@macro@ADC1_PP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_PP_R",
+    "location": {
+      "column": "9",
+      "line": "1332",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_PP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@83180@macro@ADC1_PC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_PC_R",
+    "location": {
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+      "line": "1333",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_PC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@83250@macro@ADC1_CC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC1_CC_R",
+    "location": {
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+      "line": "1334",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC1_CC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@83524@macro@COMP_ACMIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACMIS_R",
+    "location": {
+      "column": "9",
+      "line": "1341",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACMIS_R",
+    "origin": "user_include",
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+    },
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+    },
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+  {
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+    },
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+    },
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+    },
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+  },
+  {
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+    "display": "USB0_FIFO5_R",
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+    },
+    "name": "USB0_FIFO5_R",
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+    "display": "USB0_FIFO6_R",
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+    },
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+    "scope": null
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+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB0_DEVCTL_R",
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+    },
+    "name": "USB0_DEVCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB0_TXFIFOSZ_R",
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+    },
+    "name": "USB0_TXFIFOSZ_R",
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+    "scope": null
+  },
+  {
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+    },
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+    "scope": null
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+  {
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+    },
+    "name": "USB0_TXFIFOADD_R",
+    "origin": "user_include",
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+  {
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+    },
+    "name": "USB0_RXFIFOADD_R",
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+  },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+    },
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+    },
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+    },
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+    "display": "USB0_RXCSRH6_R",
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+      "line": "1712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXCSRH6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@107932@macro@USB0_RXCOUNT6_R",
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+    "defdec": "Def",
+    "display": "USB0_RXCOUNT6_R",
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+      "column": "9",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXCOUNT6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108002@macro@USB0_TXTYPE6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXTYPE6_R",
+    "location": {
+      "column": "9",
+      "line": "1714",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXTYPE6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108071@macro@USB0_TXINTERVAL6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXINTERVAL6_R",
+    "location": {
+      "column": "9",
+      "line": "1715",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXINTERVAL6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108140@macro@USB0_RXTYPE6_R",
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+    "defdec": "Def",
+    "display": "USB0_RXTYPE6_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXTYPE6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108209@macro@USB0_RXINTERVAL6_R",
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+    "defdec": "Def",
+    "display": "USB0_RXINTERVAL6_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXINTERVAL6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108278@macro@USB0_TXMAXP7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXMAXP7_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXMAXP7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108348@macro@USB0_TXCSRL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXCSRL7_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXCSRL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108417@macro@USB0_TXCSRH7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXCSRH7_R",
+    "location": {
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+      "line": "1720",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXCSRH7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108486@macro@USB0_RXMAXP7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXMAXP7_R",
+    "location": {
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+      "line": "1721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXMAXP7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108556@macro@USB0_RXCSRL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXCSRL7_R",
+    "location": {
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+      "line": "1722",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXCSRL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108625@macro@USB0_RXCSRH7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXCSRH7_R",
+    "location": {
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+      "line": "1723",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXCSRH7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108694@macro@USB0_RXCOUNT7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXCOUNT7_R",
+    "location": {
+      "column": "9",
+      "line": "1724",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXCOUNT7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108764@macro@USB0_TXTYPE7_R",
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+    "defdec": "Def",
+    "display": "USB0_TXTYPE7_R",
+    "location": {
+      "column": "9",
+      "line": "1725",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXTYPE7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108833@macro@USB0_TXINTERVAL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXINTERVAL7_R",
+    "location": {
+      "column": "9",
+      "line": "1726",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXINTERVAL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108902@macro@USB0_RXTYPE7_R",
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+    "defdec": "Def",
+    "display": "USB0_RXTYPE7_R",
+    "location": {
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+      "line": "1727",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXTYPE7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@108971@macro@USB0_RXINTERVAL7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXINTERVAL7_R",
+    "location": {
+      "column": "9",
+      "line": "1728",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXINTERVAL7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109040@macro@USB0_RQPKTCOUNT1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT1_R",
+    "location": {
+      "column": "9",
+      "line": "1729",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109110@macro@USB0_RQPKTCOUNT2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT2_R",
+    "location": {
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+      "line": "1730",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109180@macro@USB0_RQPKTCOUNT3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT3_R",
+    "location": {
+      "column": "9",
+      "line": "1731",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109250@macro@USB0_RQPKTCOUNT4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT4_R",
+    "location": {
+      "column": "9",
+      "line": "1732",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109320@macro@USB0_RQPKTCOUNT5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT5_R",
+    "location": {
+      "column": "9",
+      "line": "1733",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109390@macro@USB0_RQPKTCOUNT6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT6_R",
+    "location": {
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+      "line": "1734",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109460@macro@USB0_RQPKTCOUNT7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RQPKTCOUNT7_R",
+    "location": {
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+      "line": "1735",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RQPKTCOUNT7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109530@macro@USB0_RXDPKTBUFDIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_RXDPKTBUFDIS_R",
+    "location": {
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+      "line": "1736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_RXDPKTBUFDIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109600@macro@USB0_TXDPKTBUFDIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_TXDPKTBUFDIS_R",
+    "location": {
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+      "line": "1737",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_TXDPKTBUFDIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109670@macro@USB0_EPC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_EPC_R",
+    "location": {
+      "column": "9",
+      "line": "1738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_EPC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109740@macro@USB0_EPCRIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_EPCRIS_R",
+    "location": {
+      "column": "9",
+      "line": "1739",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_EPCRIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109810@macro@USB0_EPCIM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_EPCIM_R",
+    "location": {
+      "column": "9",
+      "line": "1740",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_EPCIM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109880@macro@USB0_EPCISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_EPCISC_R",
+    "location": {
+      "column": "9",
+      "line": "1741",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_EPCISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@109950@macro@USB0_DRRIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_DRRIS_R",
+    "location": {
+      "column": "9",
+      "line": "1742",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_DRRIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110020@macro@USB0_DRIM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_DRIM_R",
+    "location": {
+      "column": "9",
+      "line": "1743",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_DRIM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110090@macro@USB0_DRISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_DRISC_R",
+    "location": {
+      "column": "9",
+      "line": "1744",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_DRISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110160@macro@USB0_GPCS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_GPCS_R",
+    "location": {
+      "column": "9",
+      "line": "1745",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_GPCS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110230@macro@USB0_VDC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_VDC_R",
+    "location": {
+      "column": "9",
+      "line": "1746",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_VDC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110300@macro@USB0_VDCRIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_VDCRIS_R",
+    "location": {
+      "column": "9",
+      "line": "1747",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_VDCRIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110370@macro@USB0_VDCIM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_VDCIM_R",
+    "location": {
+      "column": "9",
+      "line": "1748",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_VDCIM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110440@macro@USB0_VDCISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_VDCISC_R",
+    "location": {
+      "column": "9",
+      "line": "1749",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_VDCISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110510@macro@USB0_IDVRIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_IDVRIS_R",
+    "location": {
+      "column": "9",
+      "line": "1750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_IDVRIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110580@macro@USB0_IDVIM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_IDVIM_R",
+    "location": {
+      "column": "9",
+      "line": "1751",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_IDVIM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110650@macro@USB0_IDVISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_IDVISC_R",
+    "location": {
+      "column": "9",
+      "line": "1752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_IDVISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110720@macro@USB0_DMASEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB0_DMASEL_R",
+    "location": {
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+      "line": "1753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_DMASEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@110790@macro@USB0_PP_R",
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+    "defdec": "Def",
+    "display": "USB0_PP_R",
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+      "column": "9",
+      "line": "1754",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB0_PP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111063@macro@GPIO_PORTA_AHB_DATA_BITS_R",
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+    "display": "GPIO_PORTA_AHB_DATA_BITS_R",
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+      "line": "1761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DATA_BITS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111211@macro@GPIO_PORTA_AHB_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_DATA_R",
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+      "line": "1763",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111281@macro@GPIO_PORTA_AHB_DIR_R",
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+    "display": "GPIO_PORTA_AHB_DIR_R",
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+      "line": "1764",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DIR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111351@macro@GPIO_PORTA_AHB_IS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_IS_R",
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+      "column": "9",
+      "line": "1765",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_IS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111421@macro@GPIO_PORTA_AHB_IBE_R",
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+    "display": "GPIO_PORTA_AHB_IBE_R",
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+      "line": "1766",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111491@macro@GPIO_PORTA_AHB_IEV_R",
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+    "display": "GPIO_PORTA_AHB_IEV_R",
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+      "line": "1767",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111561@macro@GPIO_PORTA_AHB_IM_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_IM_R",
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+      "line": "1768",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111631@macro@GPIO_PORTA_AHB_RIS_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTA_AHB_RIS_R",
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+      "line": "1769",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111701@macro@GPIO_PORTA_AHB_MIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_MIS_R",
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+      "line": "1770",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_MIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111771@macro@GPIO_PORTA_AHB_ICR_R",
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+      "line": "1771",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_ICR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111841@macro@GPIO_PORTA_AHB_AFSEL_R",
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+      "line": "1772",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_AFSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111911@macro@GPIO_PORTA_AHB_DR2R_R",
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+    "display": "GPIO_PORTA_AHB_DR2R_R",
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+      "line": "1773",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DR2R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@111981@macro@GPIO_PORTA_AHB_DR4R_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_DR4R_R",
+    "location": {
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+      "line": "1774",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DR4R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112051@macro@GPIO_PORTA_AHB_DR8R_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_DR8R_R",
+    "location": {
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+      "line": "1775",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DR8R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112121@macro@GPIO_PORTA_AHB_ODR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_ODR_R",
+    "location": {
+      "column": "9",
+      "line": "1776",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_ODR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112191@macro@GPIO_PORTA_AHB_PUR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_PUR_R",
+    "location": {
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+      "line": "1777",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_PUR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112261@macro@GPIO_PORTA_AHB_PDR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_PDR_R",
+    "location": {
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+      "line": "1778",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_PDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112331@macro@GPIO_PORTA_AHB_SLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_SLR_R",
+    "location": {
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+      "line": "1779",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_SLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112401@macro@GPIO_PORTA_AHB_DEN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_DEN_R",
+    "location": {
+      "column": "9",
+      "line": "1780",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112471@macro@GPIO_PORTA_AHB_LOCK_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_LOCK_R",
+    "location": {
+      "column": "9",
+      "line": "1781",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_LOCK_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112541@macro@GPIO_PORTA_AHB_CR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_CR_R",
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+      "line": "1782",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_CR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112611@macro@GPIO_PORTA_AHB_AMSEL_R",
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+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_AMSEL_R",
+    "location": {
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+      "line": "1783",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_AMSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112681@macro@GPIO_PORTA_AHB_PCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_PCTL_R",
+    "location": {
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+      "line": "1784",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_PCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112751@macro@GPIO_PORTA_AHB_ADCCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_ADCCTL_R",
+    "location": {
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+      "line": "1785",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@112821@macro@GPIO_PORTA_AHB_DMACTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_AHB_DMACTL_R",
+    "location": {
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+      "line": "1786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTA_AHB_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113094@macro@GPIO_PORTB_AHB_DATA_BITS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DATA_BITS_R",
+    "location": {
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+      "line": "1793",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DATA_BITS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113242@macro@GPIO_PORTB_AHB_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DATA_R",
+    "location": {
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+      "line": "1795",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113312@macro@GPIO_PORTB_AHB_DIR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DIR_R",
+    "location": {
+      "column": "9",
+      "line": "1796",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DIR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113382@macro@GPIO_PORTB_AHB_IS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_IS_R",
+    "location": {
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+      "line": "1797",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_IS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113452@macro@GPIO_PORTB_AHB_IBE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_IBE_R",
+    "location": {
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+      "line": "1798",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_IBE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113522@macro@GPIO_PORTB_AHB_IEV_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_IEV_R",
+    "location": {
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+      "line": "1799",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_IEV_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113592@macro@GPIO_PORTB_AHB_IM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_IM_R",
+    "location": {
+      "column": "9",
+      "line": "1800",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113662@macro@GPIO_PORTB_AHB_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "1801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113732@macro@GPIO_PORTB_AHB_MIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_MIS_R",
+    "location": {
+      "column": "9",
+      "line": "1802",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_MIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113802@macro@GPIO_PORTB_AHB_ICR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_ICR_R",
+    "location": {
+      "column": "9",
+      "line": "1803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_ICR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113872@macro@GPIO_PORTB_AHB_AFSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_AFSEL_R",
+    "location": {
+      "column": "9",
+      "line": "1804",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_AFSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@113942@macro@GPIO_PORTB_AHB_DR2R_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DR2R_R",
+    "location": {
+      "column": "9",
+      "line": "1805",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DR2R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114012@macro@GPIO_PORTB_AHB_DR4R_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DR4R_R",
+    "location": {
+      "column": "9",
+      "line": "1806",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114082@macro@GPIO_PORTB_AHB_DR8R_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTB_AHB_DR8R_R",
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+      "line": "1807",
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+    },
+    "name": "GPIO_PORTB_AHB_DR8R_R",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114152@macro@GPIO_PORTB_AHB_ODR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_ODR_R",
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+      "line": "1808",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_ODR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114222@macro@GPIO_PORTB_AHB_PUR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_PUR_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_PUR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114292@macro@GPIO_PORTB_AHB_PDR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_PDR_R",
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+      "line": "1810",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_PDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114362@macro@GPIO_PORTB_AHB_SLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_SLR_R",
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+      "line": "1811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_SLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114432@macro@GPIO_PORTB_AHB_DEN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DEN_R",
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+      "line": "1812",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114502@macro@GPIO_PORTB_AHB_LOCK_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_LOCK_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_LOCK_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114572@macro@GPIO_PORTB_AHB_CR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_CR_R",
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+      "line": "1814",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_CR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114642@macro@GPIO_PORTB_AHB_AMSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_AMSEL_R",
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+      "line": "1815",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_AMSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114712@macro@GPIO_PORTB_AHB_PCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_PCTL_R",
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+      "line": "1816",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_PCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114782@macro@GPIO_PORTB_AHB_ADCCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_ADCCTL_R",
+    "location": {
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+      "line": "1817",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@114852@macro@GPIO_PORTB_AHB_DMACTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_AHB_DMACTL_R",
+    "location": {
+      "column": "9",
+      "line": "1818",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTB_AHB_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115125@macro@GPIO_PORTC_AHB_DATA_BITS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_DATA_BITS_R",
+    "location": {
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+      "line": "1825",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DATA_BITS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115273@macro@GPIO_PORTC_AHB_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_DATA_R",
+    "location": {
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+      "line": "1827",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115343@macro@GPIO_PORTC_AHB_DIR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_DIR_R",
+    "location": {
+      "column": "9",
+      "line": "1828",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DIR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115413@macro@GPIO_PORTC_AHB_IS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_IS_R",
+    "location": {
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+      "line": "1829",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_IS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115483@macro@GPIO_PORTC_AHB_IBE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_IBE_R",
+    "location": {
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+      "line": "1830",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_IBE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115553@macro@GPIO_PORTC_AHB_IEV_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_IEV_R",
+    "location": {
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+      "line": "1831",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_IEV_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115623@macro@GPIO_PORTC_AHB_IM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_IM_R",
+    "location": {
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+      "line": "1832",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115693@macro@GPIO_PORTC_AHB_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "1833",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115763@macro@GPIO_PORTC_AHB_MIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_MIS_R",
+    "location": {
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+      "line": "1834",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_MIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115833@macro@GPIO_PORTC_AHB_ICR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_ICR_R",
+    "location": {
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+      "line": "1835",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_ICR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115903@macro@GPIO_PORTC_AHB_AFSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_AFSEL_R",
+    "location": {
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+      "line": "1836",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_AFSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@115973@macro@GPIO_PORTC_AHB_DR2R_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_DR2R_R",
+    "location": {
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+      "line": "1837",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DR2R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116043@macro@GPIO_PORTC_AHB_DR4R_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTC_AHB_DR4R_R",
+    "location": {
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+      "line": "1838",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116113@macro@GPIO_PORTC_AHB_DR8R_R",
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+    "location": {
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+      "line": "1839",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DR8R_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116183@macro@GPIO_PORTC_AHB_ODR_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTC_AHB_ODR_R",
+    "location": {
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+      "line": "1840",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_ODR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116253@macro@GPIO_PORTC_AHB_PUR_R",
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+    "display": "GPIO_PORTC_AHB_PUR_R",
+    "location": {
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+      "line": "1841",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_PUR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116323@macro@GPIO_PORTC_AHB_PDR_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTC_AHB_PDR_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_PDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116393@macro@GPIO_PORTC_AHB_SLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_SLR_R",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_SLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116463@macro@GPIO_PORTC_AHB_DEN_R",
+    "What": "MacroDef",
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+    "display": "GPIO_PORTC_AHB_DEN_R",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DEN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116533@macro@GPIO_PORTC_AHB_LOCK_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_LOCK_R",
+    "location": {
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+      "line": "1845",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_LOCK_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116603@macro@GPIO_PORTC_AHB_CR_R",
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+    "display": "GPIO_PORTC_AHB_CR_R",
+    "location": {
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+      "line": "1846",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_CR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116673@macro@GPIO_PORTC_AHB_AMSEL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_AMSEL_R",
+    "location": {
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+      "line": "1847",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_AMSEL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116743@macro@GPIO_PORTC_AHB_PCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_PCTL_R",
+    "location": {
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+      "line": "1848",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_PCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116813@macro@GPIO_PORTC_AHB_ADCCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_ADCCTL_R",
+    "location": {
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+      "line": "1849",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_ADCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@116883@macro@GPIO_PORTC_AHB_DMACTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_AHB_DMACTL_R",
+    "location": {
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+      "line": "1850",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTC_AHB_DMACTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@117156@macro@GPIO_PORTD_AHB_DATA_BITS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTD_AHB_DATA_BITS_R",
+    "location": {
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+      "line": "1857",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PORTD_AHB_DATA_BITS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@117304@macro@GPIO_PORTD_AHB_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTD_AHB_DATA_R",
+    "location": {
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+      "line": "1859",
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDONE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@123668@macro@EEPROM_EESUPP_R",
+    "What": "MacroDef",
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+    "display": "EEPROM_EESUPP_R",
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+      "line": "1959",
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+    },
+    "name": "EEPROM_EESUPP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@123738@macro@EEPROM_EEUNLOCK_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEUNLOCK_R",
+    "location": {
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+      "line": "1960",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEUNLOCK_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@123808@macro@EEPROM_EEPROT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_R",
+    "location": {
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+      "line": "1961",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@123878@macro@EEPROM_EEPASS0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS0_R",
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+      "line": "1962",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@123948@macro@EEPROM_EEPASS1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS1_R",
+    "location": {
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+      "line": "1963",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124018@macro@EEPROM_EEPASS2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS2_R",
+    "location": {
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+      "line": "1964",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124088@macro@EEPROM_EEINT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEINT_R",
+    "location": {
+      "column": "9",
+      "line": "1965",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEINT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124158@macro@EEPROM_EEHIDE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEHIDE_R",
+    "location": {
+      "column": "9",
+      "line": "1966",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEHIDE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124228@macro@EEPROM_EEDBGME_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDBGME_R",
+    "location": {
+      "column": "9",
+      "line": "1967",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDBGME_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124298@macro@EEPROM_PP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_PP_R",
+    "location": {
+      "column": "9",
+      "line": "1968",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_PP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124587@macro@SYSEXC_RIS_R",
+    "What": "MacroDef",
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+    "display": "SYSEXC_RIS_R",
+    "location": {
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+      "line": "1975",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSEXC_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124657@macro@SYSEXC_IM_R",
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+    "defdec": "Def",
+    "display": "SYSEXC_IM_R",
+    "location": {
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+      "line": "1976",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSEXC_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@124727@macro@SYSEXC_MIS_R",
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+    "location": {
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+      "line": "1977",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSEXC_MIS_R",
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+  },
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+      "line": "1978",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSEXC_IC_R",
+    "origin": "user_include",
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+  },
+  {
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+    "location": {
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+      "line": "1985",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCC_R",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125148@macro@HIB_RTCM0_R",
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+    },
+    "name": "HIB_RTCM0_R",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125218@macro@HIB_RTCLD_R",
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+      "line": "1987",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCLD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125288@macro@HIB_CTL_R",
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+    "defdec": "Def",
+    "display": "HIB_CTL_R",
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+      "line": "1988",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125358@macro@HIB_IM_R",
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+      "line": "1989",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125428@macro@HIB_RIS_R",
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+    "display": "HIB_RIS_R",
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+      "line": "1990",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125498@macro@HIB_MIS_R",
+    "What": "MacroDef",
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+    "display": "HIB_MIS_R",
+    "location": {
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+      "line": "1991",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_MIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125568@macro@HIB_IC_R",
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+    "display": "HIB_IC_R",
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+      "line": "1992",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125638@macro@HIB_RTCT_R",
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+    "defdec": "Def",
+    "display": "HIB_RTCT_R",
+    "location": {
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+      "line": "1993",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125708@macro@HIB_RTCSS_R",
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+    "display": "HIB_RTCSS_R",
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+      "line": "1994",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCSS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@125778@macro@HIB_DATA_R",
+    "What": "MacroDef",
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+    "display": "HIB_DATA_R",
+    "location": {
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+      "line": "1995",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126053@macro@FLASH_FMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMA_R",
+    "location": {
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+      "line": "2002",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126123@macro@FLASH_FMD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMD_R",
+    "location": {
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+      "line": "2003",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126193@macro@FLASH_FMC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_R",
+    "location": {
+      "column": "9",
+      "line": "2004",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126263@macro@FLASH_FCRIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_R",
+    "location": {
+      "column": "9",
+      "line": "2005",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126333@macro@FLASH_FCIM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_R",
+    "location": {
+      "column": "9",
+      "line": "2006",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126403@macro@FLASH_FCMISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_R",
+    "location": {
+      "column": "9",
+      "line": "2007",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126473@macro@FLASH_FMC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC2_R",
+    "location": {
+      "column": "9",
+      "line": "2008",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126543@macro@FLASH_FWBVAL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FWBVAL_R",
+    "location": {
+      "column": "9",
+      "line": "2009",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FWBVAL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126613@macro@FLASH_FWBN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FWBN_R",
+    "location": {
+      "column": "9",
+      "line": "2010",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FWBN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126683@macro@FLASH_FSIZE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FSIZE_R",
+    "location": {
+      "column": "9",
+      "line": "2011",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FSIZE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126753@macro@FLASH_SSIZE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_SSIZE_R",
+    "location": {
+      "column": "9",
+      "line": "2012",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_SSIZE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126823@macro@FLASH_ROMSWMAP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_ROMSWMAP_R",
+    "location": {
+      "column": "9",
+      "line": "2013",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_ROMSWMAP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126893@macro@FLASH_RMCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_RMCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2014",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_RMCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@126963@macro@FLASH_BOOTCFG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_R",
+    "location": {
+      "column": "9",
+      "line": "2015",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127033@macro@FLASH_USERREG0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG0_R",
+    "location": {
+      "column": "9",
+      "line": "2016",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127103@macro@FLASH_USERREG1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG1_R",
+    "location": {
+      "column": "9",
+      "line": "2017",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127173@macro@FLASH_USERREG2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG2_R",
+    "location": {
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+      "line": "2018",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127243@macro@FLASH_USERREG3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG3_R",
+    "location": {
+      "column": "9",
+      "line": "2019",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127313@macro@FLASH_FMPRE0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPRE0_R",
+    "location": {
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+      "line": "2020",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPRE0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127383@macro@FLASH_FMPRE1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPRE1_R",
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+      "line": "2021",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPRE1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127453@macro@FLASH_FMPRE2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPRE2_R",
+    "location": {
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+    },
+    "name": "FLASH_FMPRE2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127523@macro@FLASH_FMPRE3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPRE3_R",
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+      "line": "2023",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPRE3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127593@macro@FLASH_FMPPE0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPPE0_R",
+    "location": {
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+      "line": "2024",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPPE0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127663@macro@FLASH_FMPPE1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPPE1_R",
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+      "line": "2025",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPPE1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127733@macro@FLASH_FMPPE2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPPE2_R",
+    "location": {
+      "column": "9",
+      "line": "2026",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPPE2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@127803@macro@FLASH_FMPPE3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMPPE3_R",
+    "location": {
+      "column": "9",
+      "line": "2027",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMPPE3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128083@macro@SYSCTL_DID0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_R",
+    "location": {
+      "column": "9",
+      "line": "2034",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128153@macro@SYSCTL_DID1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_R",
+    "location": {
+      "column": "9",
+      "line": "2035",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128223@macro@SYSCTL_DC0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_R",
+    "location": {
+      "column": "9",
+      "line": "2036",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128293@macro@SYSCTL_DC1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_R",
+    "location": {
+      "column": "9",
+      "line": "2037",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128363@macro@SYSCTL_DC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_R",
+    "location": {
+      "column": "9",
+      "line": "2038",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128433@macro@SYSCTL_DC3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_R",
+    "location": {
+      "column": "9",
+      "line": "2039",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128503@macro@SYSCTL_DC4_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_R",
+    "location": {
+      "column": "9",
+      "line": "2040",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128573@macro@SYSCTL_DC5_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_R",
+    "location": {
+      "column": "9",
+      "line": "2041",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128643@macro@SYSCTL_DC6_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_R",
+    "location": {
+      "column": "9",
+      "line": "2042",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128713@macro@SYSCTL_DC7_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_R",
+    "location": {
+      "column": "9",
+      "line": "2043",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC7_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128783@macro@SYSCTL_DC8_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_R",
+    "location": {
+      "column": "9",
+      "line": "2044",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128853@macro@SYSCTL_PBORCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PBORCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2045",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PBORCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128923@macro@SYSCTL_SRCR0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_R",
+    "location": {
+      "column": "9",
+      "line": "2046",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@128993@macro@SYSCTL_SRCR1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_R",
+    "location": {
+      "column": "9",
+      "line": "2047",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129063@macro@SYSCTL_SRCR2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_R",
+    "location": {
+      "column": "9",
+      "line": "2048",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129133@macro@SYSCTL_RIS_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_R",
+    "location": {
+      "column": "9",
+      "line": "2049",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129203@macro@SYSCTL_IMC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_R",
+    "location": {
+      "column": "9",
+      "line": "2050",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129273@macro@SYSCTL_MISC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_R",
+    "location": {
+      "column": "9",
+      "line": "2051",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129343@macro@SYSCTL_RESC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_R",
+    "location": {
+      "column": "9",
+      "line": "2052",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129413@macro@SYSCTL_RCC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_R",
+    "location": {
+      "column": "9",
+      "line": "2053",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129483@macro@SYSCTL_GPIOHBCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2054",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129553@macro@SYSCTL_RCC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_R",
+    "location": {
+      "column": "9",
+      "line": "2055",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129623@macro@SYSCTL_MOSCCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2056",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MOSCCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129693@macro@SYSCTL_RCGC0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_R",
+    "location": {
+      "column": "9",
+      "line": "2057",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129763@macro@SYSCTL_RCGC1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_R",
+    "location": {
+      "column": "9",
+      "line": "2058",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129833@macro@SYSCTL_RCGC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_R",
+    "location": {
+      "column": "9",
+      "line": "2059",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129903@macro@SYSCTL_SCGC0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_R",
+    "location": {
+      "column": "9",
+      "line": "2060",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@129973@macro@SYSCTL_SCGC1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_R",
+    "location": {
+      "column": "9",
+      "line": "2061",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130043@macro@SYSCTL_SCGC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_R",
+    "location": {
+      "column": "9",
+      "line": "2062",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130113@macro@SYSCTL_DCGC0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_R",
+    "location": {
+      "column": "9",
+      "line": "2063",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130183@macro@SYSCTL_DCGC1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_R",
+    "location": {
+      "column": "9",
+      "line": "2064",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130253@macro@SYSCTL_DCGC2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_R",
+    "location": {
+      "column": "9",
+      "line": "2065",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130323@macro@SYSCTL_DSLPCLKCFG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_R",
+    "location": {
+      "column": "9",
+      "line": "2066",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130393@macro@SYSCTL_SYSPROP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SYSPROP_R",
+    "location": {
+      "column": "9",
+      "line": "2067",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SYSPROP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130463@macro@SYSCTL_PIOSCCAL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_R",
+    "location": {
+      "column": "9",
+      "line": "2068",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130533@macro@SYSCTL_PIOSCSTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_R",
+    "location": {
+      "column": "9",
+      "line": "2069",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130603@macro@SYSCTL_PLLFREQ0_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_R",
+    "location": {
+      "column": "9",
+      "line": "2070",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130673@macro@SYSCTL_PLLFREQ1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_R",
+    "location": {
+      "column": "9",
+      "line": "2071",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130743@macro@SYSCTL_PLLSTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLSTAT_R",
+    "location": {
+      "column": "9",
+      "line": "2072",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLSTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130813@macro@SYSCTL_SLPPWRCFG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_R",
+    "location": {
+      "column": "9",
+      "line": "2073",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130883@macro@SYSCTL_DSLPPWRCFG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_R",
+    "location": {
+      "column": "9",
+      "line": "2074",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@130953@macro@SYSCTL_DC9_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_R",
+    "location": {
+      "column": "9",
+      "line": "2075",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131023@macro@SYSCTL_NVMSTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NVMSTAT_R",
+    "location": {
+      "column": "9",
+      "line": "2076",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_NVMSTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131093@macro@SYSCTL_LDOSPCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2077",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131163@macro@SYSCTL_LDODPCTL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_R",
+    "location": {
+      "column": "9",
+      "line": "2078",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131233@macro@SYSCTL_PPWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD_R",
+    "location": {
+      "column": "9",
+      "line": "2079",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131303@macro@SYSCTL_PPTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2080",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131373@macro@SYSCTL_PPGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2081",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131443@macro@SYSCTL_PPDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2082",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131513@macro@SYSCTL_PPHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2083",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131583@macro@SYSCTL_PPUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_R",
+    "location": {
+      "column": "9",
+      "line": "2084",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131653@macro@SYSCTL_PPSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2085",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131723@macro@SYSCTL_PPI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2086",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131793@macro@SYSCTL_PPUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2087",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131863@macro@SYSCTL_PPCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2088",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@131933@macro@SYSCTL_PPADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC_R",
+    "location": {
+      "column": "9",
+      "line": "2089",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132003@macro@SYSCTL_PPACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2090",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132073@macro@SYSCTL_PPPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2091",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132143@macro@SYSCTL_PPQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2092",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132213@macro@SYSCTL_PPEEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2093",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPEEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132283@macro@SYSCTL_PPWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2094",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132353@macro@SYSCTL_SRWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD_R",
+    "location": {
+      "column": "9",
+      "line": "2095",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132423@macro@SYSCTL_SRTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2096",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132493@macro@SYSCTL_SRGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2097",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132563@macro@SYSCTL_SRDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2098",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132633@macro@SYSCTL_SRHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2099",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132703@macro@SYSCTL_SRUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R",
+    "location": {
+      "column": "9",
+      "line": "2100",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132773@macro@SYSCTL_SRSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2101",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132843@macro@SYSCTL_SRI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2102",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132913@macro@SYSCTL_SRUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2103",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@132983@macro@SYSCTL_SRCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2104",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133053@macro@SYSCTL_SRADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC_R",
+    "location": {
+      "column": "9",
+      "line": "2105",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133123@macro@SYSCTL_SRACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2106",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133193@macro@SYSCTL_SRPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2107",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133263@macro@SYSCTL_SRQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2108",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133333@macro@SYSCTL_SREEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2109",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SREEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133403@macro@SYSCTL_SRWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2110",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133473@macro@SYSCTL_RCGCWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD_R",
+    "location": {
+      "column": "9",
+      "line": "2111",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133543@macro@SYSCTL_RCGCTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2112",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133613@macro@SYSCTL_RCGCGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2113",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133683@macro@SYSCTL_RCGCDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2114",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133753@macro@SYSCTL_RCGCHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2115",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133823@macro@SYSCTL_RCGCUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R",
+    "location": {
+      "column": "9",
+      "line": "2116",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133893@macro@SYSCTL_RCGCSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2117",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@133963@macro@SYSCTL_RCGCI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2118",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134033@macro@SYSCTL_RCGCUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2119",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134103@macro@SYSCTL_RCGCCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2120",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134173@macro@SYSCTL_RCGCADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC_R",
+    "location": {
+      "column": "9",
+      "line": "2121",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134243@macro@SYSCTL_RCGCACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2122",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134313@macro@SYSCTL_RCGCPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2123",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134383@macro@SYSCTL_RCGCQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2124",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134453@macro@SYSCTL_RCGCEEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2125",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCEEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134523@macro@SYSCTL_RCGCWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2126",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134593@macro@SYSCTL_SCGCWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD_R",
+    "location": {
+      "column": "9",
+      "line": "2127",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134663@macro@SYSCTL_SCGCTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2128",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134733@macro@SYSCTL_SCGCGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2129",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134803@macro@SYSCTL_SCGCDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2130",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134873@macro@SYSCTL_SCGCHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2131",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@134943@macro@SYSCTL_SCGCUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_R",
+    "location": {
+      "column": "9",
+      "line": "2132",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135013@macro@SYSCTL_SCGCSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2133",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135083@macro@SYSCTL_SCGCI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2134",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135153@macro@SYSCTL_SCGCUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2135",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135223@macro@SYSCTL_SCGCCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2136",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135293@macro@SYSCTL_SCGCADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC_R",
+    "location": {
+      "column": "9",
+      "line": "2137",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135363@macro@SYSCTL_SCGCACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2138",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135433@macro@SYSCTL_SCGCPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2139",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135503@macro@SYSCTL_SCGCQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2140",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135573@macro@SYSCTL_SCGCEEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2141",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCEEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135643@macro@SYSCTL_SCGCWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2142",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135713@macro@SYSCTL_DCGCWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD_R",
+    "location": {
+      "column": "9",
+      "line": "2143",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135783@macro@SYSCTL_DCGCTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2144",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135853@macro@SYSCTL_DCGCGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2145",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135923@macro@SYSCTL_DCGCDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2146",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@135993@macro@SYSCTL_DCGCHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2147",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136063@macro@SYSCTL_DCGCUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_R",
+    "location": {
+      "column": "9",
+      "line": "2148",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136133@macro@SYSCTL_DCGCSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2149",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136203@macro@SYSCTL_DCGCI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2150",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136273@macro@SYSCTL_DCGCUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2151",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136343@macro@SYSCTL_DCGCCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2152",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136413@macro@SYSCTL_DCGCADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC_R",
+    "location": {
+      "column": "9",
+      "line": "2153",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136483@macro@SYSCTL_DCGCACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2154",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136553@macro@SYSCTL_DCGCPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2155",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136623@macro@SYSCTL_DCGCQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2156",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136693@macro@SYSCTL_DCGCEEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2157",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCEEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136763@macro@SYSCTL_DCGCWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2158",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136833@macro@SYSCTL_PRWD_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD_R",
+    "location": {
+      "column": "9",
+      "line": "2159",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWD_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136903@macro@SYSCTL_PRTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2160",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@136973@macro@SYSCTL_PRGPIO_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R",
+    "location": {
+      "column": "9",
+      "line": "2161",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137043@macro@SYSCTL_PRDMA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRDMA_R",
+    "location": {
+      "column": "9",
+      "line": "2162",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRDMA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137113@macro@SYSCTL_PRHIB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRHIB_R",
+    "location": {
+      "column": "9",
+      "line": "2163",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRHIB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137183@macro@SYSCTL_PRUART_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R",
+    "location": {
+      "column": "9",
+      "line": "2164",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137253@macro@SYSCTL_PRSSI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R",
+    "location": {
+      "column": "9",
+      "line": "2165",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRSSI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137323@macro@SYSCTL_PRI2C_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R",
+    "location": {
+      "column": "9",
+      "line": "2166",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRI2C_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137393@macro@SYSCTL_PRUSB_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUSB_R",
+    "location": {
+      "column": "9",
+      "line": "2167",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUSB_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137463@macro@SYSCTL_PRCAN_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN_R",
+    "location": {
+      "column": "9",
+      "line": "2168",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRCAN_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137533@macro@SYSCTL_PRADC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC_R",
+    "location": {
+      "column": "9",
+      "line": "2169",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRADC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137603@macro@SYSCTL_PRACMP_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRACMP_R",
+    "location": {
+      "column": "9",
+      "line": "2170",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRACMP_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137673@macro@SYSCTL_PRPWM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM_R",
+    "location": {
+      "column": "9",
+      "line": "2171",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRPWM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137743@macro@SYSCTL_PRQEI_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI_R",
+    "location": {
+      "column": "9",
+      "line": "2172",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRQEI_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137813@macro@SYSCTL_PREEPROM_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREEPROM_R",
+    "location": {
+      "column": "9",
+      "line": "2173",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PREEPROM_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@137883@macro@SYSCTL_PRWTIMER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R",
+    "location": {
+      "column": "9",
+      "line": "2174",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138173@macro@UDMA_STAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_R",
+    "location": {
+      "column": "9",
+      "line": "2181",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138243@macro@UDMA_CFG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CFG_R",
+    "location": {
+      "column": "9",
+      "line": "2182",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CFG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138313@macro@UDMA_CTLBASE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CTLBASE_R",
+    "location": {
+      "column": "9",
+      "line": "2183",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CTLBASE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138383@macro@UDMA_ALTBASE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTBASE_R",
+    "location": {
+      "column": "9",
+      "line": "2184",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTBASE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138453@macro@UDMA_WAITSTAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_WAITSTAT_R",
+    "location": {
+      "column": "9",
+      "line": "2185",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_WAITSTAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138523@macro@UDMA_SWREQ_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_SWREQ_R",
+    "location": {
+      "column": "9",
+      "line": "2186",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_SWREQ_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138593@macro@UDMA_USEBURSTSET_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_USEBURSTSET_R",
+    "location": {
+      "column": "9",
+      "line": "2187",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_USEBURSTSET_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138663@macro@UDMA_USEBURSTCLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_USEBURSTCLR_R",
+    "location": {
+      "column": "9",
+      "line": "2188",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_USEBURSTCLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138733@macro@UDMA_REQMASKSET_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_REQMASKSET_R",
+    "location": {
+      "column": "9",
+      "line": "2189",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_REQMASKSET_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138803@macro@UDMA_REQMASKCLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_REQMASKCLR_R",
+    "location": {
+      "column": "9",
+      "line": "2190",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_REQMASKCLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138873@macro@UDMA_ENASET_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ENASET_R",
+    "location": {
+      "column": "9",
+      "line": "2191",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ENASET_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@138943@macro@UDMA_ENACLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ENACLR_R",
+    "location": {
+      "column": "9",
+      "line": "2192",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ENACLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@139013@macro@UDMA_ALTSET_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTSET_R",
+    "location": {
+      "column": "9",
+      "line": "2193",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTSET_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@139083@macro@UDMA_ALTCLR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTCLR_R",
+    "location": {
+      "column": "9",
+      "line": "2194",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTCLR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@139153@macro@UDMA_PRIOSET_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_PRIOSET_R",
+    "location": {
+      "column": "9",
+      "line": "2195",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_PRIOSET_R",
+    "origin": "user_include",
+    "scope": null
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+    "ID": "c:tm4c123gh6pm.h@145594@macro@NVIC_SYS_PRI3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_R",
+    "location": {
+      "column": "9",
+      "line": "2293",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@145664@macro@NVIC_SYS_HND_CTRL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_R",
+    "location": {
+      "column": "9",
+      "line": "2294",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@145734@macro@NVIC_FAULT_STAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_R",
+    "location": {
+      "column": "9",
+      "line": "2295",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@145804@macro@NVIC_HFAULT_STAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_HFAULT_STAT_R",
+    "location": {
+      "column": "9",
+      "line": "2296",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_HFAULT_STAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@145874@macro@NVIC_DEBUG_STAT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_R",
+    "location": {
+      "column": "9",
+      "line": "2297",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@145944@macro@NVIC_MM_ADDR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MM_ADDR_R",
+    "location": {
+      "column": "9",
+      "line": "2298",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MM_ADDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146014@macro@NVIC_FAULT_ADDR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_ADDR_R",
+    "location": {
+      "column": "9",
+      "line": "2299",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_ADDR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146084@macro@NVIC_CPAC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_R",
+    "location": {
+      "column": "9",
+      "line": "2300",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146154@macro@NVIC_MPU_TYPE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_R",
+    "location": {
+      "column": "9",
+      "line": "2301",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146224@macro@NVIC_MPU_CTRL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_CTRL_R",
+    "location": {
+      "column": "9",
+      "line": "2302",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_CTRL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146294@macro@NVIC_MPU_NUMBER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_NUMBER_R",
+    "location": {
+      "column": "9",
+      "line": "2303",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_NUMBER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146364@macro@NVIC_MPU_BASE_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_R",
+    "location": {
+      "column": "9",
+      "line": "2304",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146434@macro@NVIC_MPU_ATTR_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_R",
+    "location": {
+      "column": "9",
+      "line": "2305",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146504@macro@NVIC_MPU_BASE1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE1_R",
+    "location": {
+      "column": "9",
+      "line": "2306",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146574@macro@NVIC_MPU_ATTR1_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR1_R",
+    "location": {
+      "column": "9",
+      "line": "2307",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR1_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146644@macro@NVIC_MPU_BASE2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE2_R",
+    "location": {
+      "column": "9",
+      "line": "2308",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146714@macro@NVIC_MPU_ATTR2_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR2_R",
+    "location": {
+      "column": "9",
+      "line": "2309",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR2_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146784@macro@NVIC_MPU_BASE3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE3_R",
+    "location": {
+      "column": "9",
+      "line": "2310",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146854@macro@NVIC_MPU_ATTR3_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR3_R",
+    "location": {
+      "column": "9",
+      "line": "2311",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146924@macro@NVIC_DBG_CTRL_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DBG_CTRL_R",
+    "location": {
+      "column": "9",
+      "line": "2312",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DBG_CTRL_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@146994@macro@NVIC_DBG_XFER_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DBG_XFER_R",
+    "location": {
+      "column": "9",
+      "line": "2313",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DBG_XFER_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147064@macro@NVIC_DBG_DATA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DBG_DATA_R",
+    "location": {
+      "column": "9",
+      "line": "2314",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DBG_DATA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147134@macro@NVIC_DBG_INT_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DBG_INT_R",
+    "location": {
+      "column": "9",
+      "line": "2315",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DBG_INT_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147204@macro@NVIC_SW_TRIG_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SW_TRIG_R",
+    "location": {
+      "column": "9",
+      "line": "2316",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SW_TRIG_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147274@macro@NVIC_FPCC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FPCC_R",
+    "location": {
+      "column": "9",
+      "line": "2317",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FPCC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147344@macro@NVIC_FPCA_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FPCA_R",
+    "location": {
+      "column": "9",
+      "line": "2318",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FPCA_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147414@macro@NVIC_FPDSC_R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FPDSC_R",
+    "location": {
+      "column": "9",
+      "line": "2319",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FPDSC_R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147733@macro@WDT_LOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_LOAD_M",
+    "location": {
+      "column": "9",
+      "line": "2326",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_LOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@147801@macro@WDT_LOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_LOAD_S",
+    "location": {
+      "column": "9",
+      "line": "2327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_LOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148086@macro@WDT_VALUE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_VALUE_M",
+    "location": {
+      "column": "9",
+      "line": "2334",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_VALUE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148149@macro@WDT_VALUE_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_VALUE_S",
+    "location": {
+      "column": "9",
+      "line": "2335",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_VALUE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148432@macro@WDT_CTL_WRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_CTL_WRC",
+    "location": {
+      "column": "9",
+      "line": "2342",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_CTL_WRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148495@macro@WDT_CTL_INTTYPE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_CTL_INTTYPE",
+    "location": {
+      "column": "9",
+      "line": "2343",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_CTL_INTTYPE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148567@macro@WDT_CTL_RESEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_CTL_RESEN",
+    "location": {
+      "column": "9",
+      "line": "2344",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_CTL_RESEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148637@macro@WDT_CTL_INTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_CTL_INTEN",
+    "location": {
+      "column": "9",
+      "line": "2345",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_CTL_INTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@148959@macro@WDT_ICR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_ICR_M",
+    "location": {
+      "column": "9",
+      "line": "2352",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_ICR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@149032@macro@WDT_ICR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_ICR_S",
+    "location": {
+      "column": "9",
+      "line": "2353",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_ICR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@149315@macro@WDT_RIS_WDTRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_RIS_WDTRIS",
+    "location": {
+      "column": "9",
+      "line": "2360",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_RIS_WDTRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@149641@macro@WDT_MIS_WDTMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_MIS_WDTMIS",
+    "location": {
+      "column": "9",
+      "line": "2367",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_MIS_WDTMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@149971@macro@WDT_TEST_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_TEST_STALL",
+    "location": {
+      "column": "9",
+      "line": "2374",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_TEST_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@150290@macro@WDT_LOCK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_LOCK_M",
+    "location": {
+      "column": "9",
+      "line": "2381",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "WDT_LOCK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@150352@macro@WDT_LOCK_UNLOCKED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WDT_LOCK_UNLOCKED",
+    "location": {
+      "column": "9",
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@151220@macro@GPIO_RIS_GPIO_S",
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+    },
+    "name": "GPIO_RIS_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@151504@macro@GPIO_MIS_GPIO_M",
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+    },
+    "name": "GPIO_MIS_GPIO_M",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@151581@macro@GPIO_MIS_GPIO_S",
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+    "display": "GPIO_MIS_GPIO_S",
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+    },
+    "name": "GPIO_MIS_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@151865@macro@GPIO_ICR_GPIO_M",
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+    "display": "GPIO_ICR_GPIO_M",
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+      "line": "2415",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_ICR_GPIO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@151934@macro@GPIO_ICR_GPIO_S",
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+    },
+    "name": "GPIO_ICR_GPIO_S",
+    "origin": "user_include",
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+  },
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+      "line": "2423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_LOCK_M",
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+  },
+  {
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+    },
+    "name": "GPIO_LOCK_UNLOCKED",
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+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_LOCK_LOCKED",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@152575@macro@GPIO_LOCK_KEY",
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+    "defdec": "Def",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_LOCK_KEY",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@152915@macro@GPIO_PCTL_PA7_M",
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+    "display": "GPIO_PCTL_PA7_M",
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+    },
+    "name": "GPIO_PCTL_PA7_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@152972@macro@GPIO_PCTL_PA7_I2C1SDA",
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+    "display": "GPIO_PCTL_PA7_I2C1SDA",
+    "location": {
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+      "line": "2437",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA7_I2C1SDA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153035@macro@GPIO_PCTL_PA7_M1PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA7_M1PWM3",
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+      "line": "2438",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA7_M1PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153097@macro@GPIO_PCTL_PA6_M",
+    "What": "MacroDef",
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+    "display": "GPIO_PCTL_PA6_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA6_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153154@macro@GPIO_PCTL_PA6_I2C1SCL",
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+    "display": "GPIO_PCTL_PA6_I2C1SCL",
+    "location": {
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+      "line": "2440",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA6_I2C1SCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153217@macro@GPIO_PCTL_PA6_M1PWM2",
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA6_M1PWM2",
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+      "line": "2441",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA6_M1PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153279@macro@GPIO_PCTL_PA5_M",
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA5_M",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "GPIO_PCTL_PA5_SSI0TX",
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+      "line": "2443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA5_SSI0TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153398@macro@GPIO_PCTL_PA4_M",
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA4_M",
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+    },
+    "name": "GPIO_PCTL_PA4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153455@macro@GPIO_PCTL_PA4_SSI0RX",
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+    "display": "GPIO_PCTL_PA4_SSI0RX",
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+      "line": "2445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA4_SSI0RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153517@macro@GPIO_PCTL_PA3_M",
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA3_M",
+    "location": {
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+      "line": "2446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153574@macro@GPIO_PCTL_PA3_SSI0FSS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA3_SSI0FSS",
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+      "line": "2447",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA3_SSI0FSS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153637@macro@GPIO_PCTL_PA2_M",
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+    "display": "GPIO_PCTL_PA2_M",
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+      "line": "2448",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153694@macro@GPIO_PCTL_PA2_SSI0CLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA2_SSI0CLK",
+    "location": {
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+      "line": "2449",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA2_SSI0CLK",
+    "origin": "user_include",
+    "scope": null
+  },
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+      "line": "2450",
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+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA1_CAN1TX",
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+      "line": "2452",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA1_CAN1TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153936@macro@GPIO_PCTL_PA0_M",
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+    "display": "GPIO_PCTL_PA0_M",
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+      "line": "2453",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@153993@macro@GPIO_PCTL_PA0_U0RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA0_U0RX",
+    "location": {
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+      "line": "2454",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA0_U0RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154053@macro@GPIO_PCTL_PA0_CAN1RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PA0_CAN1RX",
+    "location": {
+      "column": "9",
+      "line": "2455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PA0_CAN1RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154378@macro@GPIO_PCTL_PB7_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB7_M",
+    "location": {
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+      "line": "2463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB7_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154435@macro@GPIO_PCTL_PB7_SSI2TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB7_SSI2TX",
+    "location": {
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+      "line": "2464",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB7_SSI2TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154497@macro@GPIO_PCTL_PB7_M0PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB7_M0PWM1",
+    "location": {
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+      "line": "2465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB7_M0PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154559@macro@GPIO_PCTL_PB7_T0CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB7_T0CCP1",
+    "location": {
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+      "line": "2466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB7_T0CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154621@macro@GPIO_PCTL_PB6_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB6_M",
+    "location": {
+      "column": "9",
+      "line": "2467",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB6_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@154678@macro@GPIO_PCTL_PB6_SSI2RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PB6_SSI2RX",
+    "location": {
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+      "line": "2468",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB6_SSI2RX",
+    "origin": "user_include",
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
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+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB2_I2C0SCL",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@155778@macro@GPIO_PCTL_PB2_T3CCP0",
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "GPIO_PCTL_PB1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
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+      "line": "2492",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PB0_USB0ID",
+    "origin": "user_include",
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "GPIO_PCTL_PC6_U3RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+      "line": "2508",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157008@macro@GPIO_PCTL_PC6_WT1CCP0",
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+      "line": "2509",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC6_WT1CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    "display": "GPIO_PCTL_PC6_USB0EPEN",
+    "location": {
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+      "line": "2510",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC6_USB0EPEN",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "GPIO_PCTL_PC5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157192@macro@GPIO_PCTL_PC5_U4TX",
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+      "line": "2512",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
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+    "display": "GPIO_PCTL_PC5_M0PWM7",
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+      "line": "2514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157374@macro@GPIO_PCTL_PC5_PHA1",
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+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC5_PHA1",
+    "location": {
+      "column": "9",
+      "line": "2515",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC5_PHA1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157434@macro@GPIO_PCTL_PC5_WT0CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC5_WT0CCP1",
+    "location": {
+      "column": "9",
+      "line": "2516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC5_WT0CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157497@macro@GPIO_PCTL_PC5_U1CTS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC5_U1CTS",
+    "location": {
+      "column": "9",
+      "line": "2517",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC5_U1CTS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157558@macro@GPIO_PCTL_PC4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_M",
+    "location": {
+      "column": "9",
+      "line": "2518",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157615@macro@GPIO_PCTL_PC4_U4RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_U4RX",
+    "location": {
+      "column": "9",
+      "line": "2519",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_U4RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157675@macro@GPIO_PCTL_PC4_U1RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_U1RX",
+    "location": {
+      "column": "9",
+      "line": "2520",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_U1RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157735@macro@GPIO_PCTL_PC4_M0PWM6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_M0PWM6",
+    "location": {
+      "column": "9",
+      "line": "2521",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_M0PWM6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157797@macro@GPIO_PCTL_PC4_IDX1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_IDX1",
+    "location": {
+      "column": "9",
+      "line": "2522",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_IDX1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157857@macro@GPIO_PCTL_PC4_WT0CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_WT0CCP0",
+    "location": {
+      "column": "9",
+      "line": "2523",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_WT0CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157920@macro@GPIO_PCTL_PC4_U1RTS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC4_U1RTS",
+    "location": {
+      "column": "9",
+      "line": "2524",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC4_U1RTS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@157981@macro@GPIO_PCTL_PC3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC3_M",
+    "location": {
+      "column": "9",
+      "line": "2525",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158038@macro@GPIO_PCTL_PC3_TDO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC3_TDO",
+    "location": {
+      "column": "9",
+      "line": "2526",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC3_TDO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158097@macro@GPIO_PCTL_PC3_T5CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC3_T5CCP1",
+    "location": {
+      "column": "9",
+      "line": "2527",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC3_T5CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158159@macro@GPIO_PCTL_PC2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC2_M",
+    "location": {
+      "column": "9",
+      "line": "2528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158216@macro@GPIO_PCTL_PC2_TDI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC2_TDI",
+    "location": {
+      "column": "9",
+      "line": "2529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC2_TDI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158275@macro@GPIO_PCTL_PC2_T5CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC2_T5CCP0",
+    "location": {
+      "column": "9",
+      "line": "2530",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC2_T5CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158337@macro@GPIO_PCTL_PC1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC1_M",
+    "location": {
+      "column": "9",
+      "line": "2531",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158394@macro@GPIO_PCTL_PC1_TMS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC1_TMS",
+    "location": {
+      "column": "9",
+      "line": "2532",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC1_TMS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158453@macro@GPIO_PCTL_PC1_T4CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC1_T4CCP1",
+    "location": {
+      "column": "9",
+      "line": "2533",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC1_T4CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158515@macro@GPIO_PCTL_PC0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC0_M",
+    "location": {
+      "column": "9",
+      "line": "2534",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158572@macro@GPIO_PCTL_PC0_TCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC0_TCK",
+    "location": {
+      "column": "9",
+      "line": "2535",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC0_TCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158631@macro@GPIO_PCTL_PC0_T4CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PC0_T4CCP0",
+    "location": {
+      "column": "9",
+      "line": "2536",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PC0_T4CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@158956@macro@GPIO_PCTL_PD7_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD7_M",
+    "location": {
+      "column": "9",
+      "line": "2544",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD7_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159013@macro@GPIO_PCTL_PD7_U2TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD7_U2TX",
+    "location": {
+      "column": "9",
+      "line": "2545",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD7_U2TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159073@macro@GPIO_PCTL_PD7_PHB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD7_PHB0",
+    "location": {
+      "column": "9",
+      "line": "2546",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD7_PHB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159133@macro@GPIO_PCTL_PD7_WT5CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD7_WT5CCP1",
+    "location": {
+      "column": "9",
+      "line": "2547",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD7_WT5CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159196@macro@GPIO_PCTL_PD7_NMI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD7_NMI",
+    "location": {
+      "column": "9",
+      "line": "2548",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD7_NMI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159255@macro@GPIO_PCTL_PD6_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD6_M",
+    "location": {
+      "column": "9",
+      "line": "2549",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD6_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159312@macro@GPIO_PCTL_PD6_U2RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD6_U2RX",
+    "location": {
+      "column": "9",
+      "line": "2550",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD6_U2RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159372@macro@GPIO_PCTL_PD6_M0FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD6_M0FAULT0",
+    "location": {
+      "column": "9",
+      "line": "2551",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD6_M0FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159436@macro@GPIO_PCTL_PD6_PHA0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD6_PHA0",
+    "location": {
+      "column": "9",
+      "line": "2552",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD6_PHA0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159496@macro@GPIO_PCTL_PD6_WT5CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD6_WT5CCP0",
+    "location": {
+      "column": "9",
+      "line": "2553",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD6_WT5CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159559@macro@GPIO_PCTL_PD5_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD5_M",
+    "location": {
+      "column": "9",
+      "line": "2554",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159616@macro@GPIO_PCTL_PD5_USB0DP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD5_USB0DP",
+    "location": {
+      "column": "9",
+      "line": "2555",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD5_USB0DP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159678@macro@GPIO_PCTL_PD5_U6TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD5_U6TX",
+    "location": {
+      "column": "9",
+      "line": "2556",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD5_U6TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159738@macro@GPIO_PCTL_PD5_WT4CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD5_WT4CCP1",
+    "location": {
+      "column": "9",
+      "line": "2557",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD5_WT4CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159801@macro@GPIO_PCTL_PD4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD4_M",
+    "location": {
+      "column": "9",
+      "line": "2558",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159858@macro@GPIO_PCTL_PD4_USB0DM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD4_USB0DM",
+    "location": {
+      "column": "9",
+      "line": "2559",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD4_USB0DM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159920@macro@GPIO_PCTL_PD4_U6RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD4_U6RX",
+    "location": {
+      "column": "9",
+      "line": "2560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD4_U6RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@159980@macro@GPIO_PCTL_PD4_WT4CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PD4_WT4CCP0",
+    "location": {
+      "column": "9",
+      "line": "2561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PD4_WT4CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+    },
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+  },
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+    },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+    "origin": "user_include",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+  },
+  {
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+    },
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+  },
+  {
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    "display": "GPIO_PCTL_PD0_SSI3CLK",
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+      "line": "2586",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    },
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+    "origin": "user_include",
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+      "line": "2601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "line": "2602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE5_I2C2SDA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    "display": "GPIO_PCTL_PE5_M0PWM5",
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+      "line": "2603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162454@macro@GPIO_PCTL_PE5_M1PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE5_M1PWM3",
+    "location": {
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+      "line": "2604",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE5_M1PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162516@macro@GPIO_PCTL_PE5_CAN0TX",
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+      "line": "2605",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE5_CAN0TX",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "GPIO_PCTL_PE4_M",
+    "origin": "user_include",
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+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
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+      "line": "2607",
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE4_U5RX",
+    "location": {
+      "column": "9",
+      "line": "2608",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE4_U5RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162755@macro@GPIO_PCTL_PE4_I2C2SCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE4_I2C2SCL",
+    "location": {
+      "column": "9",
+      "line": "2609",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE4_I2C2SCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162818@macro@GPIO_PCTL_PE4_M0PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE4_M0PWM4",
+    "location": {
+      "column": "9",
+      "line": "2610",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE4_M0PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162880@macro@GPIO_PCTL_PE4_M1PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE4_M1PWM2",
+    "location": {
+      "column": "9",
+      "line": "2611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE4_M1PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@162942@macro@GPIO_PCTL_PE4_CAN0RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE4_CAN0RX",
+    "location": {
+      "column": "9",
+      "line": "2612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE4_CAN0RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163004@macro@GPIO_PCTL_PE3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE3_M",
+    "location": {
+      "column": "9",
+      "line": "2613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163061@macro@GPIO_PCTL_PE3_AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE3_AIN0",
+    "location": {
+      "column": "9",
+      "line": "2614",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE3_AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163121@macro@GPIO_PCTL_PE2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE2_M",
+    "location": {
+      "column": "9",
+      "line": "2615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163178@macro@GPIO_PCTL_PE2_AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE2_AIN1",
+    "location": {
+      "column": "9",
+      "line": "2616",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE2_AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163238@macro@GPIO_PCTL_PE1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE1_M",
+    "location": {
+      "column": "9",
+      "line": "2617",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163295@macro@GPIO_PCTL_PE1_AIN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE1_AIN2",
+    "location": {
+      "column": "9",
+      "line": "2618",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE1_AIN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163355@macro@GPIO_PCTL_PE1_U7TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE1_U7TX",
+    "location": {
+      "column": "9",
+      "line": "2619",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE1_U7TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163415@macro@GPIO_PCTL_PE0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE0_M",
+    "location": {
+      "column": "9",
+      "line": "2620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163472@macro@GPIO_PCTL_PE0_AIN3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE0_AIN3",
+    "location": {
+      "column": "9",
+      "line": "2621",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE0_AIN3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163532@macro@GPIO_PCTL_PE0_U7RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PE0_U7RX",
+    "location": {
+      "column": "9",
+      "line": "2622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PE0_U7RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163855@macro@GPIO_PCTL_PF4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF4_M",
+    "location": {
+      "column": "9",
+      "line": "2630",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163912@macro@GPIO_PCTL_PF4_M1FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF4_M1FAULT0",
+    "location": {
+      "column": "9",
+      "line": "2631",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF4_M1FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@163976@macro@GPIO_PCTL_PF4_IDX0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF4_IDX0",
+    "location": {
+      "column": "9",
+      "line": "2632",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF4_IDX0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164036@macro@GPIO_PCTL_PF4_T2CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF4_T2CCP0",
+    "location": {
+      "column": "9",
+      "line": "2633",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF4_T2CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164098@macro@GPIO_PCTL_PF4_USB0EPEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF4_USB0EPEN",
+    "location": {
+      "column": "9",
+      "line": "2634",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF4_USB0EPEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164162@macro@GPIO_PCTL_PF3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_M",
+    "location": {
+      "column": "9",
+      "line": "2635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164219@macro@GPIO_PCTL_PF3_SSI1FSS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_SSI1FSS",
+    "location": {
+      "column": "9",
+      "line": "2636",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_SSI1FSS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164282@macro@GPIO_PCTL_PF3_CAN0TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_CAN0TX",
+    "location": {
+      "column": "9",
+      "line": "2637",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_CAN0TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164344@macro@GPIO_PCTL_PF3_M1PWM7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_M1PWM7",
+    "location": {
+      "column": "9",
+      "line": "2638",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_M1PWM7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164406@macro@GPIO_PCTL_PF3_T1CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_T1CCP1",
+    "location": {
+      "column": "9",
+      "line": "2639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_T1CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164468@macro@GPIO_PCTL_PF3_TRCLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF3_TRCLK",
+    "location": {
+      "column": "9",
+      "line": "2640",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF3_TRCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164529@macro@GPIO_PCTL_PF2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_M",
+    "location": {
+      "column": "9",
+      "line": "2641",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164586@macro@GPIO_PCTL_PF2_SSI1CLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_SSI1CLK",
+    "location": {
+      "column": "9",
+      "line": "2642",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_SSI1CLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164649@macro@GPIO_PCTL_PF2_M0FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_M0FAULT0",
+    "location": {
+      "column": "9",
+      "line": "2643",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_M0FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164713@macro@GPIO_PCTL_PF2_M1PWM6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_M1PWM6",
+    "location": {
+      "column": "9",
+      "line": "2644",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_M1PWM6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164775@macro@GPIO_PCTL_PF2_T1CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_T1CCP0",
+    "location": {
+      "column": "9",
+      "line": "2645",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_T1CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164837@macro@GPIO_PCTL_PF2_TRD0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF2_TRD0",
+    "location": {
+      "column": "9",
+      "line": "2646",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF2_TRD0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164897@macro@GPIO_PCTL_PF1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_M",
+    "location": {
+      "column": "9",
+      "line": "2647",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@164954@macro@GPIO_PCTL_PF1_U1CTS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_U1CTS",
+    "location": {
+      "column": "9",
+      "line": "2648",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_U1CTS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165015@macro@GPIO_PCTL_PF1_SSI1TX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_SSI1TX",
+    "location": {
+      "column": "9",
+      "line": "2649",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_SSI1TX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165077@macro@GPIO_PCTL_PF1_M1PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_M1PWM5",
+    "location": {
+      "column": "9",
+      "line": "2650",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_M1PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165139@macro@GPIO_PCTL_PF1_PHB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_PHB0",
+    "location": {
+      "column": "9",
+      "line": "2651",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_PHB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165199@macro@GPIO_PCTL_PF1_T0CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_T0CCP1",
+    "location": {
+      "column": "9",
+      "line": "2652",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_T0CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165261@macro@GPIO_PCTL_PF1_C1O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_C1O",
+    "location": {
+      "column": "9",
+      "line": "2653",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_C1O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@165320@macro@GPIO_PCTL_PF1_TRD1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PCTL_PF1_TRD1",
+    "location": {
+      "column": "9",
+      "line": "2654",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "GPIO_PCTL_PF1_TRD1",
+    "origin": "user_include",
+    "scope": null
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_SR_TNF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169032@macro@SSI_SR_TFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_SR_TFE",
+    "location": {
+      "column": "9",
+      "line": "2721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_SR_TFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169353@macro@SSI_CPSR_CPSDVSR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_CPSR_CPSDVSR_M",
+    "location": {
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+      "line": "2728",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_CPSR_CPSDVSR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169428@macro@SSI_CPSR_CPSDVSR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_CPSR_CPSDVSR_S",
+    "location": {
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+      "line": "2729",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_CPSR_CPSDVSR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169710@macro@SSI_IM_TXIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_IM_TXIM",
+    "location": {
+      "column": "9",
+      "line": "2736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_IM_TXIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169791@macro@SSI_IM_RXIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_IM_RXIM",
+    "location": {
+      "column": "9",
+      "line": "2737",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_IM_RXIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@169871@macro@SSI_IM_RTIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_IM_RTIM",
+    "location": {
+      "column": "9",
+      "line": "2738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_IM_RTIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@170003@macro@SSI_IM_RORIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_IM_RORIM",
+    "location": {
+      "column": "9",
+      "line": "2740",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_IM_RORIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@170382@macro@SSI_RIS_TXRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_RIS_TXRIS",
+    "location": {
+      "column": "9",
+      "line": "2748",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_RIS_TXRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@170517@macro@SSI_RIS_RXRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_RIS_RXRIS",
+    "location": {
+      "column": "9",
+      "line": "2750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_RIS_RXRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@170651@macro@SSI_RIS_RTRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_RIS_RTRIS",
+    "location": {
+      "column": "9",
+      "line": "2752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_RIS_RTRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@170789@macro@SSI_RIS_RORRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_RIS_RORRIS",
+    "location": {
+      "column": "9",
+      "line": "2754",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_RIS_RORRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@171174@macro@SSI_MIS_TXMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_MIS_TXMIS",
+    "location": {
+      "column": "9",
+      "line": "2762",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_MIS_TXMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@171312@macro@SSI_MIS_RXMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_MIS_RXMIS",
+    "location": {
+      "column": "9",
+      "line": "2764",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_MIS_RXMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@171449@macro@SSI_MIS_RTMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_MIS_RTMIS",
+    "location": {
+      "column": "9",
+      "line": "2766",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_MIS_RTMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@171590@macro@SSI_MIS_RORMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_MIS_RORMIS",
+    "location": {
+      "column": "9",
+      "line": "2768",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_MIS_RORMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@171978@macro@SSI_ICR_RTIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_ICR_RTIC",
+    "location": {
+      "column": "9",
+      "line": "2776",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_ICR_RTIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@172111@macro@SSI_ICR_RORIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_ICR_RORIC",
+    "location": {
+      "column": "9",
+      "line": "2778",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_ICR_RORIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@172494@macro@SSI_DMACTL_TXDMAE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_DMACTL_TXDMAE",
+    "location": {
+      "column": "9",
+      "line": "2786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_DMACTL_TXDMAE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@172562@macro@SSI_DMACTL_RXDMAE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_DMACTL_RXDMAE",
+    "location": {
+      "column": "9",
+      "line": "2787",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_DMACTL_RXDMAE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@172876@macro@SSI_CC_CS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_CC_CS_M",
+    "location": {
+      "column": "9",
+      "line": "2794",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_CC_CS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@172946@macro@SSI_CC_CS_SYSPLL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_CC_CS_SYSPLL",
+    "location": {
+      "column": "9",
+      "line": "2795",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_CC_CS_SYSPLL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173098@macro@SSI_CC_CS_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI_CC_CS_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "2797",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SSI_CC_CS_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173400@macro@UART_DR_OE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_OE",
+    "location": {
+      "column": "9",
+      "line": "2804",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_OE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173467@macro@UART_DR_BE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_BE",
+    "location": {
+      "column": "9",
+      "line": "2805",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_BE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173532@macro@UART_DR_PE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_PE",
+    "location": {
+      "column": "9",
+      "line": "2806",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_PE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173598@macro@UART_DR_FE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_FE",
+    "location": {
+      "column": "9",
+      "line": "2807",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_FE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173665@macro@UART_DR_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "2808",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@173742@macro@UART_DR_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_DR_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "2809",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_DR_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174026@macro@UART_RSR_OE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_RSR_OE",
+    "location": {
+      "column": "9",
+      "line": "2816",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_RSR_OE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174093@macro@UART_RSR_BE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_RSR_BE",
+    "location": {
+      "column": "9",
+      "line": "2817",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_RSR_BE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174158@macro@UART_RSR_PE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_RSR_PE",
+    "location": {
+      "column": "9",
+      "line": "2818",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_RSR_PE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174224@macro@UART_RSR_FE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_RSR_FE",
+    "location": {
+      "column": "9",
+      "line": "2819",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_RSR_FE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174540@macro@UART_ECR_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_ECR_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "2826",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_ECR_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174600@macro@UART_ECR_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_ECR_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "2827",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_ECR_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174883@macro@UART_FR_TXFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_TXFE",
+    "location": {
+      "column": "9",
+      "line": "2834",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_TXFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@174956@macro@UART_FR_RXFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_RXFF",
+    "location": {
+      "column": "9",
+      "line": "2835",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_RXFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@175027@macro@UART_FR_TXFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_TXFF",
+    "location": {
+      "column": "9",
+      "line": "2836",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_TXFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@175099@macro@UART_FR_RXFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_RXFE",
+    "location": {
+      "column": "9",
+      "line": "2837",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_RXFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@175171@macro@UART_FR_BUSY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_BUSY",
+    "location": {
+      "column": "9",
+      "line": "2838",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_BUSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@175229@macro@UART_FR_CTS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_FR_CTS",
+    "location": {
+      "column": "9",
+      "line": "2839",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_FR_CTS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@175541@macro@UART_ILPR_ILPDVSR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_ILPR_ILPDVSR_M",
+    "location": {
+      "column": "9",
+      "line": "2846",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_ILPR_ILPDVSR_M",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "UART_9BITAMASK_MASK_S",
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+      "line": "3028",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_9BITAMASK_MASK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@186186@macro@UART_PP_NB",
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+    "defdec": "Def",
+    "display": "UART_PP_NB",
+    "location": {
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+      "line": "3035",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_PP_NB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@186248@macro@UART_PP_SC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_PP_SC",
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+      "line": "3036",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_PP_SC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@186563@macro@UART_CC_CS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_CC_CS_M",
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+      "line": "3043",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_CC_CS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@186634@macro@UART_CC_CS_SYSCLK",
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+    "defdec": "Def",
+    "display": "UART_CC_CS_SYSCLK",
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+      "line": "3044",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_CC_CS_SYSCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@186786@macro@UART_CC_CS_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UART_CC_CS_PIOSC",
+    "location": {
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+      "line": "3046",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UART_CC_CS_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187088@macro@I2C_MSA_SA_M",
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+    "display": "I2C_MSA_SA_M",
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+      "line": "3053",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MSA_SA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187154@macro@I2C_MSA_RS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MSA_RS",
+    "location": {
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+      "line": "3054",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MSA_RS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187219@macro@I2C_MSA_SA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MSA_SA_S",
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+      "line": "3055",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MSA_SA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187502@macro@I2C_MCS_CLKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_CLKTO",
+    "location": {
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+      "line": "3062",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_CLKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187570@macro@I2C_MCS_BUSBSY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_BUSBSY",
+    "location": {
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+      "line": "3063",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_BUSBSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187627@macro@I2C_MCS_IDLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_IDLE",
+    "location": {
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+      "line": "3064",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_IDLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187684@macro@I2C_MCS_ARBLST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_ARBLST",
+    "location": {
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+      "line": "3065",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_ARBLST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187749@macro@I2C_MCS_HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_HS",
+    "location": {
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+      "line": "3066",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187815@macro@I2C_MCS_ACK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_ACK",
+    "location": {
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+      "line": "3067",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_ACK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187887@macro@I2C_MCS_DATACK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_DATACK",
+    "location": {
+      "column": "9",
+      "line": "3068",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_DATACK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@187952@macro@I2C_MCS_ADRACK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_ADRACK",
+    "location": {
+      "column": "9",
+      "line": "3069",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_ADRACK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188020@macro@I2C_MCS_STOP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_STOP",
+    "location": {
+      "column": "9",
+      "line": "3070",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_STOP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188082@macro@I2C_MCS_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_ERROR",
+    "location": {
+      "column": "9",
+      "line": "3071",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188136@macro@I2C_MCS_START",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_START",
+    "location": {
+      "column": "9",
+      "line": "3072",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_START",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188199@macro@I2C_MCS_RUN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_RUN",
+    "location": {
+      "column": "9",
+      "line": "3073",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_RUN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188265@macro@I2C_MCS_BUSY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCS_BUSY",
+    "location": {
+      "column": "9",
+      "line": "3074",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCS_BUSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188570@macro@I2C_MDR_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MDR_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "3081",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MDR_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@188727@macro@I2C_MDR_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MDR_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "3083",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MDR_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189011@macro@I2C_MTPR_HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MTPR_HS",
+    "location": {
+      "column": "9",
+      "line": "3090",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MTPR_HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189077@macro@I2C_MTPR_TPR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MTPR_TPR_M",
+    "location": {
+      "column": "9",
+      "line": "3091",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MTPR_TPR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189138@macro@I2C_MTPR_TPR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MTPR_TPR_S",
+    "location": {
+      "column": "9",
+      "line": "3092",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MTPR_TPR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189422@macro@I2C_MIMR_CLKIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MIMR_CLKIM",
+    "location": {
+      "column": "9",
+      "line": "3099",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MIMR_CLKIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189499@macro@I2C_MIMR_IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MIMR_IM",
+    "location": {
+      "column": "9",
+      "line": "3100",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MIMR_IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189818@macro@I2C_MRIS_CLKRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MRIS_CLKRIS",
+    "location": {
+      "column": "9",
+      "line": "3107",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MRIS_CLKRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@189949@macro@I2C_MRIS_RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MRIS_RIS",
+    "location": {
+      "column": "9",
+      "line": "3109",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MRIS_RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@190274@macro@I2C_MMIS_CLKMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MMIS_CLKMIS",
+    "location": {
+      "column": "9",
+      "line": "3116",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MMIS_CLKMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@190408@macro@I2C_MMIS_MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MMIS_MIS",
+    "location": {
+      "column": "9",
+      "line": "3118",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MMIS_MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@190729@macro@I2C_MICR_CLKIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MICR_CLKIC",
+    "location": {
+      "column": "9",
+      "line": "3125",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MICR_CLKIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@190807@macro@I2C_MICR_IC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MICR_IC",
+    "location": {
+      "column": "9",
+      "line": "3126",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MICR_IC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191126@macro@I2C_MCR_GFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCR_GFE",
+    "location": {
+      "column": "9",
+      "line": "3133",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCR_GFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191199@macro@I2C_MCR_SFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCR_SFE",
+    "location": {
+      "column": "9",
+      "line": "3134",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCR_SFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191273@macro@I2C_MCR_MFE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCR_MFE",
+    "location": {
+      "column": "9",
+      "line": "3135",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCR_MFE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191348@macro@I2C_MCR_LPBK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCR_LPBK",
+    "location": {
+      "column": "9",
+      "line": "3136",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCR_LPBK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191662@macro@I2C_MCLKOCNT_CNTL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCLKOCNT_CNTL_M",
+    "location": {
+      "column": "9",
+      "line": "3143",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCLKOCNT_CNTL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@191727@macro@I2C_MCLKOCNT_CNTL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "I2C_MCLKOCNT_CNTL_S",
+    "location": {
+      "column": "9",
+      "line": "3144",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "I2C_MCLKOCNT_CNTL_S",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    },
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+    },
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+    },
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+  },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    },
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+    },
+    "name": "I2C_PC_HS",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@198055@macro@PWM_CTL_GLOBALSYNC3",
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+    },
+    "name": "PWM_CTL_GLOBALSYNC3",
+    "origin": "user_include",
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+  },
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+  {
+    "ID": "c:tm4c123gh6pm.h@202422@macro@PWM_RIS_INTPWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_RIS_INTPWM1",
+    "location": {
+      "column": "9",
+      "line": "3350",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_RIS_INTPWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@202494@macro@PWM_RIS_INTPWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_RIS_INTPWM0",
+    "location": {
+      "column": "9",
+      "line": "3351",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_RIS_INTPWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@202814@macro@PWM_ISC_INTFAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTFAULT1",
+    "location": {
+      "column": "9",
+      "line": "3358",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTFAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@202888@macro@PWM_ISC_INTFAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTFAULT0",
+    "location": {
+      "column": "9",
+      "line": "3359",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTFAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@202962@macro@PWM_ISC_INTPWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTPWM3",
+    "location": {
+      "column": "9",
+      "line": "3360",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTPWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203032@macro@PWM_ISC_INTPWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTPWM2",
+    "location": {
+      "column": "9",
+      "line": "3361",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTPWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203102@macro@PWM_ISC_INTPWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTPWM1",
+    "location": {
+      "column": "9",
+      "line": "3362",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTPWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203172@macro@PWM_ISC_INTPWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ISC_INTPWM0",
+    "location": {
+      "column": "9",
+      "line": "3363",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ISC_INTPWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203493@macro@PWM_STATUS_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_STATUS_FAULT1",
+    "location": {
+      "column": "9",
+      "line": "3370",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_STATUS_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203566@macro@PWM_STATUS_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_STATUS_FAULT0",
+    "location": {
+      "column": "9",
+      "line": "3371",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_STATUS_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203892@macro@PWM_FAULTVAL_PWM7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM7",
+    "location": {
+      "column": "9",
+      "line": "3378",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@203959@macro@PWM_FAULTVAL_PWM6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM6",
+    "location": {
+      "column": "9",
+      "line": "3379",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204026@macro@PWM_FAULTVAL_PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM5",
+    "location": {
+      "column": "9",
+      "line": "3380",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204093@macro@PWM_FAULTVAL_PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM4",
+    "location": {
+      "column": "9",
+      "line": "3381",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204160@macro@PWM_FAULTVAL_PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM3",
+    "location": {
+      "column": "9",
+      "line": "3382",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204227@macro@PWM_FAULTVAL_PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM2",
+    "location": {
+      "column": "9",
+      "line": "3383",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204294@macro@PWM_FAULTVAL_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM1",
+    "location": {
+      "column": "9",
+      "line": "3384",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204361@macro@PWM_FAULTVAL_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_FAULTVAL_PWM0",
+    "location": {
+      "column": "9",
+      "line": "3385",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_FAULTVAL_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204678@macro@PWM_ENUPD_ENUPD7_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD7_M",
+    "location": {
+      "column": "9",
+      "line": "3392",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD7_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204752@macro@PWM_ENUPD_ENUPD7_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD7_IMM",
+    "location": {
+      "column": "9",
+      "line": "3393",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD7_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204810@macro@PWM_ENUPD_ENUPD7_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD7_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3394",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD7_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204879@macro@PWM_ENUPD_ENUPD7_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD7_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3395",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD7_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@204949@macro@PWM_ENUPD_ENUPD6_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD6_M",
+    "location": {
+      "column": "9",
+      "line": "3396",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD6_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205023@macro@PWM_ENUPD_ENUPD6_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD6_IMM",
+    "location": {
+      "column": "9",
+      "line": "3397",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD6_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205081@macro@PWM_ENUPD_ENUPD6_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD6_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3398",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD6_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205150@macro@PWM_ENUPD_ENUPD6_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD6_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3399",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD6_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205220@macro@PWM_ENUPD_ENUPD5_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD5_M",
+    "location": {
+      "column": "9",
+      "line": "3400",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205294@macro@PWM_ENUPD_ENUPD5_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD5_IMM",
+    "location": {
+      "column": "9",
+      "line": "3401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD5_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205352@macro@PWM_ENUPD_ENUPD5_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD5_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3402",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD5_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205421@macro@PWM_ENUPD_ENUPD5_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD5_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3403",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD5_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205491@macro@PWM_ENUPD_ENUPD4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD4_M",
+    "location": {
+      "column": "9",
+      "line": "3404",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205565@macro@PWM_ENUPD_ENUPD4_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD4_IMM",
+    "location": {
+      "column": "9",
+      "line": "3405",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD4_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205623@macro@PWM_ENUPD_ENUPD4_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD4_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3406",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD4_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205692@macro@PWM_ENUPD_ENUPD4_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD4_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3407",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD4_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205762@macro@PWM_ENUPD_ENUPD3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD3_M",
+    "location": {
+      "column": "9",
+      "line": "3408",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205836@macro@PWM_ENUPD_ENUPD3_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD3_IMM",
+    "location": {
+      "column": "9",
+      "line": "3409",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD3_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205894@macro@PWM_ENUPD_ENUPD3_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD3_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3410",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD3_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@205963@macro@PWM_ENUPD_ENUPD3_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD3_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3411",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD3_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206033@macro@PWM_ENUPD_ENUPD2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD2_M",
+    "location": {
+      "column": "9",
+      "line": "3412",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206107@macro@PWM_ENUPD_ENUPD2_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD2_IMM",
+    "location": {
+      "column": "9",
+      "line": "3413",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD2_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206165@macro@PWM_ENUPD_ENUPD2_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD2_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3414",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD2_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206234@macro@PWM_ENUPD_ENUPD2_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD2_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3415",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD2_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206304@macro@PWM_ENUPD_ENUPD1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD1_M",
+    "location": {
+      "column": "9",
+      "line": "3416",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206378@macro@PWM_ENUPD_ENUPD1_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD1_IMM",
+    "location": {
+      "column": "9",
+      "line": "3417",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD1_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206436@macro@PWM_ENUPD_ENUPD1_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD1_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3418",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD1_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206505@macro@PWM_ENUPD_ENUPD1_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD1_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD1_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206575@macro@PWM_ENUPD_ENUPD0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD0_M",
+    "location": {
+      "column": "9",
+      "line": "3420",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206649@macro@PWM_ENUPD_ENUPD0_IMM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD0_IMM",
+    "location": {
+      "column": "9",
+      "line": "3421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD0_IMM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206707@macro@PWM_ENUPD_ENUPD0_LSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD0_LSYNC",
+    "location": {
+      "column": "9",
+      "line": "3422",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD0_LSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@206776@macro@PWM_ENUPD_ENUPD0_GSYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_ENUPD_ENUPD0_GSYNC",
+    "location": {
+      "column": "9",
+      "line": "3423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_ENUPD_ENUPD0_GSYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207096@macro@PWM_0_CTL_LATCH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_LATCH",
+    "location": {
+      "column": "9",
+      "line": "3430",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_LATCH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207162@macro@PWM_0_CTL_MINFLTPER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_MINFLTPER",
+    "location": {
+      "column": "9",
+      "line": "3431",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_MINFLTPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207231@macro@PWM_0_CTL_FLTSRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_FLTSRC",
+    "location": {
+      "column": "9",
+      "line": "3432",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_FLTSRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207302@macro@PWM_0_CTL_DBFALLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBFALLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3433",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBFALLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207373@macro@PWM_0_CTL_DBFALLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBFALLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3434",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBFALLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207431@macro@PWM_0_CTL_DBFALLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBFALLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3435",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBFALLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207500@macro@PWM_0_CTL_DBFALLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBFALLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3436",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBFALLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207570@macro@PWM_0_CTL_DBRISEUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBRISEUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3437",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBRISEUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207641@macro@PWM_0_CTL_DBRISEUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBRISEUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3438",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBRISEUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207699@macro@PWM_0_CTL_DBRISEUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBRISEUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3439",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBRISEUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207768@macro@PWM_0_CTL_DBRISEUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBRISEUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3440",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBRISEUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207838@macro@PWM_0_CTL_DBCTLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBCTLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3441",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBCTLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207908@macro@PWM_0_CTL_DBCTLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBCTLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3442",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBCTLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@207966@macro@PWM_0_CTL_DBCTLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBCTLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBCTLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208035@macro@PWM_0_CTL_DBCTLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DBCTLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3444",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DBCTLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208105@macro@PWM_0_CTL_GENBUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENBUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENBUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208174@macro@PWM_0_CTL_GENBUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENBUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENBUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208232@macro@PWM_0_CTL_GENBUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENBUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3447",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENBUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208301@macro@PWM_0_CTL_GENBUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENBUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3448",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENBUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208371@macro@PWM_0_CTL_GENAUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENAUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3449",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENAUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208440@macro@PWM_0_CTL_GENAUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENAUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3450",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENAUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208498@macro@PWM_0_CTL_GENAUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENAUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3451",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENAUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208567@macro@PWM_0_CTL_GENAUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_GENAUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3452",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_GENAUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208637@macro@PWM_0_CTL_CMPBUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_CMPBUPD",
+    "location": {
+      "column": "9",
+      "line": "3453",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_CMPBUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208710@macro@PWM_0_CTL_CMPAUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_CMPAUPD",
+    "location": {
+      "column": "9",
+      "line": "3454",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_CMPAUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208783@macro@PWM_0_CTL_LOADUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_LOADUPD",
+    "location": {
+      "column": "9",
+      "line": "3455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_LOADUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208857@macro@PWM_0_CTL_DEBUG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_DEBUG",
+    "location": {
+      "column": "9",
+      "line": "3456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_DEBUG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@208916@macro@PWM_0_CTL_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_CTL_MODE",
+    "location": {
+      "column": "9",
+      "line": "3457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_CTL_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "column": "9",
+      "line": "3611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAD_ONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@217984@macro@PWM_0_GENB_ACTCMPAU_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTCMPAU_M",
+    "location": {
+      "column": "9",
+      "line": "3612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAU_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218059@macro@PWM_0_GENB_ACTCMPAU_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTCMPAU_NONE",
+    "location": {
+      "column": "9",
+      "line": "3613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAU_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218199@macro@PWM_0_GENB_ACTCMPAU_INV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTCMPAU_INV",
+    "location": {
+      "column": "9",
+      "line": "3615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAU_INV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218259@macro@PWM_0_GENB_ACTCMPAU_ZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTCMPAU_ZERO",
+    "location": {
+      "column": "9",
+      "line": "3616",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAU_ZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218403@macro@PWM_0_GENB_ACTCMPAU_ONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTCMPAU_ONE",
+    "location": {
+      "column": "9",
+      "line": "3618",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTCMPAU_ONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218467@macro@PWM_0_GENB_ACTLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "3619",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218539@macro@PWM_0_GENB_ACTLOAD_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTLOAD_NONE",
+    "location": {
+      "column": "9",
+      "line": "3620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTLOAD_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218598@macro@PWM_0_GENB_ACTLOAD_INV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTLOAD_INV",
+    "location": {
+      "column": "9",
+      "line": "3621",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTLOAD_INV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218658@macro@PWM_0_GENB_ACTLOAD_ZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTLOAD_ZERO",
+    "location": {
+      "column": "9",
+      "line": "3622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTLOAD_ZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218721@macro@PWM_0_GENB_ACTLOAD_ONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTLOAD_ONE",
+    "location": {
+      "column": "9",
+      "line": "3623",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTLOAD_ONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218785@macro@PWM_0_GENB_ACTZERO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTZERO_M",
+    "location": {
+      "column": "9",
+      "line": "3624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTZERO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218854@macro@PWM_0_GENB_ACTZERO_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTZERO_NONE",
+    "location": {
+      "column": "9",
+      "line": "3625",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTZERO_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218913@macro@PWM_0_GENB_ACTZERO_INV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTZERO_INV",
+    "location": {
+      "column": "9",
+      "line": "3626",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTZERO_INV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@218973@macro@PWM_0_GENB_ACTZERO_ZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTZERO_ZERO",
+    "location": {
+      "column": "9",
+      "line": "3627",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTZERO_ZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@219036@macro@PWM_0_GENB_ACTZERO_ONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_GENB_ACTZERO_ONE",
+    "location": {
+      "column": "9",
+      "line": "3628",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_GENB_ACTZERO_ONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@219352@macro@PWM_0_DBCTL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_DBCTL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "3635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_DBCTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@219680@macro@PWM_0_DBRISE_DELAY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_DBRISE_DELAY_M",
+    "location": {
+      "column": "9",
+      "line": "3642",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_DBRISE_DELAY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@219749@macro@PWM_0_DBRISE_DELAY_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_DBRISE_DELAY_S",
+    "location": {
+      "column": "9",
+      "line": "3643",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_DBRISE_DELAY_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220037@macro@PWM_0_DBFALL_DELAY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_DBFALL_DELAY_M",
+    "location": {
+      "column": "9",
+      "line": "3650",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_DBFALL_DELAY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220106@macro@PWM_0_DBFALL_DELAY_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_DBFALL_DELAY_S",
+    "location": {
+      "column": "9",
+      "line": "3651",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_DBFALL_DELAY_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220399@macro@PWM_0_FLTSRC0_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC0_FAULT1",
+    "location": {
+      "column": "9",
+      "line": "3659",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC0_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220460@macro@PWM_0_FLTSRC0_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC0_FAULT0",
+    "location": {
+      "column": "9",
+      "line": "3660",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220779@macro@PWM_0_FLTSRC1_DCMP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP7",
+    "location": {
+      "column": "9",
+      "line": "3668",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220848@macro@PWM_0_FLTSRC1_DCMP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP6",
+    "location": {
+      "column": "9",
+      "line": "3669",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220917@macro@PWM_0_FLTSRC1_DCMP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP5",
+    "location": {
+      "column": "9",
+      "line": "3670",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@220986@macro@PWM_0_FLTSRC1_DCMP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP4",
+    "location": {
+      "column": "9",
+      "line": "3671",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221055@macro@PWM_0_FLTSRC1_DCMP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP3",
+    "location": {
+      "column": "9",
+      "line": "3672",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221124@macro@PWM_0_FLTSRC1_DCMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP2",
+    "location": {
+      "column": "9",
+      "line": "3673",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221193@macro@PWM_0_FLTSRC1_DCMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP1",
+    "location": {
+      "column": "9",
+      "line": "3674",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221262@macro@PWM_0_FLTSRC1_DCMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSRC1_DCMP0",
+    "location": {
+      "column": "9",
+      "line": "3675",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSRC1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221591@macro@PWM_0_MINFLTPER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_MINFLTPER_M",
+    "location": {
+      "column": "9",
+      "line": "3683",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_MINFLTPER_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221660@macro@PWM_0_MINFLTPER_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_MINFLTPER_S",
+    "location": {
+      "column": "9",
+      "line": "3684",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_MINFLTPER_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@221945@macro@PWM_1_CTL_LATCH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_LATCH",
+    "location": {
+      "column": "9",
+      "line": "3691",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_LATCH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222011@macro@PWM_1_CTL_MINFLTPER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_MINFLTPER",
+    "location": {
+      "column": "9",
+      "line": "3692",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_MINFLTPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222080@macro@PWM_1_CTL_FLTSRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_FLTSRC",
+    "location": {
+      "column": "9",
+      "line": "3693",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_FLTSRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222151@macro@PWM_1_CTL_DBFALLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBFALLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3694",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBFALLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222222@macro@PWM_1_CTL_DBFALLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBFALLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3695",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBFALLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222280@macro@PWM_1_CTL_DBFALLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBFALLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3696",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBFALLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222349@macro@PWM_1_CTL_DBFALLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBFALLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3697",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBFALLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222419@macro@PWM_1_CTL_DBRISEUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBRISEUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3698",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBRISEUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222490@macro@PWM_1_CTL_DBRISEUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBRISEUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3699",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBRISEUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222548@macro@PWM_1_CTL_DBRISEUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBRISEUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3700",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBRISEUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222617@macro@PWM_1_CTL_DBRISEUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBRISEUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3701",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBRISEUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222687@macro@PWM_1_CTL_DBCTLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBCTLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3702",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBCTLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222757@macro@PWM_1_CTL_DBCTLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBCTLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3703",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBCTLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222815@macro@PWM_1_CTL_DBCTLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBCTLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3704",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBCTLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222884@macro@PWM_1_CTL_DBCTLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DBCTLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3705",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DBCTLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@222954@macro@PWM_1_CTL_GENBUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENBUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3706",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENBUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223023@macro@PWM_1_CTL_GENBUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENBUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3707",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENBUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223081@macro@PWM_1_CTL_GENBUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENBUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3708",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENBUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223150@macro@PWM_1_CTL_GENBUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENBUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENBUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223220@macro@PWM_1_CTL_GENAUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENAUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3710",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENAUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223289@macro@PWM_1_CTL_GENAUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENAUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3711",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENAUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223347@macro@PWM_1_CTL_GENAUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENAUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENAUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223416@macro@PWM_1_CTL_GENAUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_GENAUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3713",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_GENAUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223486@macro@PWM_1_CTL_CMPBUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_CMPBUPD",
+    "location": {
+      "column": "9",
+      "line": "3714",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_CMPBUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223559@macro@PWM_1_CTL_CMPAUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_CMPAUPD",
+    "location": {
+      "column": "9",
+      "line": "3715",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_CMPAUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223632@macro@PWM_1_CTL_LOADUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_LOADUPD",
+    "location": {
+      "column": "9",
+      "line": "3716",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_LOADUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223706@macro@PWM_1_CTL_DEBUG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_DEBUG",
+    "location": {
+      "column": "9",
+      "line": "3717",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_DEBUG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223765@macro@PWM_1_CTL_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_MODE",
+    "location": {
+      "column": "9",
+      "line": "3718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@223826@macro@PWM_1_CTL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_CTL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "3719",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_CTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224143@macro@PWM_1_INTEN_TRCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCMPBD",
+    "location": {
+      "column": "9",
+      "line": "3726",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224273@macro@PWM_1_INTEN_TRCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCMPBU",
+    "location": {
+      "column": "9",
+      "line": "3728",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224353@macro@PWM_1_INTEN_TRCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCMPAD",
+    "location": {
+      "column": "9",
+      "line": "3729",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224483@macro@PWM_1_INTEN_TRCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCMPAU",
+    "location": {
+      "column": "9",
+      "line": "3731",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224563@macro@PWM_1_INTEN_TRCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "3732",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224640@macro@PWM_1_INTEN_TRCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_TRCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "3733",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_TRCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224710@macro@PWM_1_INTEN_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "3734",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224842@macro@PWM_1_INTEN_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "3736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@224972@macro@PWM_1_INTEN_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "3738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225104@macro@PWM_1_INTEN_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "3740",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225234@macro@PWM_1_INTEN_INTCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "3742",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225313@macro@PWM_1_INTEN_INTCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_INTEN_INTCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "3743",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_INTEN_INTCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225635@macro@PWM_1_RIS_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_RIS_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "3750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_RIS_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225766@macro@PWM_1_RIS_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_RIS_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "3752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_RIS_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225847@macro@PWM_1_RIS_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_RIS_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "3753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_RIS_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@225978@macro@PWM_1_RIS_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_RIS_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "3755",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_RIS_INTCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_DBCTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@234529@macro@PWM_1_DBRISE_RISEDELAY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_DBRISE_RISEDELAY_M",
+    "location": {
+      "column": "9",
+      "line": "3903",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_DBRISE_RISEDELAY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@234679@macro@PWM_1_DBRISE_RISEDELAY_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_DBRISE_RISEDELAY_S",
+    "location": {
+      "column": "9",
+      "line": "3905",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_DBRISE_RISEDELAY_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@235048@macro@PWM_1_DBFALL_FALLDELAY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_DBFALL_FALLDELAY_M",
+    "location": {
+      "column": "9",
+      "line": "3913",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_DBFALL_FALLDELAY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@235198@macro@PWM_1_DBFALL_FALLDELAY_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_DBFALL_FALLDELAY_S",
+    "location": {
+      "column": "9",
+      "line": "3915",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_DBFALL_FALLDELAY_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@235572@macro@PWM_1_FLTSRC0_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC0_FAULT1",
+    "location": {
+      "column": "9",
+      "line": "3924",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC0_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@235633@macro@PWM_1_FLTSRC0_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC0_FAULT0",
+    "location": {
+      "column": "9",
+      "line": "3925",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@235952@macro@PWM_1_FLTSRC1_DCMP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP7",
+    "location": {
+      "column": "9",
+      "line": "3933",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236021@macro@PWM_1_FLTSRC1_DCMP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP6",
+    "location": {
+      "column": "9",
+      "line": "3934",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236090@macro@PWM_1_FLTSRC1_DCMP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP5",
+    "location": {
+      "column": "9",
+      "line": "3935",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236159@macro@PWM_1_FLTSRC1_DCMP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP4",
+    "location": {
+      "column": "9",
+      "line": "3936",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236228@macro@PWM_1_FLTSRC1_DCMP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP3",
+    "location": {
+      "column": "9",
+      "line": "3937",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236297@macro@PWM_1_FLTSRC1_DCMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP2",
+    "location": {
+      "column": "9",
+      "line": "3938",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236366@macro@PWM_1_FLTSRC1_DCMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP1",
+    "location": {
+      "column": "9",
+      "line": "3939",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236435@macro@PWM_1_FLTSRC1_DCMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSRC1_DCMP0",
+    "location": {
+      "column": "9",
+      "line": "3940",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSRC1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236764@macro@PWM_1_MINFLTPER_MFP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_MINFLTPER_MFP_M",
+    "location": {
+      "column": "9",
+      "line": "3948",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_MINFLTPER_MFP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@236833@macro@PWM_1_MINFLTPER_MFP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_MINFLTPER_MFP_S",
+    "location": {
+      "column": "9",
+      "line": "3949",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_MINFLTPER_MFP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237118@macro@PWM_2_CTL_LATCH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_LATCH",
+    "location": {
+      "column": "9",
+      "line": "3956",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_LATCH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237184@macro@PWM_2_CTL_MINFLTPER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_MINFLTPER",
+    "location": {
+      "column": "9",
+      "line": "3957",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_MINFLTPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237253@macro@PWM_2_CTL_FLTSRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_FLTSRC",
+    "location": {
+      "column": "9",
+      "line": "3958",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_FLTSRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237324@macro@PWM_2_CTL_DBFALLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBFALLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3959",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBFALLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237395@macro@PWM_2_CTL_DBFALLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBFALLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3960",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBFALLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237453@macro@PWM_2_CTL_DBFALLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBFALLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3961",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBFALLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237522@macro@PWM_2_CTL_DBFALLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBFALLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3962",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBFALLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237592@macro@PWM_2_CTL_DBRISEUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBRISEUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3963",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBRISEUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237663@macro@PWM_2_CTL_DBRISEUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBRISEUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3964",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBRISEUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237721@macro@PWM_2_CTL_DBRISEUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBRISEUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3965",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBRISEUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237790@macro@PWM_2_CTL_DBRISEUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBRISEUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3966",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBRISEUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237860@macro@PWM_2_CTL_DBCTLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBCTLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3967",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBCTLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237930@macro@PWM_2_CTL_DBCTLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBCTLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3968",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBCTLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@237988@macro@PWM_2_CTL_DBCTLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBCTLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3969",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBCTLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238057@macro@PWM_2_CTL_DBCTLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DBCTLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3970",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DBCTLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238127@macro@PWM_2_CTL_GENBUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENBUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3971",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENBUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238196@macro@PWM_2_CTL_GENBUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENBUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3972",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENBUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238254@macro@PWM_2_CTL_GENBUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENBUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3973",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENBUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238323@macro@PWM_2_CTL_GENBUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENBUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3974",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENBUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238393@macro@PWM_2_CTL_GENAUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENAUPD_M",
+    "location": {
+      "column": "9",
+      "line": "3975",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENAUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238462@macro@PWM_2_CTL_GENAUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENAUPD_I",
+    "location": {
+      "column": "9",
+      "line": "3976",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENAUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238520@macro@PWM_2_CTL_GENAUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENAUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "3977",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENAUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238589@macro@PWM_2_CTL_GENAUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_GENAUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "3978",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_GENAUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238659@macro@PWM_2_CTL_CMPBUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_CMPBUPD",
+    "location": {
+      "column": "9",
+      "line": "3979",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_CMPBUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238732@macro@PWM_2_CTL_CMPAUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_CMPAUPD",
+    "location": {
+      "column": "9",
+      "line": "3980",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_CMPAUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238805@macro@PWM_2_CTL_LOADUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_LOADUPD",
+    "location": {
+      "column": "9",
+      "line": "3981",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_LOADUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238879@macro@PWM_2_CTL_DEBUG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_DEBUG",
+    "location": {
+      "column": "9",
+      "line": "3982",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_DEBUG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238938@macro@PWM_2_CTL_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_MODE",
+    "location": {
+      "column": "9",
+      "line": "3983",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@238999@macro@PWM_2_CTL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CTL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "3984",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239316@macro@PWM_2_INTEN_TRCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCMPBD",
+    "location": {
+      "column": "9",
+      "line": "3991",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239446@macro@PWM_2_INTEN_TRCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCMPBU",
+    "location": {
+      "column": "9",
+      "line": "3993",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239526@macro@PWM_2_INTEN_TRCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCMPAD",
+    "location": {
+      "column": "9",
+      "line": "3994",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239656@macro@PWM_2_INTEN_TRCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCMPAU",
+    "location": {
+      "column": "9",
+      "line": "3996",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239736@macro@PWM_2_INTEN_TRCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "3997",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239813@macro@PWM_2_INTEN_TRCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_TRCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "3998",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_TRCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@239883@macro@PWM_2_INTEN_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "3999",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240015@macro@PWM_2_INTEN_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "4001",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240145@macro@PWM_2_INTEN_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "4003",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240277@macro@PWM_2_INTEN_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "4005",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240407@macro@PWM_2_INTEN_INTCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "4007",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240486@macro@PWM_2_INTEN_INTCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_INTEN_INTCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "4008",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_INTEN_INTCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240808@macro@PWM_2_RIS_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "4015",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@240939@macro@PWM_2_RIS_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "4017",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241020@macro@PWM_2_RIS_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "4018",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241151@macro@PWM_2_RIS_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "4020",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241232@macro@PWM_2_RIS_INTCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "4021",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241310@macro@PWM_2_RIS_INTCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_RIS_INTCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "4022",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_RIS_INTCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241635@macro@PWM_2_ISC_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "4029",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241711@macro@PWM_2_ISC_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "4030",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241785@macro@PWM_2_ISC_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "4031",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241861@macro@PWM_2_ISC_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "4032",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@241935@macro@PWM_2_ISC_INTCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "4033",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@242006@macro@PWM_2_ISC_INTCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_ISC_INTCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "4034",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_ISC_INTCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@242325@macro@PWM_2_LOAD_LOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_LOAD_LOAD_M",
+    "location": {
+      "column": "9",
+      "line": "4041",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_LOAD_LOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@242392@macro@PWM_2_LOAD_LOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_LOAD_LOAD_S",
+    "location": {
+      "column": "9",
+      "line": "4042",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_LOAD_LOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@242679@macro@PWM_2_COUNT_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_COUNT_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "4049",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_COUNT_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@242741@macro@PWM_2_COUNT_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_COUNT_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "4050",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_COUNT_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@243027@macro@PWM_2_CMPA_COMPA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CMPA_COMPA_M",
+    "location": {
+      "column": "9",
+      "line": "4057",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CMPA_COMPA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@243094@macro@PWM_2_CMPA_COMPA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CMPA_COMPA_S",
+    "location": {
+      "column": "9",
+      "line": "4058",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CMPA_COMPA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@243380@macro@PWM_2_CMPB_COMPB_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CMPB_COMPB_M",
+    "location": {
+      "column": "9",
+      "line": "4065",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CMPB_COMPB_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@243447@macro@PWM_2_CMPB_COMPB_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_CMPB_COMPB_S",
+    "location": {
+      "column": "9",
+      "line": "4066",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_CMPB_COMPB_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@243733@macro@PWM_2_GENA_ACTCMPBD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_GENA_ACTCMPBD_M",
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+    },
+    "name": "PWM_2_MINFLTPER_MFP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252291@macro@PWM_3_CTL_LATCH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_LATCH",
+    "location": {
+      "column": "9",
+      "line": "4221",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_LATCH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252357@macro@PWM_3_CTL_MINFLTPER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_MINFLTPER",
+    "location": {
+      "column": "9",
+      "line": "4222",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_MINFLTPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252426@macro@PWM_3_CTL_FLTSRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_FLTSRC",
+    "location": {
+      "column": "9",
+      "line": "4223",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_FLTSRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252497@macro@PWM_3_CTL_DBFALLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBFALLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "4224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBFALLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252568@macro@PWM_3_CTL_DBFALLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBFALLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "4225",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBFALLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252626@macro@PWM_3_CTL_DBFALLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBFALLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "4226",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBFALLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252695@macro@PWM_3_CTL_DBFALLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBFALLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "4227",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBFALLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252765@macro@PWM_3_CTL_DBRISEUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBRISEUPD_M",
+    "location": {
+      "column": "9",
+      "line": "4228",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBRISEUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252836@macro@PWM_3_CTL_DBRISEUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBRISEUPD_I",
+    "location": {
+      "column": "9",
+      "line": "4229",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBRISEUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252894@macro@PWM_3_CTL_DBRISEUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBRISEUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "4230",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBRISEUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@252963@macro@PWM_3_CTL_DBRISEUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBRISEUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "4231",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBRISEUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253033@macro@PWM_3_CTL_DBCTLUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBCTLUPD_M",
+    "location": {
+      "column": "9",
+      "line": "4232",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBCTLUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253103@macro@PWM_3_CTL_DBCTLUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBCTLUPD_I",
+    "location": {
+      "column": "9",
+      "line": "4233",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBCTLUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253161@macro@PWM_3_CTL_DBCTLUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBCTLUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "4234",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBCTLUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253230@macro@PWM_3_CTL_DBCTLUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DBCTLUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "4235",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DBCTLUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253300@macro@PWM_3_CTL_GENBUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENBUPD_M",
+    "location": {
+      "column": "9",
+      "line": "4236",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENBUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253369@macro@PWM_3_CTL_GENBUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENBUPD_I",
+    "location": {
+      "column": "9",
+      "line": "4237",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENBUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253427@macro@PWM_3_CTL_GENBUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENBUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "4238",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENBUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253496@macro@PWM_3_CTL_GENBUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENBUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "4239",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENBUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253566@macro@PWM_3_CTL_GENAUPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENAUPD_M",
+    "location": {
+      "column": "9",
+      "line": "4240",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENAUPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253635@macro@PWM_3_CTL_GENAUPD_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENAUPD_I",
+    "location": {
+      "column": "9",
+      "line": "4241",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENAUPD_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253693@macro@PWM_3_CTL_GENAUPD_LS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENAUPD_LS",
+    "location": {
+      "column": "9",
+      "line": "4242",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENAUPD_LS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253762@macro@PWM_3_CTL_GENAUPD_GS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_GENAUPD_GS",
+    "location": {
+      "column": "9",
+      "line": "4243",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_GENAUPD_GS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253832@macro@PWM_3_CTL_CMPBUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_CMPBUPD",
+    "location": {
+      "column": "9",
+      "line": "4244",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_CMPBUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253905@macro@PWM_3_CTL_CMPAUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_CMPAUPD",
+    "location": {
+      "column": "9",
+      "line": "4245",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_CMPAUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@253978@macro@PWM_3_CTL_LOADUPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_LOADUPD",
+    "location": {
+      "column": "9",
+      "line": "4246",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_LOADUPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254052@macro@PWM_3_CTL_DEBUG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_DEBUG",
+    "location": {
+      "column": "9",
+      "line": "4247",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_DEBUG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254111@macro@PWM_3_CTL_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_MODE",
+    "location": {
+      "column": "9",
+      "line": "4248",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254172@macro@PWM_3_CTL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_CTL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "4249",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_CTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254489@macro@PWM_3_INTEN_TRCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCMPBD",
+    "location": {
+      "column": "9",
+      "line": "4256",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254619@macro@PWM_3_INTEN_TRCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCMPBU",
+    "location": {
+      "column": "9",
+      "line": "4258",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254699@macro@PWM_3_INTEN_TRCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCMPAD",
+    "location": {
+      "column": "9",
+      "line": "4259",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254829@macro@PWM_3_INTEN_TRCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCMPAU",
+    "location": {
+      "column": "9",
+      "line": "4261",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCMPAU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254909@macro@PWM_3_INTEN_TRCNTLOAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCNTLOAD",
+    "location": {
+      "column": "9",
+      "line": "4262",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCNTLOAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@254986@macro@PWM_3_INTEN_TRCNTZERO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_TRCNTZERO",
+    "location": {
+      "column": "9",
+      "line": "4263",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_TRCNTZERO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@255056@macro@PWM_3_INTEN_INTCMPBD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_INTCMPBD",
+    "location": {
+      "column": "9",
+      "line": "4264",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_INTCMPBD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@255188@macro@PWM_3_INTEN_INTCMPBU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_INTCMPBU",
+    "location": {
+      "column": "9",
+      "line": "4266",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_INTCMPBU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@255318@macro@PWM_3_INTEN_INTCMPAD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_INTCMPAD",
+    "location": {
+      "column": "9",
+      "line": "4268",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_INTEN_INTCMPAD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@255450@macro@PWM_3_INTEN_INTCMPAU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_INTEN_INTCMPAU",
+    "location": {
+      "column": "9",
+      "line": "4270",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@264049@macro@PWM_3_GENB_ACTZERO_NONE",
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+    "display": "PWM_3_GENB_ACTZERO_NONE",
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@264108@macro@PWM_3_GENB_ACTZERO_INV",
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+    "display": "PWM_3_GENB_ACTZERO_INV",
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+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@264168@macro@PWM_3_GENB_ACTZERO_ZERO",
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+    "display": "PWM_3_GENB_ACTZERO_ZERO",
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+    },
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+  },
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+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_DBCTL_ENABLE",
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+    },
+    "name": "PWM_3_DBRISE_RISEDELAY_M",
+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@265025@macro@PWM_3_DBRISE_RISEDELAY_S",
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+    },
+    "name": "PWM_3_DBRISE_RISEDELAY_S",
+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@265394@macro@PWM_3_DBFALL_FALLDELAY_M",
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+    "display": "PWM_3_DBFALL_FALLDELAY_M",
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+    },
+    "name": "PWM_3_DBFALL_FALLDELAY_M",
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+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@265544@macro@PWM_3_DBFALL_FALLDELAY_S",
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+    "display": "PWM_3_DBFALL_FALLDELAY_S",
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+    },
+    "name": "PWM_3_DBFALL_FALLDELAY_S",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@265918@macro@PWM_3_FLTSRC0_FAULT1",
+    "What": "MacroDef",
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+    "display": "PWM_3_FLTSRC0_FAULT1",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@265979@macro@PWM_3_FLTSRC0_FAULT0",
+    "What": "MacroDef",
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+    "display": "PWM_3_FLTSRC0_FAULT0",
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+    },
+    "name": "PWM_3_FLTSRC0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@266298@macro@PWM_3_FLTSRC1_DCMP7",
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+    "display": "PWM_3_FLTSRC1_DCMP7",
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+    },
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+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@266367@macro@PWM_3_FLTSRC1_DCMP6",
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+    },
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+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@266436@macro@PWM_3_FLTSRC1_DCMP5",
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+    "display": "PWM_3_FLTSRC1_DCMP5",
+    "location": {
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+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@266505@macro@PWM_3_FLTSRC1_DCMP4",
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+    "display": "PWM_3_FLTSRC1_DCMP4",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@266574@macro@PWM_3_FLTSRC1_DCMP3",
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+    "display": "PWM_3_FLTSRC1_DCMP3",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_3_FLTSRC1_DCMP2",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@266712@macro@PWM_3_FLTSRC1_DCMP1",
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+    "display": "PWM_3_FLTSRC1_DCMP1",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_3_FLTSRC1_DCMP0",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_3_MINFLTPER_MFP_M",
+    "location": {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_3_MINFLTPER_MFP_S",
+    "location": {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_0_FLTSEN_FAULT0",
+    "location": {
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+      "line": "4487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSEN_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_0_FLTSTAT0_FAULT1",
+    "location": {
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+      "line": "4495",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_0_FLTSTAT0_FAULT0",
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+    },
+    "name": "PWM_0_FLTSTAT0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_0_FLTSTAT1_DCMP7",
+    "location": {
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+      "line": "4504",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSTAT1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_0_FLTSTAT1_DCMP6",
+    "location": {
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+      "line": "4505",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_0_FLTSTAT1_DCMP5",
+    "location": {
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+      "line": "4506",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "PWM_0_FLTSTAT1_DCMP4",
+    "location": {
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+      "line": "4507",
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+    },
+    "name": "PWM_0_FLTSTAT1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_0_FLTSTAT1_DCMP3",
+    "location": {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "PWM_0_FLTSTAT1_DCMP2",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSTAT1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_0_FLTSTAT1_DCMP1",
+    "location": {
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+    },
+    "name": "PWM_0_FLTSTAT1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@268770@macro@PWM_0_FLTSTAT1_DCMP0",
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+    "display": "PWM_0_FLTSTAT1_DCMP0",
+    "location": {
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+      "line": "4511",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_0_FLTSTAT1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269100@macro@PWM_1_FLTSEN_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSEN_FAULT1",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSEN_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269161@macro@PWM_1_FLTSEN_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSEN_FAULT0",
+    "location": {
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+    },
+    "name": "PWM_1_FLTSEN_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269481@macro@PWM_1_FLTSTAT0_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT0_FAULT1",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT0_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269543@macro@PWM_1_FLTSTAT0_FAULT0",
+    "What": "MacroDef",
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+    "display": "PWM_1_FLTSTAT0_FAULT0",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269864@macro@PWM_1_FLTSTAT1_DCMP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP7",
+    "location": {
+      "column": "9",
+      "line": "4536",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@269941@macro@PWM_1_FLTSTAT1_DCMP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP6",
+    "location": {
+      "column": "9",
+      "line": "4537",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270018@macro@PWM_1_FLTSTAT1_DCMP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP5",
+    "location": {
+      "column": "9",
+      "line": "4538",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270095@macro@PWM_1_FLTSTAT1_DCMP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP4",
+    "location": {
+      "column": "9",
+      "line": "4539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270172@macro@PWM_1_FLTSTAT1_DCMP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP3",
+    "location": {
+      "column": "9",
+      "line": "4540",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270249@macro@PWM_1_FLTSTAT1_DCMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP2",
+    "location": {
+      "column": "9",
+      "line": "4541",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270326@macro@PWM_1_FLTSTAT1_DCMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP1",
+    "location": {
+      "column": "9",
+      "line": "4542",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270403@macro@PWM_1_FLTSTAT1_DCMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_1_FLTSTAT1_DCMP0",
+    "location": {
+      "column": "9",
+      "line": "4543",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_1_FLTSTAT1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270739@macro@PWM_2_FLTSTAT0_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT0_FAULT1",
+    "location": {
+      "column": "9",
+      "line": "4551",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT0_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@270801@macro@PWM_2_FLTSTAT0_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT0_FAULT0",
+    "location": {
+      "column": "9",
+      "line": "4552",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271122@macro@PWM_2_FLTSTAT1_DCMP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP7",
+    "location": {
+      "column": "9",
+      "line": "4560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271199@macro@PWM_2_FLTSTAT1_DCMP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP6",
+    "location": {
+      "column": "9",
+      "line": "4561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271276@macro@PWM_2_FLTSTAT1_DCMP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP5",
+    "location": {
+      "column": "9",
+      "line": "4562",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271353@macro@PWM_2_FLTSTAT1_DCMP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP4",
+    "location": {
+      "column": "9",
+      "line": "4563",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271430@macro@PWM_2_FLTSTAT1_DCMP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP3",
+    "location": {
+      "column": "9",
+      "line": "4564",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271507@macro@PWM_2_FLTSTAT1_DCMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP2",
+    "location": {
+      "column": "9",
+      "line": "4565",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271584@macro@PWM_2_FLTSTAT1_DCMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP1",
+    "location": {
+      "column": "9",
+      "line": "4566",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271661@macro@PWM_2_FLTSTAT1_DCMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_2_FLTSTAT1_DCMP0",
+    "location": {
+      "column": "9",
+      "line": "4567",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_2_FLTSTAT1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@271997@macro@PWM_3_FLTSTAT0_FAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT0_FAULT1",
+    "location": {
+      "column": "9",
+      "line": "4575",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT0_FAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272059@macro@PWM_3_FLTSTAT0_FAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT0_FAULT0",
+    "location": {
+      "column": "9",
+      "line": "4576",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT0_FAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272380@macro@PWM_3_FLTSTAT1_DCMP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP7",
+    "location": {
+      "column": "9",
+      "line": "4584",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272457@macro@PWM_3_FLTSTAT1_DCMP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP6",
+    "location": {
+      "column": "9",
+      "line": "4585",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272534@macro@PWM_3_FLTSTAT1_DCMP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP5",
+    "location": {
+      "column": "9",
+      "line": "4586",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272611@macro@PWM_3_FLTSTAT1_DCMP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP4",
+    "location": {
+      "column": "9",
+      "line": "4587",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272688@macro@PWM_3_FLTSTAT1_DCMP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP3",
+    "location": {
+      "column": "9",
+      "line": "4588",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272765@macro@PWM_3_FLTSTAT1_DCMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP2",
+    "location": {
+      "column": "9",
+      "line": "4589",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272842@macro@PWM_3_FLTSTAT1_DCMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP1",
+    "location": {
+      "column": "9",
+      "line": "4590",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@272919@macro@PWM_3_FLTSTAT1_DCMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_3_FLTSTAT1_DCMP0",
+    "location": {
+      "column": "9",
+      "line": "4591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_3_FLTSTAT1_DCMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273243@macro@PWM_PP_ONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_ONE",
+    "location": {
+      "column": "9",
+      "line": "4598",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_ONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273305@macro@PWM_PP_EFAULT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_EFAULT",
+    "location": {
+      "column": "9",
+      "line": "4599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_EFAULT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273368@macro@PWM_PP_ESYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_ESYNC",
+    "location": {
+      "column": "9",
+      "line": "4600",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_ESYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273441@macro@PWM_PP_FCNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_FCNT_M",
+    "location": {
+      "column": "9",
+      "line": "4601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_FCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273517@macro@PWM_PP_GCNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_GCNT_M",
+    "location": {
+      "column": "9",
+      "line": "4602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_GCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273576@macro@PWM_PP_FCNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_FCNT_S",
+    "location": {
+      "column": "9",
+      "line": "4603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_FCNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273611@macro@PWM_PP_GCNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "PWM_PP_GCNT_S",
+    "location": {
+      "column": "9",
+      "line": "4604",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "PWM_PP_GCNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273894@macro@QEI_CTL_FILTCNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_FILTCNT_M",
+    "location": {
+      "column": "9",
+      "line": "4611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_FILTCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@273970@macro@QEI_CTL_FILTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_FILTEN",
+    "location": {
+      "column": "9",
+      "line": "4612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_FILTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274038@macro@QEI_CTL_STALLEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_STALLEN",
+    "location": {
+      "column": "9",
+      "line": "4613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_STALLEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274096@macro@QEI_CTL_INVI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_INVI",
+    "location": {
+      "column": "9",
+      "line": "4614",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_INVI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274163@macro@QEI_CTL_INVB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_INVB",
+    "location": {
+      "column": "9",
+      "line": "4615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_INVB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274222@macro@QEI_CTL_INVA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_INVA",
+    "location": {
+      "column": "9",
+      "line": "4616",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_INVA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274281@macro@QEI_CTL_VELDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_M",
+    "location": {
+      "column": "9",
+      "line": "4617",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274348@macro@QEI_CTL_VELDIV_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_1",
+    "location": {
+      "column": "9",
+      "line": "4618",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274409@macro@QEI_CTL_VELDIV_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_2",
+    "location": {
+      "column": "9",
+      "line": "4619",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274470@macro@QEI_CTL_VELDIV_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_4",
+    "location": {
+      "column": "9",
+      "line": "4620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274531@macro@QEI_CTL_VELDIV_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_8",
+    "location": {
+      "column": "9",
+      "line": "4621",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274592@macro@QEI_CTL_VELDIV_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_16",
+    "location": {
+      "column": "9",
+      "line": "4622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274654@macro@QEI_CTL_VELDIV_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_32",
+    "location": {
+      "column": "9",
+      "line": "4623",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274716@macro@QEI_CTL_VELDIV_64",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_64",
+    "location": {
+      "column": "9",
+      "line": "4624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274778@macro@QEI_CTL_VELDIV_128",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELDIV_128",
+    "location": {
+      "column": "9",
+      "line": "4625",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELDIV_128",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274841@macro@QEI_CTL_VELEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_VELEN",
+    "location": {
+      "column": "9",
+      "line": "4626",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_VELEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274906@macro@QEI_CTL_RESMODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_RESMODE",
+    "location": {
+      "column": "9",
+      "line": "4627",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_RESMODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@274965@macro@QEI_CTL_CAPMODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_CAPMODE",
+    "location": {
+      "column": "9",
+      "line": "4628",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_CAPMODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275026@macro@QEI_CTL_SIGMODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_SIGMODE",
+    "location": {
+      "column": "9",
+      "line": "4629",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_SIGMODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275086@macro@QEI_CTL_SWAP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_SWAP",
+    "location": {
+      "column": "9",
+      "line": "4630",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_SWAP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275147@macro@QEI_CTL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "4631",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275206@macro@QEI_CTL_FILTCNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_CTL_FILTCNT_S",
+    "location": {
+      "column": "9",
+      "line": "4632",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_CTL_FILTCNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275491@macro@QEI_STAT_DIRECTION",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_STAT_DIRECTION",
+    "location": {
+      "column": "9",
+      "line": "4639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_STAT_DIRECTION",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275561@macro@QEI_STAT_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_STAT_ERROR",
+    "location": {
+      "column": "9",
+      "line": "4640",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_STAT_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@275872@macro@QEI_POS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_POS_M",
+    "location": {
+      "column": "9",
+      "line": "4647",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_POS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@276002@macro@QEI_POS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_POS_S",
+    "location": {
+      "column": "9",
+      "line": "4649",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_POS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@276288@macro@QEI_MAXPOS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_MAXPOS_M",
+    "location": {
+      "column": "9",
+      "line": "4656",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_MAXPOS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@276418@macro@QEI_MAXPOS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_MAXPOS_S",
+    "location": {
+      "column": "9",
+      "line": "4658",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_MAXPOS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@276702@macro@QEI_LOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_LOAD_M",
+    "location": {
+      "column": "9",
+      "line": "4665",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_LOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@276776@macro@QEI_LOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_LOAD_S",
+    "location": {
+      "column": "9",
+      "line": "4666",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_LOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277060@macro@QEI_TIME_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_TIME_M",
+    "location": {
+      "column": "9",
+      "line": "4673",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_TIME_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277137@macro@QEI_TIME_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_TIME_S",
+    "location": {
+      "column": "9",
+      "line": "4674",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_TIME_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277422@macro@QEI_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "4681",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277491@macro@QEI_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "4682",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277776@macro@QEI_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "4689",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@277833@macro@QEI_SPEED_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_SPEED_S",
+    "location": {
+      "column": "9",
+      "line": "4690",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_SPEED_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278118@macro@QEI_INTEN_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_INTEN_ERROR",
+    "location": {
+      "column": "9",
+      "line": "4697",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_INTEN_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278195@macro@QEI_INTEN_DIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_INTEN_DIR",
+    "location": {
+      "column": "9",
+      "line": "4698",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_INTEN_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278325@macro@QEI_INTEN_TIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_INTEN_TIMER",
+    "location": {
+      "column": "9",
+      "line": "4700",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_INTEN_TIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278404@macro@QEI_INTEN_INDEX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_INTEN_INDEX",
+    "location": {
+      "column": "9",
+      "line": "4701",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_INTEN_INDEX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278786@macro@QEI_RIS_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_RIS_ERROR",
+    "location": {
+      "column": "9",
+      "line": "4709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_RIS_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278855@macro@QEI_RIS_DIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_RIS_DIR",
+    "location": {
+      "column": "9",
+      "line": "4710",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_RIS_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@278929@macro@QEI_RIS_TIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_RIS_TIMER",
+    "location": {
+      "column": "9",
+      "line": "4711",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_RIS_TIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279000@macro@QEI_RIS_INDEX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_RIS_INDEX",
+    "location": {
+      "column": "9",
+      "line": "4712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_RIS_INDEX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279317@macro@QEI_ISC_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_ISC_ERROR",
+    "location": {
+      "column": "9",
+      "line": "4719",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_ISC_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279387@macro@QEI_ISC_DIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_ISC_DIR",
+    "location": {
+      "column": "9",
+      "line": "4720",
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+    },
+    "name": "QEI_ISC_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279462@macro@QEI_ISC_TIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_ISC_TIMER",
+    "location": {
+      "column": "9",
+      "line": "4721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_ISC_TIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279543@macro@QEI_ISC_INDEX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "QEI_ISC_INDEX",
+    "location": {
+      "column": "9",
+      "line": "4722",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "QEI_ISC_INDEX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279863@macro@TIMER_CFG_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CFG_M",
+    "location": {
+      "column": "9",
+      "line": "4729",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CFG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@279930@macro@TIMER_CFG_32_BIT_TIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CFG_32_BIT_TIMER",
+    "location": {
+      "column": "9",
+      "line": "4730",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CFG_32_BIT_TIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@280147@macro@TIMER_CFG_32_BIT_RTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CFG_32_BIT_RTC",
+    "location": {
+      "column": "9",
+      "line": "4733",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CFG_32_BIT_RTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@280436@macro@TIMER_CFG_16_BIT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CFG_16_BIT",
+    "location": {
+      "column": "9",
+      "line": "4737",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CFG_16_BIT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@280904@macro@TIMER_TAMR_TAPLO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAPLO",
+    "location": {
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+      "line": "4746",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAPLO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281034@macro@TIMER_TAMR_TAMRSU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMRSU",
+    "location": {
+      "column": "9",
+      "line": "4748",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMRSU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281165@macro@TIMER_TAMR_TAPWMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAPWMIE",
+    "location": {
+      "column": "9",
+      "line": "4750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAPWMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281295@macro@TIMER_TAMR_TAILD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAILD",
+    "location": {
+      "column": "9",
+      "line": "4752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAILD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281376@macro@TIMER_TAMR_TASNAPS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TASNAPS",
+    "location": {
+      "column": "9",
+      "line": "4753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TASNAPS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281452@macro@TIMER_TAMR_TAWOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAWOT",
+    "location": {
+      "column": "9",
+      "line": "4754",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAWOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281529@macro@TIMER_TAMR_TAMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMIE",
+    "location": {
+      "column": "9",
+      "line": "4755",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281661@macro@TIMER_TAMR_TACDIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TACDIR",
+    "location": {
+      "column": "9",
+      "line": "4757",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TACDIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281738@macro@TIMER_TAMR_TAAMS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAAMS",
+    "location": {
+      "column": "9",
+      "line": "4758",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAAMS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281869@macro@TIMER_TAMR_TACMR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TACMR",
+    "location": {
+      "column": "9",
+      "line": "4760",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TACMR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@281943@macro@TIMER_TAMR_TAMR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMR_M",
+    "location": {
+      "column": "9",
+      "line": "4761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282009@macro@TIMER_TAMR_TAMR_1_SHOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMR_1_SHOT",
+    "location": {
+      "column": "9",
+      "line": "4762",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMR_1_SHOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282077@macro@TIMER_TAMR_TAMR_PERIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMR_PERIOD",
+    "location": {
+      "column": "9",
+      "line": "4763",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMR_PERIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282145@macro@TIMER_TAMR_TAMR_CAP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TAMR_TAMR_CAP",
+    "location": {
+      "column": "9",
+      "line": "4764",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TAMR_TAMR_CAP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282457@macro@TIMER_TBMR_TBPLO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBPLO",
+    "location": {
+      "column": "9",
+      "line": "4771",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBPLO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282587@macro@TIMER_TBMR_TBMRSU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMRSU",
+    "location": {
+      "column": "9",
+      "line": "4773",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMRSU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282718@macro@TIMER_TBMR_TBPWMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBPWMIE",
+    "location": {
+      "column": "9",
+      "line": "4775",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBPWMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282848@macro@TIMER_TBMR_TBILD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBILD",
+    "location": {
+      "column": "9",
+      "line": "4777",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBILD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@282929@macro@TIMER_TBMR_TBSNAPS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBSNAPS",
+    "location": {
+      "column": "9",
+      "line": "4778",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBSNAPS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283005@macro@TIMER_TBMR_TBWOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBWOT",
+    "location": {
+      "column": "9",
+      "line": "4779",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBWOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283082@macro@TIMER_TBMR_TBMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMIE",
+    "location": {
+      "column": "9",
+      "line": "4780",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283214@macro@TIMER_TBMR_TBCDIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBCDIR",
+    "location": {
+      "column": "9",
+      "line": "4782",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBCDIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283291@macro@TIMER_TBMR_TBAMS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBAMS",
+    "location": {
+      "column": "9",
+      "line": "4783",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBAMS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283422@macro@TIMER_TBMR_TBCMR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBCMR",
+    "location": {
+      "column": "9",
+      "line": "4785",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBCMR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283496@macro@TIMER_TBMR_TBMR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_M",
+    "location": {
+      "column": "9",
+      "line": "4786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283562@macro@TIMER_TBMR_TBMR_1_SHOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_1_SHOT",
+    "location": {
+      "column": "9",
+      "line": "4787",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMR_1_SHOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283630@macro@TIMER_TBMR_TBMR_PERIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_PERIOD",
+    "location": {
+      "column": "9",
+      "line": "4788",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMR_PERIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@283698@macro@TIMER_TBMR_TBMR_CAP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_CAP",
+    "location": {
+      "column": "9",
+      "line": "4789",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_TBMR_TBMR_CAP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284009@macro@TIMER_CTL_TBPWML",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBPWML",
+    "location": {
+      "column": "9",
+      "line": "4796",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBPWML",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284087@macro@TIMER_CTL_TBOTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBOTE",
+    "location": {
+      "column": "9",
+      "line": "4797",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBOTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284218@macro@TIMER_CTL_TBEVENT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_M",
+    "location": {
+      "column": "9",
+      "line": "4799",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284290@macro@TIMER_CTL_TBEVENT_POS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_POS",
+    "location": {
+      "column": "9",
+      "line": "4800",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_POS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284352@macro@TIMER_CTL_TBEVENT_NEG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_NEG",
+    "location": {
+      "column": "9",
+      "line": "4801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_NEG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284414@macro@TIMER_CTL_TBEVENT_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_BOTH",
+    "location": {
+      "column": "9",
+      "line": "4802",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284473@macro@TIMER_CTL_TBSTALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBSTALL",
+    "location": {
+      "column": "9",
+      "line": "4803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBSTALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284547@macro@TIMER_CTL_TBEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEN",
+    "location": {
+      "column": "9",
+      "line": "4804",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TBEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284615@macro@TIMER_CTL_TAPWML",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAPWML",
+    "location": {
+      "column": "9",
+      "line": "4805",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAPWML",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284693@macro@TIMER_CTL_TAOTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAOTE",
+    "location": {
+      "column": "9",
+      "line": "4806",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAOTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284824@macro@TIMER_CTL_RTCEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_RTCEN",
+    "location": {
+      "column": "9",
+      "line": "4808",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_RTCEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284894@macro@TIMER_CTL_TAEVENT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_M",
+    "location": {
+      "column": "9",
+      "line": "4809",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@284966@macro@TIMER_CTL_TAEVENT_POS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_POS",
+    "location": {
+      "column": "9",
+      "line": "4810",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_POS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285028@macro@TIMER_CTL_TAEVENT_NEG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_NEG",
+    "location": {
+      "column": "9",
+      "line": "4811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_NEG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285090@macro@TIMER_CTL_TAEVENT_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_BOTH",
+    "location": {
+      "column": "9",
+      "line": "4812",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285149@macro@TIMER_CTL_TASTALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TASTALL",
+    "location": {
+      "column": "9",
+      "line": "4813",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TASTALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285223@macro@TIMER_CTL_TAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEN",
+    "location": {
+      "column": "9",
+      "line": "4814",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_CTL_TAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285542@macro@TIMER_SYNC_SYNCWT5_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_M",
+    "location": {
+      "column": "9",
+      "line": "4821",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285673@macro@TIMER_SYNC_SYNCWT5_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_NONE",
+    "location": {
+      "column": "9",
+      "line": "4823",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@285808@macro@TIMER_SYNC_SYNCWT5_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_TA",
+    "location": {
+      "column": "9",
+      "line": "4825",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286019@macro@TIMER_SYNC_SYNCWT5_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_TB",
+    "location": {
+      "column": "9",
+      "line": "4828",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_TB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286230@macro@TIMER_SYNC_SYNCWT5_TATB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_TATB",
+    "location": {
+      "column": "9",
+      "line": "4831",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_TATB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286458@macro@TIMER_SYNC_SYNCWT4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT4_M",
+    "location": {
+      "column": "9",
+      "line": "4834",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286589@macro@TIMER_SYNC_SYNCWT4_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT4_NONE",
+    "location": {
+      "column": "9",
+      "line": "4836",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT4_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286724@macro@TIMER_SYNC_SYNCWT4_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT4_TA",
+    "location": {
+      "column": "9",
+      "line": "4838",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT4_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@286935@macro@TIMER_SYNC_SYNCWT4_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT4_TB",
+    "location": {
+      "column": "9",
+      "line": "4841",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT4_TB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@287146@macro@TIMER_SYNC_SYNCWT4_TATB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT4_TATB",
+    "location": {
+      "column": "9",
+      "line": "4844",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT4_TATB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@287374@macro@TIMER_SYNC_SYNCWT3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT3_M",
+    "location": {
+      "column": "9",
+      "line": "4847",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@287505@macro@TIMER_SYNC_SYNCWT3_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT3_NONE",
+    "location": {
+      "column": "9",
+      "line": "4849",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT3_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@287640@macro@TIMER_SYNC_SYNCWT3_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT3_TA",
+    "location": {
+      "column": "9",
+      "line": "4851",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT3_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@287851@macro@TIMER_SYNC_SYNCWT3_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT3_TB",
+    "location": {
+      "column": "9",
+      "line": "4854",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT3_TB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288062@macro@TIMER_SYNC_SYNCWT3_TATB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT3_TATB",
+    "location": {
+      "column": "9",
+      "line": "4857",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT3_TATB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288290@macro@TIMER_SYNC_SYNCWT2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT2_M",
+    "location": {
+      "column": "9",
+      "line": "4860",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288421@macro@TIMER_SYNC_SYNCWT2_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT2_NONE",
+    "location": {
+      "column": "9",
+      "line": "4862",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT2_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288556@macro@TIMER_SYNC_SYNCWT2_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT2_TA",
+    "location": {
+      "column": "9",
+      "line": "4864",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT2_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288767@macro@TIMER_SYNC_SYNCWT2_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT2_TB",
+    "location": {
+      "column": "9",
+      "line": "4867",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT2_TB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@288978@macro@TIMER_SYNC_SYNCWT2_TATB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT2_TATB",
+    "location": {
+      "column": "9",
+      "line": "4870",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT2_TATB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@289206@macro@TIMER_SYNC_SYNCWT1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT1_M",
+    "location": {
+      "column": "9",
+      "line": "4873",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@289337@macro@TIMER_SYNC_SYNCWT1_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT1_NONE",
+    "location": {
+      "column": "9",
+      "line": "4875",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT1_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@289472@macro@TIMER_SYNC_SYNCWT1_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT1_TA",
+    "location": {
+      "column": "9",
+      "line": "4877",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT1_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@289683@macro@TIMER_SYNC_SYNCWT1_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT1_TB",
+    "location": {
+      "column": "9",
+      "line": "4880",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT1_TB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@289894@macro@TIMER_SYNC_SYNCWT1_TATB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT1_TATB",
+    "location": {
+      "column": "9",
+      "line": "4883",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT1_TATB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@290122@macro@TIMER_SYNC_SYNCWT0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT0_M",
+    "location": {
+      "column": "9",
+      "line": "4886",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@290253@macro@TIMER_SYNC_SYNCWT0_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT0_NONE",
+    "location": {
+      "column": "9",
+      "line": "4888",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT0_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@290388@macro@TIMER_SYNC_SYNCWT0_TA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT0_TA",
+    "location": {
+      "column": "9",
+      "line": "4890",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT0_TA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@290599@macro@TIMER_SYNC_SYNCWT0_TB",
+    "What": "MacroDef",
+    "defdec": "Def",
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+    },
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+    "ID": "c:tm4c123gh6pm.h@345282@macro@ADC_DCRIC_DCINT4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCRIC_DCINT4",
+    "location": {
+      "column": "9",
+      "line": "5855",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCRIC_DCINT4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@345361@macro@ADC_DCRIC_DCINT3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCRIC_DCINT3",
+    "location": {
+      "column": "9",
+      "line": "5856",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCRIC_DCINT3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@345440@macro@ADC_DCRIC_DCINT2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCRIC_DCINT2",
+    "location": {
+      "column": "9",
+      "line": "5857",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCRIC_DCINT2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@345519@macro@ADC_DCRIC_DCINT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCRIC_DCINT1",
+    "location": {
+      "column": "9",
+      "line": "5858",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCRIC_DCINT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@345598@macro@ADC_DCRIC_DCINT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCRIC_DCINT0",
+    "location": {
+      "column": "9",
+      "line": "5859",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCRIC_DCINT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@345928@macro@ADC_DCCTL0_CTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTE",
+    "location": {
+      "column": "9",
+      "line": "5866",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346002@macro@ADC_DCCTL0_CTC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTC_M",
+    "location": {
+      "column": "9",
+      "line": "5867",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346079@macro@ADC_DCCTL0_CTC_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTC_LOW",
+    "location": {
+      "column": "9",
+      "line": "5868",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTC_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346136@macro@ADC_DCCTL0_CTC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTC_MID",
+    "location": {
+      "column": "9",
+      "line": "5869",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346193@macro@ADC_DCCTL0_CTC_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTC_HIGH",
+    "location": {
+      "column": "9",
+      "line": "5870",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346251@macro@ADC_DCCTL0_CTM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTM_M",
+    "location": {
+      "column": "9",
+      "line": "5871",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346323@macro@ADC_DCCTL0_CTM_ALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTM_ALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5872",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTM_ALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346378@macro@ADC_DCCTL0_CTM_ONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTM_ONCE",
+    "location": {
+      "column": "9",
+      "line": "5873",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTM_ONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346431@macro@ADC_DCCTL0_CTM_HALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTM_HALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5874",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTM_HALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346497@macro@ADC_DCCTL0_CTM_HONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CTM_HONCE",
+    "location": {
+      "column": "9",
+      "line": "5875",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CTM_HONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346561@macro@ADC_DCCTL0_CIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIE",
+    "location": {
+      "column": "9",
+      "line": "5876",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346637@macro@ADC_DCCTL0_CIC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIC_M",
+    "location": {
+      "column": "9",
+      "line": "5877",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346716@macro@ADC_DCCTL0_CIC_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIC_LOW",
+    "location": {
+      "column": "9",
+      "line": "5878",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIC_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346773@macro@ADC_DCCTL0_CIC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIC_MID",
+    "location": {
+      "column": "9",
+      "line": "5879",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346830@macro@ADC_DCCTL0_CIC_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIC_HIGH",
+    "location": {
+      "column": "9",
+      "line": "5880",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346888@macro@ADC_DCCTL0_CIM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIM_M",
+    "location": {
+      "column": "9",
+      "line": "5881",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@346962@macro@ADC_DCCTL0_CIM_ALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIM_ALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5882",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIM_ALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347017@macro@ADC_DCCTL0_CIM_ONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIM_ONCE",
+    "location": {
+      "column": "9",
+      "line": "5883",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIM_ONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347070@macro@ADC_DCCTL0_CIM_HALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIM_HALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5884",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIM_HALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347136@macro@ADC_DCCTL0_CIM_HONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL0_CIM_HONCE",
+    "location": {
+      "column": "9",
+      "line": "5885",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL0_CIM_HONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347451@macro@ADC_DCCTL1_CTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTE",
+    "location": {
+      "column": "9",
+      "line": "5892",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347525@macro@ADC_DCCTL1_CTC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTC_M",
+    "location": {
+      "column": "9",
+      "line": "5893",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347602@macro@ADC_DCCTL1_CTC_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTC_LOW",
+    "location": {
+      "column": "9",
+      "line": "5894",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTC_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347659@macro@ADC_DCCTL1_CTC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTC_MID",
+    "location": {
+      "column": "9",
+      "line": "5895",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347716@macro@ADC_DCCTL1_CTC_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTC_HIGH",
+    "location": {
+      "column": "9",
+      "line": "5896",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347774@macro@ADC_DCCTL1_CTM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTM_M",
+    "location": {
+      "column": "9",
+      "line": "5897",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347846@macro@ADC_DCCTL1_CTM_ALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTM_ALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5898",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTM_ALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347901@macro@ADC_DCCTL1_CTM_ONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTM_ONCE",
+    "location": {
+      "column": "9",
+      "line": "5899",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTM_ONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@347954@macro@ADC_DCCTL1_CTM_HALWAYS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTM_HALWAYS",
+    "location": {
+      "column": "9",
+      "line": "5900",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTM_HALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348020@macro@ADC_DCCTL1_CTM_HONCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CTM_HONCE",
+    "location": {
+      "column": "9",
+      "line": "5901",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CTM_HONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348084@macro@ADC_DCCTL1_CIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CIE",
+    "location": {
+      "column": "9",
+      "line": "5902",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348160@macro@ADC_DCCTL1_CIC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CIC_M",
+    "location": {
+      "column": "9",
+      "line": "5903",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CIC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348239@macro@ADC_DCCTL1_CIC_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CIC_LOW",
+    "location": {
+      "column": "9",
+      "line": "5904",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CIC_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348296@macro@ADC_DCCTL1_CIC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CIC_MID",
+    "location": {
+      "column": "9",
+      "line": "5905",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CIC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348353@macro@ADC_DCCTL1_CIC_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL1_CIC_HIGH",
+    "location": {
+      "column": "9",
+      "line": "5906",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL1_CIC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348411@macro@ADC_DCCTL1_CIM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@348540@macro@ADC_DCCTL1_CIM_ONCE",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348593@macro@ADC_DCCTL1_CIM_HALWAYS",
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+    },
+    "name": "ADC_DCCTL1_CIM_HALWAYS",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@348659@macro@ADC_DCCTL1_CIM_HONCE",
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+    },
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+    "ID": "c:tm4c123gh6pm.h@348974@macro@ADC_DCCTL2_CTE",
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+    },
+    "name": "ADC_DCCTL2_CTE",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349048@macro@ADC_DCCTL2_CTC_M",
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+    "display": "ADC_DCCTL2_CTC_M",
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+    },
+    "name": "ADC_DCCTL2_CTC_M",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349125@macro@ADC_DCCTL2_CTC_LOW",
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+    "display": "ADC_DCCTL2_CTC_LOW",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CTC_LOW",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349182@macro@ADC_DCCTL2_CTC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL2_CTC_MID",
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+      "line": "5921",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CTC_MID",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349239@macro@ADC_DCCTL2_CTC_HIGH",
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+    "defdec": "Def",
+    "display": "ADC_DCCTL2_CTC_HIGH",
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+      "line": "5922",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CTC_HIGH",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349297@macro@ADC_DCCTL2_CTM_M",
+    "What": "MacroDef",
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+      "line": "5923",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CTM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349369@macro@ADC_DCCTL2_CTM_ALWAYS",
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+    "display": "ADC_DCCTL2_CTM_ALWAYS",
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+      "line": "5924",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CTM_ALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349424@macro@ADC_DCCTL2_CTM_ONCE",
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+    "display": "ADC_DCCTL2_CTM_ONCE",
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+    },
+    "name": "ADC_DCCTL2_CTM_ONCE",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349477@macro@ADC_DCCTL2_CTM_HALWAYS",
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+      "line": "5926",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349543@macro@ADC_DCCTL2_CTM_HONCE",
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+    },
+    "name": "ADC_DCCTL2_CTM_HONCE",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@349607@macro@ADC_DCCTL2_CIE",
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+    },
+    "name": "ADC_DCCTL2_CIE",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349683@macro@ADC_DCCTL2_CIC_M",
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+    "display": "ADC_DCCTL2_CIC_M",
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+      "line": "5929",
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+    },
+    "name": "ADC_DCCTL2_CIC_M",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349762@macro@ADC_DCCTL2_CIC_LOW",
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+    "display": "ADC_DCCTL2_CIC_LOW",
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+      "line": "5930",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIC_LOW",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349819@macro@ADC_DCCTL2_CIC_MID",
+    "What": "MacroDef",
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+    "display": "ADC_DCCTL2_CIC_MID",
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+      "line": "5931",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349876@macro@ADC_DCCTL2_CIC_HIGH",
+    "What": "MacroDef",
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+    "display": "ADC_DCCTL2_CIC_HIGH",
+    "location": {
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+      "line": "5932",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@349934@macro@ADC_DCCTL2_CIM_M",
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+      "line": "5933",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350008@macro@ADC_DCCTL2_CIM_ALWAYS",
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+    "display": "ADC_DCCTL2_CIM_ALWAYS",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350063@macro@ADC_DCCTL2_CIM_ONCE",
+    "What": "MacroDef",
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+    "display": "ADC_DCCTL2_CIM_ONCE",
+    "location": {
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+      "line": "5935",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIM_ONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350116@macro@ADC_DCCTL2_CIM_HALWAYS",
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+      "line": "5936",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIM_HALWAYS",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350182@macro@ADC_DCCTL2_CIM_HONCE",
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+    "display": "ADC_DCCTL2_CIM_HONCE",
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+      "line": "5937",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL2_CIM_HONCE",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350497@macro@ADC_DCCTL3_CTE",
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+      "line": "5944",
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+    },
+    "name": "ADC_DCCTL3_CTE",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350571@macro@ADC_DCCTL3_CTC_M",
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+    "display": "ADC_DCCTL3_CTC_M",
+    "location": {
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+      "line": "5945",
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+    },
+    "name": "ADC_DCCTL3_CTC_M",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350648@macro@ADC_DCCTL3_CTC_LOW",
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+    "display": "ADC_DCCTL3_CTC_LOW",
+    "location": {
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+      "line": "5946",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CTC_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350705@macro@ADC_DCCTL3_CTC_MID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_DCCTL3_CTC_MID",
+    "location": {
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+      "line": "5947",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CTC_MID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350762@macro@ADC_DCCTL3_CTC_HIGH",
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+    "display": "ADC_DCCTL3_CTC_HIGH",
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+      "line": "5948",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350820@macro@ADC_DCCTL3_CTM_M",
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+      "line": "5949",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CTM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350892@macro@ADC_DCCTL3_CTM_ALWAYS",
+    "What": "MacroDef",
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+    "display": "ADC_DCCTL3_CTM_ALWAYS",
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+      "line": "5950",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@350947@macro@ADC_DCCTL3_CTM_ONCE",
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+    "display": "ADC_DCCTL3_CTM_ONCE",
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+      "line": "5951",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CTM_ONCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351000@macro@ADC_DCCTL3_CTM_HALWAYS",
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+    "display": "ADC_DCCTL3_CTM_HALWAYS",
+    "location": {
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+      "line": "5952",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CTM_HALWAYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351066@macro@ADC_DCCTL3_CTM_HONCE",
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+    "display": "ADC_DCCTL3_CTM_HONCE",
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+      "line": "5953",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "ADC_DCCTL3_CIE",
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+      "line": "5954",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351206@macro@ADC_DCCTL3_CIC_M",
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+    "display": "ADC_DCCTL3_CIC_M",
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+      "line": "5955",
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+    },
+    "name": "ADC_DCCTL3_CIC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351285@macro@ADC_DCCTL3_CIC_LOW",
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+    "display": "ADC_DCCTL3_CIC_LOW",
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+      "line": "5956",
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+    },
+    "name": "ADC_DCCTL3_CIC_LOW",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351342@macro@ADC_DCCTL3_CIC_MID",
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+      "line": "5957",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351399@macro@ADC_DCCTL3_CIC_HIGH",
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+    "display": "ADC_DCCTL3_CIC_HIGH",
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+      "line": "5958",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_DCCTL3_CIC_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@351457@macro@ADC_DCCTL3_CIM_M",
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+    },
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+    "ID": "c:tm4c123gh6pm.h@352285@macro@ADC_DCCTL4_CTC_HIGH",
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@353751@macro@ADC_DCCTL5_CTC_MID",
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+    },
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+    },
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+    },
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+    },
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+    "ID": "c:tm4c123gh6pm.h@354331@macro@ADC_DCCTL5_CIC_LOW",
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+    "ID": "c:tm4c123gh6pm.h@355140@macro@ADC_DCCTL6_CTC_M",
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+    },
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+    "ID": "c:tm4c123gh6pm.h@355217@macro@ADC_DCCTL6_CTC_LOW",
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+    },
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+    "ID": "c:tm4c123gh6pm.h@355274@macro@ADC_DCCTL6_CTC_MID",
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+    "display": "ADC_DCCTL6_CTC_MID",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@355331@macro@ADC_DCCTL6_CTC_HIGH",
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+    "defdec": "Def",
+    "display": "ADC_DCCTL6_CTC_HIGH",
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+      "line": "6026",
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+    },
+    "name": "ADC_DCCTL6_CTC_HIGH",
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+  },
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@355461@macro@ADC_DCCTL6_CTM_ALWAYS",
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+    "display": "ADC_DCCTL6_CTM_ALWAYS",
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+      "line": "6028",
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+    },
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@355516@macro@ADC_DCCTL6_CTM_ONCE",
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+    "display": "ADC_DCCTL6_CTM_ONCE",
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+    },
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@355635@macro@ADC_DCCTL6_CTM_HONCE",
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+    },
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+    },
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+    "display": "ADC_DCCTL6_CIC_LOW",
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    "scope": null
+  },
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+      "line": "6056",
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+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357158@macro@ADC_DCCTL7_CTM_HONCE",
+    "What": "MacroDef",
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+    "display": "ADC_DCCTL7_CTM_HONCE",
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+      "line": "6057",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "display": "ADC_DCCTL7_CIE",
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+      "line": "6058",
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+    },
+    "name": "ADC_DCCTL7_CIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357298@macro@ADC_DCCTL7_CIC_M",
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+    "display": "ADC_DCCTL7_CIC_M",
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+      "line": "6059",
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+    },
+    "name": "ADC_DCCTL7_CIC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357377@macro@ADC_DCCTL7_CIC_LOW",
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+    },
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357434@macro@ADC_DCCTL7_CIC_MID",
+    "What": "MacroDef",
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+    },
+    "name": "ADC_DCCTL7_CIC_MID",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357491@macro@ADC_DCCTL7_CIC_HIGH",
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+      "line": "6062",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@357549@macro@ADC_DCCTL7_CIM_M",
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+      "line": "6157",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_TYPE_SAR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@361855@macro@ADC_PP_DC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_DC_M",
+    "location": {
+      "column": "9",
+      "line": "6158",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_DC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@361928@macro@ADC_PP_CH_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_CH_M",
+    "location": {
+      "column": "9",
+      "line": "6159",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_CH_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@361994@macro@ADC_PP_MSR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_MSR_M",
+    "location": {
+      "column": "9",
+      "line": "6160",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_MSR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362066@macro@ADC_PP_MSR_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_MSR_125K",
+    "location": {
+      "column": "9",
+      "line": "6161",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_MSR_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362123@macro@ADC_PP_MSR_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_MSR_250K",
+    "location": {
+      "column": "9",
+      "line": "6162",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_MSR_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362180@macro@ADC_PP_MSR_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_MSR_500K",
+    "location": {
+      "column": "9",
+      "line": "6163",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_MSR_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362237@macro@ADC_PP_MSR_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_MSR_1M",
+    "location": {
+      "column": "9",
+      "line": "6164",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_MSR_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362292@macro@ADC_PP_RSL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_RSL_S",
+    "location": {
+      "column": "9",
+      "line": "6165",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_RSL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362328@macro@ADC_PP_DC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_DC_S",
+    "location": {
+      "column": "9",
+      "line": "6166",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_DC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362364@macro@ADC_PP_CH_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PP_CH_S",
+    "location": {
+      "column": "9",
+      "line": "6167",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PP_CH_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362646@macro@ADC_PC_SR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PC_SR_M",
+    "location": {
+      "column": "9",
+      "line": "6174",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PC_SR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362710@macro@ADC_PC_SR_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PC_SR_125K",
+    "location": {
+      "column": "9",
+      "line": "6175",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PC_SR_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362767@macro@ADC_PC_SR_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PC_SR_250K",
+    "location": {
+      "column": "9",
+      "line": "6176",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PC_SR_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362824@macro@ADC_PC_SR_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PC_SR_500K",
+    "location": {
+      "column": "9",
+      "line": "6177",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PC_SR_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@362881@macro@ADC_PC_SR_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_PC_SR_1M",
+    "location": {
+      "column": "9",
+      "line": "6178",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_PC_SR_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@363183@macro@ADC_CC_CS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_CC_CS_M",
+    "location": {
+      "column": "9",
+      "line": "6185",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_CC_CS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@363248@macro@ADC_CC_CS_SYSPLL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_CC_CS_SYSPLL",
+    "location": {
+      "column": "9",
+      "line": "6186",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_CC_CS_SYSPLL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@363322@macro@ADC_CC_CS_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ADC_CC_CS_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "6187",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "ADC_CC_CS_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@363627@macro@COMP_ACMIS_IN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACMIS_IN1",
+    "location": {
+      "column": "9",
+      "line": "6194",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACMIS_IN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@363760@macro@COMP_ACMIS_IN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACMIS_IN0",
+    "location": {
+      "column": "9",
+      "line": "6196",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACMIS_IN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@364144@macro@COMP_ACRIS_IN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACRIS_IN1",
+    "location": {
+      "column": "9",
+      "line": "6204",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACRIS_IN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@364222@macro@COMP_ACRIS_IN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACRIS_IN0",
+    "location": {
+      "column": "9",
+      "line": "6205",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACRIS_IN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@364553@macro@COMP_ACINTEN_IN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACINTEN_IN1",
+    "location": {
+      "column": "9",
+      "line": "6212",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACINTEN_IN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@364631@macro@COMP_ACINTEN_IN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACINTEN_IN0",
+    "location": {
+      "column": "9",
+      "line": "6213",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACINTEN_IN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@364967@macro@COMP_ACREFCTL_EN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACREFCTL_EN",
+    "location": {
+      "column": "9",
+      "line": "6221",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACREFCTL_EN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365038@macro@COMP_ACREFCTL_RNG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACREFCTL_RNG",
+    "location": {
+      "column": "9",
+      "line": "6222",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACREFCTL_RNG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365108@macro@COMP_ACREFCTL_VREF_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACREFCTL_VREF_M",
+    "location": {
+      "column": "9",
+      "line": "6223",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACREFCTL_VREF_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365184@macro@COMP_ACREFCTL_VREF_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACREFCTL_VREF_S",
+    "location": {
+      "column": "9",
+      "line": "6224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACREFCTL_VREF_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365472@macro@COMP_ACSTAT0_OVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACSTAT0_OVAL",
+    "location": {
+      "column": "9",
+      "line": "6231",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACSTAT0_OVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365796@macro@COMP_ACCTL0_TOEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TOEN",
+    "location": {
+      "column": "9",
+      "line": "6238",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TOEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365866@macro@COMP_ACCTL0_ASRCP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ASRCP_M",
+    "location": {
+      "column": "9",
+      "line": "6239",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ASRCP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@365937@macro@COMP_ACCTL0_ASRCP_PIN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ASRCP_PIN",
+    "location": {
+      "column": "9",
+      "line": "6240",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ASRCP_PIN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366002@macro@COMP_ACCTL0_ASRCP_PIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ASRCP_PIN0",
+    "location": {
+      "column": "9",
+      "line": "6241",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ASRCP_PIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366067@macro@COMP_ACCTL0_ASRCP_REF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ASRCP_REF",
+    "location": {
+      "column": "9",
+      "line": "6242",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ASRCP_REF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366142@macro@COMP_ACCTL0_TSLVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSLVAL",
+    "location": {
+      "column": "9",
+      "line": "6243",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSLVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366216@macro@COMP_ACCTL0_TSEN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSEN_M",
+    "location": {
+      "column": "9",
+      "line": "6244",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366278@macro@COMP_ACCTL0_TSEN_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSEN_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "6245",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSEN_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366350@macro@COMP_ACCTL0_TSEN_FALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSEN_FALL",
+    "location": {
+      "column": "9",
+      "line": "6246",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSEN_FALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366411@macro@COMP_ACCTL0_TSEN_RISE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSEN_RISE",
+    "location": {
+      "column": "9",
+      "line": "6247",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSEN_RISE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366471@macro@COMP_ACCTL0_TSEN_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_TSEN_BOTH",
+    "location": {
+      "column": "9",
+      "line": "6248",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_TSEN_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366531@macro@COMP_ACCTL0_ISLVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISLVAL",
+    "location": {
+      "column": "9",
+      "line": "6249",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISLVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366607@macro@COMP_ACCTL0_ISEN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISEN_M",
+    "location": {
+      "column": "9",
+      "line": "6250",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366671@macro@COMP_ACCTL0_ISEN_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISEN_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "6251",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISEN_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366743@macro@COMP_ACCTL0_ISEN_FALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISEN_FALL",
+    "location": {
+      "column": "9",
+      "line": "6252",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISEN_FALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366804@macro@COMP_ACCTL0_ISEN_RISE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISEN_RISE",
+    "location": {
+      "column": "9",
+      "line": "6253",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISEN_RISE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366864@macro@COMP_ACCTL0_ISEN_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_ISEN_BOTH",
+    "location": {
+      "column": "9",
+      "line": "6254",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_ISEN_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@366924@macro@COMP_ACCTL0_CINV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL0_CINV",
+    "location": {
+      "column": "9",
+      "line": "6255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL0_CINV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367250@macro@COMP_ACSTAT1_OVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACSTAT1_OVAL",
+    "location": {
+      "column": "9",
+      "line": "6262",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACSTAT1_OVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367574@macro@COMP_ACCTL1_TOEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TOEN",
+    "location": {
+      "column": "9",
+      "line": "6269",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TOEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367644@macro@COMP_ACCTL1_ASRCP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ASRCP_M",
+    "location": {
+      "column": "9",
+      "line": "6270",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ASRCP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367715@macro@COMP_ACCTL1_ASRCP_PIN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ASRCP_PIN",
+    "location": {
+      "column": "9",
+      "line": "6271",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ASRCP_PIN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367780@macro@COMP_ACCTL1_ASRCP_PIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ASRCP_PIN0",
+    "location": {
+      "column": "9",
+      "line": "6272",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ASRCP_PIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367845@macro@COMP_ACCTL1_ASRCP_REF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ASRCP_REF",
+    "location": {
+      "column": "9",
+      "line": "6273",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ASRCP_REF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367920@macro@COMP_ACCTL1_TSLVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSLVAL",
+    "location": {
+      "column": "9",
+      "line": "6274",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSLVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@367994@macro@COMP_ACCTL1_TSEN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSEN_M",
+    "location": {
+      "column": "9",
+      "line": "6275",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368056@macro@COMP_ACCTL1_TSEN_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSEN_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "6276",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSEN_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368128@macro@COMP_ACCTL1_TSEN_FALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSEN_FALL",
+    "location": {
+      "column": "9",
+      "line": "6277",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSEN_FALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368189@macro@COMP_ACCTL1_TSEN_RISE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSEN_RISE",
+    "location": {
+      "column": "9",
+      "line": "6278",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSEN_RISE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368249@macro@COMP_ACCTL1_TSEN_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_TSEN_BOTH",
+    "location": {
+      "column": "9",
+      "line": "6279",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_TSEN_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368309@macro@COMP_ACCTL1_ISLVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISLVAL",
+    "location": {
+      "column": "9",
+      "line": "6280",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISLVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368385@macro@COMP_ACCTL1_ISEN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISEN_M",
+    "location": {
+      "column": "9",
+      "line": "6281",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368449@macro@COMP_ACCTL1_ISEN_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISEN_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "6282",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISEN_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368521@macro@COMP_ACCTL1_ISEN_FALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISEN_FALL",
+    "location": {
+      "column": "9",
+      "line": "6283",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISEN_FALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368582@macro@COMP_ACCTL1_ISEN_RISE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISEN_RISE",
+    "location": {
+      "column": "9",
+      "line": "6284",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISEN_RISE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368642@macro@COMP_ACCTL1_ISEN_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_ISEN_BOTH",
+    "location": {
+      "column": "9",
+      "line": "6285",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_ISEN_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@368702@macro@COMP_ACCTL1_CINV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_ACCTL1_CINV",
+    "location": {
+      "column": "9",
+      "line": "6286",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_ACCTL1_CINV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369023@macro@COMP_PP_C1O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_PP_C1O",
+    "location": {
+      "column": "9",
+      "line": "6293",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_PP_C1O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369099@macro@COMP_PP_C0O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_PP_C0O",
+    "location": {
+      "column": "9",
+      "line": "6294",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_PP_C0O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369175@macro@COMP_PP_CMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_PP_CMP1",
+    "location": {
+      "column": "9",
+      "line": "6295",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_PP_CMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369244@macro@COMP_PP_CMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "COMP_PP_CMP0",
+    "location": {
+      "column": "9",
+      "line": "6296",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "COMP_PP_CMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369561@macro@CAN_CTL_TEST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_TEST",
+    "location": {
+      "column": "9",
+      "line": "6303",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_TEST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369626@macro@CAN_CTL_CCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_CCE",
+    "location": {
+      "column": "9",
+      "line": "6304",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_CCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369702@macro@CAN_CTL_DAR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_DAR",
+    "location": {
+      "column": "9",
+      "line": "6305",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_DAR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369783@macro@CAN_CTL_EIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_EIE",
+    "location": {
+      "column": "9",
+      "line": "6306",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_EIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369854@macro@CAN_CTL_SIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_SIE",
+    "location": {
+      "column": "9",
+      "line": "6307",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_SIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369926@macro@CAN_CTL_IE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_IE",
+    "location": {
+      "column": "9",
+      "line": "6308",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_IE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@369995@macro@CAN_CTL_INIT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_CTL_INIT",
+    "location": {
+      "column": "9",
+      "line": "6309",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_CTL_INIT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370306@macro@CAN_STS_BOFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_BOFF",
+    "location": {
+      "column": "9",
+      "line": "6316",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_BOFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370369@macro@CAN_STS_EWARN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_EWARN",
+    "location": {
+      "column": "9",
+      "line": "6317",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_EWARN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370432@macro@CAN_STS_EPASS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_EPASS",
+    "location": {
+      "column": "9",
+      "line": "6318",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_EPASS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370494@macro@CAN_STS_RXOK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_RXOK",
+    "location": {
+      "column": "9",
+      "line": "6319",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_RXOK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370574@macro@CAN_STS_TXOK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_TXOK",
+    "location": {
+      "column": "9",
+      "line": "6320",
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+    },
+    "name": "CAN_STS_TXOK",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370705@macro@CAN_STS_LEC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_M",
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+    },
+    "name": "CAN_STS_LEC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370769@macro@CAN_STS_LEC_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_NONE",
+    "location": {
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+      "line": "6323",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370826@macro@CAN_STS_LEC_STUFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_STUFF",
+    "location": {
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+      "line": "6324",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_STUFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370886@macro@CAN_STS_LEC_FORM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_FORM",
+    "location": {
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+      "line": "6325",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_FORM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@370947@macro@CAN_STS_LEC_ACK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_ACK",
+    "location": {
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+      "line": "6326",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_ACK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371005@macro@CAN_STS_LEC_BIT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_BIT1",
+    "location": {
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+      "line": "6327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_BIT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371065@macro@CAN_STS_LEC_BIT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_BIT0",
+    "location": {
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+      "line": "6328",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_BIT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371125@macro@CAN_STS_LEC_CRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_CRC",
+    "location": {
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+      "line": "6329",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_CRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371183@macro@CAN_STS_LEC_NOEVENT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_STS_LEC_NOEVENT",
+    "location": {
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+      "line": "6330",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_STS_LEC_NOEVENT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371488@macro@CAN_ERR_RP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_ERR_RP",
+    "location": {
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+      "line": "6337",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_ERR_RP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371559@macro@CAN_ERR_REC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_ERR_REC_M",
+    "location": {
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+      "line": "6338",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_ERR_REC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371629@macro@CAN_ERR_TEC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_ERR_TEC_M",
+    "location": {
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+      "line": "6339",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_ERR_TEC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371700@macro@CAN_ERR_REC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_ERR_REC_S",
+    "location": {
+      "column": "9",
+      "line": "6340",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_ERR_REC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@371735@macro@CAN_ERR_TEC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_ERR_TEC_S",
+    "location": {
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+      "line": "6341",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_ERR_TEC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372018@macro@CAN_BIT_TSEG2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_TSEG2_M",
+    "location": {
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+      "line": "6348",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_TSEG2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372098@macro@CAN_BIT_TSEG1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_TSEG1_M",
+    "location": {
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+      "line": "6349",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_TSEG1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372179@macro@CAN_BIT_SJW_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_SJW_M",
+    "location": {
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+      "line": "6350",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_SJW_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372258@macro@CAN_BIT_BRP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_BRP_M",
+    "location": {
+      "column": "9",
+      "line": "6351",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_BRP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372326@macro@CAN_BIT_TSEG2_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_TSEG2_S",
+    "location": {
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+      "line": "6352",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_TSEG2_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372362@macro@CAN_BIT_TSEG1_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_TSEG1_S",
+    "location": {
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+      "line": "6353",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_TSEG1_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372397@macro@CAN_BIT_SJW_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_SJW_S",
+    "location": {
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+      "line": "6354",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_SJW_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372432@macro@CAN_BIT_BRP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BIT_BRP_S",
+    "location": {
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+      "line": "6355",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BIT_BRP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_INT_INTID_M",
+    "location": {
+      "column": "9",
+      "line": "6362",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_INT_INTID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372784@macro@CAN_INT_INTID_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_INT_INTID_NONE",
+    "location": {
+      "column": "9",
+      "line": "6363",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_INT_INTID_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@372853@macro@CAN_INT_INTID_STATUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_INT_INTID_STATUS",
+    "location": {
+      "column": "9",
+      "line": "6364",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_INT_INTID_STATUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373166@macro@CAN_TST_RX",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_RX",
+    "location": {
+      "column": "9",
+      "line": "6371",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_RX",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373234@macro@CAN_TST_TX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_TX_M",
+    "location": {
+      "column": "9",
+      "line": "6372",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_TX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373299@macro@CAN_TST_TX_CANCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_TX_CANCTL",
+    "location": {
+      "column": "9",
+      "line": "6373",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_TX_CANCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373366@macro@CAN_TST_TX_SAMPLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_TX_SAMPLE",
+    "location": {
+      "column": "9",
+      "line": "6374",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_TX_SAMPLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373427@macro@CAN_TST_TX_DOMINANT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_TX_DOMINANT",
+    "location": {
+      "column": "9",
+      "line": "6375",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_TX_DOMINANT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373486@macro@CAN_TST_TX_RECESSIVE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_TX_RECESSIVE",
+    "location": {
+      "column": "9",
+      "line": "6376",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_TX_RECESSIVE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373546@macro@CAN_TST_LBACK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_LBACK",
+    "location": {
+      "column": "9",
+      "line": "6377",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_LBACK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373608@macro@CAN_TST_SILENT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_SILENT",
+    "location": {
+      "column": "9",
+      "line": "6378",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_SILENT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373668@macro@CAN_TST_BASIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_TST_BASIC",
+    "location": {
+      "column": "9",
+      "line": "6379",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_TST_BASIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@373976@macro@CAN_BRPE_BRPE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BRPE_BRPE_M",
+    "location": {
+      "column": "9",
+      "line": "6386",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BRPE_BRPE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374054@macro@CAN_BRPE_BRPE_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_BRPE_BRPE_S",
+    "location": {
+      "column": "9",
+      "line": "6387",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_BRPE_BRPE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374340@macro@CAN_IF1CRQ_BUSY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CRQ_BUSY",
+    "location": {
+      "column": "9",
+      "line": "6394",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CRQ_BUSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374398@macro@CAN_IF1CRQ_MNUM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CRQ_MNUM_M",
+    "location": {
+      "column": "9",
+      "line": "6395",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CRQ_MNUM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374461@macro@CAN_IF1CRQ_MNUM_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CRQ_MNUM_S",
+    "location": {
+      "column": "9",
+      "line": "6396",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CRQ_MNUM_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374748@macro@CAN_IF1CMSK_WRNRD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_WRNRD",
+    "location": {
+      "column": "9",
+      "line": "6403",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_WRNRD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374812@macro@CAN_IF1CMSK_MASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_MASK",
+    "location": {
+      "column": "9",
+      "line": "6404",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_MASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374877@macro@CAN_IF1CMSK_ARB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_ARB",
+    "location": {
+      "column": "9",
+      "line": "6405",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_ARB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@374949@macro@CAN_IF1CMSK_CONTROL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_CONTROL",
+    "location": {
+      "column": "9",
+      "line": "6406",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_CONTROL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375017@macro@CAN_IF1CMSK_CLRINTPND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_CLRINTPND",
+    "location": {
+      "column": "9",
+      "line": "6407",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_CLRINTPND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375093@macro@CAN_IF1CMSK_NEWDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_NEWDAT",
+    "location": {
+      "column": "9",
+      "line": "6408",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_NEWDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375157@macro@CAN_IF1CMSK_TXRQST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_TXRQST",
+    "location": {
+      "column": "9",
+      "line": "6409",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_TXRQST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375233@macro@CAN_IF1CMSK_DATAA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_DATAA",
+    "location": {
+      "column": "9",
+      "line": "6410",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_DATAA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375305@macro@CAN_IF1CMSK_DATAB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1CMSK_DATAB",
+    "location": {
+      "column": "9",
+      "line": "6411",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1CMSK_DATAB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375629@macro@CAN_IF1MSK1_IDMSK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK1_IDMSK_M",
+    "location": {
+      "column": "9",
+      "line": "6418",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK1_IDMSK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375693@macro@CAN_IF1MSK1_IDMSK_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK1_IDMSK_S",
+    "location": {
+      "column": "9",
+      "line": "6419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK1_IDMSK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@375980@macro@CAN_IF1MSK2_MXTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK2_MXTD",
+    "location": {
+      "column": "9",
+      "line": "6426",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK2_MXTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376053@macro@CAN_IF1MSK2_MDIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK2_MDIR",
+    "location": {
+      "column": "9",
+      "line": "6427",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK2_MDIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376124@macro@CAN_IF1MSK2_IDMSK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK2_IDMSK_M",
+    "location": {
+      "column": "9",
+      "line": "6428",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK2_IDMSK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376188@macro@CAN_IF1MSK2_IDMSK_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MSK2_IDMSK_S",
+    "location": {
+      "column": "9",
+      "line": "6429",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MSK2_IDMSK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376475@macro@CAN_IF1ARB1_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB1_ID_M",
+    "location": {
+      "column": "9",
+      "line": "6436",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB1_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376542@macro@CAN_IF1ARB1_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB1_ID_S",
+    "location": {
+      "column": "9",
+      "line": "6437",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB1_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376829@macro@CAN_IF1ARB2_MSGVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB2_MSGVAL",
+    "location": {
+      "column": "9",
+      "line": "6444",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB2_MSGVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376891@macro@CAN_IF1ARB2_XTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB2_XTD",
+    "location": {
+      "column": "9",
+      "line": "6445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB2_XTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@376959@macro@CAN_IF1ARB2_DIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB2_DIR",
+    "location": {
+      "column": "9",
+      "line": "6446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB2_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377025@macro@CAN_IF1ARB2_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB2_ID_M",
+    "location": {
+      "column": "9",
+      "line": "6447",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB2_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377092@macro@CAN_IF1ARB2_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1ARB2_ID_S",
+    "location": {
+      "column": "9",
+      "line": "6448",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1ARB2_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377379@macro@CAN_IF1MCTL_NEWDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_NEWDAT",
+    "location": {
+      "column": "9",
+      "line": "6455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_NEWDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377436@macro@CAN_IF1MCTL_MSGLST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_MSGLST",
+    "location": {
+      "column": "9",
+      "line": "6456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_MSGLST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377497@macro@CAN_IF1MCTL_INTPND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_INTPND",
+    "location": {
+      "column": "9",
+      "line": "6457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_INTPND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377563@macro@CAN_IF1MCTL_UMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_UMASK",
+    "location": {
+      "column": "9",
+      "line": "6458",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_UMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377631@macro@CAN_IF1MCTL_TXIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_TXIE",
+    "location": {
+      "column": "9",
+      "line": "6459",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_TXIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377705@macro@CAN_IF1MCTL_RXIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_RXIE",
+    "location": {
+      "column": "9",
+      "line": "6460",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_RXIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377778@macro@CAN_IF1MCTL_RMTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_RMTEN",
+    "location": {
+      "column": "9",
+      "line": "6461",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_RMTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377840@macro@CAN_IF1MCTL_TXRQST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_TXRQST",
+    "location": {
+      "column": "9",
+      "line": "6462",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_TXRQST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377905@macro@CAN_IF1MCTL_EOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_EOB",
+    "location": {
+      "column": "9",
+      "line": "6463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_EOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@377967@macro@CAN_IF1MCTL_DLC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_DLC_M",
+    "location": {
+      "column": "9",
+      "line": "6464",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_DLC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378032@macro@CAN_IF1MCTL_DLC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1MCTL_DLC_S",
+    "location": {
+      "column": "9",
+      "line": "6465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1MCTL_DLC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378318@macro@CAN_IF1DA1_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DA1_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6472",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DA1_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378371@macro@CAN_IF1DA1_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DA1_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6473",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DA1_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378657@macro@CAN_IF1DA2_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DA2_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6480",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DA2_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378710@macro@CAN_IF1DA2_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DA2_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6481",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DA2_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@378996@macro@CAN_IF1DB1_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DB1_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6488",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DB1_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379049@macro@CAN_IF1DB1_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DB1_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DB1_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379335@macro@CAN_IF1DB2_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DB2_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6496",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DB2_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379388@macro@CAN_IF1DB2_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF1DB2_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6497",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF1DB2_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379674@macro@CAN_IF2CRQ_BUSY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CRQ_BUSY",
+    "location": {
+      "column": "9",
+      "line": "6504",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CRQ_BUSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379732@macro@CAN_IF2CRQ_MNUM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CRQ_MNUM_M",
+    "location": {
+      "column": "9",
+      "line": "6505",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CRQ_MNUM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@379795@macro@CAN_IF2CRQ_MNUM_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CRQ_MNUM_S",
+    "location": {
+      "column": "9",
+      "line": "6506",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CRQ_MNUM_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380082@macro@CAN_IF2CMSK_WRNRD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_WRNRD",
+    "location": {
+      "column": "9",
+      "line": "6513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_WRNRD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380146@macro@CAN_IF2CMSK_MASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_MASK",
+    "location": {
+      "column": "9",
+      "line": "6514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_MASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380211@macro@CAN_IF2CMSK_ARB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_ARB",
+    "location": {
+      "column": "9",
+      "line": "6515",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_ARB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380283@macro@CAN_IF2CMSK_CONTROL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_CONTROL",
+    "location": {
+      "column": "9",
+      "line": "6516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_CONTROL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380351@macro@CAN_IF2CMSK_CLRINTPND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_CLRINTPND",
+    "location": {
+      "column": "9",
+      "line": "6517",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_CLRINTPND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380427@macro@CAN_IF2CMSK_NEWDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_NEWDAT",
+    "location": {
+      "column": "9",
+      "line": "6518",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_NEWDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380491@macro@CAN_IF2CMSK_TXRQST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_TXRQST",
+    "location": {
+      "column": "9",
+      "line": "6519",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_TXRQST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380567@macro@CAN_IF2CMSK_DATAA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_DATAA",
+    "location": {
+      "column": "9",
+      "line": "6520",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_DATAA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380639@macro@CAN_IF2CMSK_DATAB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2CMSK_DATAB",
+    "location": {
+      "column": "9",
+      "line": "6521",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2CMSK_DATAB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@380963@macro@CAN_IF2MSK1_IDMSK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK1_IDMSK_M",
+    "location": {
+      "column": "9",
+      "line": "6528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK1_IDMSK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381027@macro@CAN_IF2MSK1_IDMSK_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK1_IDMSK_S",
+    "location": {
+      "column": "9",
+      "line": "6529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK1_IDMSK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381314@macro@CAN_IF2MSK2_MXTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK2_MXTD",
+    "location": {
+      "column": "9",
+      "line": "6536",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK2_MXTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381387@macro@CAN_IF2MSK2_MDIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK2_MDIR",
+    "location": {
+      "column": "9",
+      "line": "6537",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK2_MDIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381458@macro@CAN_IF2MSK2_IDMSK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK2_IDMSK_M",
+    "location": {
+      "column": "9",
+      "line": "6538",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK2_IDMSK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381522@macro@CAN_IF2MSK2_IDMSK_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MSK2_IDMSK_S",
+    "location": {
+      "column": "9",
+      "line": "6539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MSK2_IDMSK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381809@macro@CAN_IF2ARB1_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB1_ID_M",
+    "location": {
+      "column": "9",
+      "line": "6546",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB1_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@381876@macro@CAN_IF2ARB1_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB1_ID_S",
+    "location": {
+      "column": "9",
+      "line": "6547",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB1_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382163@macro@CAN_IF2ARB2_MSGVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB2_MSGVAL",
+    "location": {
+      "column": "9",
+      "line": "6554",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB2_MSGVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382225@macro@CAN_IF2ARB2_XTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB2_XTD",
+    "location": {
+      "column": "9",
+      "line": "6555",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB2_XTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382293@macro@CAN_IF2ARB2_DIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB2_DIR",
+    "location": {
+      "column": "9",
+      "line": "6556",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB2_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382359@macro@CAN_IF2ARB2_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB2_ID_M",
+    "location": {
+      "column": "9",
+      "line": "6557",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB2_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382426@macro@CAN_IF2ARB2_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2ARB2_ID_S",
+    "location": {
+      "column": "9",
+      "line": "6558",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2ARB2_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382713@macro@CAN_IF2MCTL_NEWDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_NEWDAT",
+    "location": {
+      "column": "9",
+      "line": "6565",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_NEWDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382770@macro@CAN_IF2MCTL_MSGLST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_MSGLST",
+    "location": {
+      "column": "9",
+      "line": "6566",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_MSGLST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382831@macro@CAN_IF2MCTL_INTPND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_INTPND",
+    "location": {
+      "column": "9",
+      "line": "6567",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_INTPND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382897@macro@CAN_IF2MCTL_UMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_UMASK",
+    "location": {
+      "column": "9",
+      "line": "6568",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_UMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@382965@macro@CAN_IF2MCTL_TXIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_TXIE",
+    "location": {
+      "column": "9",
+      "line": "6569",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_TXIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383039@macro@CAN_IF2MCTL_RXIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_RXIE",
+    "location": {
+      "column": "9",
+      "line": "6570",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_RXIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383112@macro@CAN_IF2MCTL_RMTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_RMTEN",
+    "location": {
+      "column": "9",
+      "line": "6571",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_RMTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383174@macro@CAN_IF2MCTL_TXRQST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_TXRQST",
+    "location": {
+      "column": "9",
+      "line": "6572",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_TXRQST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383239@macro@CAN_IF2MCTL_EOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_EOB",
+    "location": {
+      "column": "9",
+      "line": "6573",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_EOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383301@macro@CAN_IF2MCTL_DLC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_DLC_M",
+    "location": {
+      "column": "9",
+      "line": "6574",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_DLC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383366@macro@CAN_IF2MCTL_DLC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2MCTL_DLC_S",
+    "location": {
+      "column": "9",
+      "line": "6575",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2MCTL_DLC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383652@macro@CAN_IF2DA1_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2DA1_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6582",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2DA1_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383705@macro@CAN_IF2DA1_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2DA1_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6583",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2DA1_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@383991@macro@CAN_IF2DA2_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2DA2_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "6590",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2DA2_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@384044@macro@CAN_IF2DA2_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2DA2_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "6591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "CAN_IF2DA2_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@384330@macro@CAN_IF2DB1_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "CAN_IF2DB1_DATA_M",
+    "location": {
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+      "line": "6598",
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+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIS_EP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390098@macro@USB_RXIS_EP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIS_EP1",
+    "location": {
+      "column": "9",
+      "line": "6718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIS_EP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390419@macro@USB_TXIE_EP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP7",
+    "location": {
+      "column": "9",
+      "line": "6725",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390498@macro@USB_TXIE_EP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP6",
+    "location": {
+      "column": "9",
+      "line": "6726",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390577@macro@USB_TXIE_EP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP5",
+    "location": {
+      "column": "9",
+      "line": "6727",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390656@macro@USB_TXIE_EP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP4",
+    "location": {
+      "column": "9",
+      "line": "6728",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390735@macro@USB_TXIE_EP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP3",
+    "location": {
+      "column": "9",
+      "line": "6729",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390814@macro@USB_TXIE_EP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP2",
+    "location": {
+      "column": "9",
+      "line": "6730",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390893@macro@USB_TXIE_EP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP1",
+    "location": {
+      "column": "9",
+      "line": "6731",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@390972@macro@USB_TXIE_EP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXIE_EP0",
+    "location": {
+      "column": "9",
+      "line": "6732",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXIE_EP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391355@macro@USB_RXIE_EP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP7",
+    "location": {
+      "column": "9",
+      "line": "6740",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391434@macro@USB_RXIE_EP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP6",
+    "location": {
+      "column": "9",
+      "line": "6741",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391513@macro@USB_RXIE_EP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP5",
+    "location": {
+      "column": "9",
+      "line": "6742",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391592@macro@USB_RXIE_EP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP4",
+    "location": {
+      "column": "9",
+      "line": "6743",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391671@macro@USB_RXIE_EP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP3",
+    "location": {
+      "column": "9",
+      "line": "6744",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391750@macro@USB_RXIE_EP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP2",
+    "location": {
+      "column": "9",
+      "line": "6745",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@391829@macro@USB_RXIE_EP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXIE_EP1",
+    "location": {
+      "column": "9",
+      "line": "6746",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXIE_EP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392155@macro@USB_IS_VBUSERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_VBUSERR",
+    "location": {
+      "column": "9",
+      "line": "6753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_VBUSERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392225@macro@USB_IS_SESREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_SESREQ",
+    "location": {
+      "column": "9",
+      "line": "6754",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_SESREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392300@macro@USB_IS_DISCON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_DISCON",
+    "location": {
+      "column": "9",
+      "line": "6755",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_DISCON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392378@macro@USB_IS_CONN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_CONN",
+    "location": {
+      "column": "9",
+      "line": "6756",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_CONN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392442@macro@USB_IS_SOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_SOF",
+    "location": {
+      "column": "9",
+      "line": "6757",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_SOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392505@macro@USB_IS_BABBLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_BABBLE",
+    "location": {
+      "column": "9",
+      "line": "6758",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_BABBLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392569@macro@USB_IS_RESET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_RESET",
+    "location": {
+      "column": "9",
+      "line": "6759",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_RESET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392642@macro@USB_IS_RESUME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_RESUME",
+    "location": {
+      "column": "9",
+      "line": "6760",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_RESUME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@392716@macro@USB_IS_SUSPEND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IS_SUSPEND",
+    "location": {
+      "column": "9",
+      "line": "6761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IS_SUSPEND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393038@macro@USB_IE_VBUSERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_VBUSERR",
+    "location": {
+      "column": "9",
+      "line": "6768",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_VBUSERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393173@macro@USB_IE_SESREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_SESREQ",
+    "location": {
+      "column": "9",
+      "line": "6770",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_SESREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393303@macro@USB_IE_DISCON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_DISCON",
+    "location": {
+      "column": "9",
+      "line": "6772",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_DISCON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393379@macro@USB_IE_CONN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_CONN",
+    "location": {
+      "column": "9",
+      "line": "6773",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_CONN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393452@macro@USB_IE_SOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_SOF",
+    "location": {
+      "column": "9",
+      "line": "6774",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_SOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393532@macro@USB_IE_BABBLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_BABBLE",
+    "location": {
+      "column": "9",
+      "line": "6775",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_BABBLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393604@macro@USB_IE_RESET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_RESET",
+    "location": {
+      "column": "9",
+      "line": "6776",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_RESET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393675@macro@USB_IE_RESUME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_RESUME",
+    "location": {
+      "column": "9",
+      "line": "6777",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_RESUME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@393747@macro@USB_IE_SUSPND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IE_SUSPND",
+    "location": {
+      "column": "9",
+      "line": "6778",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IE_SUSPND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394070@macro@USB_FRAME_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FRAME_M",
+    "location": {
+      "column": "9",
+      "line": "6785",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FRAME_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394131@macro@USB_FRAME_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FRAME_S",
+    "location": {
+      "column": "9",
+      "line": "6786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FRAME_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394416@macro@USB_EPIDX_EPIDX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPIDX_EPIDX_M",
+    "location": {
+      "column": "9",
+      "line": "6793",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPIDX_EPIDX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394479@macro@USB_EPIDX_EPIDX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPIDX_EPIDX_S",
+    "location": {
+      "column": "9",
+      "line": "6794",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPIDX_EPIDX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394763@macro@USB_TEST_FORCEH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TEST_FORCEH",
+    "location": {
+      "column": "9",
+      "line": "6801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TEST_FORCEH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394827@macro@USB_TEST_FIFOACC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TEST_FIFOACC",
+    "location": {
+      "column": "9",
+      "line": "6802",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TEST_FIFOACC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@394887@macro@USB_TEST_FORCEFS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TEST_FORCEFS",
+    "location": {
+      "column": "9",
+      "line": "6803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TEST_FORCEFS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395207@macro@USB_FIFO0_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO0_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6810",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO0_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395269@macro@USB_FIFO0_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO0_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO0_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395554@macro@USB_FIFO1_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO1_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6818",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO1_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395616@macro@USB_FIFO1_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO1_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6819",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO1_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395901@macro@USB_FIFO2_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO2_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6826",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO2_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@395963@macro@USB_FIFO2_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO2_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6827",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO2_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@396248@macro@USB_FIFO3_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO3_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6834",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO3_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@396310@macro@USB_FIFO3_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO3_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6835",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO3_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@396595@macro@USB_FIFO4_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO4_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6842",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO4_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@396657@macro@USB_FIFO4_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO4_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6843",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO4_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@396942@macro@USB_FIFO5_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO5_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6850",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO5_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397004@macro@USB_FIFO5_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO5_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6851",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO5_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397289@macro@USB_FIFO6_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO6_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6858",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO6_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397351@macro@USB_FIFO6_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO6_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6859",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO6_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397636@macro@USB_FIFO7_EPDATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO7_EPDATA_M",
+    "location": {
+      "column": "9",
+      "line": "6866",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO7_EPDATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397698@macro@USB_FIFO7_EPDATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_FIFO7_EPDATA_S",
+    "location": {
+      "column": "9",
+      "line": "6867",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FIFO7_EPDATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@397984@macro@USB_DEVCTL_DEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_DEV",
+    "location": {
+      "column": "9",
+      "line": "6874",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_DEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398055@macro@USB_DEVCTL_FSDEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_FSDEV",
+    "location": {
+      "column": "9",
+      "line": "6875",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_FSDEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398130@macro@USB_DEVCTL_LSDEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_LSDEV",
+    "location": {
+      "column": "9",
+      "line": "6876",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_LSDEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398204@macro@USB_DEVCTL_VBUS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_VBUS_M",
+    "location": {
+      "column": "9",
+      "line": "6877",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_VBUS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398274@macro@USB_DEVCTL_VBUS_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_VBUS_NONE",
+    "location": {
+      "column": "9",
+      "line": "6878",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_VBUS_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398339@macro@USB_DEVCTL_VBUS_SEND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_VBUS_SEND",
+    "location": {
+      "column": "9",
+      "line": "6879",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_VBUS_SEND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398418@macro@USB_DEVCTL_VBUS_AVALID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_VBUS_AVALID",
+    "location": {
+      "column": "9",
+      "line": "6880",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_VBUS_AVALID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398496@macro@USB_DEVCTL_VBUS_VALID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_VBUS_VALID",
+    "location": {
+      "column": "9",
+      "line": "6881",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_VBUS_VALID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398560@macro@USB_DEVCTL_HOST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_HOST",
+    "location": {
+      "column": "9",
+      "line": "6882",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_HOST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398618@macro@USB_DEVCTL_HOSTREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_HOSTREQ",
+    "location": {
+      "column": "9",
+      "line": "6883",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_HOSTREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@398690@macro@USB_DEVCTL_SESSION",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DEVCTL_SESSION",
+    "location": {
+      "column": "9",
+      "line": "6884",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DEVCTL_SESSION",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399020@macro@USB_TXFIFOSZ_DPB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_DPB",
+    "location": {
+      "column": "9",
+      "line": "6891",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_DPB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399097@macro@USB_TXFIFOSZ_SIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_M",
+    "location": {
+      "column": "9",
+      "line": "6892",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399161@macro@USB_TXFIFOSZ_SIZE_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_8",
+    "location": {
+      "column": "9",
+      "line": "6893",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399211@macro@USB_TXFIFOSZ_SIZE_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_16",
+    "location": {
+      "column": "9",
+      "line": "6894",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399262@macro@USB_TXFIFOSZ_SIZE_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_32",
+    "location": {
+      "column": "9",
+      "line": "6895",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399313@macro@USB_TXFIFOSZ_SIZE_64",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_64",
+    "location": {
+      "column": "9",
+      "line": "6896",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399364@macro@USB_TXFIFOSZ_SIZE_128",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_128",
+    "location": {
+      "column": "9",
+      "line": "6897",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_128",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399416@macro@USB_TXFIFOSZ_SIZE_256",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_256",
+    "location": {
+      "column": "9",
+      "line": "6898",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_256",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399468@macro@USB_TXFIFOSZ_SIZE_512",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_512",
+    "location": {
+      "column": "9",
+      "line": "6899",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_512",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399520@macro@USB_TXFIFOSZ_SIZE_1024",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_1024",
+    "location": {
+      "column": "9",
+      "line": "6900",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_1024",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399573@macro@USB_TXFIFOSZ_SIZE_2048",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFIFOSZ_SIZE_2048",
+    "location": {
+      "column": "9",
+      "line": "6901",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOSZ_SIZE_2048",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399879@macro@USB_RXFIFOSZ_DPB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXFIFOSZ_DPB",
+    "location": {
+      "column": "9",
+      "line": "6908",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_DPB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@399956@macro@USB_RXFIFOSZ_SIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXFIFOSZ_SIZE_M",
+    "location": {
+      "column": "9",
+      "line": "6909",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400020@macro@USB_RXFIFOSZ_SIZE_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXFIFOSZ_SIZE_8",
+    "location": {
+      "column": "9",
+      "line": "6910",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_RXFIFOSZ_SIZE_16",
+    "location": {
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+      "line": "6911",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_16",
+    "origin": "user_include",
+    "scope": null
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+  {
+    "ID": "c:tm4c123gh6pm.h@400121@macro@USB_RXFIFOSZ_SIZE_32",
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+    "display": "USB_RXFIFOSZ_SIZE_32",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400172@macro@USB_RXFIFOSZ_SIZE_64",
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+    "display": "USB_RXFIFOSZ_SIZE_64",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400223@macro@USB_RXFIFOSZ_SIZE_128",
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+    "display": "USB_RXFIFOSZ_SIZE_128",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_128",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400275@macro@USB_RXFIFOSZ_SIZE_256",
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+    "display": "USB_RXFIFOSZ_SIZE_256",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_256",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400327@macro@USB_RXFIFOSZ_SIZE_512",
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+    "display": "USB_RXFIFOSZ_SIZE_512",
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+      "line": "6916",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_512",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400379@macro@USB_RXFIFOSZ_SIZE_1024",
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+    "display": "USB_RXFIFOSZ_SIZE_1024",
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+      "line": "6917",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_1024",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400432@macro@USB_RXFIFOSZ_SIZE_2048",
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+    "display": "USB_RXFIFOSZ_SIZE_2048",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOSZ_SIZE_2048",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_TXFIFOADD_ADDR_M",
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+      "line": "6926",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOADD_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@400822@macro@USB_TXFIFOADD_ADDR_S",
+    "What": "MacroDef",
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+    "display": "USB_TXFIFOADD_ADDR_S",
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+      "line": "6927",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFIFOADD_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401115@macro@USB_RXFIFOADD_ADDR_M",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOADD_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401194@macro@USB_RXFIFOADD_ADDR_S",
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+    "display": "USB_RXFIFOADD_ADDR_S",
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+      "line": "6936",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFIFOADD_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401480@macro@USB_CONTIM_WTCON_M",
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+    "display": "USB_CONTIM_WTCON_M",
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+    },
+    "name": "USB_CONTIM_WTCON_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401541@macro@USB_CONTIM_WTID_M",
+    "What": "MacroDef",
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+    "display": "USB_CONTIM_WTID_M",
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+      "line": "6944",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CONTIM_WTID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401597@macro@USB_CONTIM_WTCON_S",
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+    "defdec": "Def",
+    "display": "USB_CONTIM_WTCON_S",
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+    },
+    "name": "USB_CONTIM_WTCON_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401632@macro@USB_CONTIM_WTID_S",
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+    "display": "USB_CONTIM_WTID_S",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CONTIM_WTID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401917@macro@USB_VPLEN_VPLEN_M",
+    "What": "MacroDef",
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+    "display": "USB_VPLEN_VPLEN_M",
+    "location": {
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+      "line": "6953",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VPLEN_VPLEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@401983@macro@USB_VPLEN_VPLEN_S",
+    "What": "MacroDef",
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+    "display": "USB_VPLEN_VPLEN_S",
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+      "line": "6954",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VPLEN_VPLEN_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@402268@macro@USB_FSEOF_FSEOFG_M",
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+    "display": "USB_FSEOF_FSEOFG_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FSEOF_FSEOFG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@402344@macro@USB_FSEOF_FSEOFG_S",
+    "What": "MacroDef",
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+    "display": "USB_FSEOF_FSEOFG_S",
+    "location": {
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+      "line": "6962",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_FSEOF_FSEOFG_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@402629@macro@USB_LSEOF_LSEOFG_M",
+    "What": "MacroDef",
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+    "display": "USB_LSEOF_LSEOFG_M",
+    "location": {
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+      "line": "6969",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_LSEOF_LSEOFG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@402704@macro@USB_LSEOF_LSEOFG_S",
+    "What": "MacroDef",
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+    "display": "USB_LSEOF_LSEOFG_S",
+    "location": {
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+      "line": "6970",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_LSEOF_LSEOFG_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@402999@macro@USB_TXFUNCADDR0_ADDR_M",
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+    "display": "USB_TXFUNCADDR0_ADDR_M",
+    "location": {
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+      "line": "6978",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFUNCADDR0_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@403062@macro@USB_TXFUNCADDR0_ADDR_S",
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+    "display": "USB_TXFUNCADDR0_ADDR_S",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFUNCADDR0_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@403356@macro@USB_TXHUBADDR0_ADDR_M",
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+    "display": "USB_TXHUBADDR0_ADDR_M",
+    "location": {
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+      "line": "6987",
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+    },
+    "name": "USB_TXHUBADDR0_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_TXHUBADDR0_ADDR_S",
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+    },
+    "name": "USB_TXHUBADDR0_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_TXHUBPORT0_PORT_M",
+    "location": {
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+      "line": "6996",
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+    },
+    "name": "USB_TXHUBPORT0_PORT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_TXHUBPORT0_PORT_S",
+    "location": {
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+      "line": "6997",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404062@macro@USB_TXFUNCADDR1_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXFUNCADDR1_ADDR_M",
+    "location": {
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+      "line": "7005",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXFUNCADDR1_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404125@macro@USB_TXFUNCADDR1_ADDR_S",
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+    "display": "USB_TXFUNCADDR1_ADDR_S",
+    "location": {
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+    },
+    "name": "USB_TXFUNCADDR1_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404419@macro@USB_TXHUBADDR1_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXHUBADDR1_ADDR_M",
+    "location": {
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+    },
+    "name": "USB_TXHUBADDR1_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404479@macro@USB_TXHUBADDR1_ADDR_S",
+    "What": "MacroDef",
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+    "display": "USB_TXHUBADDR1_ADDR_S",
+    "location": {
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+    },
+    "name": "USB_TXHUBADDR1_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404773@macro@USB_TXHUBPORT1_PORT_M",
+    "What": "MacroDef",
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+    "display": "USB_TXHUBPORT1_PORT_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXHUBPORT1_PORT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@404830@macro@USB_TXHUBPORT1_PORT_S",
+    "What": "MacroDef",
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+    "display": "USB_TXHUBPORT1_PORT_S",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXHUBPORT1_PORT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405125@macro@USB_RXFUNCADDR1_ADDR_M",
+    "What": "MacroDef",
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+    "display": "USB_RXFUNCADDR1_ADDR_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXFUNCADDR1_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405188@macro@USB_RXFUNCADDR1_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXFUNCADDR1_ADDR_S",
+    "location": {
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+    },
+    "name": "USB_RXFUNCADDR1_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405482@macro@USB_RXHUBADDR1_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXHUBADDR1_ADDR_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXHUBADDR1_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405542@macro@USB_RXHUBADDR1_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXHUBADDR1_ADDR_S",
+    "location": {
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+    },
+    "name": "USB_RXHUBADDR1_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405836@macro@USB_RXHUBPORT1_PORT_M",
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+    "display": "USB_RXHUBPORT1_PORT_M",
+    "location": {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@405893@macro@USB_RXHUBPORT1_PORT_S",
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+    "display": "USB_RXHUBPORT1_PORT_S",
+    "location": {
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+    },
+    "name": "USB_RXHUBPORT1_PORT_S",
+    "origin": "user_include",
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+    "ID": "c:tm4c123gh6pm.h@419414@macro@USB_CSRL0_DATAEND",
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+    "defdec": "Def",
+    "display": "USB_CSRL0_DATAEND",
+    "location": {
+      "column": "9",
+      "line": "7390",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRL0_DATAEND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@419471@macro@USB_CSRL0_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRL0_SETUP",
+    "location": {
+      "column": "9",
+      "line": "7391",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRL0_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@419532@macro@USB_CSRL0_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRL0_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7392",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRL0_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@419597@macro@USB_CSRL0_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRL0_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "7393",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRL0_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@419667@macro@USB_CSRL0_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRL0_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "7394",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRL0_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@419986@macro@USB_CSRH0_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRH0_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRH0_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420059@macro@USB_CSRH0_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRH0_DT",
+    "location": {
+      "column": "9",
+      "line": "7402",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRH0_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420119@macro@USB_CSRH0_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_CSRH0_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7403",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_CSRH0_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420429@macro@USB_COUNT0_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_COUNT0_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "7410",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_COUNT0_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420488@macro@USB_COUNT0_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_COUNT0_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "7411",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_COUNT0_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420773@macro@USB_TYPE0_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TYPE0_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7418",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TYPE0_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420837@macro@USB_TYPE0_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TYPE0_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "7419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TYPE0_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@420890@macro@USB_TYPE0_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TYPE0_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7420",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TYPE0_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421193@macro@USB_NAKLMT_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_NAKLMT_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "7427",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_NAKLMT_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421255@macro@USB_NAKLMT_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_NAKLMT_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "7428",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_NAKLMT_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421542@macro@USB_TXMAXP1_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP1_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7435",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP1_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421606@macro@USB_TXMAXP1_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP1_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7436",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP1_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421893@macro@USB_TXCSRL1_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@421953@macro@USB_TXCSRL1_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7444",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422019@macro@USB_TXCSRL1_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422084@macro@USB_TXCSRL1_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_STALL",
+    "location": {
+      "column": "9",
+      "line": "7446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422143@macro@USB_TXCSRL1_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_SETUP",
+    "location": {
+      "column": "9",
+      "line": "7447",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422204@macro@USB_TXCSRL1_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7448",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422263@macro@USB_TXCSRL1_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7449",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422317@macro@USB_TXCSRL1_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "7450",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422374@macro@USB_TXCSRL1_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "7451",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422437@macro@USB_TXCSRL1_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL1_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "7452",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL1_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422759@macro@USB_TXCSRH1_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "7459",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422816@macro@USB_TXCSRH1_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_ISO",
+    "location": {
+      "column": "9",
+      "line": "7460",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422886@macro@USB_TXCSRH1_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_MODE",
+    "location": {
+      "column": "9",
+      "line": "7461",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@422939@macro@USB_TXCSRH1_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7462",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423006@macro@USB_TXCSRH1_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_FDT",
+    "location": {
+      "column": "9",
+      "line": "7463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423072@macro@USB_TXCSRH1_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7464",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423137@macro@USB_TXCSRH1_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423210@macro@USB_TXCSRH1_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH1_DT",
+    "location": {
+      "column": "9",
+      "line": "7466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH1_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423522@macro@USB_RXMAXP1_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP1_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7473",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP1_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423586@macro@USB_RXMAXP1_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP1_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7474",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP1_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423873@macro@USB_RXCSRL1_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7481",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@423939@macro@USB_RXCSRL1_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7482",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424004@macro@USB_RXCSRL1_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_STALL",
+    "location": {
+      "column": "9",
+      "line": "7483",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424063@macro@USB_RXCSRL1_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "7484",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424126@macro@USB_RXCSRL1_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7485",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424185@macro@USB_RXCSRL1_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "7486",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424244@macro@USB_RXCSRL1_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424304@macro@USB_RXCSRL1_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_OVER",
+    "location": {
+      "column": "9",
+      "line": "7488",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424360@macro@USB_RXCSRL1_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424414@macro@USB_RXCSRL1_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_FULL",
+    "location": {
+      "column": "9",
+      "line": "7490",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424472@macro@USB_RXCSRL1_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL1_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "7491",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL1_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424793@macro@USB_RXCSRH1_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "7498",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424852@macro@USB_RXCSRH1_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "7499",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424913@macro@USB_RXCSRH1_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_ISO",
+    "location": {
+      "column": "9",
+      "line": "7500",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@424983@macro@USB_RXCSRH1_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7501",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425050@macro@USB_RXCSRH1_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "7502",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425111@macro@USB_RXCSRH1_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "7503",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425169@macro@USB_RXCSRH1_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7504",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425234@macro@USB_RXCSRH1_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7505",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425307@macro@USB_RXCSRH1_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH1_DT",
+    "location": {
+      "column": "9",
+      "line": "7506",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH1_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425620@macro@USB_RXCOUNT1_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT1_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "7513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT1_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425689@macro@USB_RXCOUNT1_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT1_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "7514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT1_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@425976@macro@USB_TXTYPE1_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7521",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426040@macro@USB_TXTYPE1_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "7522",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426096@macro@USB_TXTYPE1_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "7523",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426149@macro@USB_TXTYPE1_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7524",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426201@macro@USB_TXTYPE1_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "7525",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426258@macro@USB_TXTYPE1_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7526",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426314@macro@USB_TXTYPE1_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "7527",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426374@macro@USB_TXTYPE1_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "7528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426427@macro@USB_TXTYPE1_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "7529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426485@macro@USB_TXTYPE1_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "7530",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426556@macro@USB_TXTYPE1_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE1_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "7531",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE1_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426851@macro@USB_TXINTERVAL1_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL1_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "7539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL1_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@426990@macro@USB_TXINTERVAL1_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL1_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "7541",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL1_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427130@macro@USB_TXINTERVAL1_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL1_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "7543",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL1_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427246@macro@USB_TXINTERVAL1_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL1_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "7545",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL1_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427614@macro@USB_RXTYPE1_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7553",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427678@macro@USB_RXTYPE1_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "7554",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427734@macro@USB_RXTYPE1_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "7555",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427787@macro@USB_RXTYPE1_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7556",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427839@macro@USB_RXTYPE1_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "7557",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427896@macro@USB_RXTYPE1_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7558",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@427952@macro@USB_RXTYPE1_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "7559",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428012@macro@USB_RXTYPE1_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "7560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428065@macro@USB_RXTYPE1_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "7561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428123@macro@USB_RXTYPE1_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "7562",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428194@macro@USB_RXTYPE1_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE1_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "7563",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE1_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428489@macro@USB_RXINTERVAL1_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL1_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "7571",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL1_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428629@macro@USB_RXINTERVAL1_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL1_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "7573",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL1_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428768@macro@USB_RXINTERVAL1_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL1_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "7575",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL1_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@428884@macro@USB_RXINTERVAL1_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL1_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "7577",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL1_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429252@macro@USB_TXMAXP2_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP2_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7585",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP2_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429316@macro@USB_TXMAXP2_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP2_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7586",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP2_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429603@macro@USB_TXCSRL2_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429663@macro@USB_TXCSRL2_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7594",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429729@macro@USB_TXCSRL2_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429794@macro@USB_TXCSRL2_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_SETUP",
+    "location": {
+      "column": "9",
+      "line": "7596",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429855@macro@USB_TXCSRL2_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_STALL",
+    "location": {
+      "column": "9",
+      "line": "7597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429914@macro@USB_TXCSRL2_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7598",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@429973@macro@USB_TXCSRL2_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430027@macro@USB_TXCSRL2_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "7600",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430084@macro@USB_TXCSRL2_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "7601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430147@macro@USB_TXCSRL2_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL2_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "7602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL2_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430469@macro@USB_TXCSRH2_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "7609",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430526@macro@USB_TXCSRH2_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_ISO",
+    "location": {
+      "column": "9",
+      "line": "7610",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430596@macro@USB_TXCSRH2_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_MODE",
+    "location": {
+      "column": "9",
+      "line": "7611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430649@macro@USB_TXCSRH2_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430716@macro@USB_TXCSRH2_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_FDT",
+    "location": {
+      "column": "9",
+      "line": "7613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430782@macro@USB_TXCSRH2_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7614",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430847@macro@USB_TXCSRH2_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@430920@macro@USB_TXCSRH2_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH2_DT",
+    "location": {
+      "column": "9",
+      "line": "7616",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH2_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431232@macro@USB_RXMAXP2_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP2_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7623",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP2_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431296@macro@USB_RXMAXP2_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP2_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP2_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431583@macro@USB_RXCSRL2_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7631",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431649@macro@USB_RXCSRL2_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7632",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431714@macro@USB_RXCSRL2_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "7633",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431777@macro@USB_RXCSRL2_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_STALL",
+    "location": {
+      "column": "9",
+      "line": "7634",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431836@macro@USB_RXCSRL2_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431895@macro@USB_RXCSRL2_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "7636",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@431954@macro@USB_RXCSRL2_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7637",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432014@macro@USB_RXCSRL2_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7638",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432068@macro@USB_RXCSRL2_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_OVER",
+    "location": {
+      "column": "9",
+      "line": "7639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432124@macro@USB_RXCSRL2_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_FULL",
+    "location": {
+      "column": "9",
+      "line": "7640",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432182@macro@USB_RXCSRL2_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL2_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "7641",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL2_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432503@macro@USB_RXCSRH2_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "7648",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432562@macro@USB_RXCSRH2_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "7649",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432623@macro@USB_RXCSRH2_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_ISO",
+    "location": {
+      "column": "9",
+      "line": "7650",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432693@macro@USB_RXCSRH2_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7651",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432760@macro@USB_RXCSRH2_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "7652",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432821@macro@USB_RXCSRH2_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "7653",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432879@macro@USB_RXCSRH2_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7654",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@432944@macro@USB_RXCSRH2_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7655",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433017@macro@USB_RXCSRH2_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH2_DT",
+    "location": {
+      "column": "9",
+      "line": "7656",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH2_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433330@macro@USB_RXCOUNT2_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT2_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "7663",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT2_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433399@macro@USB_RXCOUNT2_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT2_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "7664",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT2_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433686@macro@USB_TXTYPE2_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7671",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433750@macro@USB_TXTYPE2_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "7672",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433806@macro@USB_TXTYPE2_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "7673",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433859@macro@USB_TXTYPE2_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7674",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433911@macro@USB_TXTYPE2_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "7675",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@433968@macro@USB_TXTYPE2_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7676",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434024@macro@USB_TXTYPE2_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "7677",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434084@macro@USB_TXTYPE2_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "7678",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434137@macro@USB_TXTYPE2_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "7679",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434195@macro@USB_TXTYPE2_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "7680",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434266@macro@USB_TXTYPE2_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE2_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "7681",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE2_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434561@macro@USB_TXINTERVAL2_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL2_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "7689",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL2_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434701@macro@USB_TXINTERVAL2_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL2_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "7691",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL2_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434840@macro@USB_TXINTERVAL2_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL2_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "7693",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL2_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@434956@macro@USB_TXINTERVAL2_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL2_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "7695",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL2_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435324@macro@USB_RXTYPE2_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7703",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435388@macro@USB_RXTYPE2_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "7704",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435444@macro@USB_RXTYPE2_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "7705",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435497@macro@USB_RXTYPE2_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7706",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435549@macro@USB_RXTYPE2_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "7707",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435606@macro@USB_RXTYPE2_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7708",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435662@macro@USB_RXTYPE2_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "7709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435722@macro@USB_RXTYPE2_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "7710",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435775@macro@USB_RXTYPE2_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "7711",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435833@macro@USB_RXTYPE2_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "7712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@435904@macro@USB_RXTYPE2_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE2_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "7713",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE2_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@436199@macro@USB_RXINTERVAL2_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL2_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "7721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL2_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@436339@macro@USB_RXINTERVAL2_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL2_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "7723",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL2_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@436478@macro@USB_RXINTERVAL2_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL2_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "7725",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL2_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@436594@macro@USB_RXINTERVAL2_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL2_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "7727",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL2_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@436962@macro@USB_TXMAXP3_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP3_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7735",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP3_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437026@macro@USB_TXMAXP3_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP3_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP3_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437313@macro@USB_TXCSRL3_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7743",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437373@macro@USB_TXCSRL3_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7744",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437439@macro@USB_TXCSRL3_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7745",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437504@macro@USB_TXCSRL3_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_SETUP",
+    "location": {
+      "column": "9",
+      "line": "7746",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437565@macro@USB_TXCSRL3_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_STALL",
+    "location": {
+      "column": "9",
+      "line": "7747",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437624@macro@USB_TXCSRL3_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7748",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437683@macro@USB_TXCSRL3_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7749",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437737@macro@USB_TXCSRL3_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "7750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437794@macro@USB_TXCSRL3_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "7751",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@437857@macro@USB_TXCSRL3_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL3_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "7752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL3_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438179@macro@USB_TXCSRH3_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "7759",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438236@macro@USB_TXCSRH3_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_ISO",
+    "location": {
+      "column": "9",
+      "line": "7760",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438306@macro@USB_TXCSRH3_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_MODE",
+    "location": {
+      "column": "9",
+      "line": "7761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438359@macro@USB_TXCSRH3_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7762",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438426@macro@USB_TXCSRH3_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_FDT",
+    "location": {
+      "column": "9",
+      "line": "7763",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438492@macro@USB_TXCSRH3_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7764",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438557@macro@USB_TXCSRH3_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7765",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438630@macro@USB_TXCSRH3_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH3_DT",
+    "location": {
+      "column": "9",
+      "line": "7766",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH3_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@438942@macro@USB_RXMAXP3_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP3_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7773",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP3_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439006@macro@USB_RXMAXP3_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP3_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7774",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP3_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439293@macro@USB_RXCSRL3_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7781",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439359@macro@USB_RXCSRL3_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7782",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439424@macro@USB_RXCSRL3_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_STALL",
+    "location": {
+      "column": "9",
+      "line": "7783",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439483@macro@USB_RXCSRL3_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "7784",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439546@macro@USB_RXCSRL3_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7785",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439605@macro@USB_RXCSRL3_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "7786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439664@macro@USB_RXCSRL3_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7787",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439724@macro@USB_RXCSRL3_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7788",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439778@macro@USB_RXCSRL3_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_OVER",
+    "location": {
+      "column": "9",
+      "line": "7789",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439834@macro@USB_RXCSRL3_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_FULL",
+    "location": {
+      "column": "9",
+      "line": "7790",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@439892@macro@USB_RXCSRL3_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL3_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "7791",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL3_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440213@macro@USB_RXCSRH3_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "7798",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440272@macro@USB_RXCSRH3_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "7799",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440333@macro@USB_RXCSRH3_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_ISO",
+    "location": {
+      "column": "9",
+      "line": "7800",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440403@macro@USB_RXCSRH3_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440470@macro@USB_RXCSRH3_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "7802",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440531@macro@USB_RXCSRH3_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "7803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440589@macro@USB_RXCSRH3_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7804",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440654@macro@USB_RXCSRH3_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_DTWE",
+    "location": {
+      "column": "9",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@440727@macro@USB_RXCSRH3_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH3_DT",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH3_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441040@macro@USB_RXCOUNT3_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT3_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "7813",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT3_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441109@macro@USB_RXCOUNT3_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT3_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "7814",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT3_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@441396@macro@USB_TXTYPE3_SPEED_M",
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+    "defdec": "Def",
+    "display": "USB_TXTYPE3_SPEED_M",
+    "location": {
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+      "line": "7821",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441460@macro@USB_TXTYPE3_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_SPEED_DFLT",
+    "location": {
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+      "line": "7822",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441516@macro@USB_TXTYPE3_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_SPEED_FULL",
+    "location": {
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+      "line": "7823",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441569@macro@USB_TXTYPE3_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_SPEED_LOW",
+    "location": {
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+      "line": "7824",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441621@macro@USB_TXTYPE3_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "7825",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441678@macro@USB_TXTYPE3_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7826",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441734@macro@USB_TXTYPE3_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_PROTO_ISOC",
+    "location": {
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+      "line": "7827",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441794@macro@USB_TXTYPE3_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_PROTO_BULK",
+    "location": {
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+      "line": "7828",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441847@macro@USB_TXTYPE3_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "7829",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441905@macro@USB_TXTYPE3_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_TEP_M",
+    "location": {
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+      "line": "7830",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@441976@macro@USB_TXTYPE3_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE3_TEP_S",
+    "location": {
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+      "line": "7831",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE3_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@442271@macro@USB_TXINTERVAL3_TXPOLL_M",
+    "What": "MacroDef",
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+    "display": "USB_TXINTERVAL3_TXPOLL_M",
+    "location": {
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+      "line": "7839",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL3_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@442411@macro@USB_TXINTERVAL3_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL3_NAKLMT_M",
+    "location": {
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+      "line": "7841",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL3_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@442550@macro@USB_TXINTERVAL3_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL3_TXPOLL_S",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL3_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@442666@macro@USB_TXINTERVAL3_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL3_NAKLMT_S",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL3_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443034@macro@USB_RXTYPE3_SPEED_M",
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+    "defdec": "Def",
+    "display": "USB_RXTYPE3_SPEED_M",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443098@macro@USB_RXTYPE3_SPEED_DFLT",
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+    "display": "USB_RXTYPE3_SPEED_DFLT",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443154@macro@USB_RXTYPE3_SPEED_FULL",
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+    "display": "USB_RXTYPE3_SPEED_FULL",
+    "location": {
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+      "line": "7855",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443207@macro@USB_RXTYPE3_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_SPEED_LOW",
+    "location": {
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+      "line": "7856",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443259@macro@USB_RXTYPE3_PROTO_M",
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+    "defdec": "Def",
+    "display": "USB_RXTYPE3_PROTO_M",
+    "location": {
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+      "line": "7857",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443316@macro@USB_RXTYPE3_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_PROTO_CTRL",
+    "location": {
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+      "line": "7858",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443372@macro@USB_RXTYPE3_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_PROTO_ISOC",
+    "location": {
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+      "line": "7859",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443432@macro@USB_RXTYPE3_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_PROTO_BULK",
+    "location": {
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+      "line": "7860",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443485@macro@USB_RXTYPE3_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_PROTO_INT",
+    "location": {
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+      "line": "7861",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443543@macro@USB_RXTYPE3_TEP_M",
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+    "display": "USB_RXTYPE3_TEP_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@443614@macro@USB_RXTYPE3_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE3_TEP_S",
+    "location": {
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+      "line": "7863",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE3_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "USB_RXINTERVAL3_TXPOLL_M",
+    "location": {
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+      "line": "7871",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@444049@macro@USB_RXINTERVAL3_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL3_NAKLMT_M",
+    "location": {
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+      "line": "7873",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL3_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@444188@macro@USB_RXINTERVAL3_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL3_TXPOLL_S",
+    "location": {
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+      "line": "7875",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL3_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@444304@macro@USB_RXINTERVAL3_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL3_NAKLMT_S",
+    "location": {
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+      "line": "7877",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL3_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@444672@macro@USB_TXMAXP4_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP4_MAXLOAD_M",
+    "location": {
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+      "line": "7885",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP4_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@444736@macro@USB_TXMAXP4_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP4_MAXLOAD_S",
+    "location": {
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+      "line": "7886",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP4_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445023@macro@USB_TXCSRL4_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_NAKTO",
+    "location": {
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+      "line": "7893",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445083@macro@USB_TXCSRL4_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_CLRDT",
+    "location": {
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+      "line": "7894",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445149@macro@USB_TXCSRL4_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_STALLED",
+    "location": {
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+      "line": "7895",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445214@macro@USB_TXCSRL4_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_SETUP",
+    "location": {
+      "column": "9",
+      "line": "7896",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445275@macro@USB_TXCSRL4_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_STALL",
+    "location": {
+      "column": "9",
+      "line": "7897",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445334@macro@USB_TXCSRL4_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7898",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445393@macro@USB_TXCSRL4_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7899",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445447@macro@USB_TXCSRL4_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "7900",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445504@macro@USB_TXCSRL4_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "7901",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445567@macro@USB_TXCSRL4_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL4_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "7902",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL4_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445889@macro@USB_TXCSRH4_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "7909",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@445946@macro@USB_TXCSRH4_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_ISO",
+    "location": {
+      "column": "9",
+      "line": "7910",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446016@macro@USB_TXCSRH4_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_MODE",
+    "location": {
+      "column": "9",
+      "line": "7911",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446069@macro@USB_TXCSRH4_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7912",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446136@macro@USB_TXCSRH4_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_FDT",
+    "location": {
+      "column": "9",
+      "line": "7913",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446202@macro@USB_TXCSRH4_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7914",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446267@macro@USB_TXCSRH4_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7915",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446340@macro@USB_TXCSRH4_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH4_DT",
+    "location": {
+      "column": "9",
+      "line": "7916",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH4_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446652@macro@USB_RXMAXP4_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP4_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "7923",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP4_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@446716@macro@USB_RXMAXP4_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP4_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "7924",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP4_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447003@macro@USB_RXCSRL4_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "7931",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447069@macro@USB_RXCSRL4_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_STALLED",
+    "location": {
+      "column": "9",
+      "line": "7932",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447134@macro@USB_RXCSRL4_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_STALL",
+    "location": {
+      "column": "9",
+      "line": "7933",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447193@macro@USB_RXCSRL4_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "7934",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447256@macro@USB_RXCSRL4_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "7935",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447315@macro@USB_RXCSRL4_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "7936",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447375@macro@USB_RXCSRL4_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "7937",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447434@macro@USB_RXCSRL4_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_OVER",
+    "location": {
+      "column": "9",
+      "line": "7938",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447490@macro@USB_RXCSRL4_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_ERROR",
+    "location": {
+      "column": "9",
+      "line": "7939",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447544@macro@USB_RXCSRL4_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_FULL",
+    "location": {
+      "column": "9",
+      "line": "7940",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447602@macro@USB_RXCSRL4_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL4_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "7941",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL4_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447923@macro@USB_RXCSRH4_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "7948",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@447982@macro@USB_RXCSRH4_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "7949",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448043@macro@USB_RXCSRH4_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_ISO",
+    "location": {
+      "column": "9",
+      "line": "7950",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448113@macro@USB_RXCSRH4_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "7951",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448180@macro@USB_RXCSRH4_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "7952",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448241@macro@USB_RXCSRH4_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "7953",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448299@macro@USB_RXCSRH4_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "7954",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448364@macro@USB_RXCSRH4_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_DTWE",
+    "location": {
+      "column": "9",
+      "line": "7955",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448437@macro@USB_RXCSRH4_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH4_DT",
+    "location": {
+      "column": "9",
+      "line": "7956",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH4_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448750@macro@USB_RXCOUNT4_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT4_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "7963",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT4_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@448819@macro@USB_RXCOUNT4_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT4_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "7964",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT4_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449106@macro@USB_TXTYPE4_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "7971",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449170@macro@USB_TXTYPE4_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "7972",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449226@macro@USB_TXTYPE4_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_SPEED_FULL",
+    "location": {
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+      "line": "7973",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449279@macro@USB_TXTYPE4_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "7974",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449331@macro@USB_TXTYPE4_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_PROTO_M",
+    "location": {
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+      "line": "7975",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449388@macro@USB_TXTYPE4_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "7976",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449444@macro@USB_TXTYPE4_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_PROTO_ISOC",
+    "location": {
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+      "line": "7977",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449504@macro@USB_TXTYPE4_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_PROTO_BULK",
+    "location": {
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+      "line": "7978",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449557@macro@USB_TXTYPE4_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_PROTO_INT",
+    "location": {
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+      "line": "7979",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449615@macro@USB_TXTYPE4_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_TEP_M",
+    "location": {
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+      "line": "7980",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449686@macro@USB_TXTYPE4_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE4_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "7981",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE4_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@449981@macro@USB_TXINTERVAL4_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL4_TXPOLL_M",
+    "location": {
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+      "line": "7989",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL4_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450121@macro@USB_TXINTERVAL4_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL4_NAKLMT_M",
+    "location": {
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+      "line": "7991",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL4_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450260@macro@USB_TXINTERVAL4_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL4_NAKLMT_S",
+    "location": {
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+      "line": "7993",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL4_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450376@macro@USB_TXINTERVAL4_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL4_TXPOLL_S",
+    "location": {
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+      "line": "7995",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL4_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450744@macro@USB_RXTYPE4_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8003",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450808@macro@USB_RXTYPE4_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_SPEED_DFLT",
+    "location": {
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+      "line": "8004",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450864@macro@USB_RXTYPE4_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8005",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450917@macro@USB_RXTYPE4_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8006",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@450969@macro@USB_RXTYPE4_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8007",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451026@macro@USB_RXTYPE4_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8008",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451082@macro@USB_RXTYPE4_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_PROTO_ISOC",
+    "location": {
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+      "line": "8009",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451142@macro@USB_RXTYPE4_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_PROTO_BULK",
+    "location": {
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+      "line": "8010",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451195@macro@USB_RXTYPE4_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8011",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451253@macro@USB_RXTYPE4_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8012",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451324@macro@USB_RXTYPE4_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE4_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8013",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE4_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451619@macro@USB_RXINTERVAL4_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL4_TXPOLL_M",
+    "location": {
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+      "line": "8021",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL4_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451759@macro@USB_RXINTERVAL4_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL4_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8023",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL4_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@451898@macro@USB_RXINTERVAL4_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL4_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8025",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL4_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452014@macro@USB_RXINTERVAL4_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL4_TXPOLL_S",
+    "location": {
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+      "line": "8027",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL4_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452382@macro@USB_TXMAXP5_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP5_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8035",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP5_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452446@macro@USB_TXMAXP5_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP5_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8036",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP5_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452733@macro@USB_TXCSRL5_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8043",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452793@macro@USB_TXCSRL5_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8044",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452859@macro@USB_TXCSRL5_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8045",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452924@macro@USB_TXCSRL5_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_SETUP",
+    "location": {
+      "column": "9",
+      "line": "8046",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@452985@macro@USB_TXCSRL5_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_STALL",
+    "location": {
+      "column": "9",
+      "line": "8047",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453044@macro@USB_TXCSRL5_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8048",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453103@macro@USB_TXCSRL5_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8049",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453157@macro@USB_TXCSRL5_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "8050",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453214@macro@USB_TXCSRL5_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "8051",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453277@macro@USB_TXCSRL5_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL5_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "8052",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL5_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453599@macro@USB_TXCSRH5_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "8059",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453656@macro@USB_TXCSRH5_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_ISO",
+    "location": {
+      "column": "9",
+      "line": "8060",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453726@macro@USB_TXCSRH5_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_MODE",
+    "location": {
+      "column": "9",
+      "line": "8061",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453779@macro@USB_TXCSRH5_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8062",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453846@macro@USB_TXCSRH5_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_FDT",
+    "location": {
+      "column": "9",
+      "line": "8063",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453912@macro@USB_TXCSRH5_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8064",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@453977@macro@USB_TXCSRH5_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8065",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454050@macro@USB_TXCSRH5_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH5_DT",
+    "location": {
+      "column": "9",
+      "line": "8066",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH5_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454362@macro@USB_RXMAXP5_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP5_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8073",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP5_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454426@macro@USB_RXMAXP5_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP5_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8074",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP5_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454713@macro@USB_RXCSRL5_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8081",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454779@macro@USB_RXCSRL5_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8082",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454844@macro@USB_RXCSRL5_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_STALL",
+    "location": {
+      "column": "9",
+      "line": "8083",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454903@macro@USB_RXCSRL5_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "8084",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@454966@macro@USB_RXCSRL5_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8085",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455025@macro@USB_RXCSRL5_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8086",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455085@macro@USB_RXCSRL5_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "8087",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455144@macro@USB_RXCSRL5_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8088",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455198@macro@USB_RXCSRL5_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_OVER",
+    "location": {
+      "column": "9",
+      "line": "8089",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455254@macro@USB_RXCSRL5_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_FULL",
+    "location": {
+      "column": "9",
+      "line": "8090",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455312@macro@USB_RXCSRL5_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL5_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "8091",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL5_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455633@macro@USB_RXCSRH5_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "8098",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455692@macro@USB_RXCSRH5_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "8099",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455753@macro@USB_RXCSRH5_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_ISO",
+    "location": {
+      "column": "9",
+      "line": "8100",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455823@macro@USB_RXCSRH5_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8101",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455890@macro@USB_RXCSRH5_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "8102",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@455951@macro@USB_RXCSRH5_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "8103",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456009@macro@USB_RXCSRH5_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8104",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456074@macro@USB_RXCSRH5_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8105",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456147@macro@USB_RXCSRH5_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH5_DT",
+    "location": {
+      "column": "9",
+      "line": "8106",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH5_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456460@macro@USB_RXCOUNT5_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT5_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "8113",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT5_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456529@macro@USB_RXCOUNT5_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT5_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "8114",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT5_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456816@macro@USB_TXTYPE5_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8121",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456880@macro@USB_TXTYPE5_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8122",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456936@macro@USB_TXTYPE5_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8123",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@456989@macro@USB_TXTYPE5_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8124",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457041@macro@USB_TXTYPE5_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8125",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457098@macro@USB_TXTYPE5_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8126",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457154@macro@USB_TXTYPE5_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8127",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457214@macro@USB_TXTYPE5_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "8128",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457267@macro@USB_TXTYPE5_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8129",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457325@macro@USB_TXTYPE5_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8130",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457396@macro@USB_TXTYPE5_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE5_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8131",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE5_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457691@macro@USB_TXINTERVAL5_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL5_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "8139",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL5_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457831@macro@USB_TXINTERVAL5_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL5_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8141",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL5_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@457970@macro@USB_TXINTERVAL5_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL5_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8143",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL5_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458086@macro@USB_TXINTERVAL5_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL5_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "8145",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL5_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458454@macro@USB_RXTYPE5_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8153",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458518@macro@USB_RXTYPE5_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8154",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458574@macro@USB_RXTYPE5_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8155",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458627@macro@USB_RXTYPE5_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8156",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458679@macro@USB_RXTYPE5_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8157",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458736@macro@USB_RXTYPE5_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8158",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458792@macro@USB_RXTYPE5_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8159",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458852@macro@USB_RXTYPE5_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "8160",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458905@macro@USB_RXTYPE5_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8161",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@458963@macro@USB_RXTYPE5_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8162",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@459034@macro@USB_RXTYPE5_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE5_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8163",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE5_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@459329@macro@USB_RXINTERVAL5_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL5_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "8171",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL5_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@459469@macro@USB_RXINTERVAL5_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL5_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8173",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL5_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@459608@macro@USB_RXINTERVAL5_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL5_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "8175",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL5_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@459724@macro@USB_RXINTERVAL5_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL5_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8177",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL5_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460092@macro@USB_TXMAXP6_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP6_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8185",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP6_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460156@macro@USB_TXMAXP6_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP6_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8186",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP6_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460443@macro@USB_TXCSRL6_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8193",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460503@macro@USB_TXCSRL6_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8194",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460569@macro@USB_TXCSRL6_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8195",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460634@macro@USB_TXCSRL6_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_STALL",
+    "location": {
+      "column": "9",
+      "line": "8196",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460693@macro@USB_TXCSRL6_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_SETUP",
+    "location": {
+      "column": "9",
+      "line": "8197",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460754@macro@USB_TXCSRL6_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8198",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460813@macro@USB_TXCSRL6_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8199",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460867@macro@USB_TXCSRL6_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "8200",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460924@macro@USB_TXCSRL6_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "8201",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@460987@macro@USB_TXCSRL6_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL6_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "8202",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL6_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461309@macro@USB_TXCSRH6_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "8209",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461366@macro@USB_TXCSRH6_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_ISO",
+    "location": {
+      "column": "9",
+      "line": "8210",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461436@macro@USB_TXCSRH6_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_MODE",
+    "location": {
+      "column": "9",
+      "line": "8211",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461489@macro@USB_TXCSRH6_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8212",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461556@macro@USB_TXCSRH6_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_FDT",
+    "location": {
+      "column": "9",
+      "line": "8213",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461622@macro@USB_TXCSRH6_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8214",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461687@macro@USB_TXCSRH6_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8215",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@461760@macro@USB_TXCSRH6_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH6_DT",
+    "location": {
+      "column": "9",
+      "line": "8216",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH6_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462072@macro@USB_RXMAXP6_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP6_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8223",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP6_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462136@macro@USB_RXMAXP6_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP6_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP6_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462423@macro@USB_RXCSRL6_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8231",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462489@macro@USB_RXCSRL6_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8232",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462554@macro@USB_RXCSRL6_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "8233",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462617@macro@USB_RXCSRL6_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_STALL",
+    "location": {
+      "column": "9",
+      "line": "8234",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462676@macro@USB_RXCSRL6_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8235",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462735@macro@USB_RXCSRL6_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8236",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462795@macro@USB_RXCSRL6_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "8237",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462854@macro@USB_RXCSRL6_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8238",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462908@macro@USB_RXCSRL6_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_OVER",
+    "location": {
+      "column": "9",
+      "line": "8239",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@462964@macro@USB_RXCSRL6_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_FULL",
+    "location": {
+      "column": "9",
+      "line": "8240",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463022@macro@USB_RXCSRL6_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL6_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "8241",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL6_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463343@macro@USB_RXCSRH6_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "8248",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463402@macro@USB_RXCSRH6_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "8249",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463463@macro@USB_RXCSRH6_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_ISO",
+    "location": {
+      "column": "9",
+      "line": "8250",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463533@macro@USB_RXCSRH6_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8251",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463600@macro@USB_RXCSRH6_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "8252",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463661@macro@USB_RXCSRH6_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "8253",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463719@macro@USB_RXCSRH6_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8254",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463784@macro@USB_RXCSRH6_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@463857@macro@USB_RXCSRH6_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH6_DT",
+    "location": {
+      "column": "9",
+      "line": "8256",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH6_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464170@macro@USB_RXCOUNT6_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT6_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "8263",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT6_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464239@macro@USB_RXCOUNT6_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT6_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "8264",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT6_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464526@macro@USB_TXTYPE6_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8271",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464590@macro@USB_TXTYPE6_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8272",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464646@macro@USB_TXTYPE6_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8273",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464699@macro@USB_TXTYPE6_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8274",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464751@macro@USB_TXTYPE6_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8275",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464808@macro@USB_TXTYPE6_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8276",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464864@macro@USB_TXTYPE6_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8277",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464924@macro@USB_TXTYPE6_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "8278",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@464977@macro@USB_TXTYPE6_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8279",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465035@macro@USB_TXTYPE6_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8280",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465106@macro@USB_TXTYPE6_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE6_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8281",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE6_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465401@macro@USB_TXINTERVAL6_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL6_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "8289",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL6_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465541@macro@USB_TXINTERVAL6_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL6_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8291",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL6_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465680@macro@USB_TXINTERVAL6_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL6_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "8293",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL6_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@465796@macro@USB_TXINTERVAL6_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL6_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8295",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL6_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466164@macro@USB_RXTYPE6_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8303",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466228@macro@USB_RXTYPE6_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8304",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466284@macro@USB_RXTYPE6_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8305",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466337@macro@USB_RXTYPE6_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8306",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466389@macro@USB_RXTYPE6_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8307",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466446@macro@USB_RXTYPE6_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8308",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466502@macro@USB_RXTYPE6_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8309",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466562@macro@USB_RXTYPE6_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "8310",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466615@macro@USB_RXTYPE6_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8311",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466673@macro@USB_RXTYPE6_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8312",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@466744@macro@USB_RXTYPE6_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE6_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8313",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE6_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467039@macro@USB_RXINTERVAL6_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL6_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "8321",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL6_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467179@macro@USB_RXINTERVAL6_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL6_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8323",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL6_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467318@macro@USB_RXINTERVAL6_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL6_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8325",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL6_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467434@macro@USB_RXINTERVAL6_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL6_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "8327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL6_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467802@macro@USB_TXMAXP7_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP7_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8335",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP7_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@467866@macro@USB_TXMAXP7_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXMAXP7_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8336",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXMAXP7_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468153@macro@USB_TXCSRL7_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8343",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468213@macro@USB_TXCSRL7_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8344",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468279@macro@USB_TXCSRL7_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8345",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468344@macro@USB_TXCSRL7_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_STALL",
+    "location": {
+      "column": "9",
+      "line": "8346",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468403@macro@USB_TXCSRL7_SETUP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_SETUP",
+    "location": {
+      "column": "9",
+      "line": "8347",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_SETUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468464@macro@USB_TXCSRL7_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8348",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468523@macro@USB_TXCSRL7_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8349",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468577@macro@USB_TXCSRL7_UNDRN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_UNDRN",
+    "location": {
+      "column": "9",
+      "line": "8350",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_UNDRN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468634@macro@USB_TXCSRL7_FIFONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_FIFONE",
+    "location": {
+      "column": "9",
+      "line": "8351",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_FIFONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@468697@macro@USB_TXCSRL7_TXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRL7_TXRDY",
+    "location": {
+      "column": "9",
+      "line": "8352",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRL7_TXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469019@macro@USB_TXCSRH7_AUTOSET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_AUTOSET",
+    "location": {
+      "column": "9",
+      "line": "8359",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_AUTOSET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469076@macro@USB_TXCSRH7_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_ISO",
+    "location": {
+      "column": "9",
+      "line": "8360",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469146@macro@USB_TXCSRH7_MODE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_MODE",
+    "location": {
+      "column": "9",
+      "line": "8361",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_MODE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469199@macro@USB_TXCSRH7_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8362",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469266@macro@USB_TXCSRH7_FDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_FDT",
+    "location": {
+      "column": "9",
+      "line": "8363",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_FDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469332@macro@USB_TXCSRH7_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8364",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469397@macro@USB_TXCSRH7_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8365",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469470@macro@USB_TXCSRH7_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXCSRH7_DT",
+    "location": {
+      "column": "9",
+      "line": "8366",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXCSRH7_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469782@macro@USB_RXMAXP7_MAXLOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP7_MAXLOAD_M",
+    "location": {
+      "column": "9",
+      "line": "8373",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP7_MAXLOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@469846@macro@USB_RXMAXP7_MAXLOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXMAXP7_MAXLOAD_S",
+    "location": {
+      "column": "9",
+      "line": "8374",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXMAXP7_MAXLOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470133@macro@USB_RXCSRL7_CLRDT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_CLRDT",
+    "location": {
+      "column": "9",
+      "line": "8381",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_CLRDT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470199@macro@USB_RXCSRL7_STALLED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_STALLED",
+    "location": {
+      "column": "9",
+      "line": "8382",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_STALLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470264@macro@USB_RXCSRL7_REQPKT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_REQPKT",
+    "location": {
+      "column": "9",
+      "line": "8383",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_REQPKT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470327@macro@USB_RXCSRL7_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_STALL",
+    "location": {
+      "column": "9",
+      "line": "8384",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470386@macro@USB_RXCSRL7_FLUSH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_FLUSH",
+    "location": {
+      "column": "9",
+      "line": "8385",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_FLUSH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470445@macro@USB_RXCSRL7_DATAERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_DATAERR",
+    "location": {
+      "column": "9",
+      "line": "8386",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_DATAERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470504@macro@USB_RXCSRL7_NAKTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_NAKTO",
+    "location": {
+      "column": "9",
+      "line": "8387",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_NAKTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470564@macro@USB_RXCSRL7_ERROR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_ERROR",
+    "location": {
+      "column": "9",
+      "line": "8388",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_ERROR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470618@macro@USB_RXCSRL7_OVER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_OVER",
+    "location": {
+      "column": "9",
+      "line": "8389",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_OVER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470674@macro@USB_RXCSRL7_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_FULL",
+    "location": {
+      "column": "9",
+      "line": "8390",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@470732@macro@USB_RXCSRL7_RXRDY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRL7_RXRDY",
+    "location": {
+      "column": "9",
+      "line": "8391",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRL7_RXRDY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471053@macro@USB_RXCSRH7_AUTOCL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_AUTOCL",
+    "location": {
+      "column": "9",
+      "line": "8398",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_AUTOCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471112@macro@USB_RXCSRH7_ISO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_ISO",
+    "location": {
+      "column": "9",
+      "line": "8399",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_ISO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471182@macro@USB_RXCSRH7_AUTORQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_AUTORQ",
+    "location": {
+      "column": "9",
+      "line": "8400",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_AUTORQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471243@macro@USB_RXCSRH7_DMAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_DMAEN",
+    "location": {
+      "column": "9",
+      "line": "8401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_DMAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471310@macro@USB_RXCSRH7_PIDERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_PIDERR",
+    "location": {
+      "column": "9",
+      "line": "8402",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_PIDERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471368@macro@USB_RXCSRH7_DISNYET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_DISNYET",
+    "location": {
+      "column": "9",
+      "line": "8403",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_DISNYET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471429@macro@USB_RXCSRH7_DMAMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_DMAMOD",
+    "location": {
+      "column": "9",
+      "line": "8404",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_DMAMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471494@macro@USB_RXCSRH7_DTWE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_DTWE",
+    "location": {
+      "column": "9",
+      "line": "8405",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_DTWE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471567@macro@USB_RXCSRH7_DT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCSRH7_DT",
+    "location": {
+      "column": "9",
+      "line": "8406",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCSRH7_DT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471880@macro@USB_RXCOUNT7_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT7_COUNT_M",
+    "location": {
+      "column": "9",
+      "line": "8413",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT7_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@471949@macro@USB_RXCOUNT7_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXCOUNT7_COUNT_S",
+    "location": {
+      "column": "9",
+      "line": "8414",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXCOUNT7_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472236@macro@USB_TXTYPE7_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472300@macro@USB_TXTYPE7_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8422",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472356@macro@USB_TXTYPE7_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472409@macro@USB_TXTYPE7_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8424",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472461@macro@USB_TXTYPE7_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8425",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472518@macro@USB_TXTYPE7_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8426",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472574@macro@USB_TXTYPE7_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8427",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472634@macro@USB_TXTYPE7_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_PROTO_BULK",
+    "location": {
+      "column": "9",
+      "line": "8428",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472687@macro@USB_TXTYPE7_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_PROTO_INT",
+    "location": {
+      "column": "9",
+      "line": "8429",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472745@macro@USB_TXTYPE7_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_TEP_M",
+    "location": {
+      "column": "9",
+      "line": "8430",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@472816@macro@USB_TXTYPE7_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXTYPE7_TEP_S",
+    "location": {
+      "column": "9",
+      "line": "8431",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXTYPE7_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473111@macro@USB_TXINTERVAL7_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL7_TXPOLL_M",
+    "location": {
+      "column": "9",
+      "line": "8439",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL7_TXPOLL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473251@macro@USB_TXINTERVAL7_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL7_NAKLMT_M",
+    "location": {
+      "column": "9",
+      "line": "8441",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL7_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473390@macro@USB_TXINTERVAL7_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL7_NAKLMT_S",
+    "location": {
+      "column": "9",
+      "line": "8443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL7_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473506@macro@USB_TXINTERVAL7_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXINTERVAL7_TXPOLL_S",
+    "location": {
+      "column": "9",
+      "line": "8445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXINTERVAL7_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473874@macro@USB_RXTYPE7_SPEED_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_SPEED_M",
+    "location": {
+      "column": "9",
+      "line": "8453",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_SPEED_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473938@macro@USB_RXTYPE7_SPEED_DFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_SPEED_DFLT",
+    "location": {
+      "column": "9",
+      "line": "8454",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_SPEED_DFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@473994@macro@USB_RXTYPE7_SPEED_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_SPEED_FULL",
+    "location": {
+      "column": "9",
+      "line": "8455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_SPEED_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474047@macro@USB_RXTYPE7_SPEED_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_SPEED_LOW",
+    "location": {
+      "column": "9",
+      "line": "8456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_SPEED_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474099@macro@USB_RXTYPE7_PROTO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_PROTO_M",
+    "location": {
+      "column": "9",
+      "line": "8457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_PROTO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474156@macro@USB_RXTYPE7_PROTO_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_PROTO_CTRL",
+    "location": {
+      "column": "9",
+      "line": "8458",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_PROTO_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474212@macro@USB_RXTYPE7_PROTO_ISOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_PROTO_ISOC",
+    "location": {
+      "column": "9",
+      "line": "8459",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_PROTO_ISOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474272@macro@USB_RXTYPE7_PROTO_BULK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_PROTO_BULK",
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+      "line": "8460",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_PROTO_BULK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474325@macro@USB_RXTYPE7_PROTO_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_PROTO_INT",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_PROTO_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474383@macro@USB_RXTYPE7_TEP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_TEP_M",
+    "location": {
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+      "line": "8462",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_TEP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474454@macro@USB_RXTYPE7_TEP_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXTYPE7_TEP_S",
+    "location": {
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+      "line": "8463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXTYPE7_TEP_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474749@macro@USB_RXINTERVAL7_TXPOLL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL7_TXPOLL_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@474889@macro@USB_RXINTERVAL7_NAKLMT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL7_NAKLMT_M",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL7_NAKLMT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475028@macro@USB_RXINTERVAL7_NAKLMT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL7_NAKLMT_S",
+    "location": {
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+      "line": "8475",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL7_NAKLMT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475144@macro@USB_RXINTERVAL7_TXPOLL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXINTERVAL7_TXPOLL_S",
+    "location": {
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+      "line": "8477",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXINTERVAL7_TXPOLL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475520@macro@USB_RQPKTCOUNT1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT1_M",
+    "location": {
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+      "line": "8486",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475596@macro@USB_RQPKTCOUNT1_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT1_S",
+    "location": {
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+      "line": "8487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT1_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475891@macro@USB_RQPKTCOUNT2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT2_M",
+    "location": {
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+      "line": "8495",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@475967@macro@USB_RQPKTCOUNT2_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT2_S",
+    "location": {
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+      "line": "8496",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT2_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@476262@macro@USB_RQPKTCOUNT3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT3_M",
+    "location": {
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+      "line": "8504",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@476338@macro@USB_RQPKTCOUNT3_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT3_S",
+    "location": {
+      "column": "9",
+      "line": "8505",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT3_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@476633@macro@USB_RQPKTCOUNT4_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT4_COUNT_M",
+    "location": {
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+      "line": "8513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT4_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@476709@macro@USB_RQPKTCOUNT4_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT4_COUNT_S",
+    "location": {
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+      "line": "8514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT4_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477004@macro@USB_RQPKTCOUNT5_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT5_COUNT_M",
+    "location": {
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+      "line": "8522",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT5_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477080@macro@USB_RQPKTCOUNT5_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT5_COUNT_S",
+    "location": {
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+      "line": "8523",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT5_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477375@macro@USB_RQPKTCOUNT6_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT6_COUNT_M",
+    "location": {
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+      "line": "8531",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT6_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477451@macro@USB_RQPKTCOUNT6_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT6_COUNT_S",
+    "location": {
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+      "line": "8532",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT6_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477746@macro@USB_RQPKTCOUNT7_COUNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT7_COUNT_M",
+    "location": {
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+      "line": "8540",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT7_COUNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@477822@macro@USB_RQPKTCOUNT7_COUNT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RQPKTCOUNT7_COUNT_S",
+    "location": {
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+      "line": "8541",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RQPKTCOUNT7_COUNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478118@macro@USB_RXDPKTBUFDIS_EP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP7",
+    "location": {
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+      "line": "8549",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478250@macro@USB_RXDPKTBUFDIS_EP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP6",
+    "location": {
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+      "line": "8551",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478382@macro@USB_RXDPKTBUFDIS_EP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP5",
+    "location": {
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+      "line": "8553",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478514@macro@USB_RXDPKTBUFDIS_EP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP4",
+    "location": {
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+      "line": "8555",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478646@macro@USB_RXDPKTBUFDIS_EP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP3",
+    "location": {
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+      "line": "8557",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478778@macro@USB_RXDPKTBUFDIS_EP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP2",
+    "location": {
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+      "line": "8559",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@478910@macro@USB_RXDPKTBUFDIS_EP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_RXDPKTBUFDIS_EP1",
+    "location": {
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+      "line": "8561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_RXDPKTBUFDIS_EP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479303@macro@USB_TXDPKTBUFDIS_EP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP7",
+    "location": {
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+      "line": "8570",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479435@macro@USB_TXDPKTBUFDIS_EP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP6",
+    "location": {
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+      "line": "8572",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479567@macro@USB_TXDPKTBUFDIS_EP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP5",
+    "location": {
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+      "line": "8574",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479699@macro@USB_TXDPKTBUFDIS_EP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP4",
+    "location": {
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+      "line": "8576",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479831@macro@USB_TXDPKTBUFDIS_EP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP3",
+    "location": {
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+      "line": "8578",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@479963@macro@USB_TXDPKTBUFDIS_EP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP2",
+    "location": {
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+      "line": "8580",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480095@macro@USB_TXDPKTBUFDIS_EP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_TXDPKTBUFDIS_EP1",
+    "location": {
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+      "line": "8582",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_TXDPKTBUFDIS_EP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480475@macro@USB_EPC_PFLTACT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTACT_M",
+    "location": {
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+      "line": "8590",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTACT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480542@macro@USB_EPC_PFLTACT_UNCHG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTACT_UNCHG",
+    "location": {
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+      "line": "8591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTACT_UNCHG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480600@macro@USB_EPC_PFLTACT_TRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTACT_TRIS",
+    "location": {
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+      "line": "8592",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTACT_TRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480657@macro@USB_EPC_PFLTACT_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTACT_LOW",
+    "location": {
+      "column": "9",
+      "line": "8593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTACT_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480709@macro@USB_EPC_PFLTACT_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTACT_HIGH",
+    "location": {
+      "column": "9",
+      "line": "8594",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTACT_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480762@macro@USB_EPC_PFLTAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTAEN",
+    "location": {
+      "column": "9",
+      "line": "8595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480836@macro@USB_EPC_PFLTSEN_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTSEN_HIGH",
+    "location": {
+      "column": "9",
+      "line": "8596",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTSEN_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480902@macro@USB_EPC_PFLTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_PFLTEN",
+    "location": {
+      "column": "9",
+      "line": "8597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_PFLTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@480975@macro@USB_EPC_EPENDE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPENDE",
+    "location": {
+      "column": "9",
+      "line": "8598",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPENDE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481041@macro@USB_EPC_EPEN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPEN_M",
+    "location": {
+      "column": "9",
+      "line": "8599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPEN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481180@macro@USB_EPC_EPEN_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPEN_LOW",
+    "location": {
+      "column": "9",
+      "line": "8601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPEN_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481252@macro@USB_EPC_EPEN_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPEN_HIGH",
+    "location": {
+      "column": "9",
+      "line": "8602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPEN_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481325@macro@USB_EPC_EPEN_VBLOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPEN_VBLOW",
+    "location": {
+      "column": "9",
+      "line": "8603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPEN_VBLOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481462@macro@USB_EPC_EPEN_VBHIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPC_EPEN_VBHIGH",
+    "location": {
+      "column": "9",
+      "line": "8605",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPC_EPEN_VBHIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@481851@macro@USB_EPCRIS_PF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPCRIS_PF",
+    "location": {
+      "column": "9",
+      "line": "8613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPCRIS_PF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@482182@macro@USB_EPCIM_PF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPCIM_PF",
+    "location": {
+      "column": "9",
+      "line": "8620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPCIM_PF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@482512@macro@USB_EPCISC_PF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_EPCISC_PF",
+    "location": {
+      "column": "9",
+      "line": "8627",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_EPCISC_PF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@482901@macro@USB_DRRIS_RESUME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DRRIS_RESUME",
+    "location": {
+      "column": "9",
+      "line": "8635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DRRIS_RESUME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@483222@macro@USB_DRIM_RESUME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DRIM_RESUME",
+    "location": {
+      "column": "9",
+      "line": "8642",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DRIM_RESUME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@483542@macro@USB_DRISC_RESUME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DRISC_RESUME",
+    "location": {
+      "column": "9",
+      "line": "8649",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DRISC_RESUME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@483921@macro@USB_GPCS_DEVMODOTG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_GPCS_DEVMODOTG",
+    "location": {
+      "column": "9",
+      "line": "8657",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_GPCS_DEVMODOTG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@483988@macro@USB_GPCS_DEVMOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_GPCS_DEVMOD",
+    "location": {
+      "column": "9",
+      "line": "8658",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_GPCS_DEVMOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@484296@macro@USB_VDC_VBDEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_VDC_VBDEN",
+    "location": {
+      "column": "9",
+      "line": "8665",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VDC_VBDEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@484613@macro@USB_VDCRIS_VD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_VDCRIS_VD",
+    "location": {
+      "column": "9",
+      "line": "8672",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VDCRIS_VD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@484943@macro@USB_VDCIM_VD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_VDCIM_VD",
+    "location": {
+      "column": "9",
+      "line": "8679",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VDCIM_VD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@485268@macro@USB_VDCISC_VD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_VDCISC_VD",
+    "location": {
+      "column": "9",
+      "line": "8686",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_VDCISC_VD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@485653@macro@USB_IDVRIS_ID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IDVRIS_ID",
+    "location": {
+      "column": "9",
+      "line": "8694",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IDVRIS_ID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486036@macro@USB_IDVIM_ID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IDVIM_ID",
+    "location": {
+      "column": "9",
+      "line": "8702",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IDVIM_ID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486366@macro@USB_IDVISC_ID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_IDVISC_ID",
+    "location": {
+      "column": "9",
+      "line": "8709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_IDVISC_ID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486756@macro@USB_DMASEL_DMACTX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMACTX_M",
+    "location": {
+      "column": "9",
+      "line": "8717",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMACTX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486820@macro@USB_DMASEL_DMACRX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMACRX_M",
+    "location": {
+      "column": "9",
+      "line": "8718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMACRX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486884@macro@USB_DMASEL_DMABTX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMABTX_M",
+    "location": {
+      "column": "9",
+      "line": "8719",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMABTX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@486948@macro@USB_DMASEL_DMABRX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMABRX_M",
+    "location": {
+      "column": "9",
+      "line": "8720",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMABRX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487012@macro@USB_DMASEL_DMAATX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMAATX_M",
+    "location": {
+      "column": "9",
+      "line": "8721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMAATX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487076@macro@USB_DMASEL_DMAARX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMAARX_M",
+    "location": {
+      "column": "9",
+      "line": "8722",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMAARX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487140@macro@USB_DMASEL_DMACTX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMACTX_S",
+    "location": {
+      "column": "9",
+      "line": "8723",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMACTX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487176@macro@USB_DMASEL_DMACRX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMACRX_S",
+    "location": {
+      "column": "9",
+      "line": "8724",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMACRX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487212@macro@USB_DMASEL_DMABTX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMABTX_S",
+    "location": {
+      "column": "9",
+      "line": "8725",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMABTX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487248@macro@USB_DMASEL_DMABRX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMABRX_S",
+    "location": {
+      "column": "9",
+      "line": "8726",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMABRX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487283@macro@USB_DMASEL_DMAATX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMAATX_S",
+    "location": {
+      "column": "9",
+      "line": "8727",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMAATX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487318@macro@USB_DMASEL_DMAARX_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_DMASEL_DMAARX_S",
+    "location": {
+      "column": "9",
+      "line": "8728",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_DMASEL_DMAARX_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487600@macro@USB_PP_ECNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_PP_ECNT_M",
+    "location": {
+      "column": "9",
+      "line": "8735",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_PP_ECNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487663@macro@USB_PP_USB_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_PP_USB_M",
+    "location": {
+      "column": "9",
+      "line": "8736",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_PP_USB_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487726@macro@USB_PP_USB_DEVICE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_PP_USB_DEVICE",
+    "location": {
+      "column": "9",
+      "line": "8737",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_PP_USB_DEVICE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487781@macro@USB_PP_USB_HOSTDEVICE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "USB_PP_USB_HOSTDEVICE",
+    "location": {
+      "column": "9",
+      "line": "8738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "USB_PP_USB_HOSTDEVICE",
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+  {
+    "ID": "c:tm4c123gh6pm.h@487834@macro@USB_PP_USB_OTG",
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+    },
+    "name": "USB_PP_USB_OTG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487886@macro@USB_PP_PHY",
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+    "display": "USB_PP_PHY",
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+    },
+    "name": "USB_PP_PHY",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@487946@macro@USB_PP_TYPE_M",
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+    },
+    "name": "USB_PP_TYPE_M",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488010@macro@USB_PP_TYPE_0",
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+    },
+    "name": "USB_PP_TYPE_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488142@macro@USB_PP_ECNT_S",
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+    },
+    "name": "USB_PP_ECNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "ID": "c:tm4c123gh6pm.h@488429@macro@EEPROM_EESIZE_BLKCNT_M",
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+    "display": "EEPROM_EESIZE_BLKCNT_M",
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+    },
+    "name": "EEPROM_EESIZE_BLKCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488502@macro@EEPROM_EESIZE_WORDCNT_M",
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+    "display": "EEPROM_EESIZE_WORDCNT_M",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EESIZE_WORDCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488573@macro@EEPROM_EESIZE_BLKCNT_S",
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+    "display": "EEPROM_EESIZE_BLKCNT_S",
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+    },
+    "name": "EEPROM_EESIZE_BLKCNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488609@macro@EEPROM_EESIZE_WORDCNT_S",
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+    "display": "EEPROM_EESIZE_WORDCNT_S",
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+      "line": "8754",
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+    },
+    "name": "EEPROM_EESIZE_WORDCNT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488897@macro@EEPROM_EEBLOCK_BLOCK_M",
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+    "display": "EEPROM_EEBLOCK_BLOCK_M",
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+      "line": "8761",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEBLOCK_BLOCK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@488959@macro@EEPROM_EEBLOCK_BLOCK_S",
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+    "defdec": "Def",
+    "display": "EEPROM_EEBLOCK_BLOCK_S",
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+      "line": "8762",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEBLOCK_BLOCK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@489252@macro@EEPROM_EEOFFSET_OFFSET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEOFFSET_OFFSET_M",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEOFFSET_OFFSET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@489404@macro@EEPROM_EEOFFSET_OFFSET_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEOFFSET_OFFSET_S",
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEOFFSET_OFFSET_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@489772@macro@EEPROM_EERDWR_VALUE_M",
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+    "display": "EEPROM_EERDWR_VALUE_M",
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+      "line": "8780",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EERDWR_VALUE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@489846@macro@EEPROM_EERDWR_VALUE_S",
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+    "display": "EEPROM_EERDWR_VALUE_S",
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+      "line": "8781",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EERDWR_VALUE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490140@macro@EEPROM_EERDWRINC_VALUE_M",
+    "What": "MacroDef",
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+    "display": "EEPROM_EERDWRINC_VALUE_M",
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+      "line": "8789",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EERDWRINC_VALUE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490358@macro@EEPROM_EERDWRINC_VALUE_S",
+    "What": "MacroDef",
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+    "display": "EEPROM_EERDWRINC_VALUE_S",
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+      "line": "8792",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EERDWRINC_VALUE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490726@macro@EEPROM_EEDONE_WRBUSY",
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+    "display": "EEPROM_EEDONE_WRBUSY",
+    "location": {
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+      "line": "8800",
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+    },
+    "name": "EEPROM_EEDONE_WRBUSY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490785@macro@EEPROM_EEDONE_NOPERM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDONE_NOPERM",
+    "location": {
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+      "line": "8801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDONE_NOPERM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490858@macro@EEPROM_EEDONE_WKCOPY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDONE_WKCOPY",
+    "location": {
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+      "line": "8802",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDONE_WKCOPY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490924@macro@EEPROM_EEDONE_WKERASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDONE_WKERASE",
+    "location": {
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+      "line": "8803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDONE_WKERASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@490992@macro@EEPROM_EEDONE_WORKING",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDONE_WORKING",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDONE_WORKING",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@491307@macro@EEPROM_EESUPP_PRETRY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EESUPP_PRETRY",
+    "location": {
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+      "line": "8811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EESUPP_PRETRY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@491383@macro@EEPROM_EESUPP_ERETRY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EESUPP_ERETRY",
+    "location": {
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+      "line": "8812",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EESUPP_ERETRY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@491711@macro@EEPROM_EEUNLOCK_UNLOCK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEUNLOCK_UNLOCK_M",
+    "location": {
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+      "line": "8820",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEUNLOCK_UNLOCK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@492106@macro@EEPROM_EEPROT_ACC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_ACC",
+    "location": {
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+      "line": "8828",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_ACC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@492169@macro@EEPROM_EEPROT_PROT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_PROT_M",
+    "location": {
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+      "line": "8829",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_PROT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@492236@macro@EEPROM_EEPROT_PROT_RWNPW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_PROT_RWNPW",
+    "location": {
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+      "line": "8830",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_PROT_RWNPW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@492619@macro@EEPROM_EEPROT_PROT_RWPW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_PROT_RWPW",
+    "location": {
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+      "line": "8835",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_PROT_RWPW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@492840@macro@EEPROM_EEPROT_PROT_RONPW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPROT_PROT_RONPW",
+    "location": {
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+      "line": "8838",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPROT_PROT_RONPW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@493331@macro@EEPROM_EEPASS0_PASS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS0_PASS_M",
+    "location": {
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+      "line": "8847",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS0_PASS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@493388@macro@EEPROM_EEPASS0_PASS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS0_PASS_S",
+    "location": {
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+      "line": "8848",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS0_PASS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@493676@macro@EEPROM_EEPASS1_PASS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS1_PASS_M",
+    "location": {
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+      "line": "8855",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS1_PASS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@493733@macro@EEPROM_EEPASS1_PASS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS1_PASS_S",
+    "location": {
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+      "line": "8856",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS1_PASS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@494021@macro@EEPROM_EEPASS2_PASS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS2_PASS_M",
+    "location": {
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+      "line": "8863",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS2_PASS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@494078@macro@EEPROM_EEPASS2_PASS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEPASS2_PASS_S",
+    "location": {
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+      "line": "8864",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEPASS2_PASS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@494364@macro@EEPROM_EEINT_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEINT_INT",
+    "location": {
+      "column": "9",
+      "line": "8871",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEINT_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@494681@macro@EEPROM_EEHIDE_HN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEHIDE_HN_M",
+    "location": {
+      "column": "9",
+      "line": "8878",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEHIDE_HN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@494993@macro@EEPROM_EEDBGME_KEY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDBGME_KEY_M",
+    "location": {
+      "column": "9",
+      "line": "8885",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDBGME_KEY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@495051@macro@EEPROM_EEDBGME_ME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "EEPROM_EEDBGME_ME",
+    "location": {
+      "column": "9",
+      "line": "8886",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "EEPROM_EEDBGME_ME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@495110@macro@EEPROM_EEDBGME_KEY_S",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502081@macro@HIB_CTL_VBATSEL_2_5V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_VBATSEL_2_5V",
+    "location": {
+      "column": "9",
+      "line": "9010",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_VBATSEL_2_5V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502139@macro@HIB_CTL_BATCHK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_BATCHK",
+    "location": {
+      "column": "9",
+      "line": "9011",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_BATCHK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502208@macro@HIB_CTL_BATWKEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_BATWKEN",
+    "location": {
+      "column": "9",
+      "line": "9012",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_BATWKEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502276@macro@HIB_CTL_VDD3ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_VDD3ON",
+    "location": {
+      "column": "9",
+      "line": "9013",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_VDD3ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502336@macro@HIB_CTL_VABORT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_VABORT",
+    "location": {
+      "column": "9",
+      "line": "9014",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_VABORT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502407@macro@HIB_CTL_CLK32EN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_CLK32EN",
+    "location": {
+      "column": "9",
+      "line": "9015",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_CLK32EN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502471@macro@HIB_CTL_PINWEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_PINWEN",
+    "location": {
+      "column": "9",
+      "line": "9016",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_PINWEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502544@macro@HIB_CTL_RTCWEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_RTCWEN",
+    "location": {
+      "column": "9",
+      "line": "9017",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_RTCWEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502611@macro@HIB_CTL_HIBREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_HIBREQ",
+    "location": {
+      "column": "9",
+      "line": "9018",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_HIBREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502679@macro@HIB_CTL_RTCEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_CTL_RTCEN",
+    "location": {
+      "column": "9",
+      "line": "9019",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_CTL_RTCEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@502989@macro@HIB_IM_WC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IM_WC",
+    "location": {
+      "column": "9",
+      "line": "9026",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IM_WC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503132@macro@HIB_IM_EXTW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IM_EXTW",
+    "location": {
+      "column": "9",
+      "line": "9028",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IM_EXTW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503212@macro@HIB_IM_LOWBAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IM_LOWBAT",
+    "location": {
+      "column": "9",
+      "line": "9029",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IM_LOWBAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503343@macro@HIB_IM_RTCALT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IM_RTCALT0",
+    "location": {
+      "column": "9",
+      "line": "9031",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IM_RTCALT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503664@macro@HIB_RIS_WC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RIS_WC",
+    "location": {
+      "column": "9",
+      "line": "9038",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RIS_WC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503804@macro@HIB_RIS_EXTW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RIS_EXTW",
+    "location": {
+      "column": "9",
+      "line": "9040",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RIS_EXTW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@503938@macro@HIB_RIS_LOWBAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RIS_LOWBAT",
+    "location": {
+      "column": "9",
+      "line": "9042",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RIS_LOWBAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@504075@macro@HIB_RIS_RTCALT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RIS_RTCALT0",
+    "location": {
+      "column": "9",
+      "line": "9044",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RIS_RTCALT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@504402@macro@HIB_MIS_WC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_MIS_WC",
+    "location": {
+      "column": "9",
+      "line": "9051",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_MIS_WC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@504545@macro@HIB_MIS_EXTW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_MIS_EXTW",
+    "location": {
+      "column": "9",
+      "line": "9053",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_MIS_EXTW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@504682@macro@HIB_MIS_LOWBAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_MIS_LOWBAT",
+    "location": {
+      "column": "9",
+      "line": "9055",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_MIS_LOWBAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@504822@macro@HIB_MIS_RTCALT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_MIS_RTCALT0",
+    "location": {
+      "column": "9",
+      "line": "9057",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_MIS_RTCALT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505199@macro@HIB_IC_WC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IC_WC",
+    "location": {
+      "column": "9",
+      "line": "9065",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IC_WC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505334@macro@HIB_IC_EXTW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IC_EXTW",
+    "location": {
+      "column": "9",
+      "line": "9067",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IC_EXTW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505415@macro@HIB_IC_LOWBAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IC_LOWBAT",
+    "location": {
+      "column": "9",
+      "line": "9068",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IC_LOWBAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505547@macro@HIB_IC_RTCALT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_IC_RTCALT0",
+    "location": {
+      "column": "9",
+      "line": "9070",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_IC_RTCALT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505924@macro@HIB_RTCT_TRIM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCT_TRIM_M",
+    "location": {
+      "column": "9",
+      "line": "9078",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCT_TRIM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@505987@macro@HIB_RTCT_TRIM_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCT_TRIM_S",
+    "location": {
+      "column": "9",
+      "line": "9079",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCT_TRIM_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506270@macro@HIB_RTCSS_RTCSSM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCSS_RTCSSM_M",
+    "location": {
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+      "line": "9086",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCSS_RTCSSM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506340@macro@HIB_RTCSS_RTCSSC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCSS_RTCSSC_M",
+    "location": {
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+      "line": "9087",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCSS_RTCSSC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506410@macro@HIB_RTCSS_RTCSSM_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCSS_RTCSSM_S",
+    "location": {
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+      "line": "9088",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCSS_RTCSSM_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506446@macro@HIB_RTCSS_RTCSSC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_RTCSS_RTCSSC_S",
+    "location": {
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+      "line": "9089",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_RTCSS_RTCSSC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506728@macro@HIB_DATA_RTD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_DATA_RTD_M",
+    "location": {
+      "column": "9",
+      "line": "9096",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_DATA_RTD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@506803@macro@HIB_DATA_RTD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "HIB_DATA_RTD_S",
+    "location": {
+      "column": "9",
+      "line": "9097",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "HIB_DATA_RTD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507086@macro@FLASH_FMA_OFFSET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMA_OFFSET_M",
+    "location": {
+      "column": "9",
+      "line": "9104",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMA_OFFSET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507149@macro@FLASH_FMA_OFFSET_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMA_OFFSET_S",
+    "location": {
+      "column": "9",
+      "line": "9105",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMA_OFFSET_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507432@macro@FLASH_FMD_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMD_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9112",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMD_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507491@macro@FLASH_FMD_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMD_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "9113",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMD_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507774@macro@FLASH_FMC_WRKEY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_WRKEY",
+    "location": {
+      "column": "9",
+      "line": "9120",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_WRKEY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507838@macro@FLASH_FMC_COMT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_COMT",
+    "location": {
+      "column": "9",
+      "line": "9121",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_COMT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507908@macro@FLASH_FMC_MERASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_MERASE",
+    "location": {
+      "column": "9",
+      "line": "9122",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_MERASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@507980@macro@FLASH_FMC_ERASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_ERASE",
+    "location": {
+      "column": "9",
+      "line": "9123",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_ERASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508057@macro@FLASH_FMC_WRITE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC_WRITE",
+    "location": {
+      "column": "9",
+      "line": "9124",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC_WRITE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508386@macro@FLASH_FCRIS_PROGRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_PROGRIS",
+    "location": {
+      "column": "9",
+      "line": "9131",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_PROGRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508524@macro@FLASH_FCRIS_ERRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_ERRIS",
+    "location": {
+      "column": "9",
+      "line": "9133",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_ERRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508660@macro@FLASH_FCRIS_INVDRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_INVDRIS",
+    "location": {
+      "column": "9",
+      "line": "9135",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_INVDRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508790@macro@FLASH_FCRIS_VOLTRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_VOLTRIS",
+    "location": {
+      "column": "9",
+      "line": "9137",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_VOLTRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508920@macro@FLASH_FCRIS_ERIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_ERIS",
+    "location": {
+      "column": "9",
+      "line": "9139",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_ERIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@508996@macro@FLASH_FCRIS_PRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_PRIS",
+    "location": {
+      "column": "9",
+      "line": "9140",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_PRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509077@macro@FLASH_FCRIS_ARIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCRIS_ARIS",
+    "location": {
+      "column": "9",
+      "line": "9141",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCRIS_ARIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509402@macro@FLASH_FCIM_PROGMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_PROGMASK",
+    "location": {
+      "column": "9",
+      "line": "9148",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_PROGMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509473@macro@FLASH_FCIM_ERMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_ERMASK",
+    "location": {
+      "column": "9",
+      "line": "9149",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_ERMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509542@macro@FLASH_FCIM_INVDMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_INVDMASK",
+    "location": {
+      "column": "9",
+      "line": "9150",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_INVDMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509618@macro@FLASH_FCIM_VOLTMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_VOLTMASK",
+    "location": {
+      "column": "9",
+      "line": "9151",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_VOLTMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509686@macro@FLASH_FCIM_EMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_EMASK",
+    "location": {
+      "column": "9",
+      "line": "9152",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_EMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509756@macro@FLASH_FCIM_PMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_PMASK",
+    "location": {
+      "column": "9",
+      "line": "9153",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_PMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@509831@macro@FLASH_FCIM_AMASK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCIM_AMASK",
+    "location": {
+      "column": "9",
+      "line": "9154",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCIM_AMASK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510152@macro@FLASH_FCMISC_PROGMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_PROGMISC",
+    "location": {
+      "column": "9",
+      "line": "9161",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_PROGMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510290@macro@FLASH_FCMISC_ERMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_ERMISC",
+    "location": {
+      "column": "9",
+      "line": "9163",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_ERMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510426@macro@FLASH_FCMISC_INVDMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_INVDMISC",
+    "location": {
+      "column": "9",
+      "line": "9165",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_INVDMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510569@macro@FLASH_FCMISC_VOLTMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_VOLTMISC",
+    "location": {
+      "column": "9",
+      "line": "9167",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_VOLTMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510704@macro@FLASH_FCMISC_EMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_EMISC",
+    "location": {
+      "column": "9",
+      "line": "9169",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_EMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510841@macro@FLASH_FCMISC_PMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_PMISC",
+    "location": {
+      "column": "9",
+      "line": "9171",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_PMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@510983@macro@FLASH_FCMISC_AMISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FCMISC_AMISC",
+    "location": {
+      "column": "9",
+      "line": "9173",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FCMISC_AMISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@511369@macro@FLASH_FMC2_WRBUF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FMC2_WRBUF",
+    "location": {
+      "column": "9",
+      "line": "9181",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FMC2_WRBUF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@511696@macro@FLASH_FWBVAL_FWB_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FWBVAL_FWB_M",
+    "location": {
+      "column": "9",
+      "line": "9188",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FWBVAL_FWB_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@512019@macro@FLASH_FWBN_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FWBN_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9195",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FWBN_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@512322@macro@FLASH_FSIZE_SIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FSIZE_SIZE_M",
+    "location": {
+      "column": "9",
+      "line": "9202",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FSIZE_SIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@512381@macro@FLASH_FSIZE_SIZE_256KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_FSIZE_SIZE_256KB",
+    "location": {
+      "column": "9",
+      "line": "9203",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_FSIZE_SIZE_256KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@512695@macro@FLASH_SSIZE_SIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_SSIZE_SIZE_M",
+    "location": {
+      "column": "9",
+      "line": "9210",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_SSIZE_SIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@512753@macro@FLASH_SSIZE_SIZE_32KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_SSIZE_SIZE_32KB",
+    "location": {
+      "column": "9",
+      "line": "9211",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_SSIZE_SIZE_32KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513068@macro@FLASH_ROMSWMAP_SAFERTOS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_ROMSWMAP_SAFERTOS",
+    "location": {
+      "column": "9",
+      "line": "9218",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_ROMSWMAP_SAFERTOS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513383@macro@FLASH_RMCTL_BA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_RMCTL_BA",
+    "location": {
+      "column": "9",
+      "line": "9225",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_RMCTL_BA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513694@macro@FLASH_BOOTCFG_NW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_NW",
+    "location": {
+      "column": "9",
+      "line": "9232",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_NW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513754@macro@FLASH_BOOTCFG_PORT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_M",
+    "location": {
+      "column": "9",
+      "line": "9233",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513817@macro@FLASH_BOOTCFG_PORT_A",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_A",
+    "location": {
+      "column": "9",
+      "line": "9234",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_A",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513872@macro@FLASH_BOOTCFG_PORT_B",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_B",
+    "location": {
+      "column": "9",
+      "line": "9235",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_B",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513927@macro@FLASH_BOOTCFG_PORT_C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_C",
+    "location": {
+      "column": "9",
+      "line": "9236",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@513982@macro@FLASH_BOOTCFG_PORT_D",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_D",
+    "location": {
+      "column": "9",
+      "line": "9237",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_D",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514037@macro@FLASH_BOOTCFG_PORT_E",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_E",
+    "location": {
+      "column": "9",
+      "line": "9238",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_E",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514092@macro@FLASH_BOOTCFG_PORT_F",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_F",
+    "location": {
+      "column": "9",
+      "line": "9239",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_F",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514147@macro@FLASH_BOOTCFG_PORT_G",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_G",
+    "location": {
+      "column": "9",
+      "line": "9240",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_G",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514202@macro@FLASH_BOOTCFG_PORT_H",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PORT_H",
+    "location": {
+      "column": "9",
+      "line": "9241",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PORT_H",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514257@macro@FLASH_BOOTCFG_PIN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_M",
+    "location": {
+      "column": "9",
+      "line": "9242",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514319@macro@FLASH_BOOTCFG_PIN_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_0",
+    "location": {
+      "column": "9",
+      "line": "9243",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514373@macro@FLASH_BOOTCFG_PIN_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_1",
+    "location": {
+      "column": "9",
+      "line": "9244",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514427@macro@FLASH_BOOTCFG_PIN_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_2",
+    "location": {
+      "column": "9",
+      "line": "9245",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514481@macro@FLASH_BOOTCFG_PIN_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_3",
+    "location": {
+      "column": "9",
+      "line": "9246",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514535@macro@FLASH_BOOTCFG_PIN_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_4",
+    "location": {
+      "column": "9",
+      "line": "9247",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514589@macro@FLASH_BOOTCFG_PIN_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_5",
+    "location": {
+      "column": "9",
+      "line": "9248",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514643@macro@FLASH_BOOTCFG_PIN_6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_6",
+    "location": {
+      "column": "9",
+      "line": "9249",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514697@macro@FLASH_BOOTCFG_PIN_7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_PIN_7",
+    "location": {
+      "column": "9",
+      "line": "9250",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_PIN_7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514751@macro@FLASH_BOOTCFG_POL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_POL",
+    "location": {
+      "column": "9",
+      "line": "9251",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_POL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514818@macro@FLASH_BOOTCFG_EN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_EN",
+    "location": {
+      "column": "9",
+      "line": "9252",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_EN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514883@macro@FLASH_BOOTCFG_KEY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_KEY",
+    "location": {
+      "column": "9",
+      "line": "9253",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_KEY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@514942@macro@FLASH_BOOTCFG_DBG1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_DBG1",
+    "location": {
+      "column": "9",
+      "line": "9254",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_DBG1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@515006@macro@FLASH_BOOTCFG_DBG0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BOOTCFG_DBG0",
+    "location": {
+      "column": "9",
+      "line": "9255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_BOOTCFG_DBG0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@515323@macro@FLASH_USERREG0_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG0_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9262",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG0_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@515381@macro@FLASH_USERREG0_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG0_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "9263",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG0_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@515669@macro@FLASH_USERREG1_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG1_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9270",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG1_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@515727@macro@FLASH_USERREG1_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG1_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "9271",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG1_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516015@macro@FLASH_USERREG2_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG2_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9278",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG2_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516073@macro@FLASH_USERREG2_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG2_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "9279",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG2_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516361@macro@FLASH_USERREG3_DATA_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG3_DATA_M",
+    "location": {
+      "column": "9",
+      "line": "9286",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG3_DATA_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516419@macro@FLASH_USERREG3_DATA_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_USERREG3_DATA_S",
+    "location": {
+      "column": "9",
+      "line": "9287",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "FLASH_USERREG3_DATA_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516704@macro@SYSCTL_DID0_VER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_VER_M",
+    "location": {
+      "column": "9",
+      "line": "9294",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_VER_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516765@macro@SYSCTL_DID0_VER_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_VER_1",
+    "location": {
+      "column": "9",
+      "line": "9295",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_VER_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516905@macro@SYSCTL_DID0_CLASS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_M",
+    "location": {
+      "column": "9",
+      "line": "9297",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@516966@macro@SYSCTL_DID0_CLASS_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "9298",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517187@macro@SYSCTL_DID0_MAJ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_M",
+    "location": {
+      "column": "9",
+      "line": "9301",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517250@macro@SYSCTL_DID0_MAJ_REVA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVA",
+    "location": {
+      "column": "9",
+      "line": "9302",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517326@macro@SYSCTL_DID0_MAJ_REVB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVB",
+    "location": {
+      "column": "9",
+      "line": "9303",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517461@macro@SYSCTL_DID0_MAJ_REVC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVC",
+    "location": {
+      "column": "9",
+      "line": "9305",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517597@macro@SYSCTL_DID0_MIN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_M",
+    "location": {
+      "column": "9",
+      "line": "9307",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MIN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517660@macro@SYSCTL_DID0_MIN_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_0",
+    "location": {
+      "column": "9",
+      "line": "9308",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MIN_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517799@macro@SYSCTL_DID0_MIN_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_1",
+    "location": {
+      "column": "9",
+      "line": "9310",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MIN_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@517872@macro@SYSCTL_DID0_MIN_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_2",
+    "location": {
+      "column": "9",
+      "line": "9311",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID0_MIN_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518196@macro@SYSCTL_DID1_VER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_VER_M",
+    "location": {
+      "column": "9",
+      "line": "9318",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_VER_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518257@macro@SYSCTL_DID1_VER_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_VER_1",
+    "location": {
+      "column": "9",
+      "line": "9319",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_VER_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518313@macro@SYSCTL_DID1_FAM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_FAM_M",
+    "location": {
+      "column": "9",
+      "line": "9320",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_FAM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518368@macro@SYSCTL_DID1_FAM_TIVA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_FAM_TIVA",
+    "location": {
+      "column": "9",
+      "line": "9321",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_FAM_TIVA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518447@macro@SYSCTL_DID1_PRTNO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PRTNO_M",
+    "location": {
+      "column": "9",
+      "line": "9322",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PRTNO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518507@macro@SYSCTL_DID1_PRTNO_TM4C123GH6PM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PRTNO_TM4C123GH6PM",
+    "location": {
+      "column": "9",
+      "line": "9323",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PRTNO_TM4C123GH6PM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518649@macro@SYSCTL_DID1_PINCNT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_M",
+    "location": {
+      "column": "9",
+      "line": "9325",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518715@macro@SYSCTL_DID1_PINCNT_100",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_100",
+    "location": {
+      "column": "9",
+      "line": "9326",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_100",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518784@macro@SYSCTL_DID1_PINCNT_64",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_64",
+    "location": {
+      "column": "9",
+      "line": "9327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518852@macro@SYSCTL_DID1_PINCNT_144",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_144",
+    "location": {
+      "column": "9",
+      "line": "9328",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_144",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518921@macro@SYSCTL_DID1_PINCNT_157",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_157",
+    "location": {
+      "column": "9",
+      "line": "9329",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_157",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@518989@macro@SYSCTL_DID1_PINCNT_128",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PINCNT_128",
+    "location": {
+      "column": "9",
+      "line": "9330",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PINCNT_128",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519058@macro@SYSCTL_DID1_TEMP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_TEMP_M",
+    "location": {
+      "column": "9",
+      "line": "9331",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_TEMP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519124@macro@SYSCTL_DID1_TEMP_I",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_TEMP_I",
+    "location": {
+      "column": "9",
+      "line": "9332",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_TEMP_I",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519201@macro@SYSCTL_DID1_TEMP_E",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_TEMP_E",
+    "location": {
+      "column": "9",
+      "line": "9333",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_TEMP_E",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519276@macro@SYSCTL_DID1_TEMP_IE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_TEMP_IE",
+    "location": {
+      "column": "9",
+      "line": "9334",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_TEMP_IE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519588@macro@SYSCTL_DID1_PKG_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PKG_M",
+    "location": {
+      "column": "9",
+      "line": "9338",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PKG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519649@macro@SYSCTL_DID1_PKG_QFP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PKG_QFP",
+    "location": {
+      "column": "9",
+      "line": "9339",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PKG_QFP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519709@macro@SYSCTL_DID1_PKG_BGA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_PKG_BGA",
+    "location": {
+      "column": "9",
+      "line": "9340",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_PKG_BGA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519769@macro@SYSCTL_DID1_ROHS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_ROHS",
+    "location": {
+      "column": "9",
+      "line": "9341",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_ROHS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519833@macro@SYSCTL_DID1_QUAL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_QUAL_M",
+    "location": {
+      "column": "9",
+      "line": "9342",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519902@macro@SYSCTL_DID1_QUAL_ES",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_QUAL_ES",
+    "location": {
+      "column": "9",
+      "line": "9343",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_ES",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@519983@macro@SYSCTL_DID1_QUAL_PP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_QUAL_PP",
+    "location": {
+      "column": "9",
+      "line": "9344",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_PP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520062@macro@SYSCTL_DID1_QUAL_FQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_QUAL_FQ",
+    "location": {
+      "column": "9",
+      "line": "9345",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_FQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520375@macro@SYSCTL_DC0_SRAMSZ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_M",
+    "location": {
+      "column": "9",
+      "line": "9352",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520433@macro@SYSCTL_DC0_SRAMSZ_2KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_2KB",
+    "location": {
+      "column": "9",
+      "line": "9353",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_2KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520494@macro@SYSCTL_DC0_SRAMSZ_4KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_4KB",
+    "location": {
+      "column": "9",
+      "line": "9354",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_4KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520555@macro@SYSCTL_DC0_SRAMSZ_6KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_6KB",
+    "location": {
+      "column": "9",
+      "line": "9355",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_6KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520616@macro@SYSCTL_DC0_SRAMSZ_8KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_8KB",
+    "location": {
+      "column": "9",
+      "line": "9356",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_8KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520677@macro@SYSCTL_DC0_SRAMSZ_12KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_12KB",
+    "location": {
+      "column": "9",
+      "line": "9357",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_12KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520739@macro@SYSCTL_DC0_SRAMSZ_16KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_16KB",
+    "location": {
+      "column": "9",
+      "line": "9358",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_16KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520801@macro@SYSCTL_DC0_SRAMSZ_20KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_20KB",
+    "location": {
+      "column": "9",
+      "line": "9359",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_20KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520863@macro@SYSCTL_DC0_SRAMSZ_24KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_24KB",
+    "location": {
+      "column": "9",
+      "line": "9360",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_24KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520925@macro@SYSCTL_DC0_SRAMSZ_32KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_32KB",
+    "location": {
+      "column": "9",
+      "line": "9361",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_32KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@520987@macro@SYSCTL_DC0_FLASHSZ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_M",
+    "location": {
+      "column": "9",
+      "line": "9362",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521046@macro@SYSCTL_DC0_FLASHSZ_8KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_8KB",
+    "location": {
+      "column": "9",
+      "line": "9363",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_8KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521108@macro@SYSCTL_DC0_FLASHSZ_16KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_16KB",
+    "location": {
+      "column": "9",
+      "line": "9364",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_16KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521171@macro@SYSCTL_DC0_FLASHSZ_32KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_32KB",
+    "location": {
+      "column": "9",
+      "line": "9365",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_32KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521234@macro@SYSCTL_DC0_FLASHSZ_64KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_64KB",
+    "location": {
+      "column": "9",
+      "line": "9366",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_64KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521297@macro@SYSCTL_DC0_FLASHSZ_96KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_96KB",
+    "location": {
+      "column": "9",
+      "line": "9367",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_96KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521360@macro@SYSCTL_DC0_FLASHSZ_128K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_128K",
+    "location": {
+      "column": "9",
+      "line": "9368",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_128K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521424@macro@SYSCTL_DC0_FLASHSZ_192K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_192K",
+    "location": {
+      "column": "9",
+      "line": "9369",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_192K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521488@macro@SYSCTL_DC0_FLASHSZ_256K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_256K",
+    "location": {
+      "column": "9",
+      "line": "9370",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_256K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521801@macro@SYSCTL_DC1_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9377",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
+    "display": "SYSCTL_DC1_CAN1",
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+      "line": "9378",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@521942@macro@SYSCTL_DC1_CAN0",
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+    "defdec": "Def",
+    "display": "SYSCTL_DC1_CAN0",
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+      "column": "9",
+      "line": "9379",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522011@macro@SYSCTL_DC1_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PWM1",
+    "location": {
+      "column": "9",
+      "line": "9380",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522080@macro@SYSCTL_DC1_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9381",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522149@macro@SYSCTL_DC1_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1",
+    "location": {
+      "column": "9",
+      "line": "9382",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522218@macro@SYSCTL_DC1_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0",
+    "location": {
+      "column": "9",
+      "line": "9383",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522287@macro@SYSCTL_DC1_MINSYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_M",
+    "location": {
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+      "line": "9384",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522356@macro@SYSCTL_DC1_MINSYSDIV_80",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_80",
+    "location": {
+      "column": "9",
+      "line": "9385",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_80",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522508@macro@SYSCTL_DC1_MINSYSDIV_50",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_50",
+    "location": {
+      "column": "9",
+      "line": "9387",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_50",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522657@macro@SYSCTL_DC1_MINSYSDIV_40",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_40",
+    "location": {
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+      "line": "9389",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_40",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522806@macro@SYSCTL_DC1_MINSYSDIV_25",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_25",
+    "location": {
+      "column": "9",
+      "line": "9391",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_25",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@522951@macro@SYSCTL_DC1_MINSYSDIV_20",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_20",
+    "location": {
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+      "line": "9393",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_20",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523097@macro@SYSCTL_DC1_ADC1SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_M",
+    "location": {
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+      "line": "9395",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523160@macro@SYSCTL_DC1_ADC1SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "9396",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523228@macro@SYSCTL_DC1_ADC1SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "9397",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523296@macro@SYSCTL_DC1_ADC1SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "9398",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523364@macro@SYSCTL_DC1_ADC1SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "9399",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523430@macro@SYSCTL_DC1_ADC0SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_M",
+    "location": {
+      "column": "9",
+      "line": "9400",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523493@macro@SYSCTL_DC1_ADC0SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "9401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523561@macro@SYSCTL_DC1_ADC0SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "9402",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523629@macro@SYSCTL_DC1_ADC0SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "9403",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523697@macro@SYSCTL_DC1_ADC0SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "9404",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523763@macro@SYSCTL_DC1_MPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MPU",
+    "location": {
+      "column": "9",
+      "line": "9405",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_MPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523823@macro@SYSCTL_DC1_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_HIB",
+    "location": {
+      "column": "9",
+      "line": "9406",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523898@macro@SYSCTL_DC1_TEMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_TEMP",
+    "location": {
+      "column": "9",
+      "line": "9407",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_TEMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@523966@macro@SYSCTL_DC1_PLL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PLL",
+    "location": {
+      "column": "9",
+      "line": "9408",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_PLL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524026@macro@SYSCTL_DC1_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9409",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524099@macro@SYSCTL_DC1_SWO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_SWO",
+    "location": {
+      "column": "9",
+      "line": "9410",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_SWO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524170@macro@SYSCTL_DC1_SWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_SWD",
+    "location": {
+      "column": "9",
+      "line": "9411",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_SWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524230@macro@SYSCTL_DC1_JTAG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_JTAG",
+    "location": {
+      "column": "9",
+      "line": "9412",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC1_JTAG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524540@macro@SYSCTL_DC2_EPI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_EPI0",
+    "location": {
+      "column": "9",
+      "line": "9419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_EPI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524609@macro@SYSCTL_DC2_I2S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2S0",
+    "location": {
+      "column": "9",
+      "line": "9420",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_I2S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524678@macro@SYSCTL_DC2_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP2",
+    "location": {
+      "column": "9",
+      "line": "9421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524754@macro@SYSCTL_DC2_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP1",
+    "location": {
+      "column": "9",
+      "line": "9422",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524830@macro@SYSCTL_DC2_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP0",
+    "location": {
+      "column": "9",
+      "line": "9423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524906@macro@SYSCTL_DC2_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "9424",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@524977@macro@SYSCTL_DC2_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "9425",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525048@macro@SYSCTL_DC2_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "9426",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525119@macro@SYSCTL_DC2_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "9427",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525190@macro@SYSCTL_DC2_I2C1HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C1HS",
+    "location": {
+      "column": "9",
+      "line": "9428",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_I2C1HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525257@macro@SYSCTL_DC2_I2C1",
+    "What": "MacroDef",
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+      "line": "9429",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_I2C1",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525326@macro@SYSCTL_DC2_I2C0HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C0HS",
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+      "line": "9430",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_I2C0HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525393@macro@SYSCTL_DC2_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C0",
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+      "line": "9431",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525462@macro@SYSCTL_DC2_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_QEI1",
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+      "column": "9",
+      "line": "9432",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525531@macro@SYSCTL_DC2_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_QEI0",
+    "location": {
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+      "line": "9433",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525600@macro@SYSCTL_DC2_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_SSI1",
+    "location": {
+      "column": "9",
+      "line": "9434",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525669@macro@SYSCTL_DC2_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_SSI0",
+    "location": {
+      "column": "9",
+      "line": "9435",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525738@macro@SYSCTL_DC2_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART2",
+    "location": {
+      "column": "9",
+      "line": "9436",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525808@macro@SYSCTL_DC2_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART1",
+    "location": {
+      "column": "9",
+      "line": "9437",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@525878@macro@SYSCTL_DC2_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART0",
+    "location": {
+      "column": "9",
+      "line": "9438",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC2_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526197@macro@SYSCTL_DC3_32KHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_32KHZ",
+    "location": {
+      "column": "9",
+      "line": "9445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_32KHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526273@macro@SYSCTL_DC3_CCP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP5",
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+      "column": "9",
+      "line": "9446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526340@macro@SYSCTL_DC3_CCP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP4",
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+      "line": "9447",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526407@macro@SYSCTL_DC3_CCP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP3",
+    "location": {
+      "column": "9",
+      "line": "9448",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526474@macro@SYSCTL_DC3_CCP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP2",
+    "location": {
+      "column": "9",
+      "line": "9449",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526541@macro@SYSCTL_DC3_CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP1",
+    "location": {
+      "column": "9",
+      "line": "9450",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526608@macro@SYSCTL_DC3_CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP0",
+    "location": {
+      "column": "9",
+      "line": "9451",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526675@macro@SYSCTL_DC3_ADC0AIN7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN7",
+    "location": {
+      "column": "9",
+      "line": "9452",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526753@macro@SYSCTL_DC3_ADC0AIN6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN6",
+    "location": {
+      "column": "9",
+      "line": "9453",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526831@macro@SYSCTL_DC3_ADC0AIN5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN5",
+    "location": {
+      "column": "9",
+      "line": "9454",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526909@macro@SYSCTL_DC3_ADC0AIN4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN4",
+    "location": {
+      "column": "9",
+      "line": "9455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@526987@macro@SYSCTL_DC3_ADC0AIN3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN3",
+    "location": {
+      "column": "9",
+      "line": "9456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527065@macro@SYSCTL_DC3_ADC0AIN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN2",
+    "location": {
+      "column": "9",
+      "line": "9457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527143@macro@SYSCTL_DC3_ADC0AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN1",
+    "location": {
+      "column": "9",
+      "line": "9458",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527221@macro@SYSCTL_DC3_ADC0AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN0",
+    "location": {
+      "column": "9",
+      "line": "9459",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527299@macro@SYSCTL_DC3_PWMFAULT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWMFAULT",
+    "location": {
+      "column": "9",
+      "line": "9460",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWMFAULT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527369@macro@SYSCTL_DC3_C2O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2O",
+    "location": {
+      "column": "9",
+      "line": "9461",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C2O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527433@macro@SYSCTL_DC3_C2PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2PLUS",
+    "location": {
+      "column": "9",
+      "line": "9462",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C2PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527497@macro@SYSCTL_DC3_C2MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2MINUS",
+    "location": {
+      "column": "9",
+      "line": "9463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C2MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527561@macro@SYSCTL_DC3_C1O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1O",
+    "location": {
+      "column": "9",
+      "line": "9464",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C1O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527625@macro@SYSCTL_DC3_C1PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1PLUS",
+    "location": {
+      "column": "9",
+      "line": "9465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C1PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527689@macro@SYSCTL_DC3_C1MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1MINUS",
+    "location": {
+      "column": "9",
+      "line": "9466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C1MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527753@macro@SYSCTL_DC3_C0O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0O",
+    "location": {
+      "column": "9",
+      "line": "9467",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C0O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527817@macro@SYSCTL_DC3_C0PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0PLUS",
+    "location": {
+      "column": "9",
+      "line": "9468",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C0PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527881@macro@SYSCTL_DC3_C0MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0MINUS",
+    "location": {
+      "column": "9",
+      "line": "9469",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_C0MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@527945@macro@SYSCTL_DC3_PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM5",
+    "location": {
+      "column": "9",
+      "line": "9470",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528010@macro@SYSCTL_DC3_PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM4",
+    "location": {
+      "column": "9",
+      "line": "9471",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528075@macro@SYSCTL_DC3_PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM3",
+    "location": {
+      "column": "9",
+      "line": "9472",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528140@macro@SYSCTL_DC3_PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM2",
+    "location": {
+      "column": "9",
+      "line": "9473",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528205@macro@SYSCTL_DC3_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM1",
+    "location": {
+      "column": "9",
+      "line": "9474",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528270@macro@SYSCTL_DC3_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9475",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC3_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528584@macro@SYSCTL_DC4_EPHY0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_EPHY0",
+    "location": {
+      "column": "9",
+      "line": "9482",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_EPHY0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528661@macro@SYSCTL_DC4_EMAC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_EMAC0",
+    "location": {
+      "column": "9",
+      "line": "9483",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_EMAC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528738@macro@SYSCTL_DC4_E1588",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_E1588",
+    "location": {
+      "column": "9",
+      "line": "9484",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_E1588",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528799@macro@SYSCTL_DC4_PICAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_PICAL",
+    "location": {
+      "column": "9",
+      "line": "9485",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_PICAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528863@macro@SYSCTL_DC4_CCP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_CCP7",
+    "location": {
+      "column": "9",
+      "line": "9486",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_CCP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528930@macro@SYSCTL_DC4_CCP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_CCP6",
+    "location": {
+      "column": "9",
+      "line": "9487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_CCP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@528997@macro@SYSCTL_DC4_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_UDMA",
+    "location": {
+      "column": "9",
+      "line": "9488",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529070@macro@SYSCTL_DC4_ROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_ROM",
+    "location": {
+      "column": "9",
+      "line": "9489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_ROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529144@macro@SYSCTL_DC4_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "9490",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529212@macro@SYSCTL_DC4_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "9491",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529280@macro@SYSCTL_DC4_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "9492",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529348@macro@SYSCTL_DC4_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "9493",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529416@macro@SYSCTL_DC4_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "9494",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529484@macro@SYSCTL_DC4_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "9495",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529552@macro@SYSCTL_DC4_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "9496",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529620@macro@SYSCTL_DC4_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "9497",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@529688@macro@SYSCTL_DC4_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "9498",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC4_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530005@macro@SYSCTL_DC5_PWMFAULT3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT3",
+    "location": {
+      "column": "9",
+      "line": "9505",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530077@macro@SYSCTL_DC5_PWMFAULT2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT2",
+    "location": {
+      "column": "9",
+      "line": "9506",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530149@macro@SYSCTL_DC5_PWMFAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT1",
+    "location": {
+      "column": "9",
+      "line": "9507",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530221@macro@SYSCTL_DC5_PWMFAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT0",
+    "location": {
+      "column": "9",
+      "line": "9508",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530293@macro@SYSCTL_DC5_PWMEFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMEFLT",
+    "location": {
+      "column": "9",
+      "line": "9509",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMEFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530367@macro@SYSCTL_DC5_PWMESYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMESYNC",
+    "location": {
+      "column": "9",
+      "line": "9510",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWMESYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530440@macro@SYSCTL_DC5_PWM7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM7",
+    "location": {
+      "column": "9",
+      "line": "9511",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530505@macro@SYSCTL_DC5_PWM6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM6",
+    "location": {
+      "column": "9",
+      "line": "9512",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530570@macro@SYSCTL_DC5_PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM5",
+    "location": {
+      "column": "9",
+      "line": "9513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530635@macro@SYSCTL_DC5_PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM4",
+    "location": {
+      "column": "9",
+      "line": "9514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530700@macro@SYSCTL_DC5_PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM3",
+    "location": {
+      "column": "9",
+      "line": "9515",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530765@macro@SYSCTL_DC5_PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM2",
+    "location": {
+      "column": "9",
+      "line": "9516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530830@macro@SYSCTL_DC5_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM1",
+    "location": {
+      "column": "9",
+      "line": "9517",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@530895@macro@SYSCTL_DC5_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9518",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC5_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531209@macro@SYSCTL_DC6_USB0PHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0PHY",
+    "location": {
+      "column": "9",
+      "line": "9525",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_USB0PHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531282@macro@SYSCTL_DC6_USB0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_M",
+    "location": {
+      "column": "9",
+      "line": "9526",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_USB0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531351@macro@SYSCTL_DC6_USB0_DEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_DEV",
+    "location": {
+      "column": "9",
+      "line": "9527",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_USB0_DEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531419@macro@SYSCTL_DC6_USB0_HOSTDEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_HOSTDEV",
+    "location": {
+      "column": "9",
+      "line": "9528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_USB0_HOSTDEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531489@macro@SYSCTL_DC6_USB0_OTG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_OTG",
+    "location": {
+      "column": "9",
+      "line": "9529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC6_USB0_OTG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531798@macro@SYSCTL_DC7_DMACH30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH30",
+    "location": {
+      "column": "9",
+      "line": "9536",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC7_DMACH30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531861@macro@SYSCTL_DC7_DMACH29",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH29",
+    "location": {
+      "column": "9",
+      "line": "9537",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC7_DMACH29",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531924@macro@SYSCTL_DC7_DMACH28",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH28",
+    "location": {
+      "column": "9",
+      "line": "9538",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC7_DMACH28",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@531987@macro@SYSCTL_DC7_DMACH27",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH27",
+    "location": {
+      "column": "9",
+      "line": "9539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC7_DMACH27",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@532050@macro@SYSCTL_DC7_DMACH26",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH26",
+    "location": {
+      "column": "9",
+      "line": "9540",
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+    },
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+    },
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+    },
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+    },
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+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
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+    },
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+    },
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+    "What": "MacroDef",
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+    },
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+    },
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+    },
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+    "What": "MacroDef",
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+    },
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+    "What": "MacroDef",
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+    },
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+    "What": "MacroDef",
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+    },
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+    },
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+    },
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+    },
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+  },
+  {
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+    },
+    "name": "SYSCTL_DC8_ADC1AIN2",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535088@macro@SYSCTL_DC8_ADC1AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC1AIN1",
+    "location": {
+      "column": "9",
+      "line": "9587",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC1AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535166@macro@SYSCTL_DC8_ADC1AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC1AIN0",
+    "location": {
+      "column": "9",
+      "line": "9588",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC1AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535244@macro@SYSCTL_DC8_ADC0AIN15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN15",
+    "location": {
+      "column": "9",
+      "line": "9589",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535323@macro@SYSCTL_DC8_ADC0AIN14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN14",
+    "location": {
+      "column": "9",
+      "line": "9590",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535402@macro@SYSCTL_DC8_ADC0AIN13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN13",
+    "location": {
+      "column": "9",
+      "line": "9591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535481@macro@SYSCTL_DC8_ADC0AIN12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN12",
+    "location": {
+      "column": "9",
+      "line": "9592",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535560@macro@SYSCTL_DC8_ADC0AIN11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN11",
+    "location": {
+      "column": "9",
+      "line": "9593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535639@macro@SYSCTL_DC8_ADC0AIN10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN10",
+    "location": {
+      "column": "9",
+      "line": "9594",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535718@macro@SYSCTL_DC8_ADC0AIN9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN9",
+    "location": {
+      "column": "9",
+      "line": "9595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535796@macro@SYSCTL_DC8_ADC0AIN8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN8",
+    "location": {
+      "column": "9",
+      "line": "9596",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535874@macro@SYSCTL_DC8_ADC0AIN7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN7",
+    "location": {
+      "column": "9",
+      "line": "9597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@535952@macro@SYSCTL_DC8_ADC0AIN6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN6",
+    "location": {
+      "column": "9",
+      "line": "9598",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536030@macro@SYSCTL_DC8_ADC0AIN5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN5",
+    "location": {
+      "column": "9",
+      "line": "9599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536108@macro@SYSCTL_DC8_ADC0AIN4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN4",
+    "location": {
+      "column": "9",
+      "line": "9600",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536186@macro@SYSCTL_DC8_ADC0AIN3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN3",
+    "location": {
+      "column": "9",
+      "line": "9601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536264@macro@SYSCTL_DC8_ADC0AIN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN2",
+    "location": {
+      "column": "9",
+      "line": "9602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536342@macro@SYSCTL_DC8_ADC0AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN1",
+    "location": {
+      "column": "9",
+      "line": "9603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536420@macro@SYSCTL_DC8_ADC0AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN0",
+    "location": {
+      "column": "9",
+      "line": "9604",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536751@macro@SYSCTL_PBORCTL_BOR0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PBORCTL_BOR0",
+    "location": {
+      "column": "9",
+      "line": "9611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PBORCTL_BOR0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@536827@macro@SYSCTL_PBORCTL_BOR1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PBORCTL_BOR1",
+    "location": {
+      "column": "9",
+      "line": "9612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PBORCTL_BOR1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537154@macro@SYSCTL_SRCR0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9619",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537221@macro@SYSCTL_SRCR0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "9620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537288@macro@SYSCTL_SRCR0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "9621",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537355@macro@SYSCTL_SRCR0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537421@macro@SYSCTL_SRCR0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "9623",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537488@macro@SYSCTL_SRCR0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "9624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537555@macro@SYSCTL_SRCR0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_HIB",
+    "location": {
+      "column": "9",
+      "line": "9625",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537621@macro@SYSCTL_SRCR0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9626",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@537939@macro@SYSCTL_SRCR1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "9633",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538015@macro@SYSCTL_SRCR1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "9634",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538091@macro@SYSCTL_SRCR1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "9635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538161@macro@SYSCTL_SRCR1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "9636",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538231@macro@SYSCTL_SRCR1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "9637",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538301@macro@SYSCTL_SRCR1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "9638",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538371@macro@SYSCTL_SRCR1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "9639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538438@macro@SYSCTL_SRCR1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "9640",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538505@macro@SYSCTL_SRCR1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "9641",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538572@macro@SYSCTL_SRCR1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "9642",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538639@macro@SYSCTL_SRCR1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "9643",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538706@macro@SYSCTL_SRCR1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "9644",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538773@macro@SYSCTL_SRCR1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART2",
+    "location": {
+      "column": "9",
+      "line": "9645",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538841@macro@SYSCTL_SRCR1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART1",
+    "location": {
+      "column": "9",
+      "line": "9646",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@538909@macro@SYSCTL_SRCR1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART0",
+    "location": {
+      "column": "9",
+      "line": "9647",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539228@macro@SYSCTL_SRCR2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_USB0",
+    "location": {
+      "column": "9",
+      "line": "9654",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539295@macro@SYSCTL_SRCR2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "9655",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539367@macro@SYSCTL_SRCR2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "9656",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539436@macro@SYSCTL_SRCR2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "9657",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539505@macro@SYSCTL_SRCR2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "9658",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539574@macro@SYSCTL_SRCR2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "9659",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539643@macro@SYSCTL_SRCR2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "9660",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@539712@macro@SYSCTL_SRCR2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "9661",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540030@macro@SYSCTL_RIS_BOR0RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_BOR0RIS",
+    "location": {
+      "column": "9",
+      "line": "9668",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_BOR0RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540162@macro@SYSCTL_RIS_VDDARIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_VDDARIS",
+    "location": {
+      "column": "9",
+      "line": "9670",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_VDDARIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540299@macro@SYSCTL_RIS_MOSCPUPRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_MOSCPUPRIS",
+    "location": {
+      "column": "9",
+      "line": "9672",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_MOSCPUPRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540430@macro@SYSCTL_RIS_USBPLLLRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_USBPLLLRIS",
+    "location": {
+      "column": "9",
+      "line": "9674",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_USBPLLLRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540560@macro@SYSCTL_RIS_PLLLRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_PLLLRIS",
+    "location": {
+      "column": "9",
+      "line": "9676",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_PLLLRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540638@macro@SYSCTL_RIS_MOFRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_MOFRIS",
+    "location": {
+      "column": "9",
+      "line": "9677",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_MOFRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@540779@macro@SYSCTL_RIS_BOR1RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_BOR1RIS",
+    "location": {
+      "column": "9",
+      "line": "9679",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RIS_BOR1RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541160@macro@SYSCTL_IMC_BOR0IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_BOR0IM",
+    "location": {
+      "column": "9",
+      "line": "9687",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_BOR0IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541238@macro@SYSCTL_IMC_VDDAIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_VDDAIM",
+    "location": {
+      "column": "9",
+      "line": "9688",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_VDDAIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541315@macro@SYSCTL_IMC_MOSCPUPIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_MOSCPUPIM",
+    "location": {
+      "column": "9",
+      "line": "9689",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_MOSCPUPIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541392@macro@SYSCTL_IMC_USBPLLLIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_USBPLLLIM",
+    "location": {
+      "column": "9",
+      "line": "9690",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_USBPLLLIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541468@macro@SYSCTL_IMC_PLLLIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_PLLLIM",
+    "location": {
+      "column": "9",
+      "line": "9691",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_PLLLIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541540@macro@SYSCTL_IMC_MOFIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_MOFIM",
+    "location": {
+      "column": "9",
+      "line": "9692",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_MOFIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@541675@macro@SYSCTL_IMC_BOR1IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_BOR1IM",
+    "location": {
+      "column": "9",
+      "line": "9694",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_IMC_BOR1IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542003@macro@SYSCTL_MISC_BOR0MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_BOR0MIS",
+    "location": {
+      "column": "9",
+      "line": "9701",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_BOR0MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542138@macro@SYSCTL_MISC_VDDAMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_VDDAMIS",
+    "location": {
+      "column": "9",
+      "line": "9703",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_VDDAMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542272@macro@SYSCTL_MISC_MOSCPUPMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_MOSCPUPMIS",
+    "location": {
+      "column": "9",
+      "line": "9705",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_MOSCPUPMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542406@macro@SYSCTL_MISC_USBPLLLMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_USBPLLLMIS",
+    "location": {
+      "column": "9",
+      "line": "9707",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_USBPLLLMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542539@macro@SYSCTL_MISC_PLLLMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_PLLLMIS",
+    "location": {
+      "column": "9",
+      "line": "9709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_PLLLMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542620@macro@SYSCTL_MISC_MOFMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_MOFMIS",
+    "location": {
+      "column": "9",
+      "line": "9710",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_MOFMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@542764@macro@SYSCTL_MISC_BOR1MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_BOR1MIS",
+    "location": {
+      "column": "9",
+      "line": "9712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MISC_BOR1MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543149@macro@SYSCTL_RESC_MOSCFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_MOSCFAIL",
+    "location": {
+      "column": "9",
+      "line": "9720",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_MOSCFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543216@macro@SYSCTL_RESC_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543287@macro@SYSCTL_RESC_SW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_SW",
+    "location": {
+      "column": "9",
+      "line": "9722",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_SW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543350@macro@SYSCTL_RESC_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9723",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543421@macro@SYSCTL_RESC_BOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_BOR",
+    "location": {
+      "column": "9",
+      "line": "9724",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_BOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543485@macro@SYSCTL_RESC_POR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_POR",
+    "location": {
+      "column": "9",
+      "line": "9725",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_POR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543548@macro@SYSCTL_RESC_EXT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_EXT",
+    "location": {
+      "column": "9",
+      "line": "9726",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RESC_EXT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543860@macro@SYSCTL_RCC_ACG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_ACG",
+    "location": {
+      "column": "9",
+      "line": "9733",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC_ACG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543926@macro@SYSCTL_RCC_SYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_SYSDIV_M",
+    "location": {
+      "column": "9",
+      "line": "9734",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC_SYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@543995@macro@SYSCTL_RCC_USESYSDIV",
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@546636@macro@SYSCTL_GPIOHBCTL_PORTF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTF",
+    "location": {
+      "column": "9",
+      "line": "9782",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@546769@macro@SYSCTL_GPIOHBCTL_PORTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTE",
+    "location": {
+      "column": "9",
+      "line": "9784",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@546902@macro@SYSCTL_GPIOHBCTL_PORTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTD",
+    "location": {
+      "column": "9",
+      "line": "9786",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547035@macro@SYSCTL_GPIOHBCTL_PORTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTC",
+    "location": {
+      "column": "9",
+      "line": "9788",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547168@macro@SYSCTL_GPIOHBCTL_PORTB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTB",
+    "location": {
+      "column": "9",
+      "line": "9790",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547301@macro@SYSCTL_GPIOHBCTL_PORTA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTA",
+    "location": {
+      "column": "9",
+      "line": "9792",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547684@macro@SYSCTL_RCC2_USERCC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_USERCC2",
+    "location": {
+      "column": "9",
+      "line": "9800",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_USERCC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547741@macro@SYSCTL_RCC2_DIV400",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_DIV400",
+    "location": {
+      "column": "9",
+      "line": "9801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_DIV400",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547871@macro@SYSCTL_RCC2_SYSDIV2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2_M",
+    "location": {
+      "column": "9",
+      "line": "9803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@547942@macro@SYSCTL_RCC2_SYSDIV2LSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2LSB",
+    "location": {
+      "column": "9",
+      "line": "9804",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2LSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548017@macro@SYSCTL_RCC2_USBPWRDN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_USBPWRDN",
+    "location": {
+      "column": "9",
+      "line": "9805",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_USBPWRDN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548084@macro@SYSCTL_RCC2_PWRDN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_PWRDN2",
+    "location": {
+      "column": "9",
+      "line": "9806",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_PWRDN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548149@macro@SYSCTL_RCC2_BYPASS2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_BYPASS2",
+    "location": {
+      "column": "9",
+      "line": "9807",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_BYPASS2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548210@macro@SYSCTL_RCC2_OSCSRC2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_M",
+    "location": {
+      "column": "9",
+      "line": "9808",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548278@macro@SYSCTL_RCC2_OSCSRC2_MO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_MO",
+    "location": {
+      "column": "9",
+      "line": "9809",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_MO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548331@macro@SYSCTL_RCC2_OSCSRC2_IO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_IO",
+    "location": {
+      "column": "9",
+      "line": "9810",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_IO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548385@macro@SYSCTL_RCC2_OSCSRC2_IO4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_IO4",
+    "location": {
+      "column": "9",
+      "line": "9811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_IO4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548441@macro@SYSCTL_RCC2_OSCSRC2_30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_30",
+    "location": {
+      "column": "9",
+      "line": "9812",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548496@macro@SYSCTL_RCC2_OSCSRC2_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_32",
+    "location": {
+      "column": "9",
+      "line": "9813",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548555@macro@SYSCTL_RCC2_SYSDIV2_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2_S",
+    "location": {
+      "column": "9",
+      "line": "9814",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548844@macro@SYSCTL_MOSCCTL_NOXTAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_NOXTAL",
+    "location": {
+      "column": "9",
+      "line": "9821",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MOSCCTL_NOXTAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548913@macro@SYSCTL_MOSCCTL_MOSCIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_MOSCIM",
+    "location": {
+      "column": "9",
+      "line": "9822",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MOSCCTL_MOSCIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@548981@macro@SYSCTL_MOSCCTL_CVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_CVAL",
+    "location": {
+      "column": "9",
+      "line": "9823",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_MOSCCTL_CVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549306@macro@SYSCTL_RCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9830",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549380@macro@SYSCTL_RCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "9831",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549454@macro@SYSCTL_RCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "9832",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549528@macro@SYSCTL_RCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9833",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549601@macro@SYSCTL_RCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "9834",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549675@macro@SYSCTL_RCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "9835",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549749@macro@SYSCTL_RCGC0_ADC1SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_M",
+    "location": {
+      "column": "9",
+      "line": "9836",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549815@macro@SYSCTL_RCGC0_ADC1SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "9837",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@549964@macro@SYSCTL_RCGC0_ADC1SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "9839",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550113@macro@SYSCTL_RCGC0_ADC1SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "9841",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550262@macro@SYSCTL_RCGC0_ADC1SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "9843",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550328@macro@SYSCTL_RCGC0_ADC0SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_M",
+    "location": {
+      "column": "9",
+      "line": "9844",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550394@macro@SYSCTL_RCGC0_ADC0SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "9845",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550543@macro@SYSCTL_RCGC0_ADC0SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "9847",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550692@macro@SYSCTL_RCGC0_ADC0SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "9849",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550841@macro@SYSCTL_RCGC0_ADC0SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "9851",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550907@macro@SYSCTL_RCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "9852",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@550980@macro@SYSCTL_RCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9853",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551305@macro@SYSCTL_RCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "9860",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551386@macro@SYSCTL_RCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "9861",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551467@macro@SYSCTL_RCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "9862",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551544@macro@SYSCTL_RCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "9863",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551621@macro@SYSCTL_RCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "9864",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551698@macro@SYSCTL_RCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "9865",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551775@macro@SYSCTL_RCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "9866",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551849@macro@SYSCTL_RCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "9867",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551923@macro@SYSCTL_RCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "9868",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@551997@macro@SYSCTL_RCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "9869",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552071@macro@SYSCTL_RCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "9870",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552145@macro@SYSCTL_RCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "9871",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552219@macro@SYSCTL_RCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "9872",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552294@macro@SYSCTL_RCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "9873",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552369@macro@SYSCTL_RCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "9874",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552695@macro@SYSCTL_RCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "9881",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552769@macro@SYSCTL_RCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "9882",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552848@macro@SYSCTL_RCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "9883",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@552924@macro@SYSCTL_RCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "9884",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553000@macro@SYSCTL_RCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "9885",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553076@macro@SYSCTL_RCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "9886",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553152@macro@SYSCTL_RCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "9887",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553228@macro@SYSCTL_RCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "9888",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553555@macro@SYSCTL_SCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9895",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553629@macro@SYSCTL_SCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "9896",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553703@macro@SYSCTL_SCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "9897",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553777@macro@SYSCTL_SCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9898",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553850@macro@SYSCTL_SCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "9899",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553924@macro@SYSCTL_SCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "9900",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@553998@macro@SYSCTL_SCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "9901",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554071@macro@SYSCTL_SCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9902",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554396@macro@SYSCTL_SCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "9909",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554477@macro@SYSCTL_SCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "9910",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554558@macro@SYSCTL_SCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "9911",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554635@macro@SYSCTL_SCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "9912",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554712@macro@SYSCTL_SCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "9913",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554789@macro@SYSCTL_SCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "9914",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554866@macro@SYSCTL_SCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "9915",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@554940@macro@SYSCTL_SCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "9916",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555014@macro@SYSCTL_SCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "9917",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555088@macro@SYSCTL_SCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "9918",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555162@macro@SYSCTL_SCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "9919",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555236@macro@SYSCTL_SCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "9920",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555310@macro@SYSCTL_SCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "9921",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555385@macro@SYSCTL_SCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "9922",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555460@macro@SYSCTL_SCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "9923",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555786@macro@SYSCTL_SCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "9930",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555860@macro@SYSCTL_SCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "9931",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@555939@macro@SYSCTL_SCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "9932",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556015@macro@SYSCTL_SCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "9933",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556091@macro@SYSCTL_SCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "9934",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556167@macro@SYSCTL_SCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "9935",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556243@macro@SYSCTL_SCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "9936",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556319@macro@SYSCTL_SCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "9937",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556646@macro@SYSCTL_DCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "9944",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556720@macro@SYSCTL_DCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "9945",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556794@macro@SYSCTL_DCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "9946",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556868@macro@SYSCTL_DCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "9947",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@556941@macro@SYSCTL_DCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "9948",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557015@macro@SYSCTL_DCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "9949",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557089@macro@SYSCTL_DCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "9950",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557162@macro@SYSCTL_DCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "9951",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557487@macro@SYSCTL_DCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "9958",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557568@macro@SYSCTL_DCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "9959",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557649@macro@SYSCTL_DCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "9960",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557726@macro@SYSCTL_DCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "9961",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557803@macro@SYSCTL_DCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "9962",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557880@macro@SYSCTL_DCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "9963",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@557957@macro@SYSCTL_DCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "9964",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558031@macro@SYSCTL_DCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "9965",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558105@macro@SYSCTL_DCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "9966",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558179@macro@SYSCTL_DCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "9967",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558253@macro@SYSCTL_DCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "9968",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558327@macro@SYSCTL_DCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "9969",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558401@macro@SYSCTL_DCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "9970",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558476@macro@SYSCTL_DCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "9971",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558551@macro@SYSCTL_DCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "9972",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558877@macro@SYSCTL_DCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "9979",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@558951@macro@SYSCTL_DCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "9980",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559030@macro@SYSCTL_DCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "9981",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559106@macro@SYSCTL_DCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "9982",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559182@macro@SYSCTL_DCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "9983",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559258@macro@SYSCTL_DCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "9984",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559334@macro@SYSCTL_DCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "9985",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559410@macro@SYSCTL_DCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "9986",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559746@macro@SYSCTL_DSLPCLKCFG_D_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_D_M",
+    "location": {
+      "column": "9",
+      "line": "9994",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_D_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559817@macro@SYSCTL_DSLPCLKCFG_O_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_M",
+    "location": {
+      "column": "9",
+      "line": "9995",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559878@macro@SYSCTL_DSLPCLKCFG_O_IGN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_IGN",
+    "location": {
+      "column": "9",
+      "line": "9996",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_IGN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559931@macro@SYSCTL_DSLPCLKCFG_O_IO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_IO",
+    "location": {
+      "column": "9",
+      "line": "9997",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_IO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@559985@macro@SYSCTL_DSLPCLKCFG_O_30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_30",
+    "location": {
+      "column": "9",
+      "line": "9998",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560040@macro@SYSCTL_DSLPCLKCFG_O_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_32",
+    "location": {
+      "column": "9",
+      "line": "9999",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560099@macro@SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "location": {
+      "column": "9",
+      "line": "10000",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560253@macro@SYSCTL_DSLPCLKCFG_D_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_D_S",
+    "location": {
+      "column": "9",
+      "line": "10002",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_D_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560542@macro@SYSCTL_SYSPROP_FPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SYSPROP_FPU",
+    "location": {
+      "column": "9",
+      "line": "10009",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SYSPROP_FPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560860@macro@SYSCTL_PIOSCCAL_UTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UTEN",
+    "location": {
+      "column": "9",
+      "line": "10017",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560928@macro@SYSCTL_PIOSCCAL_CAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_CAL",
+    "location": {
+      "column": "9",
+      "line": "10018",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_CAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@560994@macro@SYSCTL_PIOSCCAL_UPDATE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UPDATE",
+    "location": {
+      "column": "9",
+      "line": "10019",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UPDATE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561054@macro@SYSCTL_PIOSCCAL_UT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UT_M",
+    "location": {
+      "column": "9",
+      "line": "10020",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561118@macro@SYSCTL_PIOSCCAL_UT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UT_S",
+    "location": {
+      "column": "9",
+      "line": "10021",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561412@macro@SYSCTL_PIOSCSTAT_DT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_DT_M",
+    "location": {
+      "column": "9",
+      "line": "10029",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_DT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561479@macro@SYSCTL_PIOSCSTAT_CR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CR_M",
+    "location": {
+      "column": "9",
+      "line": "10030",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561546@macro@SYSCTL_PIOSCSTAT_CRNONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRNONE",
+    "location": {
+      "column": "9",
+      "line": "10031",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRNONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561677@macro@SYSCTL_PIOSCSTAT_CRPASS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRPASS",
+    "location": {
+      "column": "9",
+      "line": "10033",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRPASS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561834@macro@SYSCTL_PIOSCSTAT_CRFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRFAIL",
+    "location": {
+      "column": "9",
+      "line": "10035",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@561988@macro@SYSCTL_PIOSCSTAT_CT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CT_M",
+    "location": {
+      "column": "9",
+      "line": "10037",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562059@macro@SYSCTL_PIOSCSTAT_DT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_DT_S",
+    "location": {
+      "column": "9",
+      "line": "10038",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_DT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562095@macro@SYSCTL_PIOSCSTAT_CT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CT_S",
+    "location": {
+      "column": "9",
+      "line": "10039",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562388@macro@SYSCTL_PLLFREQ0_MFRAC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MFRAC_M",
+    "location": {
+      "column": "9",
+      "line": "10047",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MFRAC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562459@macro@SYSCTL_PLLFREQ0_MINT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MINT_M",
+    "location": {
+      "column": "9",
+      "line": "10048",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MINT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562527@macro@SYSCTL_PLLFREQ0_MFRAC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MFRAC_S",
+    "location": {
+      "column": "9",
+      "line": "10049",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MFRAC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562563@macro@SYSCTL_PLLFREQ0_MINT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MINT_S",
+    "location": {
+      "column": "9",
+      "line": "10050",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MINT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562856@macro@SYSCTL_PLLFREQ1_Q_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_Q_M",
+    "location": {
+      "column": "9",
+      "line": "10058",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_Q_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562916@macro@SYSCTL_PLLFREQ1_N_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_N_M",
+    "location": {
+      "column": "9",
+      "line": "10059",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_N_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@562976@macro@SYSCTL_PLLFREQ1_Q_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_Q_S",
+    "location": {
+      "column": "9",
+      "line": "10060",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_Q_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@563011@macro@SYSCTL_PLLFREQ1_N_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_N_S",
+    "location": {
+      "column": "9",
+      "line": "10061",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_N_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@563299@macro@SYSCTL_PLLSTAT_LOCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLSTAT_LOCK",
+    "location": {
+      "column": "9",
+      "line": "10068",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PLLSTAT_LOCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@563615@macro@SYSCTL_SLPPWRCFG_FLASHPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_M",
+    "location": {
+      "column": "9",
+      "line": "10076",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@563762@macro@SYSCTL_SLPPWRCFG_FLASHPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_NRM",
+    "location": {
+      "column": "9",
+      "line": "10078",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@563903@macro@SYSCTL_SLPPWRCFG_FLASHPM_SLP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_SLP",
+    "location": {
+      "column": "9",
+      "line": "10080",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_SLP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@564047@macro@SYSCTL_SLPPWRCFG_SRAMPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_M",
+    "location": {
+      "column": "9",
+      "line": "10082",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@564193@macro@SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "location": {
+      "column": "9",
+      "line": "10084",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@564334@macro@SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "location": {
+      "column": "9",
+      "line": "10086",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@564476@macro@SYSCTL_SLPPWRCFG_SRAMPM_LP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_LP",
+    "location": {
+      "column": "9",
+      "line": "10088",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_LP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@564880@macro@SYSCTL_DSLPPWRCFG_FLASHPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_M",
+    "location": {
+      "column": "9",
+      "line": "10097",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565027@macro@SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "location": {
+      "column": "9",
+      "line": "10099",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565168@macro@SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "location": {
+      "column": "9",
+      "line": "10101",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565312@macro@SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "location": {
+      "column": "9",
+      "line": "10103",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565458@macro@SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "location": {
+      "column": "9",
+      "line": "10105",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565599@macro@SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "location": {
+      "column": "9",
+      "line": "10107",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@565741@macro@SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "location": {
+      "column": "9",
+      "line": "10109",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566134@macro@SYSCTL_DC9_ADC1DC7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC7",
+    "location": {
+      "column": "9",
+      "line": "10117",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566199@macro@SYSCTL_DC9_ADC1DC6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC6",
+    "location": {
+      "column": "9",
+      "line": "10118",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566264@macro@SYSCTL_DC9_ADC1DC5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC5",
+    "location": {
+      "column": "9",
+      "line": "10119",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566329@macro@SYSCTL_DC9_ADC1DC4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC4",
+    "location": {
+      "column": "9",
+      "line": "10120",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566394@macro@SYSCTL_DC9_ADC1DC3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC3",
+    "location": {
+      "column": "9",
+      "line": "10121",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566459@macro@SYSCTL_DC9_ADC1DC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC2",
+    "location": {
+      "column": "9",
+      "line": "10122",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566524@macro@SYSCTL_DC9_ADC1DC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC1",
+    "location": {
+      "column": "9",
+      "line": "10123",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566589@macro@SYSCTL_DC9_ADC1DC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC0",
+    "location": {
+      "column": "9",
+      "line": "10124",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566654@macro@SYSCTL_DC9_ADC0DC7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC7",
+    "location": {
+      "column": "9",
+      "line": "10125",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566719@macro@SYSCTL_DC9_ADC0DC6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC6",
+    "location": {
+      "column": "9",
+      "line": "10126",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566784@macro@SYSCTL_DC9_ADC0DC5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC5",
+    "location": {
+      "column": "9",
+      "line": "10127",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566849@macro@SYSCTL_DC9_ADC0DC4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC4",
+    "location": {
+      "column": "9",
+      "line": "10128",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566914@macro@SYSCTL_DC9_ADC0DC3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC3",
+    "location": {
+      "column": "9",
+      "line": "10129",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@566979@macro@SYSCTL_DC9_ADC0DC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC2",
+    "location": {
+      "column": "9",
+      "line": "10130",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567044@macro@SYSCTL_DC9_ADC0DC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC1",
+    "location": {
+      "column": "9",
+      "line": "10131",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567109@macro@SYSCTL_DC9_ADC0DC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC0",
+    "location": {
+      "column": "9",
+      "line": "10132",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567427@macro@SYSCTL_NVMSTAT_FWB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NVMSTAT_FWB",
+    "location": {
+      "column": "9",
+      "line": "10139",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_NVMSTAT_FWB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567818@macro@SYSCTL_LDOSPCTL_VADJEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VADJEN",
+    "location": {
+      "column": "9",
+      "line": "10148",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VADJEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567888@macro@SYSCTL_LDOSPCTL_VLDO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_M",
+    "location": {
+      "column": "9",
+      "line": "10149",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@567955@macro@SYSCTL_LDOSPCTL_VLDO_0_90V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_0_90V",
+    "location": {
+      "column": "9",
+      "line": "10150",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_0_90V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568091@macro@SYSCTL_LDOSPCTL_VLDO_0_95V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_0_95V",
+    "location": {
+      "column": "9",
+      "line": "10152",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_0_95V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568227@macro@SYSCTL_LDOSPCTL_VLDO_1_00V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_1_00V",
+    "location": {
+      "column": "9",
+      "line": "10154",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_1_00V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568363@macro@SYSCTL_LDOSPCTL_VLDO_1_05V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_1_05V",
+    "location": {
+      "column": "9",
+      "line": "10156",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_1_05V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568499@macro@SYSCTL_LDOSPCTL_VLDO_1_10V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_1_10V",
+    "location": {
+      "column": "9",
+      "line": "10158",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_1_10V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568635@macro@SYSCTL_LDOSPCTL_VLDO_1_15V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_1_15V",
+    "location": {
+      "column": "9",
+      "line": "10160",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_1_15V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@568771@macro@SYSCTL_LDOSPCTL_VLDO_1_20V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL_VLDO_1_20V",
+    "location": {
+      "column": "9",
+      "line": "10162",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDOSPCTL_VLDO_1_20V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569165@macro@SYSCTL_LDODPCTL_VADJEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VADJEN",
+    "location": {
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+      "line": "10171",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VADJEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569235@macro@SYSCTL_LDODPCTL_VLDO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_M",
+    "location": {
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+      "line": "10172",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569302@macro@SYSCTL_LDODPCTL_VLDO_0_90V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_0_90V",
+    "location": {
+      "column": "9",
+      "line": "10173",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_0_90V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569438@macro@SYSCTL_LDODPCTL_VLDO_0_95V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_0_95V",
+    "location": {
+      "column": "9",
+      "line": "10175",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_0_95V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569574@macro@SYSCTL_LDODPCTL_VLDO_1_00V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_1_00V",
+    "location": {
+      "column": "9",
+      "line": "10177",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_1_00V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569710@macro@SYSCTL_LDODPCTL_VLDO_1_05V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_1_05V",
+    "location": {
+      "column": "9",
+      "line": "10179",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_1_05V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569846@macro@SYSCTL_LDODPCTL_VLDO_1_10V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_1_10V",
+    "location": {
+      "column": "9",
+      "line": "10181",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_1_10V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@569982@macro@SYSCTL_LDODPCTL_VLDO_1_15V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_1_15V",
+    "location": {
+      "column": "9",
+      "line": "10183",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_1_15V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@570118@macro@SYSCTL_LDODPCTL_VLDO_1_20V",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL_VLDO_1_20V",
+    "location": {
+      "column": "9",
+      "line": "10185",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_LDODPCTL_VLDO_1_20V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@570504@macro@SYSCTL_PPWD_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD_P1",
+    "location": {
+      "column": "9",
+      "line": "10193",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWD_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@570577@macro@SYSCTL_PPWD_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD_P0",
+    "location": {
+      "column": "9",
+      "line": "10194",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWD_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@570903@macro@SYSCTL_PPTIMER_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P5",
+    "location": {
+      "column": "9",
+      "line": "10201",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571041@macro@SYSCTL_PPTIMER_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P4",
+    "location": {
+      "column": "9",
+      "line": "10203",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571179@macro@SYSCTL_PPTIMER_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P3",
+    "location": {
+      "column": "9",
+      "line": "10205",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571317@macro@SYSCTL_PPTIMER_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P2",
+    "location": {
+      "column": "9",
+      "line": "10207",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571455@macro@SYSCTL_PPTIMER_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P1",
+    "location": {
+      "column": "9",
+      "line": "10209",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571593@macro@SYSCTL_PPTIMER_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P0",
+    "location": {
+      "column": "9",
+      "line": "10211",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPTIMER_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@571983@macro@SYSCTL_PPGPIO_P14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P14",
+    "location": {
+      "column": "9",
+      "line": "10219",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572051@macro@SYSCTL_PPGPIO_P13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P13",
+    "location": {
+      "column": "9",
+      "line": "10220",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572119@macro@SYSCTL_PPGPIO_P12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P12",
+    "location": {
+      "column": "9",
+      "line": "10221",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572187@macro@SYSCTL_PPGPIO_P11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P11",
+    "location": {
+      "column": "9",
+      "line": "10222",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572255@macro@SYSCTL_PPGPIO_P10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P10",
+    "location": {
+      "column": "9",
+      "line": "10223",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572323@macro@SYSCTL_PPGPIO_P9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P9",
+    "location": {
+      "column": "9",
+      "line": "10224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572391@macro@SYSCTL_PPGPIO_P8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P8",
+    "location": {
+      "column": "9",
+      "line": "10225",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572459@macro@SYSCTL_PPGPIO_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P7",
+    "location": {
+      "column": "9",
+      "line": "10226",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572527@macro@SYSCTL_PPGPIO_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P6",
+    "location": {
+      "column": "9",
+      "line": "10227",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572595@macro@SYSCTL_PPGPIO_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P5",
+    "location": {
+      "column": "9",
+      "line": "10228",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572663@macro@SYSCTL_PPGPIO_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P4",
+    "location": {
+      "column": "9",
+      "line": "10229",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572731@macro@SYSCTL_PPGPIO_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P3",
+    "location": {
+      "column": "9",
+      "line": "10230",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572799@macro@SYSCTL_PPGPIO_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P2",
+    "location": {
+      "column": "9",
+      "line": "10231",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572867@macro@SYSCTL_PPGPIO_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P1",
+    "location": {
+      "column": "9",
+      "line": "10232",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@572935@macro@SYSCTL_PPGPIO_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P0",
+    "location": {
+      "column": "9",
+      "line": "10233",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPGPIO_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@573254@macro@SYSCTL_PPDMA_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPDMA_P0",
+    "location": {
+      "column": "9",
+      "line": "10240",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPDMA_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@573573@macro@SYSCTL_PPHIB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIB_P0",
+    "location": {
+      "column": "9",
+      "line": "10247",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPHIB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@573900@macro@SYSCTL_PPUART_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P7",
+    "location": {
+      "column": "9",
+      "line": "10254",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@573970@macro@SYSCTL_PPUART_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P6",
+    "location": {
+      "column": "9",
+      "line": "10255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574040@macro@SYSCTL_PPUART_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P5",
+    "location": {
+      "column": "9",
+      "line": "10256",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574110@macro@SYSCTL_PPUART_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P4",
+    "location": {
+      "column": "9",
+      "line": "10257",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574180@macro@SYSCTL_PPUART_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P3",
+    "location": {
+      "column": "9",
+      "line": "10258",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574250@macro@SYSCTL_PPUART_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P2",
+    "location": {
+      "column": "9",
+      "line": "10259",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574320@macro@SYSCTL_PPUART_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P1",
+    "location": {
+      "column": "9",
+      "line": "10260",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574390@macro@SYSCTL_PPUART_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P0",
+    "location": {
+      "column": "9",
+      "line": "10261",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUART_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574711@macro@SYSCTL_PPSSI_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P3",
+    "location": {
+      "column": "9",
+      "line": "10268",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPSSI_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574780@macro@SYSCTL_PPSSI_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P2",
+    "location": {
+      "column": "9",
+      "line": "10269",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPSSI_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574849@macro@SYSCTL_PPSSI_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P1",
+    "location": {
+      "column": "9",
+      "line": "10270",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPSSI_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@574918@macro@SYSCTL_PPSSI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P0",
+    "location": {
+      "column": "9",
+      "line": "10271",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPSSI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575238@macro@SYSCTL_PPI2C_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P5",
+    "location": {
+      "column": "9",
+      "line": "10278",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575307@macro@SYSCTL_PPI2C_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P4",
+    "location": {
+      "column": "9",
+      "line": "10279",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575376@macro@SYSCTL_PPI2C_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P3",
+    "location": {
+      "column": "9",
+      "line": "10280",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575445@macro@SYSCTL_PPI2C_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P2",
+    "location": {
+      "column": "9",
+      "line": "10281",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575514@macro@SYSCTL_PPI2C_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P1",
+    "location": {
+      "column": "9",
+      "line": "10282",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575583@macro@SYSCTL_PPI2C_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P0",
+    "location": {
+      "column": "9",
+      "line": "10283",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPI2C_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@575903@macro@SYSCTL_PPUSB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUSB_P0",
+    "location": {
+      "column": "9",
+      "line": "10290",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPUSB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@576221@macro@SYSCTL_PPCAN_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN_P1",
+    "location": {
+      "column": "9",
+      "line": "10297",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPCAN_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@576290@macro@SYSCTL_PPCAN_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN_P0",
+    "location": {
+      "column": "9",
+      "line": "10298",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPCAN_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@576610@macro@SYSCTL_PPADC_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC_P1",
+    "location": {
+      "column": "9",
+      "line": "10305",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPADC_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@576679@macro@SYSCTL_PPADC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC_P0",
+    "location": {
+      "column": "9",
+      "line": "10306",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPADC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@577000@macro@SYSCTL_PPACMP_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPACMP_P0",
+    "location": {
+      "column": "9",
+      "line": "10313",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPACMP_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@577332@macro@SYSCTL_PPPWM_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM_P1",
+    "location": {
+      "column": "9",
+      "line": "10320",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPPWM_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@577401@macro@SYSCTL_PPPWM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM_P0",
+    "location": {
+      "column": "9",
+      "line": "10321",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPPWM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@577721@macro@SYSCTL_PPQEI_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI_P1",
+    "location": {
+      "column": "9",
+      "line": "10328",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPQEI_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@577790@macro@SYSCTL_PPQEI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI_P0",
+    "location": {
+      "column": "9",
+      "line": "10329",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPQEI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@578117@macro@SYSCTL_PPEEPROM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEEPROM_P0",
+    "location": {
+      "column": "9",
+      "line": "10337",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPEEPROM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@578445@macro@SYSCTL_PPWTIMER_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P5",
+    "location": {
+      "column": "9",
+      "line": "10345",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@578588@macro@SYSCTL_PPWTIMER_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P4",
+    "location": {
+      "column": "9",
+      "line": "10347",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@578731@macro@SYSCTL_PPWTIMER_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P3",
+    "location": {
+      "column": "9",
+      "line": "10349",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@578874@macro@SYSCTL_PPWTIMER_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P2",
+    "location": {
+      "column": "9",
+      "line": "10351",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@579017@macro@SYSCTL_PPWTIMER_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P1",
+    "location": {
+      "column": "9",
+      "line": "10353",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@579160@macro@SYSCTL_PPWTIMER_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P0",
+    "location": {
+      "column": "9",
+      "line": "10355",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@579553@macro@SYSCTL_SRWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD_R1",
+    "location": {
+      "column": "9",
+      "line": "10363",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@579633@macro@SYSCTL_SRWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD_R0",
+    "location": {
+      "column": "9",
+      "line": "10364",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@579966@macro@SYSCTL_SRTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "10371",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@580111@macro@SYSCTL_SRTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "10373",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@580256@macro@SYSCTL_SRTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "10375",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@580401@macro@SYSCTL_SRTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "10377",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@580546@macro@SYSCTL_SRTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "10379",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@580691@macro@SYSCTL_SRTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "10381",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581088@macro@SYSCTL_SRGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "10389",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581163@macro@SYSCTL_SRGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "10390",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581238@macro@SYSCTL_SRGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "10391",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581313@macro@SYSCTL_SRGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "10392",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581388@macro@SYSCTL_SRGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "10393",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581463@macro@SYSCTL_SRGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "10394",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@581789@macro@SYSCTL_SRDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "10401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582115@macro@SYSCTL_SRHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "10408",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582497@macro@SYSCTL_SRUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R7",
+    "location": {
+      "column": "9",
+      "line": "10416",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582574@macro@SYSCTL_SRUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R6",
+    "location": {
+      "column": "9",
+      "line": "10417",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582651@macro@SYSCTL_SRUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R5",
+    "location": {
+      "column": "9",
+      "line": "10418",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582728@macro@SYSCTL_SRUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R4",
+    "location": {
+      "column": "9",
+      "line": "10419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582805@macro@SYSCTL_SRUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R3",
+    "location": {
+      "column": "9",
+      "line": "10420",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582882@macro@SYSCTL_SRUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R2",
+    "location": {
+      "column": "9",
+      "line": "10421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@582959@macro@SYSCTL_SRUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R1",
+    "location": {
+      "column": "9",
+      "line": "10422",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583036@macro@SYSCTL_SRUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R0",
+    "location": {
+      "column": "9",
+      "line": "10423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583364@macro@SYSCTL_SRSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "10430",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583440@macro@SYSCTL_SRSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "10431",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583516@macro@SYSCTL_SRSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "10432",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583592@macro@SYSCTL_SRSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "10433",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583919@macro@SYSCTL_SRI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "10440",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@583995@macro@SYSCTL_SRI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "10441",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@584071@macro@SYSCTL_SRI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "10442",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@584147@macro@SYSCTL_SRI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "10443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@584474@macro@SYSCTL_SRUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "10450",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@584799@macro@SYSCTL_SRCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "10457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@584875@macro@SYSCTL_SRCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "10458",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@585202@macro@SYSCTL_SRADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC_R1",
+    "location": {
+      "column": "9",
+      "line": "10465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@585278@macro@SYSCTL_SRADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC_R0",
+    "location": {
+      "column": "9",
+      "line": "10466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@585606@macro@SYSCTL_SRACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "10473",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@585995@macro@SYSCTL_SRPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "10481",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@586071@macro@SYSCTL_SRPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "10482",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@586398@macro@SYSCTL_SRQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "10489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@586474@macro@SYSCTL_SRQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "10490",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@586808@macro@SYSCTL_SREEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "10498",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SREEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587143@macro@SYSCTL_SRWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "10506",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587293@macro@SYSCTL_SRWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "10508",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587443@macro@SYSCTL_SRWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "10510",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587593@macro@SYSCTL_SRWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "10512",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587743@macro@SYSCTL_SRWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "10514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@587893@macro@SYSCTL_SRWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "10516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@588295@macro@SYSCTL_RCGCWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD_R1",
+    "location": {
+      "column": "9",
+      "line": "10524",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@588438@macro@SYSCTL_RCGCWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD_R0",
+    "location": {
+      "column": "9",
+      "line": "10526",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@588840@macro@SYSCTL_RCGCTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "10535",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@589000@macro@SYSCTL_RCGCTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "10537",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@589160@macro@SYSCTL_RCGCTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "10539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@589320@macro@SYSCTL_RCGCTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "10541",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@589480@macro@SYSCTL_RCGCTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "10543",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@589640@macro@SYSCTL_RCGCTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "10545",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590058@macro@SYSCTL_RCGCGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "10554",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590196@macro@SYSCTL_RCGCGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "10556",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590334@macro@SYSCTL_RCGCGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "10558",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590472@macro@SYSCTL_RCGCGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "10560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590610@macro@SYSCTL_RCGCGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "10562",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@590748@macro@SYSCTL_RCGCGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "10564",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@591139@macro@SYSCTL_RCGCDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "10572",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@591530@macro@SYSCTL_RCGCHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "10580",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@591933@macro@SYSCTL_RCGCUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R7",
+    "location": {
+      "column": "9",
+      "line": "10589",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592073@macro@SYSCTL_RCGCUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R6",
+    "location": {
+      "column": "9",
+      "line": "10591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592213@macro@SYSCTL_RCGCUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R5",
+    "location": {
+      "column": "9",
+      "line": "10593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592353@macro@SYSCTL_RCGCUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R4",
+    "location": {
+      "column": "9",
+      "line": "10595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592493@macro@SYSCTL_RCGCUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R3",
+    "location": {
+      "column": "9",
+      "line": "10597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592633@macro@SYSCTL_RCGCUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R2",
+    "location": {
+      "column": "9",
+      "line": "10599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592773@macro@SYSCTL_RCGCUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R1",
+    "location": {
+      "column": "9",
+      "line": "10601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@592913@macro@SYSCTL_RCGCUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R0",
+    "location": {
+      "column": "9",
+      "line": "10603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@593306@macro@SYSCTL_RCGCSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "10611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@593445@macro@SYSCTL_RCGCSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "10613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@593584@macro@SYSCTL_RCGCSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "10615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@593723@macro@SYSCTL_RCGCSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "10617",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@594115@macro@SYSCTL_RCGCI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "10625",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@594254@macro@SYSCTL_RCGCI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "10627",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@594393@macro@SYSCTL_RCGCI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "10629",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@594532@macro@SYSCTL_RCGCI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "10631",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@594924@macro@SYSCTL_RCGCUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "10639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@595314@macro@SYSCTL_RCGCCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "10647",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@595453@macro@SYSCTL_RCGCCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "10649",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@595845@macro@SYSCTL_RCGCADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC_R1",
+    "location": {
+      "column": "9",
+      "line": "10657",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@595984@macro@SYSCTL_RCGCADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC_R0",
+    "location": {
+      "column": "9",
+      "line": "10659",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@596381@macro@SYSCTL_RCGCACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "10668",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@596787@macro@SYSCTL_RCGCPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "10676",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@596926@macro@SYSCTL_RCGCPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "10678",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@597318@macro@SYSCTL_RCGCQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "10686",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@597457@macro@SYSCTL_RCGCQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "10688",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@597856@macro@SYSCTL_RCGCEEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "10697",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCEEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@598256@macro@SYSCTL_RCGCWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "10706",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@598469@macro@SYSCTL_RCGCWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "10709",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@598682@macro@SYSCTL_RCGCWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "10712",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@598895@macro@SYSCTL_RCGCWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "10715",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@599108@macro@SYSCTL_RCGCWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "10718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@599321@macro@SYSCTL_RCGCWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "10721",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@599786@macro@SYSCTL_SCGCWD_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD_S1",
+    "location": {
+      "column": "9",
+      "line": "10730",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWD_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@599931@macro@SYSCTL_SCGCWD_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD_S0",
+    "location": {
+      "column": "9",
+      "line": "10732",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWD_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@600335@macro@SYSCTL_SCGCTIMER_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S5",
+    "location": {
+      "column": "9",
+      "line": "10741",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@600545@macro@SYSCTL_SCGCTIMER_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S4",
+    "location": {
+      "column": "9",
+      "line": "10744",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@600755@macro@SYSCTL_SCGCTIMER_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S3",
+    "location": {
+      "column": "9",
+      "line": "10747",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@600965@macro@SYSCTL_SCGCTIMER_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S2",
+    "location": {
+      "column": "9",
+      "line": "10750",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@601175@macro@SYSCTL_SCGCTIMER_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S1",
+    "location": {
+      "column": "9",
+      "line": "10753",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@601385@macro@SYSCTL_SCGCTIMER_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S0",
+    "location": {
+      "column": "9",
+      "line": "10756",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@601853@macro@SYSCTL_SCGCGPIO_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S5",
+    "location": {
+      "column": "9",
+      "line": "10766",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@601993@macro@SYSCTL_SCGCGPIO_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S4",
+    "location": {
+      "column": "9",
+      "line": "10768",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@602133@macro@SYSCTL_SCGCGPIO_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S3",
+    "location": {
+      "column": "9",
+      "line": "10770",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@602273@macro@SYSCTL_SCGCGPIO_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S2",
+    "location": {
+      "column": "9",
+      "line": "10772",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@602413@macro@SYSCTL_SCGCGPIO_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S1",
+    "location": {
+      "column": "9",
+      "line": "10774",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@602553@macro@SYSCTL_SCGCGPIO_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S0",
+    "location": {
+      "column": "9",
+      "line": "10776",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@602946@macro@SYSCTL_SCGCDMA_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCDMA_S0",
+    "location": {
+      "column": "9",
+      "line": "10784",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCDMA_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@603339@macro@SYSCTL_SCGCHIB_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCHIB_S0",
+    "location": {
+      "column": "9",
+      "line": "10792",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCHIB_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@603744@macro@SYSCTL_SCGCUART_S7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S7",
+    "location": {
+      "column": "9",
+      "line": "10801",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@603886@macro@SYSCTL_SCGCUART_S6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S6",
+    "location": {
+      "column": "9",
+      "line": "10803",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604028@macro@SYSCTL_SCGCUART_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S5",
+    "location": {
+      "column": "9",
+      "line": "10805",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604170@macro@SYSCTL_SCGCUART_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S4",
+    "location": {
+      "column": "9",
+      "line": "10807",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604312@macro@SYSCTL_SCGCUART_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S3",
+    "location": {
+      "column": "9",
+      "line": "10809",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604454@macro@SYSCTL_SCGCUART_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S2",
+    "location": {
+      "column": "9",
+      "line": "10811",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604596@macro@SYSCTL_SCGCUART_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S1",
+    "location": {
+      "column": "9",
+      "line": "10813",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@604738@macro@SYSCTL_SCGCUART_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S0",
+    "location": {
+      "column": "9",
+      "line": "10815",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUART_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@605133@macro@SYSCTL_SCGCSSI_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S3",
+    "location": {
+      "column": "9",
+      "line": "10823",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@605274@macro@SYSCTL_SCGCSSI_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S2",
+    "location": {
+      "column": "9",
+      "line": "10825",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@605415@macro@SYSCTL_SCGCSSI_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S1",
+    "location": {
+      "column": "9",
+      "line": "10827",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@605556@macro@SYSCTL_SCGCSSI_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S0",
+    "location": {
+      "column": "9",
+      "line": "10829",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@605950@macro@SYSCTL_SCGCI2C_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S3",
+    "location": {
+      "column": "9",
+      "line": "10837",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@606091@macro@SYSCTL_SCGCI2C_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S2",
+    "location": {
+      "column": "9",
+      "line": "10839",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@606232@macro@SYSCTL_SCGCI2C_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S1",
+    "location": {
+      "column": "9",
+      "line": "10841",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@606373@macro@SYSCTL_SCGCI2C_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S0",
+    "location": {
+      "column": "9",
+      "line": "10843",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@606767@macro@SYSCTL_SCGCUSB_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUSB_S0",
+    "location": {
+      "column": "9",
+      "line": "10851",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCUSB_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@607159@macro@SYSCTL_SCGCCAN_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN_S1",
+    "location": {
+      "column": "9",
+      "line": "10859",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCCAN_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@607300@macro@SYSCTL_SCGCCAN_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN_S0",
+    "location": {
+      "column": "9",
+      "line": "10861",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCCAN_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@607694@macro@SYSCTL_SCGCADC_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC_S1",
+    "location": {
+      "column": "9",
+      "line": "10869",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCADC_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@607835@macro@SYSCTL_SCGCADC_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC_S0",
+    "location": {
+      "column": "9",
+      "line": "10871",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCADC_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@608234@macro@SYSCTL_SCGCACMP_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCACMP_S0",
+    "location": {
+      "column": "9",
+      "line": "10880",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCACMP_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@608642@macro@SYSCTL_SCGCPWM_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM_S1",
+    "location": {
+      "column": "9",
+      "line": "10888",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCPWM_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@608783@macro@SYSCTL_SCGCPWM_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM_S0",
+    "location": {
+      "column": "9",
+      "line": "10890",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCPWM_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@609177@macro@SYSCTL_SCGCQEI_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI_S1",
+    "location": {
+      "column": "9",
+      "line": "10898",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCQEI_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@609318@macro@SYSCTL_SCGCQEI_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI_S0",
+    "location": {
+      "column": "9",
+      "line": "10900",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCQEI_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@609719@macro@SYSCTL_SCGCEEPROM_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEEPROM_S0",
+    "location": {
+      "column": "9",
+      "line": "10909",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCEEPROM_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@610121@macro@SYSCTL_SCGCWTIMER_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S5",
+    "location": {
+      "column": "9",
+      "line": "10918",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@610336@macro@SYSCTL_SCGCWTIMER_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S4",
+    "location": {
+      "column": "9",
+      "line": "10921",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@610551@macro@SYSCTL_SCGCWTIMER_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S3",
+    "location": {
+      "column": "9",
+      "line": "10924",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@610766@macro@SYSCTL_SCGCWTIMER_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S2",
+    "location": {
+      "column": "9",
+      "line": "10927",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@610981@macro@SYSCTL_SCGCWTIMER_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S1",
+    "location": {
+      "column": "9",
+      "line": "10930",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@611196@macro@SYSCTL_SCGCWTIMER_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S0",
+    "location": {
+      "column": "9",
+      "line": "10933",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@611663@macro@SYSCTL_DCGCWD_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD_D1",
+    "location": {
+      "column": "9",
+      "line": "10942",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWD_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@611813@macro@SYSCTL_DCGCWD_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD_D0",
+    "location": {
+      "column": "9",
+      "line": "10944",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWD_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@612222@macro@SYSCTL_DCGCTIMER_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D5",
+    "location": {
+      "column": "9",
+      "line": "10953",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@612437@macro@SYSCTL_DCGCTIMER_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D4",
+    "location": {
+      "column": "9",
+      "line": "10956",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@612652@macro@SYSCTL_DCGCTIMER_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D3",
+    "location": {
+      "column": "9",
+      "line": "10959",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@612867@macro@SYSCTL_DCGCTIMER_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D2",
+    "location": {
+      "column": "9",
+      "line": "10962",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@613082@macro@SYSCTL_DCGCTIMER_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D1",
+    "location": {
+      "column": "9",
+      "line": "10965",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@613297@macro@SYSCTL_DCGCTIMER_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D0",
+    "location": {
+      "column": "9",
+      "line": "10968",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@613770@macro@SYSCTL_DCGCGPIO_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D5",
+    "location": {
+      "column": "9",
+      "line": "10978",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@613915@macro@SYSCTL_DCGCGPIO_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D4",
+    "location": {
+      "column": "9",
+      "line": "10980",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@614060@macro@SYSCTL_DCGCGPIO_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D3",
+    "location": {
+      "column": "9",
+      "line": "10982",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@614205@macro@SYSCTL_DCGCGPIO_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D2",
+    "location": {
+      "column": "9",
+      "line": "10984",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@614350@macro@SYSCTL_DCGCGPIO_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D1",
+    "location": {
+      "column": "9",
+      "line": "10986",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@614495@macro@SYSCTL_DCGCGPIO_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D0",
+    "location": {
+      "column": "9",
+      "line": "10988",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@614893@macro@SYSCTL_DCGCDMA_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCDMA_D0",
+    "location": {
+      "column": "9",
+      "line": "10996",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCDMA_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@615291@macro@SYSCTL_DCGCHIB_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCHIB_D0",
+    "location": {
+      "column": "9",
+      "line": "11004",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCHIB_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@615701@macro@SYSCTL_DCGCUART_D7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D7",
+    "location": {
+      "column": "9",
+      "line": "11013",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@615848@macro@SYSCTL_DCGCUART_D6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D6",
+    "location": {
+      "column": "9",
+      "line": "11015",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@615995@macro@SYSCTL_DCGCUART_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D5",
+    "location": {
+      "column": "9",
+      "line": "11017",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@616142@macro@SYSCTL_DCGCUART_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D4",
+    "location": {
+      "column": "9",
+      "line": "11019",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@616289@macro@SYSCTL_DCGCUART_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D3",
+    "location": {
+      "column": "9",
+      "line": "11021",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@616436@macro@SYSCTL_DCGCUART_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D2",
+    "location": {
+      "column": "9",
+      "line": "11023",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@616583@macro@SYSCTL_DCGCUART_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D1",
+    "location": {
+      "column": "9",
+      "line": "11025",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@616730@macro@SYSCTL_DCGCUART_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D0",
+    "location": {
+      "column": "9",
+      "line": "11027",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUART_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@617130@macro@SYSCTL_DCGCSSI_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D3",
+    "location": {
+      "column": "9",
+      "line": "11035",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@617276@macro@SYSCTL_DCGCSSI_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D2",
+    "location": {
+      "column": "9",
+      "line": "11037",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@617422@macro@SYSCTL_DCGCSSI_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D1",
+    "location": {
+      "column": "9",
+      "line": "11039",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@617568@macro@SYSCTL_DCGCSSI_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D0",
+    "location": {
+      "column": "9",
+      "line": "11041",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@617967@macro@SYSCTL_DCGCI2C_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D3",
+    "location": {
+      "column": "9",
+      "line": "11049",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@618113@macro@SYSCTL_DCGCI2C_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D2",
+    "location": {
+      "column": "9",
+      "line": "11051",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@618259@macro@SYSCTL_DCGCI2C_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D1",
+    "location": {
+      "column": "9",
+      "line": "11053",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@618405@macro@SYSCTL_DCGCI2C_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D0",
+    "location": {
+      "column": "9",
+      "line": "11055",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@618804@macro@SYSCTL_DCGCUSB_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUSB_D0",
+    "location": {
+      "column": "9",
+      "line": "11063",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCUSB_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@619201@macro@SYSCTL_DCGCCAN_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN_D1",
+    "location": {
+      "column": "9",
+      "line": "11071",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCCAN_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@619347@macro@SYSCTL_DCGCCAN_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN_D0",
+    "location": {
+      "column": "9",
+      "line": "11073",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCCAN_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@619746@macro@SYSCTL_DCGCADC_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC_D1",
+    "location": {
+      "column": "9",
+      "line": "11081",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCADC_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@619892@macro@SYSCTL_DCGCADC_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC_D0",
+    "location": {
+      "column": "9",
+      "line": "11083",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCADC_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@620296@macro@SYSCTL_DCGCACMP_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCACMP_D0",
+    "location": {
+      "column": "9",
+      "line": "11092",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCACMP_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@620757@macro@SYSCTL_DCGCPWM_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM_D1",
+    "location": {
+      "column": "9",
+      "line": "11101",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCPWM_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@620903@macro@SYSCTL_DCGCPWM_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM_D0",
+    "location": {
+      "column": "9",
+      "line": "11103",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCPWM_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@621302@macro@SYSCTL_DCGCQEI_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI_D1",
+    "location": {
+      "column": "9",
+      "line": "11111",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCQEI_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@621448@macro@SYSCTL_DCGCQEI_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI_D0",
+    "location": {
+      "column": "9",
+      "line": "11113",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCQEI_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@621854@macro@SYSCTL_DCGCEEPROM_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEEPROM_D0",
+    "location": {
+      "column": "9",
+      "line": "11122",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCEEPROM_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@622261@macro@SYSCTL_DCGCWTIMER_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D5",
+    "location": {
+      "column": "9",
+      "line": "11131",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@622481@macro@SYSCTL_DCGCWTIMER_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D4",
+    "location": {
+      "column": "9",
+      "line": "11134",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@622701@macro@SYSCTL_DCGCWTIMER_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D3",
+    "location": {
+      "column": "9",
+      "line": "11137",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@622921@macro@SYSCTL_DCGCWTIMER_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D2",
+    "location": {
+      "column": "9",
+      "line": "11140",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@623141@macro@SYSCTL_DCGCWTIMER_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D1",
+    "location": {
+      "column": "9",
+      "line": "11143",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@623361@macro@SYSCTL_DCGCWTIMER_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D0",
+    "location": {
+      "column": "9",
+      "line": "11146",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@623831@macro@SYSCTL_PRWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD_R1",
+    "location": {
+      "column": "9",
+      "line": "11155",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@623961@macro@SYSCTL_PRWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD_R0",
+    "location": {
+      "column": "9",
+      "line": "11157",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@624344@macro@SYSCTL_PRTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "11165",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@624491@macro@SYSCTL_PRTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "11167",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@624638@macro@SYSCTL_PRTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "11169",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@624785@macro@SYSCTL_PRTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "11171",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@624932@macro@SYSCTL_PRTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "11173",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625079@macro@SYSCTL_PRTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "11175",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625478@macro@SYSCTL_PRGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "11183",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625555@macro@SYSCTL_PRGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "11184",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625632@macro@SYSCTL_PRGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "11185",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625709@macro@SYSCTL_PRGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "11186",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625786@macro@SYSCTL_PRGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "11187",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@625863@macro@SYSCTL_PRGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "11188",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@626191@macro@SYSCTL_PRDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "11195",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@626519@macro@SYSCTL_PRHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "11202",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@626903@macro@SYSCTL_PRUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R7",
+    "location": {
+      "column": "9",
+      "line": "11210",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@626982@macro@SYSCTL_PRUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R6",
+    "location": {
+      "column": "9",
+      "line": "11211",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627061@macro@SYSCTL_PRUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R5",
+    "location": {
+      "column": "9",
+      "line": "11212",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627140@macro@SYSCTL_PRUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R4",
+    "location": {
+      "column": "9",
+      "line": "11213",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627219@macro@SYSCTL_PRUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R3",
+    "location": {
+      "column": "9",
+      "line": "11214",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627298@macro@SYSCTL_PRUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R2",
+    "location": {
+      "column": "9",
+      "line": "11215",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627377@macro@SYSCTL_PRUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R1",
+    "location": {
+      "column": "9",
+      "line": "11216",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627456@macro@SYSCTL_PRUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R0",
+    "location": {
+      "column": "9",
+      "line": "11217",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627786@macro@SYSCTL_PRSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "11224",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627864@macro@SYSCTL_PRSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "11225",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@627942@macro@SYSCTL_PRSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "11226",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628020@macro@SYSCTL_PRSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "11227",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628349@macro@SYSCTL_PRI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "11234",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628427@macro@SYSCTL_PRI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "11235",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628505@macro@SYSCTL_PRI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "11236",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628583@macro@SYSCTL_PRI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "11237",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@628912@macro@SYSCTL_PRUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "11244",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@629239@macro@SYSCTL_PRCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "11251",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@629317@macro@SYSCTL_PRCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "11252",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@629646@macro@SYSCTL_PRADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC_R1",
+    "location": {
+      "column": "9",
+      "line": "11259",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@629724@macro@SYSCTL_PRADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC_R0",
+    "location": {
+      "column": "9",
+      "line": "11260",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@630054@macro@SYSCTL_PRACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "11267",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@630445@macro@SYSCTL_PRPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "11275",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@630523@macro@SYSCTL_PRPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "11276",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@630852@macro@SYSCTL_PRQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "11283",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@630930@macro@SYSCTL_PRQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "11284",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@631266@macro@SYSCTL_PREEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "11292",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PREEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@631603@macro@SYSCTL_PRWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "11300",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@631755@macro@SYSCTL_PRWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "11302",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@631907@macro@SYSCTL_PRWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "11304",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632059@macro@SYSCTL_PRWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "11306",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632211@macro@SYSCTL_PRWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "11308",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632363@macro@SYSCTL_PRWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "11310",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632763@macro@UDMA_STAT_DMACHANS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_DMACHANS_M",
+    "location": {
+      "column": "9",
+      "line": "11318",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_DMACHANS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632843@macro@UDMA_STAT_STATE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_M",
+    "location": {
+      "column": "9",
+      "line": "11319",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632920@macro@UDMA_STAT_STATE_IDLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_IDLE",
+    "location": {
+      "column": "9",
+      "line": "11320",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_IDLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@632973@macro@UDMA_STAT_STATE_RD_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_RD_CTRL",
+    "location": {
+      "column": "9",
+      "line": "11321",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_RD_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633053@macro@UDMA_STAT_STATE_RD_SRCENDP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_RD_SRCENDP",
+    "location": {
+      "column": "9",
+      "line": "11322",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_RD_SRCENDP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633209@macro@UDMA_STAT_STATE_RD_DSTENDP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_RD_DSTENDP",
+    "location": {
+      "column": "9",
+      "line": "11324",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_RD_DSTENDP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633370@macro@UDMA_STAT_STATE_RD_SRCDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_RD_SRCDAT",
+    "location": {
+      "column": "9",
+      "line": "11326",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_RD_SRCDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633519@macro@UDMA_STAT_STATE_WR_DSTDAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_WR_DSTDAT",
+    "location": {
+      "column": "9",
+      "line": "11328",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_WR_DSTDAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633673@macro@UDMA_STAT_STATE_WAIT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_WAIT",
+    "location": {
+      "column": "9",
+      "line": "11330",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_WAIT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633803@macro@UDMA_STAT_STATE_WR_CTRL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_WR_CTRL",
+    "location": {
+      "column": "9",
+      "line": "11332",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_WR_CTRL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633883@macro@UDMA_STAT_STATE_STALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_STALL",
+    "location": {
+      "column": "9",
+      "line": "11333",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_STALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633939@macro@UDMA_STAT_STATE_DONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_DONE",
+    "location": {
+      "column": "9",
+      "line": "11334",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_DONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@633992@macro@UDMA_STAT_STATE_UNDEF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_STATE_UNDEF",
+    "location": {
+      "column": "9",
+      "line": "11335",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_STATE_UNDEF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@634050@macro@UDMA_STAT_MASTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_MASTEN",
+    "location": {
+      "column": "9",
+      "line": "11336",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_MASTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@634119@macro@UDMA_STAT_DMACHANS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_STAT_DMACHANS_S",
+    "location": {
+      "column": "9",
+      "line": "11337",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_STAT_DMACHANS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@634402@macro@UDMA_CFG_MASTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CFG_MASTEN",
+    "location": {
+      "column": "9",
+      "line": "11344",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CFG_MASTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@634726@macro@UDMA_CTLBASE_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CTLBASE_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "11351",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CTLBASE_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@634803@macro@UDMA_CTLBASE_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CTLBASE_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "11352",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CTLBASE_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@635090@macro@UDMA_ALTBASE_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTBASE_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "11359",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTBASE_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@635220@macro@UDMA_ALTBASE_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTBASE_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "11361",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTBASE_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@635507@macro@UDMA_WAITSTAT_WAITREQ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_WAITSTAT_WAITREQ_M",
+    "location": {
+      "column": "9",
+      "line": "11368",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_WAITSTAT_WAITREQ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@635828@macro@UDMA_SWREQ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_SWREQ_M",
+    "location": {
+      "column": "9",
+      "line": "11375",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_SWREQ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@636164@macro@UDMA_USEBURSTSET_SET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_USEBURSTSET_SET_M",
+    "location": {
+      "column": "9",
+      "line": "11383",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_USEBURSTSET_SET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@636496@macro@UDMA_USEBURSTCLR_CLR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_USEBURSTCLR_CLR_M",
+    "location": {
+      "column": "9",
+      "line": "11391",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_USEBURSTCLR_CLR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@636829@macro@UDMA_REQMASKSET_SET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_REQMASKSET_SET_M",
+    "location": {
+      "column": "9",
+      "line": "11399",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_REQMASKSET_SET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@637164@macro@UDMA_REQMASKCLR_CLR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_REQMASKCLR_CLR_M",
+    "location": {
+      "column": "9",
+      "line": "11407",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_REQMASKCLR_CLR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@637493@macro@UDMA_ENASET_SET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ENASET_SET_M",
+    "location": {
+      "column": "9",
+      "line": "11414",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ENASET_SET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@637814@macro@UDMA_ENACLR_CLR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ENACLR_CLR_M",
+    "location": {
+      "column": "9",
+      "line": "11421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ENACLR_CLR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@638143@macro@UDMA_ALTSET_SET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTSET_SET_M",
+    "location": {
+      "column": "9",
+      "line": "11428",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTSET_SET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@638467@macro@UDMA_ALTCLR_CLR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ALTCLR_CLR_M",
+    "location": {
+      "column": "9",
+      "line": "11435",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ALTCLR_CLR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@638794@macro@UDMA_PRIOSET_SET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_PRIOSET_SET_M",
+    "location": {
+      "column": "9",
+      "line": "11442",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_PRIOSET_SET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@639118@macro@UDMA_PRIOCLR_CLR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_PRIOCLR_CLR_M",
+    "location": {
+      "column": "9",
+      "line": "11449",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_PRIOCLR_CLR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@639443@macro@UDMA_ERRCLR_ERRCLR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_ERRCLR_ERRCLR",
+    "location": {
+      "column": "9",
+      "line": "11456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_ERRCLR_ERRCLR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@639763@macro@UDMA_CHASGN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHASGN_M",
+    "location": {
+      "column": "9",
+      "line": "11463",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHASGN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@639841@macro@UDMA_CHASGN_PRIMARY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHASGN_PRIMARY",
+    "location": {
+      "column": "9",
+      "line": "11464",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHASGN_PRIMARY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@639972@macro@UDMA_CHASGN_SECONDARY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHASGN_SECONDARY",
+    "location": {
+      "column": "9",
+      "line": "11466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHASGN_SECONDARY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640353@macro@UDMA_CHIS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHIS_M",
+    "location": {
+      "column": "9",
+      "line": "11474",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHIS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640680@macro@UDMA_CHMAP0_CH7SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH7SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11481",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH7SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640757@macro@UDMA_CHMAP0_CH6SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH6SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11482",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH6SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640834@macro@UDMA_CHMAP0_CH5SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH5SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11483",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH5SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640911@macro@UDMA_CHMAP0_CH4SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH4SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11484",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH4SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@640988@macro@UDMA_CHMAP0_CH3SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH3SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11485",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH3SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641065@macro@UDMA_CHMAP0_CH2SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH2SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11486",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH2SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641142@macro@UDMA_CHMAP0_CH1SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH1SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH1SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641219@macro@UDMA_CHMAP0_CH0SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH0SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11488",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH0SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641296@macro@UDMA_CHMAP0_CH7SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH7SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH7SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641332@macro@UDMA_CHMAP0_CH6SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH6SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11490",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH6SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641368@macro@UDMA_CHMAP0_CH5SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH5SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11491",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH5SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641404@macro@UDMA_CHMAP0_CH4SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH4SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11492",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH4SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641440@macro@UDMA_CHMAP0_CH3SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH3SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11493",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH3SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641476@macro@UDMA_CHMAP0_CH2SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH2SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11494",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH2SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641511@macro@UDMA_CHMAP0_CH1SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH1SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11495",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP0_CH1SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641546@macro@UDMA_CHMAP0_CH0SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP0_CH0SEL_S",
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+      "line": "11496",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641831@macro@UDMA_CHMAP1_CH15SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH15SEL_M",
+    "location": {
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+      "line": "11503",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH15SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641909@macro@UDMA_CHMAP1_CH14SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH14SEL_M",
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+      "line": "11504",
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+    },
+    "name": "UDMA_CHMAP1_CH14SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@641987@macro@UDMA_CHMAP1_CH13SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH13SEL_M",
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+      "line": "11505",
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+    },
+    "name": "UDMA_CHMAP1_CH13SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642065@macro@UDMA_CHMAP1_CH12SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH12SEL_M",
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+      "line": "11506",
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+    },
+    "name": "UDMA_CHMAP1_CH12SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642143@macro@UDMA_CHMAP1_CH11SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH11SEL_M",
+    "location": {
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+      "line": "11507",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH11SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642221@macro@UDMA_CHMAP1_CH10SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH10SEL_M",
+    "location": {
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+      "line": "11508",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH10SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642299@macro@UDMA_CHMAP1_CH9SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH9SEL_M",
+    "location": {
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+      "line": "11509",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH9SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642376@macro@UDMA_CHMAP1_CH8SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH8SEL_M",
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+      "line": "11510",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH8SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642453@macro@UDMA_CHMAP1_CH15SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH15SEL_S",
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+      "line": "11511",
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+    },
+    "name": "UDMA_CHMAP1_CH15SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642489@macro@UDMA_CHMAP1_CH14SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH14SEL_S",
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+      "line": "11512",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH14SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642525@macro@UDMA_CHMAP1_CH13SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH13SEL_S",
+    "location": {
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+      "line": "11513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH13SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642561@macro@UDMA_CHMAP1_CH12SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH12SEL_S",
+    "location": {
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+      "line": "11514",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH12SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642597@macro@UDMA_CHMAP1_CH11SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH11SEL_S",
+    "location": {
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+      "line": "11515",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH11SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642633@macro@UDMA_CHMAP1_CH10SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH10SEL_S",
+    "location": {
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+      "line": "11516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH10SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642668@macro@UDMA_CHMAP1_CH9SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH9SEL_S",
+    "location": {
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+      "line": "11517",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH9SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642703@macro@UDMA_CHMAP1_CH8SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP1_CH8SEL_S",
+    "location": {
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+      "line": "11518",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP1_CH8SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@642988@macro@UDMA_CHMAP2_CH23SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH23SEL_M",
+    "location": {
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+      "line": "11525",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH23SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643066@macro@UDMA_CHMAP2_CH22SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH22SEL_M",
+    "location": {
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+      "line": "11526",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH22SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643144@macro@UDMA_CHMAP2_CH21SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH21SEL_M",
+    "location": {
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+      "line": "11527",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH21SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643222@macro@UDMA_CHMAP2_CH20SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH20SEL_M",
+    "location": {
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+      "line": "11528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH20SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643300@macro@UDMA_CHMAP2_CH19SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH19SEL_M",
+    "location": {
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+      "line": "11529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH19SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643378@macro@UDMA_CHMAP2_CH18SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH18SEL_M",
+    "location": {
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+      "line": "11530",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH18SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643456@macro@UDMA_CHMAP2_CH17SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH17SEL_M",
+    "location": {
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+      "line": "11531",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH17SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643534@macro@UDMA_CHMAP2_CH16SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH16SEL_M",
+    "location": {
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+      "line": "11532",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH16SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643612@macro@UDMA_CHMAP2_CH23SEL_S",
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+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH23SEL_S",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH23SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643648@macro@UDMA_CHMAP2_CH22SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH22SEL_S",
+    "location": {
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+      "line": "11534",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH22SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643684@macro@UDMA_CHMAP2_CH21SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH21SEL_S",
+    "location": {
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+      "line": "11535",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH21SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643720@macro@UDMA_CHMAP2_CH20SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH20SEL_S",
+    "location": {
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+      "line": "11536",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH20SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643756@macro@UDMA_CHMAP2_CH19SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH19SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11537",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH19SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643792@macro@UDMA_CHMAP2_CH18SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH18SEL_S",
+    "location": {
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+      "line": "11538",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH18SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643827@macro@UDMA_CHMAP2_CH17SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH17SEL_S",
+    "location": {
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+      "line": "11539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH17SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@643862@macro@UDMA_CHMAP2_CH16SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP2_CH16SEL_S",
+    "location": {
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+      "line": "11540",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP2_CH16SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644147@macro@UDMA_CHMAP3_CH31SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH31SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11547",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH31SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644225@macro@UDMA_CHMAP3_CH30SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH30SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11548",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH30SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644303@macro@UDMA_CHMAP3_CH29SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH29SEL_M",
+    "location": {
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+      "line": "11549",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH29SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644381@macro@UDMA_CHMAP3_CH28SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH28SEL_M",
+    "location": {
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+      "line": "11550",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH28SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644459@macro@UDMA_CHMAP3_CH27SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH27SEL_M",
+    "location": {
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+      "line": "11551",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH27SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644537@macro@UDMA_CHMAP3_CH26SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH26SEL_M",
+    "location": {
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+      "line": "11552",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH26SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644615@macro@UDMA_CHMAP3_CH25SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH25SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11553",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH25SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644693@macro@UDMA_CHMAP3_CH24SEL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH24SEL_M",
+    "location": {
+      "column": "9",
+      "line": "11554",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH24SEL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644771@macro@UDMA_CHMAP3_CH31SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH31SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11555",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH31SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644807@macro@UDMA_CHMAP3_CH30SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH30SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11556",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH30SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644843@macro@UDMA_CHMAP3_CH29SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH29SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11557",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH29SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644879@macro@UDMA_CHMAP3_CH28SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH28SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11558",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH28SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644915@macro@UDMA_CHMAP3_CH27SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH27SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11559",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH27SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644951@macro@UDMA_CHMAP3_CH26SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH26SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH26SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@644986@macro@UDMA_CHMAP3_CH25SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH25SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH25SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@645021@macro@UDMA_CHMAP3_CH24SEL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHMAP3_CH24SEL_S",
+    "location": {
+      "column": "9",
+      "line": "11562",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHMAP3_CH24SEL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@645309@macro@UDMA_SRCENDP_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_SRCENDP_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "11569",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_SRCENDP_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@645384@macro@UDMA_SRCENDP_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_SRCENDP_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "11570",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_SRCENDP_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@645672@macro@UDMA_DSTENDP_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_DSTENDP_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "11577",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_DSTENDP_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@645752@macro@UDMA_DSTENDP_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_DSTENDP_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "11578",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_DSTENDP_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646038@macro@UDMA_CHCTL_DSTINC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTINC_M",
+    "location": {
+      "column": "9",
+      "line": "11585",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTINC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646116@macro@UDMA_CHCTL_DSTINC_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTINC_8",
+    "location": {
+      "column": "9",
+      "line": "11586",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTINC_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646169@macro@UDMA_CHCTL_DSTINC_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTINC_16",
+    "location": {
+      "column": "9",
+      "line": "11587",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTINC_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646227@macro@UDMA_CHCTL_DSTINC_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTINC_32",
+    "location": {
+      "column": "9",
+      "line": "11588",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTINC_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646280@macro@UDMA_CHCTL_DSTINC_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTINC_NONE",
+    "location": {
+      "column": "9",
+      "line": "11589",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTINC_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646341@macro@UDMA_CHCTL_DSTSIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTSIZE_M",
+    "location": {
+      "column": "9",
+      "line": "11590",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTSIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646411@macro@UDMA_CHCTL_DSTSIZE_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTSIZE_8",
+    "location": {
+      "column": "9",
+      "line": "11591",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTSIZE_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646464@macro@UDMA_CHCTL_DSTSIZE_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTSIZE_16",
+    "location": {
+      "column": "9",
+      "line": "11592",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTSIZE_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646522@macro@UDMA_CHCTL_DSTSIZE_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_DSTSIZE_32",
+    "location": {
+      "column": "9",
+      "line": "11593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_DSTSIZE_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646575@macro@UDMA_CHCTL_SRCINC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCINC_M",
+    "location": {
+      "column": "9",
+      "line": "11594",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCINC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646648@macro@UDMA_CHCTL_SRCINC_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCINC_8",
+    "location": {
+      "column": "9",
+      "line": "11595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCINC_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646701@macro@UDMA_CHCTL_SRCINC_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCINC_16",
+    "location": {
+      "column": "9",
+      "line": "11596",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCINC_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646759@macro@UDMA_CHCTL_SRCINC_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCINC_32",
+    "location": {
+      "column": "9",
+      "line": "11597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCINC_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646812@macro@UDMA_CHCTL_SRCINC_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCINC_NONE",
+    "location": {
+      "column": "9",
+      "line": "11598",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCINC_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646873@macro@UDMA_CHCTL_SRCSIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCSIZE_M",
+    "location": {
+      "column": "9",
+      "line": "11599",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCSIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646938@macro@UDMA_CHCTL_SRCSIZE_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCSIZE_8",
+    "location": {
+      "column": "9",
+      "line": "11600",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCSIZE_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@646991@macro@UDMA_CHCTL_SRCSIZE_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCSIZE_16",
+    "location": {
+      "column": "9",
+      "line": "11601",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCSIZE_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647049@macro@UDMA_CHCTL_SRCSIZE_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_SRCSIZE_32",
+    "location": {
+      "column": "9",
+      "line": "11602",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_SRCSIZE_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647102@macro@UDMA_CHCTL_ARBSIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_M",
+    "location": {
+      "column": "9",
+      "line": "11603",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647167@macro@UDMA_CHCTL_ARBSIZE_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_1",
+    "location": {
+      "column": "9",
+      "line": "11604",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647226@macro@UDMA_CHCTL_ARBSIZE_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_2",
+    "location": {
+      "column": "9",
+      "line": "11605",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647286@macro@UDMA_CHCTL_ARBSIZE_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_4",
+    "location": {
+      "column": "9",
+      "line": "11606",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647346@macro@UDMA_CHCTL_ARBSIZE_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_8",
+    "location": {
+      "column": "9",
+      "line": "11607",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647406@macro@UDMA_CHCTL_ARBSIZE_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_16",
+    "location": {
+      "column": "9",
+      "line": "11608",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647467@macro@UDMA_CHCTL_ARBSIZE_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_32",
+    "location": {
+      "column": "9",
+      "line": "11609",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647528@macro@UDMA_CHCTL_ARBSIZE_64",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_64",
+    "location": {
+      "column": "9",
+      "line": "11610",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647589@macro@UDMA_CHCTL_ARBSIZE_128",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_128",
+    "location": {
+      "column": "9",
+      "line": "11611",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_128",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647651@macro@UDMA_CHCTL_ARBSIZE_256",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_256",
+    "location": {
+      "column": "9",
+      "line": "11612",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_256",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647713@macro@UDMA_CHCTL_ARBSIZE_512",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_512",
+    "location": {
+      "column": "9",
+      "line": "11613",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_512",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647775@macro@UDMA_CHCTL_ARBSIZE_1024",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_ARBSIZE_1024",
+    "location": {
+      "column": "9",
+      "line": "11614",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_ARBSIZE_1024",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647838@macro@UDMA_CHCTL_XFERSIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERSIZE_M",
+    "location": {
+      "column": "9",
+      "line": "11615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERSIZE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647910@macro@UDMA_CHCTL_NXTUSEBURST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_NXTUSEBURST",
+    "location": {
+      "column": "9",
+      "line": "11616",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_NXTUSEBURST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@647972@macro@UDMA_CHCTL_XFERMODE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_M",
+    "location": {
+      "column": "9",
+      "line": "11617",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648039@macro@UDMA_CHCTL_XFERMODE_STOP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_STOP",
+    "location": {
+      "column": "9",
+      "line": "11618",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_STOP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648173@macro@UDMA_CHCTL_XFERMODE_BASIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_BASIC",
+    "location": {
+      "column": "9",
+      "line": "11620",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_BASIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648308@macro@UDMA_CHCTL_XFERMODE_AUTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_AUTO",
+    "location": {
+      "column": "9",
+      "line": "11622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_AUTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648450@macro@UDMA_CHCTL_XFERMODE_PINGPONG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_PINGPONG",
+    "location": {
+      "column": "9",
+      "line": "11624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_PINGPONG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648589@macro@UDMA_CHCTL_XFERMODE_MEM_SG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_MEM_SG",
+    "location": {
+      "column": "9",
+      "line": "11626",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_MEM_SG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648740@macro@UDMA_CHCTL_XFERMODE_MEM_SGA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_MEM_SGA",
+    "location": {
+      "column": "9",
+      "line": "11628",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_MEM_SGA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@648901@macro@UDMA_CHCTL_XFERMODE_PER_SG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_PER_SG",
+    "location": {
+      "column": "9",
+      "line": "11630",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_PER_SG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649056@macro@UDMA_CHCTL_XFERMODE_PER_SGA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERMODE_PER_SGA",
+    "location": {
+      "column": "9",
+      "line": "11632",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERMODE_PER_SGA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649269@macro@UDMA_CHCTL_XFERSIZE_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "UDMA_CHCTL_XFERSIZE_S",
+    "location": {
+      "column": "9",
+      "line": "11635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "UDMA_CHCTL_XFERSIZE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649553@macro@NVIC_ACTLR_DISOOFP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ACTLR_DISOOFP",
+    "location": {
+      "column": "9",
+      "line": "11642",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ACTLR_DISOOFP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649685@macro@NVIC_ACTLR_DISFPCA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ACTLR_DISFPCA",
+    "location": {
+      "column": "9",
+      "line": "11644",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ACTLR_DISFPCA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649749@macro@NVIC_ACTLR_DISFOLD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ACTLR_DISFOLD",
+    "location": {
+      "column": "9",
+      "line": "11645",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ACTLR_DISFOLD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649816@macro@NVIC_ACTLR_DISWBUF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ACTLR_DISWBUF",
+    "location": {
+      "column": "9",
+      "line": "11646",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ACTLR_DISWBUF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@649885@macro@NVIC_ACTLR_DISMCYC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ACTLR_DISMCYC",
+    "location": {
+      "column": "9",
+      "line": "11647",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ACTLR_DISMCYC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650282@macro@NVIC_ST_CTRL_COUNT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CTRL_COUNT",
+    "location": {
+      "column": "9",
+      "line": "11655",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CTRL_COUNT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650341@macro@NVIC_ST_CTRL_CLK_SRC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CTRL_CLK_SRC",
+    "location": {
+      "column": "9",
+      "line": "11656",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CTRL_CLK_SRC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650402@macro@NVIC_ST_CTRL_INTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CTRL_INTEN",
+    "location": {
+      "column": "9",
+      "line": "11657",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CTRL_INTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650467@macro@NVIC_ST_CTRL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CTRL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "11658",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CTRL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650775@macro@NVIC_ST_RELOAD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_RELOAD_M",
+    "location": {
+      "column": "9",
+      "line": "11665",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_RELOAD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@650836@macro@NVIC_ST_RELOAD_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_RELOAD_S",
+    "location": {
+      "column": "9",
+      "line": "11666",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_RELOAD_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@651129@macro@NVIC_ST_CURRENT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CURRENT_M",
+    "location": {
+      "column": "9",
+      "line": "11674",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CURRENT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@651191@macro@NVIC_ST_CURRENT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_ST_CURRENT_S",
+    "location": {
+      "column": "9",
+      "line": "11675",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_ST_CURRENT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@651473@macro@NVIC_EN0_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_EN0_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11682",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_EN0_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@651785@macro@NVIC_EN1_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_EN1_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11689",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_EN1_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@652097@macro@NVIC_EN2_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_EN2_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11696",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_EN2_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@652409@macro@NVIC_EN3_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_EN3_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11703",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_EN3_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@652721@macro@NVIC_EN4_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_EN4_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11710",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_EN4_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@653034@macro@NVIC_DIS0_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DIS0_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11717",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DIS0_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@653348@macro@NVIC_DIS1_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DIS1_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11724",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DIS1_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@653662@macro@NVIC_DIS2_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DIS2_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11731",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DIS2_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@653976@macro@NVIC_DIS3_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DIS3_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11738",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DIS3_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@654290@macro@NVIC_DIS4_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DIS4_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11745",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DIS4_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@654605@macro@NVIC_PEND0_INT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_PEND0_INT_M",
+    "location": {
+      "column": "9",
+      "line": "11752",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_PEND0_INT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@686464@macro@NVIC_INT_CTRL_RET_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_INT_CTRL_RET_BASE",
+    "location": {
+      "column": "9",
+      "line": "12392",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_INT_CTRL_RET_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@686527@macro@NVIC_INT_CTRL_VEC_ACT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_INT_CTRL_VEC_ACT_M",
+    "location": {
+      "column": "9",
+      "line": "12393",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_INT_CTRL_VEC_ACT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@686607@macro@NVIC_INT_CTRL_VEC_ACT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_INT_CTRL_VEC_ACT_S",
+    "location": {
+      "column": "9",
+      "line": "12394",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_INT_CTRL_VEC_ACT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@686892@macro@NVIC_VTABLE_OFFSET_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_VTABLE_OFFSET_M",
+    "location": {
+      "column": "9",
+      "line": "12401",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_VTABLE_OFFSET_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@686960@macro@NVIC_VTABLE_OFFSET_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_VTABLE_OFFSET_S",
+    "location": {
+      "column": "9",
+      "line": "12402",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_VTABLE_OFFSET_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687245@macro@NVIC_APINT_VECTKEY_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_VECTKEY_M",
+    "location": {
+      "column": "9",
+      "line": "12409",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_VECTKEY_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687306@macro@NVIC_APINT_VECTKEY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_VECTKEY",
+    "location": {
+      "column": "9",
+      "line": "12410",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_VECTKEY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687365@macro@NVIC_APINT_ENDIANESS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_ENDIANESS",
+    "location": {
+      "column": "9",
+      "line": "12411",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_ENDIANESS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687428@macro@NVIC_APINT_PRIGROUP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_M",
+    "location": {
+      "column": "9",
+      "line": "12412",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687504@macro@NVIC_APINT_PRIGROUP_7_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_7_1",
+    "location": {
+      "column": "9",
+      "line": "12413",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_7_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687577@macro@NVIC_APINT_PRIGROUP_6_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_6_2",
+    "location": {
+      "column": "9",
+      "line": "12414",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_6_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687650@macro@NVIC_APINT_PRIGROUP_5_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_5_3",
+    "location": {
+      "column": "9",
+      "line": "12415",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_5_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687723@macro@NVIC_APINT_PRIGROUP_4_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_4_4",
+    "location": {
+      "column": "9",
+      "line": "12416",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_4_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687796@macro@NVIC_APINT_PRIGROUP_3_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_3_5",
+    "location": {
+      "column": "9",
+      "line": "12417",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_3_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687869@macro@NVIC_APINT_PRIGROUP_2_6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_2_6",
+    "location": {
+      "column": "9",
+      "line": "12418",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_2_6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@687942@macro@NVIC_APINT_PRIGROUP_1_7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_1_7",
+    "location": {
+      "column": "9",
+      "line": "12419",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_1_7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688015@macro@NVIC_APINT_PRIGROUP_0_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_PRIGROUP_0_8",
+    "location": {
+      "column": "9",
+      "line": "12420",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_PRIGROUP_0_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688088@macro@NVIC_APINT_SYSRESETREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_SYSRESETREQ",
+    "location": {
+      "column": "9",
+      "line": "12421",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_SYSRESETREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688157@macro@NVIC_APINT_VECT_CLR_ACT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_VECT_CLR_ACT",
+    "location": {
+      "column": "9",
+      "line": "12422",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_VECT_CLR_ACT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688230@macro@NVIC_APINT_VECT_RESET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_APINT_VECT_RESET",
+    "location": {
+      "column": "9",
+      "line": "12423",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_APINT_VECT_RESET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688543@macro@NVIC_SYS_CTRL_SEVONPEND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_CTRL_SEVONPEND",
+    "location": {
+      "column": "9",
+      "line": "12430",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_CTRL_SEVONPEND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688610@macro@NVIC_SYS_CTRL_SLEEPDEEP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_CTRL_SLEEPDEEP",
+    "location": {
+      "column": "9",
+      "line": "12431",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_CTRL_SLEEPDEEP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688676@macro@NVIC_SYS_CTRL_SLEEPEXIT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_CTRL_SLEEPEXIT",
+    "location": {
+      "column": "9",
+      "line": "12432",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_CTRL_SLEEPEXIT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@688994@macro@NVIC_CFG_CTRL_STKALIGN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_STKALIGN",
+    "location": {
+      "column": "9",
+      "line": "12439",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_STKALIGN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689125@macro@NVIC_CFG_CTRL_BFHFNMIGN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_BFHFNMIGN",
+    "location": {
+      "column": "9",
+      "line": "12441",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_BFHFNMIGN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689255@macro@NVIC_CFG_CTRL_DIV0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_DIV0",
+    "location": {
+      "column": "9",
+      "line": "12443",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_DIV0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689323@macro@NVIC_CFG_CTRL_UNALIGNED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_UNALIGNED",
+    "location": {
+      "column": "9",
+      "line": "12444",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_UNALIGNED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689396@macro@NVIC_CFG_CTRL_MAIN_PEND",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_MAIN_PEND",
+    "location": {
+      "column": "9",
+      "line": "12445",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_MAIN_PEND",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689473@macro@NVIC_CFG_CTRL_BASE_THR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CFG_CTRL_BASE_THR",
+    "location": {
+      "column": "9",
+      "line": "12446",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CFG_CTRL_BASE_THR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689794@macro@NVIC_SYS_PRI1_USAGE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_USAGE_M",
+    "location": {
+      "column": "9",
+      "line": "12453",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_USAGE_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689863@macro@NVIC_SYS_PRI1_BUS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_BUS_M",
+    "location": {
+      "column": "9",
+      "line": "12454",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_BUS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@689930@macro@NVIC_SYS_PRI1_MEM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_MEM_M",
+    "location": {
+      "column": "9",
+      "line": "12455",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_MEM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690011@macro@NVIC_SYS_PRI1_USAGE_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_USAGE_S",
+    "location": {
+      "column": "9",
+      "line": "12456",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_USAGE_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690047@macro@NVIC_SYS_PRI1_BUS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_BUS_S",
+    "location": {
+      "column": "9",
+      "line": "12457",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_BUS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690083@macro@NVIC_SYS_PRI1_MEM_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI1_MEM_S",
+    "location": {
+      "column": "9",
+      "line": "12458",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI1_MEM_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690370@macro@NVIC_SYS_PRI2_SVC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI2_SVC_M",
+    "location": {
+      "column": "9",
+      "line": "12465",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI2_SVC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690434@macro@NVIC_SYS_PRI2_SVC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI2_SVC_S",
+    "location": {
+      "column": "9",
+      "line": "12466",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI2_SVC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690722@macro@NVIC_SYS_PRI3_TICK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_TICK_M",
+    "location": {
+      "column": "9",
+      "line": "12473",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_TICK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690797@macro@NVIC_SYS_PRI3_PENDSV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_PENDSV_M",
+    "location": {
+      "column": "9",
+      "line": "12474",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_PENDSV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690861@macro@NVIC_SYS_PRI3_DEBUG_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_DEBUG_M",
+    "location": {
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+      "line": "12475",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_DEBUG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690924@macro@NVIC_SYS_PRI3_TICK_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_TICK_S",
+    "location": {
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+      "line": "12476",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_TICK_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690960@macro@NVIC_SYS_PRI3_PENDSV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_PENDSV_S",
+    "location": {
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+      "line": "12477",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_PENDSV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@690996@macro@NVIC_SYS_PRI3_DEBUG_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_PRI3_DEBUG_S",
+    "location": {
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+      "line": "12478",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_PRI3_DEBUG_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691291@macro@NVIC_SYS_HND_CTRL_USAGE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_USAGE",
+    "location": {
+      "column": "9",
+      "line": "12486",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_USAGE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691358@macro@NVIC_SYS_HND_CTRL_BUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_BUS",
+    "location": {
+      "column": "9",
+      "line": "12487",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_BUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691423@macro@NVIC_SYS_HND_CTRL_MEM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_MEM",
+    "location": {
+      "column": "9",
+      "line": "12488",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_MEM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691502@macro@NVIC_SYS_HND_CTRL_SVC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_SVC",
+    "location": {
+      "column": "9",
+      "line": "12489",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_SVC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691567@macro@NVIC_SYS_HND_CTRL_BUSP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_BUSP",
+    "location": {
+      "column": "9",
+      "line": "12490",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_BUSP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691633@macro@NVIC_SYS_HND_CTRL_MEMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_MEMP",
+    "location": {
+      "column": "9",
+      "line": "12491",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_MEMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691713@macro@NVIC_SYS_HND_CTRL_USAGEP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_USAGEP",
+    "location": {
+      "column": "9",
+      "line": "12492",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_USAGEP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691862@macro@NVIC_SYS_HND_CTRL_TICK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_TICK",
+    "location": {
+      "column": "9",
+      "line": "12494",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_TICK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@691935@macro@NVIC_SYS_HND_CTRL_PNDSV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_PNDSV",
+    "location": {
+      "column": "9",
+      "line": "12495",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_PNDSV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692007@macro@NVIC_SYS_HND_CTRL_MON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_MON",
+    "location": {
+      "column": "9",
+      "line": "12496",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_MON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692076@macro@NVIC_SYS_HND_CTRL_SVCA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_SVCA",
+    "location": {
+      "column": "9",
+      "line": "12497",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_SVCA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692140@macro@NVIC_SYS_HND_CTRL_USGA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_USGA",
+    "location": {
+      "column": "9",
+      "line": "12498",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_USGA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692207@macro@NVIC_SYS_HND_CTRL_BUSA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_BUSA",
+    "location": {
+      "column": "9",
+      "line": "12499",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_BUSA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692272@macro@NVIC_SYS_HND_CTRL_MEMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_SYS_HND_CTRL_MEMA",
+    "location": {
+      "column": "9",
+      "line": "12500",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_SYS_HND_CTRL_MEMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692609@macro@NVIC_FAULT_STAT_DIV0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_DIV0",
+    "location": {
+      "column": "9",
+      "line": "12508",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_DIV0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692684@macro@NVIC_FAULT_STAT_UNALIGN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_UNALIGN",
+    "location": {
+      "column": "9",
+      "line": "12509",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_UNALIGN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692761@macro@NVIC_FAULT_STAT_NOCP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_NOCP",
+    "location": {
+      "column": "9",
+      "line": "12510",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_NOCP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692836@macro@NVIC_FAULT_STAT_INVPC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_INVPC",
+    "location": {
+      "column": "9",
+      "line": "12511",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_INVPC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692912@macro@NVIC_FAULT_STAT_INVSTAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_INVSTAT",
+    "location": {
+      "column": "9",
+      "line": "12512",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_INVSTAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@692986@macro@NVIC_FAULT_STAT_UNDEF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_UNDEF",
+    "location": {
+      "column": "9",
+      "line": "12513",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_UNDEF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693116@macro@NVIC_FAULT_STAT_BFARV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_BFARV",
+    "location": {
+      "column": "9",
+      "line": "12515",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_BFARV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693197@macro@NVIC_FAULT_STAT_BLSPERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_BLSPERR",
+    "location": {
+      "column": "9",
+      "line": "12516",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_BLSPERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693345@macro@NVIC_FAULT_STAT_BSTKE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_BSTKE",
+    "location": {
+      "column": "9",
+      "line": "12518",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_BSTKE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693409@macro@NVIC_FAULT_STAT_BUSTKE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_BUSTKE",
+    "location": {
+      "column": "9",
+      "line": "12519",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_BUSTKE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693475@macro@NVIC_FAULT_STAT_IMPRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_IMPRE",
+    "location": {
+      "column": "9",
+      "line": "12520",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_IMPRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693548@macro@NVIC_FAULT_STAT_PRECISE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_PRECISE",
+    "location": {
+      "column": "9",
+      "line": "12521",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_PRECISE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693619@macro@NVIC_FAULT_STAT_IBUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_IBUS",
+    "location": {
+      "column": "9",
+      "line": "12522",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_IBUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693689@macro@NVIC_FAULT_STAT_MMARV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_MMARV",
+    "location": {
+      "column": "9",
+      "line": "12523",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_MMARV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@693832@macro@NVIC_FAULT_STAT_MLSPERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_MLSPERR",
+    "location": {
+      "column": "9",
+      "line": "12525",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_MLSPERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694042@macro@NVIC_FAULT_STAT_MSTKE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_MSTKE",
+    "location": {
+      "column": "9",
+      "line": "12528",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_MSTKE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694113@macro@NVIC_FAULT_STAT_MUSTKE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_MUSTKE",
+    "location": {
+      "column": "9",
+      "line": "12529",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_MUSTKE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694186@macro@NVIC_FAULT_STAT_DERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_DERR",
+    "location": {
+      "column": "9",
+      "line": "12530",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_DERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694256@macro@NVIC_FAULT_STAT_IERR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_STAT_IERR",
+    "location": {
+      "column": "9",
+      "line": "12531",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_STAT_IERR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694592@macro@NVIC_HFAULT_STAT_DBG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_HFAULT_STAT_DBG",
+    "location": {
+      "column": "9",
+      "line": "12539",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_HFAULT_STAT_DBG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694652@macro@NVIC_HFAULT_STAT_FORCED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_HFAULT_STAT_FORCED",
+    "location": {
+      "column": "9",
+      "line": "12540",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_HFAULT_STAT_FORCED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@694718@macro@NVIC_HFAULT_STAT_VECT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_HFAULT_STAT_VECT",
+    "location": {
+      "column": "9",
+      "line": "12541",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_HFAULT_STAT_VECT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695048@macro@NVIC_DEBUG_STAT_EXTRNL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_EXTRNL",
+    "location": {
+      "column": "9",
+      "line": "12549",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_EXTRNL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695112@macro@NVIC_DEBUG_STAT_VCATCH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_VCATCH",
+    "location": {
+      "column": "9",
+      "line": "12550",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_VCATCH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695173@macro@NVIC_DEBUG_STAT_DWTTRAP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_DWTTRAP",
+    "location": {
+      "column": "9",
+      "line": "12551",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_DWTTRAP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695231@macro@NVIC_DEBUG_STAT_BKPT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_BKPT",
+    "location": {
+      "column": "9",
+      "line": "12552",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_BKPT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695302@macro@NVIC_DEBUG_STAT_HALTED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_DEBUG_STAT_HALTED",
+    "location": {
+      "column": "9",
+      "line": "12553",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_DEBUG_STAT_HALTED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695614@macro@NVIC_MM_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MM_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "12560",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MM_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695676@macro@NVIC_MM_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MM_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "12561",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MM_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@695969@macro@NVIC_FAULT_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "12569",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696031@macro@NVIC_FAULT_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_FAULT_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "12570",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_FAULT_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696314@macro@NVIC_CPAC_CP11_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP11_M",
+    "location": {
+      "column": "9",
+      "line": "12577",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP11_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696444@macro@NVIC_CPAC_CP11_DIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP11_DIS",
+    "location": {
+      "column": "9",
+      "line": "12579",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP11_DIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696506@macro@NVIC_CPAC_CP11_PRIV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP11_PRIV",
+    "location": {
+      "column": "9",
+      "line": "12580",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP11_PRIV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696577@macro@NVIC_CPAC_CP11_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP11_FULL",
+    "location": {
+      "column": "9",
+      "line": "12581",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP11_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696637@macro@NVIC_CPAC_CP10_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP10_M",
+    "location": {
+      "column": "9",
+      "line": "12582",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP10_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696767@macro@NVIC_CPAC_CP10_DIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP10_DIS",
+    "location": {
+      "column": "9",
+      "line": "12584",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP10_DIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696829@macro@NVIC_CPAC_CP10_PRIV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP10_PRIV",
+    "location": {
+      "column": "9",
+      "line": "12585",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP10_PRIV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@696900@macro@NVIC_CPAC_CP10_FULL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_CPAC_CP10_FULL",
+    "location": {
+      "column": "9",
+      "line": "12586",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_CPAC_CP10_FULL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697212@macro@NVIC_MPU_TYPE_IREGION_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_IREGION_M",
+    "location": {
+      "column": "9",
+      "line": "12593",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_IREGION_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697280@macro@NVIC_MPU_TYPE_DREGION_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_DREGION_M",
+    "location": {
+      "column": "9",
+      "line": "12594",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_DREGION_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697348@macro@NVIC_MPU_TYPE_SEPARATE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_SEPARATE",
+    "location": {
+      "column": "9",
+      "line": "12595",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_SEPARATE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697420@macro@NVIC_MPU_TYPE_IREGION_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_IREGION_S",
+    "location": {
+      "column": "9",
+      "line": "12596",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_IREGION_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697456@macro@NVIC_MPU_TYPE_DREGION_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_TYPE_DREGION_S",
+    "location": {
+      "column": "9",
+      "line": "12597",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_TYPE_DREGION_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697743@macro@NVIC_MPU_CTRL_PRIVDEFEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_CTRL_PRIVDEFEN",
+    "location": {
+      "column": "9",
+      "line": "12604",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_CTRL_PRIVDEFEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697810@macro@NVIC_MPU_CTRL_HFNMIENA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_CTRL_HFNMIENA",
+    "location": {
+      "column": "9",
+      "line": "12605",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_CTRL_HFNMIENA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@697884@macro@NVIC_MPU_CTRL_ENABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_CTRL_ENABLE",
+    "location": {
+      "column": "9",
+      "line": "12606",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_CTRL_ENABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698201@macro@NVIC_MPU_NUMBER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_NUMBER_M",
+    "location": {
+      "column": "9",
+      "line": "12614",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_NUMBER_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698270@macro@NVIC_MPU_NUMBER_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_NUMBER_S",
+    "location": {
+      "column": "9",
+      "line": "12615",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_NUMBER_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698557@macro@NVIC_MPU_BASE_ADDR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_ADDR_M",
+    "location": {
+      "column": "9",
+      "line": "12622",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_ADDR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698623@macro@NVIC_MPU_BASE_VALID",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_VALID",
+    "location": {
+      "column": "9",
+      "line": "12623",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_VALID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698691@macro@NVIC_MPU_BASE_REGION_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_REGION_M",
+    "location": {
+      "column": "9",
+      "line": "12624",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_REGION_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698753@macro@NVIC_MPU_BASE_ADDR_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_ADDR_S",
+    "location": {
+      "column": "9",
+      "line": "12625",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@698788@macro@NVIC_MPU_BASE_REGION_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_BASE_REGION_S",
+    "location": {
+      "column": "9",
+      "line": "12626",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE_REGION_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699075@macro@NVIC_MPU_ATTR_XN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_XN",
+    "location": {
+      "column": "9",
+      "line": "12633",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_XN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699150@macro@NVIC_MPU_ATTR_AP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_AP_M",
+    "location": {
+      "column": "9",
+      "line": "12634",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_AP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699215@macro@NVIC_MPU_ATTR_TEX_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_TEX_M",
+    "location": {
+      "column": "9",
+      "line": "12635",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_TEX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699283@macro@NVIC_MPU_ATTR_SHAREABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_SHAREABLE",
+    "location": {
+      "column": "9",
+      "line": "12636",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_SHAREABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699341@macro@NVIC_MPU_ATTR_CACHEABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_CACHEABLE",
+    "location": {
+      "column": "9",
+      "line": "12637",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_CACHEABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699399@macro@NVIC_MPU_ATTR_BUFFRABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_BUFFRABLE",
+    "location": {
+      "column": "9",
+      "line": "12638",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_BUFFRABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699458@macro@NVIC_MPU_ATTR_SRD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_SRD_M",
+    "location": {
+      "column": "9",
+      "line": "12639",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_SRD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@699529@macro@NVIC_MPU_ATTR_SIZE_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR_SIZE_M",
+    "location": {
+      "column": "9",
+      "line": "12640",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR_SIZE_M",
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+    },
+    "name": "NVIC_MPU_ATTR_ENABLE",
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+    },
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+  },
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+    },
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+    },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    "ID": "c:tm4c123gh6pm.h@700914@macro@NVIC_MPU_ATTR1_BUFFRABLE",
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+    },
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+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@701054@macro@NVIC_MPU_ATTR1_SRD_M",
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    "ID": "c:tm4c123gh6pm.h@702721@macro@NVIC_MPU_ATTR2_SIZE_M",
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+    "display": "NVIC_MPU_ATTR2_SIZE_M",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@702786@macro@NVIC_MPU_ATTR2_ENABLE",
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703167@macro@NVIC_MPU_BASE3_VALID",
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+    "display": "NVIC_MPU_BASE3_VALID",
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+    },
+    "name": "NVIC_MPU_BASE3_VALID",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703235@macro@NVIC_MPU_BASE3_REGION_M",
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+    "display": "NVIC_MPU_BASE3_REGION_M",
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+    },
+    "name": "NVIC_MPU_BASE3_REGION_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703297@macro@NVIC_MPU_BASE3_ADDR_S",
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+    "display": "NVIC_MPU_BASE3_ADDR_S",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_BASE3_ADDR_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703332@macro@NVIC_MPU_BASE3_REGION_S",
+    "What": "MacroDef",
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+    "display": "NVIC_MPU_BASE3_REGION_S",
+    "location": {
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+    },
+    "name": "NVIC_MPU_BASE3_REGION_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703620@macro@NVIC_MPU_ATTR3_XN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR3_XN",
+    "location": {
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+      "line": "12717",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_XN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703695@macro@NVIC_MPU_ATTR3_AP_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR3_AP_M",
+    "location": {
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+      "line": "12718",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_AP_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703760@macro@NVIC_MPU_ATTR3_TEX_M",
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+    "display": "NVIC_MPU_ATTR3_TEX_M",
+    "location": {
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+      "line": "12719",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_TEX_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703828@macro@NVIC_MPU_ATTR3_SHAREABLE",
+    "What": "MacroDef",
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+    "display": "NVIC_MPU_ATTR3_SHAREABLE",
+    "location": {
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+      "line": "12720",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_SHAREABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:tm4c123gh6pm.h@703967@macro@NVIC_MPU_ATTR3_CACHEABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "NVIC_MPU_ATTR3_CACHEABLE",
+    "location": {
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+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\tm4c123gh6pm.h"
+    },
+    "name": "NVIC_MPU_ATTR3_CACHEABLE",
+    "origin": "user_include",
+    "scope": null
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+    },
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+    "ID": "c:tm4c123gh6pm.h@709786@macro@NVIC_FPCC_MONRDY",
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+  },
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+  },
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+    "display": "SYSCTL_IMC",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@3601@macro@SYSCTL_MISC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@3731@macro@SYSCTL_RESC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC",
+    "location": {
+      "column": "9",
+      "line": "68",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@3791@macro@SYSCTL_PWRTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWRTC",
+    "location": {
+      "column": "9",
+      "line": "69",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PWRTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@3863@macro@SYSCTL_RCC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC",
+    "location": {
+      "column": "9",
+      "line": "70",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@3940@macro@SYSCTL_NMIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC",
+    "location": {
+      "column": "9",
+      "line": "71",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4007@macro@SYSCTL_GPIOHBCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL",
+    "location": {
+      "column": "9",
+      "line": "72",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4137@macro@SYSCTL_RCC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2",
+    "location": {
+      "column": "9",
+      "line": "74",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4216@macro@SYSCTL_MOSCCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL",
+    "location": {
+      "column": "9",
+      "line": "75",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4288@macro@SYSCTL_RSCLKCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG",
+    "location": {
+      "column": "9",
+      "line": "76",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4426@macro@SYSCTL_MEMTIM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0",
+    "location": {
+      "column": "9",
+      "line": "78",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4583@macro@SYSCTL_RCGC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0",
+    "location": {
+      "column": "9",
+      "line": "80",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4720@macro@SYSCTL_RCGC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1",
+    "location": {
+      "column": "9",
+      "line": "82",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4857@macro@SYSCTL_RCGC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2",
+    "location": {
+      "column": "9",
+      "line": "84",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@4994@macro@SYSCTL_SCGC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0",
+    "location": {
+      "column": "9",
+      "line": "86",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5133@macro@SYSCTL_SCGC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1",
+    "location": {
+      "column": "9",
+      "line": "88",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5272@macro@SYSCTL_SCGC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2",
+    "location": {
+      "column": "9",
+      "line": "90",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5411@macro@SYSCTL_DCGC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0",
+    "location": {
+      "column": "9",
+      "line": "92",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5555@macro@SYSCTL_DCGC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1",
+    "location": {
+      "column": "9",
+      "line": "94",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5699@macro@SYSCTL_DCGC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2",
+    "location": {
+      "column": "9",
+      "line": "96",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5843@macro@SYSCTL_ALTCLKCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLKCFG",
+    "location": {
+      "column": "9",
+      "line": "98",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLKCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@5921@macro@SYSCTL_DSLPCLKCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG",
+    "location": {
+      "column": "9",
+      "line": "99",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6000@macro@SYSCTL_DSCLKCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG",
+    "location": {
+      "column": "9",
+      "line": "100",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6136@macro@SYSCTL_DIVSCLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK",
+    "location": {
+      "column": "9",
+      "line": "102",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6271@macro@SYSCTL_SYSPROP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SYSPROP",
+    "location": {
+      "column": "9",
+      "line": "104",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SYSPROP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6337@macro@SYSCTL_PIOSCCAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL",
+    "location": {
+      "column": "9",
+      "line": "105",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6475@macro@SYSCTL_PIOSCSTAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT",
+    "location": {
+      "column": "9",
+      "line": "107",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6612@macro@SYSCTL_PLLFREQ0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0",
+    "location": {
+      "column": "9",
+      "line": "109",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6676@macro@SYSCTL_PLLFREQ1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1",
+    "location": {
+      "column": "9",
+      "line": "110",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6740@macro@SYSCTL_PLLSTAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLSTAT",
+    "location": {
+      "column": "9",
+      "line": "111",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLSTAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6799@macro@SYSCTL_SLPPWRCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG",
+    "location": {
+      "column": "9",
+      "line": "112",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6873@macro@SYSCTL_DSLPPWRCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG",
+    "location": {
+      "column": "9",
+      "line": "113",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@6952@macro@SYSCTL_DC9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9",
+    "location": {
+      "column": "9",
+      "line": "114",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7022@macro@SYSCTL_NVMSTAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NVMSTAT",
+    "location": {
+      "column": "9",
+      "line": "115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NVMSTAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7102@macro@SYSCTL_LDOSPCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDOSPCTL",
+    "location": {
+      "column": "9",
+      "line": "116",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LDOSPCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7174@macro@SYSCTL_LDODPCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LDODPCTL",
+    "location": {
+      "column": "9",
+      "line": "117",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LDODPCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7251@macro@SYSCTL_RESBEHAVCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESBEHAVCTL",
+    "location": {
+      "column": "9",
+      "line": "118",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESBEHAVCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7331@macro@SYSCTL_HSSR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_HSSR",
+    "location": {
+      "column": "9",
+      "line": "119",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_HSSR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7411@macro@SYSCTL_USBPDS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS",
+    "location": {
+      "column": "9",
+      "line": "120",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7483@macro@SYSCTL_USBMPC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBMPC",
+    "location": {
+      "column": "9",
+      "line": "121",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBMPC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7556@macro@SYSCTL_EMACPDS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS",
+    "location": {
+      "column": "9",
+      "line": "122",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7637@macro@SYSCTL_EMACMPC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACMPC",
+    "location": {
+      "column": "9",
+      "line": "123",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACMPC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7767@macro@SYSCTL_LCDMPC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LCDMPC",
+    "location": {
+      "column": "9",
+      "line": "125",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LCDMPC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7840@macro@SYSCTL_PPWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD",
+    "location": {
+      "column": "9",
+      "line": "126",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@7970@macro@SYSCTL_PPTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER",
+    "location": {
+      "column": "9",
+      "line": "128",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8117@macro@SYSCTL_PPGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO",
+    "location": {
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+      "line": "130",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8261@macro@SYSCTL_PPDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPDMA",
+    "location": {
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+      "line": "132",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8403@macro@SYSCTL_PPEPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEPI",
+    "location": {
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+      "line": "134",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8474@macro@SYSCTL_PPHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIB",
+    "location": {
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+      "line": "135",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8553@macro@SYSCTL_PPUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART",
+    "location": {
+      "column": "9",
+      "line": "136",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8760@macro@SYSCTL_PPSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI",
+    "location": {
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+      "line": "139",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@8904@macro@SYSCTL_PPI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C",
+    "location": {
+      "column": "9",
+      "line": "141",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9044@macro@SYSCTL_PPUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUSB",
+    "location": {
+      "column": "9",
+      "line": "143",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9180@macro@SYSCTL_PPEPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEPHY",
+    "location": {
+      "column": "9",
+      "line": "145",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9260@macro@SYSCTL_PPCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN",
+    "location": {
+      "column": "9",
+      "line": "146",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9399@macro@SYSCTL_PPADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC",
+    "location": {
+      "column": "9",
+      "line": "148",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9542@macro@SYSCTL_PPACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPACMP",
+    "location": {
+      "column": "9",
+      "line": "150",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9675@macro@SYSCTL_PPPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM",
+    "location": {
+      "column": "9",
+      "line": "152",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9812@macro@SYSCTL_PPQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI",
+    "location": {
+      "column": "9",
+      "line": "154",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@9956@macro@SYSCTL_PPLPC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPLPC",
+    "location": {
+      "column": "9",
+      "line": "156",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPLPC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10095@macro@SYSCTL_PPPECI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPECI",
+    "location": {
+      "column": "9",
+      "line": "158",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPPECI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10249@macro@SYSCTL_PPFAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPFAN",
+    "location": {
+      "column": "9",
+      "line": "160",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPFAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10328@macro@SYSCTL_PPEEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEEPROM",
+    "location": {
+      "column": "9",
+      "line": "161",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10402@macro@SYSCTL_PPWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER",
+    "location": {
+      "column": "9",
+      "line": "162",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10554@macro@SYSCTL_PPRTS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPRTS",
+    "location": {
+      "column": "9",
+      "line": "164",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPRTS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10695@macro@SYSCTL_PPCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCCM",
+    "location": {
+      "column": "9",
+      "line": "166",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10840@macro@SYSCTL_PPLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPLCD",
+    "location": {
+      "column": "9",
+      "line": "168",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10911@macro@SYSCTL_PPOWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPOWIRE",
+    "location": {
+      "column": "9",
+      "line": "169",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPOWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@10985@macro@SYSCTL_PPEMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEMAC",
+    "location": {
+      "column": "9",
+      "line": "170",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11065@macro@SYSCTL_PPHIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIM",
+    "location": {
+      "column": "9",
+      "line": "171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPHIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11203@macro@SYSCTL_SRWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD",
+    "location": {
+      "column": "9",
+      "line": "173",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11281@macro@SYSCTL_SRTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER",
+    "location": {
+      "column": "9",
+      "line": "174",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11424@macro@SYSCTL_SRGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO",
+    "location": {
+      "column": "9",
+      "line": "176",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11564@macro@SYSCTL_SRDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRDMA",
+    "location": {
+      "column": "9",
+      "line": "178",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11702@macro@SYSCTL_SREPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREPI",
+    "location": {
+      "column": "9",
+      "line": "180",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11769@macro@SYSCTL_SRHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRHIB",
+    "location": {
+      "column": "9",
+      "line": "181",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@11844@macro@SYSCTL_SRUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART",
+    "location": {
+      "column": "9",
+      "line": "182",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12047@macro@SYSCTL_SRSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI",
+    "location": {
+      "column": "9",
+      "line": "185",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12187@macro@SYSCTL_SRI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C",
+    "location": {
+      "column": "9",
+      "line": "187",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12323@macro@SYSCTL_SRUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUSB",
+    "location": {
+      "column": "9",
+      "line": "189",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12455@macro@SYSCTL_SREPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREPHY",
+    "location": {
+      "column": "9",
+      "line": "191",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12531@macro@SYSCTL_SRCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN",
+    "location": {
+      "column": "9",
+      "line": "192",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12666@macro@SYSCTL_SRADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC",
+    "location": {
+      "column": "9",
+      "line": "194",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12805@macro@SYSCTL_SRACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRACMP",
+    "location": {
+      "column": "9",
+      "line": "196",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@12886@macro@SYSCTL_SRPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM",
+    "location": {
+      "column": "9",
+      "line": "197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13019@macro@SYSCTL_SRQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI",
+    "location": {
+      "column": "9",
+      "line": "199",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13159@macro@SYSCTL_SREEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREEPROM",
+    "location": {
+      "column": "9",
+      "line": "201",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13229@macro@SYSCTL_SRWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER",
+    "location": {
+      "column": "9",
+      "line": "202",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13377@macro@SYSCTL_SRCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCCM",
+    "location": {
+      "column": "9",
+      "line": "204",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13518@macro@SYSCTL_SRLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRLCD",
+    "location": {
+      "column": "9",
+      "line": "206",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13596@macro@SYSCTL_SROWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SROWIRE",
+    "location": {
+      "column": "9",
+      "line": "207",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SROWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13666@macro@SYSCTL_SREMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREMAC",
+    "location": {
+      "column": "9",
+      "line": "208",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13742@macro@SYSCTL_RCGCWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD",
+    "location": {
+      "column": "9",
+      "line": "209",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@13883@macro@SYSCTL_RCGCTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER",
+    "location": {
+      "column": "9",
+      "line": "211",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14041@macro@SYSCTL_RCGCGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO",
+    "location": {
+      "column": "9",
+      "line": "213",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14196@macro@SYSCTL_RCGCDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCDMA",
+    "location": {
+      "column": "9",
+      "line": "215",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14349@macro@SYSCTL_RCGCEPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEPI",
+    "location": {
+      "column": "9",
+      "line": "217",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14479@macro@SYSCTL_RCGCHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCHIB",
+    "location": {
+      "column": "9",
+      "line": "219",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14617@macro@SYSCTL_RCGCUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART",
+    "location": {
+      "column": "9",
+      "line": "221",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14835@macro@SYSCTL_RCGCSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI",
+    "location": {
+      "column": "9",
+      "line": "224",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@14990@macro@SYSCTL_RCGCI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C",
+    "location": {
+      "column": "9",
+      "line": "226",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15141@macro@SYSCTL_RCGCUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUSB",
+    "location": {
+      "column": "9",
+      "line": "228",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15288@macro@SYSCTL_RCGCEPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEPHY",
+    "location": {
+      "column": "9",
+      "line": "230",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15427@macro@SYSCTL_RCGCCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN",
+    "location": {
+      "column": "9",
+      "line": "232",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15577@macro@SYSCTL_RCGCADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC",
+    "location": {
+      "column": "9",
+      "line": "234",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15731@macro@SYSCTL_RCGCACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCACMP",
+    "location": {
+      "column": "9",
+      "line": "236",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@15875@macro@SYSCTL_RCGCPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM",
+    "location": {
+      "column": "9",
+      "line": "238",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16023@macro@SYSCTL_RCGCQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI",
+    "location": {
+      "column": "9",
+      "line": "240",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16178@macro@SYSCTL_RCGCEEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEEPROM",
+    "location": {
+      "column": "9",
+      "line": "242",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16311@macro@SYSCTL_RCGCWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER",
+    "location": {
+      "column": "9",
+      "line": "244",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16522@macro@SYSCTL_RCGCCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCCM",
+    "location": {
+      "column": "9",
+      "line": "247",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16678@macro@SYSCTL_RCGCLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCLCD",
+    "location": {
+      "column": "9",
+      "line": "249",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16819@macro@SYSCTL_RCGCOWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCOWIRE",
+    "location": {
+      "column": "9",
+      "line": "251",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCOWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@16952@macro@SYSCTL_RCGCEMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEMAC",
+    "location": {
+      "column": "9",
+      "line": "253",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17091@macro@SYSCTL_SCGCWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD",
+    "location": {
+      "column": "9",
+      "line": "255",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17234@macro@SYSCTL_SCGCTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER",
+    "location": {
+      "column": "9",
+      "line": "257",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17394@macro@SYSCTL_SCGCGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO",
+    "location": {
+      "column": "9",
+      "line": "259",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17551@macro@SYSCTL_SCGCDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCDMA",
+    "location": {
+      "column": "9",
+      "line": "261",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17706@macro@SYSCTL_SCGCEPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEPI",
+    "location": {
+      "column": "9",
+      "line": "263",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17838@macro@SYSCTL_SCGCHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCHIB",
+    "location": {
+      "column": "9",
+      "line": "265",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@17978@macro@SYSCTL_SCGCUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART",
+    "location": {
+      "column": "9",
+      "line": "267",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18198@macro@SYSCTL_SCGCSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI",
+    "location": {
+      "column": "9",
+      "line": "270",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18355@macro@SYSCTL_SCGCI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C",
+    "location": {
+      "column": "9",
+      "line": "272",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18508@macro@SYSCTL_SCGCUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUSB",
+    "location": {
+      "column": "9",
+      "line": "274",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18657@macro@SYSCTL_SCGCEPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEPHY",
+    "location": {
+      "column": "9",
+      "line": "276",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18798@macro@SYSCTL_SCGCCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN",
+    "location": {
+      "column": "9",
+      "line": "278",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@18950@macro@SYSCTL_SCGCADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC",
+    "location": {
+      "column": "9",
+      "line": "280",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19106@macro@SYSCTL_SCGCACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCACMP",
+    "location": {
+      "column": "9",
+      "line": "282",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19252@macro@SYSCTL_SCGCPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM",
+    "location": {
+      "column": "9",
+      "line": "284",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19402@macro@SYSCTL_SCGCQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI",
+    "location": {
+      "column": "9",
+      "line": "286",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19559@macro@SYSCTL_SCGCEEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEEPROM",
+    "location": {
+      "column": "9",
+      "line": "288",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19694@macro@SYSCTL_SCGCWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER",
+    "location": {
+      "column": "9",
+      "line": "290",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@19907@macro@SYSCTL_SCGCCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCCM",
+    "location": {
+      "column": "9",
+      "line": "293",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20065@macro@SYSCTL_SCGCLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCLCD",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20208@macro@SYSCTL_SCGCOWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCOWIRE",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCOWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20343@macro@SYSCTL_SCGCEMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEMAC",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20484@macro@SYSCTL_DCGCWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20632@macro@SYSCTL_DCGCTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER",
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+      "line": "303",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@20845@macro@SYSCTL_DCGCGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO",
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+      "line": "306",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21055@macro@SYSCTL_DCGCDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCDMA",
+    "location": {
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+      "line": "309",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21263@macro@SYSCTL_DCGCEPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEPI",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21400@macro@SYSCTL_DCGCHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCHIB",
+    "location": {
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+      "line": "314",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21545@macro@SYSCTL_DCGCUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART",
+    "location": {
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+      "line": "316",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21770@macro@SYSCTL_DCGCSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI",
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+      "line": "319",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@21980@macro@SYSCTL_DCGCI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C",
+    "location": {
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+      "line": "322",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@22186@macro@SYSCTL_DCGCUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUSB",
+    "location": {
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+      "line": "325",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@22340@macro@SYSCTL_DCGCEPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEPHY",
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+      "line": "327",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@22486@macro@SYSCTL_DCGCCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN",
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+      "line": "329",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@22691@macro@SYSCTL_DCGCADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@22900@macro@SYSCTL_DCGCACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCACMP",
+    "location": {
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+      "line": "335",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23051@macro@SYSCTL_DCGCPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM",
+    "location": {
+      "column": "9",
+      "line": "337",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23206@macro@SYSCTL_DCGCQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI",
+    "location": {
+      "column": "9",
+      "line": "339",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23416@macro@SYSCTL_DCGCEEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEEPROM",
+    "location": {
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+      "line": "342",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23556@macro@SYSCTL_DCGCWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER",
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+      "line": "344",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23774@macro@SYSCTL_DCGCCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCCM",
+    "location": {
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+      "line": "347",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@23985@macro@SYSCTL_DCGCLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCLCD",
+    "location": {
+      "column": "9",
+      "line": "350",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24133@macro@SYSCTL_DCGCOWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCOWIRE",
+    "location": {
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+      "line": "352",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCOWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24273@macro@SYSCTL_DCGCEMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEMAC",
+    "location": {
+      "column": "9",
+      "line": "354",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24419@macro@SYSCTL_PCWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCWD",
+    "location": {
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+      "line": "356",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24496@macro@SYSCTL_PCTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER",
+    "location": {
+      "column": "9",
+      "line": "357",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24638@macro@SYSCTL_PCGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO",
+    "location": {
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+      "line": "359",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24777@macro@SYSCTL_PCDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCDMA",
+    "location": {
+      "column": "9",
+      "line": "361",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@24914@macro@SYSCTL_PCEPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEPI",
+    "location": {
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+      "line": "363",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25054@macro@SYSCTL_PCHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCHIB",
+    "location": {
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+      "line": "365",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25128@macro@SYSCTL_PCUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART",
+    "location": {
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+      "line": "366",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25330@macro@SYSCTL_PCSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCSSI",
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+      "line": "369",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25469@macro@SYSCTL_PCI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C",
+    "location": {
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+      "line": "371",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25604@macro@SYSCTL_PCUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUSB",
+    "location": {
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+      "line": "373",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25735@macro@SYSCTL_PCEPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEPHY",
+    "location": {
+      "column": "9",
+      "line": "375",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25810@macro@SYSCTL_PCCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCCAN",
+    "location": {
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+      "line": "376",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@25944@macro@SYSCTL_PCADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCADC",
+    "location": {
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+      "line": "378",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26082@macro@SYSCTL_PCACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCACMP",
+    "location": {
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+      "line": "380",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26162@macro@SYSCTL_PCPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCPWM",
+    "location": {
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+      "line": "381",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26294@macro@SYSCTL_PCQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCQEI",
+    "location": {
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+      "line": "383",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26433@macro@SYSCTL_PCEEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEEPROM",
+    "location": {
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+      "line": "385",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26502@macro@SYSCTL_PCCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCCCM",
+    "location": {
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+      "line": "386",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26642@macro@SYSCTL_PCLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCLCD",
+    "location": {
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+      "line": "388",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26719@macro@SYSCTL_PCOWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCOWIRE",
+    "location": {
+      "column": "9",
+      "line": "389",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCOWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26788@macro@SYSCTL_PCEMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEMAC",
+    "location": {
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+      "line": "390",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26863@macro@SYSCTL_PRWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD",
+    "location": {
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+      "line": "391",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@26943@macro@SYSCTL_PRTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER",
+    "location": {
+      "column": "9",
+      "line": "392",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27088@macro@SYSCTL_PRGPIO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO",
+    "location": {
+      "column": "9",
+      "line": "394",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27230@macro@SYSCTL_PRDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRDMA",
+    "location": {
+      "column": "9",
+      "line": "396",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27370@macro@SYSCTL_PREPI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREPI",
+    "location": {
+      "column": "9",
+      "line": "398",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27439@macro@SYSCTL_PRHIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRHIB",
+    "location": {
+      "column": "9",
+      "line": "399",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRHIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27516@macro@SYSCTL_PRUART",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART",
+    "location": {
+      "column": "9",
+      "line": "400",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27721@macro@SYSCTL_PRSSI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI",
+    "location": {
+      "column": "9",
+      "line": "403",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@27863@macro@SYSCTL_PRI2C",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C",
+    "location": {
+      "column": "9",
+      "line": "405",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28001@macro@SYSCTL_PRUSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUSB",
+    "location": {
+      "column": "9",
+      "line": "407",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28135@macro@SYSCTL_PREPHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREPHY",
+    "location": {
+      "column": "9",
+      "line": "409",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREPHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28213@macro@SYSCTL_PRCAN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN",
+    "location": {
+      "column": "9",
+      "line": "410",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28350@macro@SYSCTL_PRADC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC",
+    "location": {
+      "column": "9",
+      "line": "412",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28491@macro@SYSCTL_PRACMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRACMP",
+    "location": {
+      "column": "9",
+      "line": "414",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRACMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28622@macro@SYSCTL_PRPWM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM",
+    "location": {
+      "column": "9",
+      "line": "416",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRPWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28757@macro@SYSCTL_PRQEI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI",
+    "location": {
+      "column": "9",
+      "line": "418",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28899@macro@SYSCTL_PREEPROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREEPROM",
+    "location": {
+      "column": "9",
+      "line": "420",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREEPROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@28971@macro@SYSCTL_PRWTIMER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER",
+    "location": {
+      "column": "9",
+      "line": "421",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29121@macro@SYSCTL_PRCCM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCCM",
+    "location": {
+      "column": "9",
+      "line": "423",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRCCM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29264@macro@SYSCTL_PRLCD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRLCD",
+    "location": {
+      "column": "9",
+      "line": "425",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29344@macro@SYSCTL_PROWIRE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PROWIRE",
+    "location": {
+      "column": "9",
+      "line": "426",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PROWIRE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29416@macro@SYSCTL_PREMAC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREMAC",
+    "location": {
+      "column": "9",
+      "line": "427",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREMAC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29494@macro@SYSCTL_UNIQUEID0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID0",
+    "location": {
+      "column": "9",
+      "line": "428",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29554@macro@SYSCTL_UNIQUEID1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID1",
+    "location": {
+      "column": "9",
+      "line": "429",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29614@macro@SYSCTL_UNIQUEID2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID2",
+    "location": {
+      "column": "9",
+      "line": "430",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29674@macro@SYSCTL_UNIQUEID3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID3",
+    "location": {
+      "column": "9",
+      "line": "431",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@29734@macro@SYSCTL_CCMCGREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CCMCGREQ",
+    "location": {
+      "column": "9",
+      "line": "432",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_CCMCGREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30123@macro@SYSCTL_DID0_VER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_VER_M",
+    "location": {
+      "column": "9",
+      "line": "440",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_VER_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30184@macro@SYSCTL_DID0_VER_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_VER_1",
+    "location": {
+      "column": "9",
+      "line": "441",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_VER_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30324@macro@SYSCTL_DID0_CLASS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_M",
+    "location": {
+      "column": "9",
+      "line": "443",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30385@macro@SYSCTL_DID0_CLASS_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_TM4C123",
+    "location": {
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+      "line": "444",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30606@macro@SYSCTL_DID0_CLASS_TM4C129",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_TM4C129",
+    "location": {
+      "column": "9",
+      "line": "447",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_TM4C129",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30823@macro@SYSCTL_DID0_MAJ_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_M",
+    "location": {
+      "column": "9",
+      "line": "450",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30886@macro@SYSCTL_DID0_MAJ_REVA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVA",
+    "location": {
+      "column": "9",
+      "line": "451",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@30962@macro@SYSCTL_DID0_MAJ_REVB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVB",
+    "location": {
+      "column": "9",
+      "line": "452",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31097@macro@SYSCTL_DID0_MAJ_REVC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MAJ_REVC",
+    "location": {
+      "column": "9",
+      "line": "454",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MAJ_REVC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31233@macro@SYSCTL_DID0_MIN_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_M",
+    "location": {
+      "column": "9",
+      "line": "456",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MIN_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31296@macro@SYSCTL_DID0_MIN_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_0",
+    "location": {
+      "column": "9",
+      "line": "457",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MIN_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31435@macro@SYSCTL_DID0_MIN_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_1",
+    "location": {
+      "column": "9",
+      "line": "459",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MIN_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31508@macro@SYSCTL_DID0_MIN_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_MIN_2",
+    "location": {
+      "column": "9",
+      "line": "460",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_MIN_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@31832@macro@SYSCTL_DID1_VER_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID1_VER_M",
+    "location": {
+      "column": "9",
+      "line": "467",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID1_VER_M",
+    "origin": "user_include",
+    "scope": null
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+    },
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+  {
+    "ID": "c:hw_sysctl.h@42245@macro@SYSCTL_DID1_PINCNT_64",
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+    },
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+  },
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+    },
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+  },
+  {
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+    },
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+  },
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+    },
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+  },
+  {
+    "ID": "c:hw_sysctl.h@42585@macro@SYSCTL_DID1_TEMP_C",
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+    "defdec": "Def",
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+    },
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+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:hw_sysctl.h@42662@macro@SYSCTL_DID1_TEMP_I",
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+    "defdec": "Def",
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+    },
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+  },
+  {
+    "ID": "c:hw_sysctl.h@42739@macro@SYSCTL_DID1_TEMP_E",
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+    },
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+  },
+  {
+    "ID": "c:hw_sysctl.h@42814@macro@SYSCTL_DID1_TEMP_IE",
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+    },
+    "name": "SYSCTL_DID1_TEMP_IE",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "SYSCTL_DID1_PKG_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_DID1_PKG_QFP",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:hw_sysctl.h@43247@macro@SYSCTL_DID1_PKG_BGA",
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+    },
+    "name": "SYSCTL_DID1_PKG_BGA",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:hw_sysctl.h@43307@macro@SYSCTL_DID1_ROHS",
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+    },
+    "name": "SYSCTL_DID1_ROHS",
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+  },
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+    },
+    "name": "SYSCTL_DID1_QUAL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@43440@macro@SYSCTL_DID1_QUAL_ES",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_ES",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@43521@macro@SYSCTL_DID1_QUAL_PP",
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+    },
+    "name": "SYSCTL_DID1_QUAL_PP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@43600@macro@SYSCTL_DID1_QUAL_FQ",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID1_QUAL_FQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_DC0_SRAMSZ_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@43971@macro@SYSCTL_DC0_SRAMSZ_2KB",
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+    "display": "SYSCTL_DC0_SRAMSZ_2KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_2KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_DC0_SRAMSZ_4KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44093@macro@SYSCTL_DC0_SRAMSZ_6KB",
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+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_6KB",
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+    },
+    "name": "SYSCTL_DC0_SRAMSZ_6KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44154@macro@SYSCTL_DC0_SRAMSZ_8KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_8KB",
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+      "line": "644",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_8KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_12KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_12KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44277@macro@SYSCTL_DC0_SRAMSZ_16KB",
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+    "display": "SYSCTL_DC0_SRAMSZ_16KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_16KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44339@macro@SYSCTL_DC0_SRAMSZ_20KB",
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+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_20KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_20KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44401@macro@SYSCTL_DC0_SRAMSZ_24KB",
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+    "defdec": "Def",
+    "display": "SYSCTL_DC0_SRAMSZ_24KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "display": "SYSCTL_DC0_SRAMSZ_32KB",
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+      "line": "649",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_SRAMSZ_32KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
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+      "line": "650",
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+    },
+    "name": "SYSCTL_DC0_FLASHSZ_M",
+    "origin": "user_include",
+    "scope": null
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+  {
+    "ID": "c:hw_sysctl.h@44584@macro@SYSCTL_DC0_FLASHSZ_8KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_8KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_8KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    "display": "SYSCTL_DC0_FLASHSZ_16KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_16KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44709@macro@SYSCTL_DC0_FLASHSZ_32KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_32KB",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_32KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44772@macro@SYSCTL_DC0_FLASHSZ_64KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_64KB",
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+      "line": "654",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_64KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44835@macro@SYSCTL_DC0_FLASHSZ_96KB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_96KB",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_96KB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44898@macro@SYSCTL_DC0_FLASHSZ_128K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_128K",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_128K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@44962@macro@SYSCTL_DC0_FLASHSZ_192K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_192K",
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+      "line": "657",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_192K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC0_FLASHSZ_256K",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC0_FLASHSZ_256K",
+    "origin": "user_include",
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+  },
+  {
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+    "defdec": "Def",
+    "display": "SYSCTL_DC1_WDT1",
+    "location": {
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+    },
+    "name": "SYSCTL_DC1_WDT1",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:hw_sysctl.h@45411@macro@SYSCTL_DC1_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_CAN1",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45480@macro@SYSCTL_DC1_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_CAN0",
+    "location": {
+      "column": "9",
+      "line": "667",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45549@macro@SYSCTL_DC1_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PWM1",
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+      "line": "668",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45618@macro@SYSCTL_DC1_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PWM0",
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+      "line": "669",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45687@macro@SYSCTL_DC1_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1",
+    "location": {
+      "column": "9",
+      "line": "670",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45756@macro@SYSCTL_DC1_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0",
+    "location": {
+      "column": "9",
+      "line": "671",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45825@macro@SYSCTL_DC1_MINSYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_M",
+    "location": {
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+      "line": "672",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@45894@macro@SYSCTL_DC1_MINSYSDIV_80",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_80",
+    "location": {
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+      "line": "673",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_80",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46046@macro@SYSCTL_DC1_MINSYSDIV_50",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_50",
+    "location": {
+      "column": "9",
+      "line": "675",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_50",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46195@macro@SYSCTL_DC1_MINSYSDIV_40",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_40",
+    "location": {
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+      "line": "677",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_40",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46344@macro@SYSCTL_DC1_MINSYSDIV_25",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_25",
+    "location": {
+      "column": "9",
+      "line": "679",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_25",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46489@macro@SYSCTL_DC1_MINSYSDIV_20",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MINSYSDIV_20",
+    "location": {
+      "column": "9",
+      "line": "681",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MINSYSDIV_20",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46635@macro@SYSCTL_DC1_ADC1SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_M",
+    "location": {
+      "column": "9",
+      "line": "683",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46698@macro@SYSCTL_DC1_ADC1SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_125K",
+    "location": {
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+      "line": "684",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46766@macro@SYSCTL_DC1_ADC1SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_250K",
+    "location": {
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+      "line": "685",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46834@macro@SYSCTL_DC1_ADC1SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_500K",
+    "location": {
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+      "line": "686",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46902@macro@SYSCTL_DC1_ADC1SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC1SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "687",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC1SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@46968@macro@SYSCTL_DC1_ADC0SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_M",
+    "location": {
+      "column": "9",
+      "line": "688",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47031@macro@SYSCTL_DC1_ADC0SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "689",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47099@macro@SYSCTL_DC1_ADC0SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "690",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47167@macro@SYSCTL_DC1_ADC0SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "691",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47235@macro@SYSCTL_DC1_ADC0SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_ADC0SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "692",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_ADC0SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47301@macro@SYSCTL_DC1_MPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_MPU",
+    "location": {
+      "column": "9",
+      "line": "693",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_MPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47361@macro@SYSCTL_DC1_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_HIB",
+    "location": {
+      "column": "9",
+      "line": "694",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47436@macro@SYSCTL_DC1_TEMP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_TEMP",
+    "location": {
+      "column": "9",
+      "line": "695",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_TEMP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47504@macro@SYSCTL_DC1_PLL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_PLL",
+    "location": {
+      "column": "9",
+      "line": "696",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_PLL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47564@macro@SYSCTL_DC1_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_WDT0",
+    "location": {
+      "column": "9",
+      "line": "697",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47637@macro@SYSCTL_DC1_SWO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_SWO",
+    "location": {
+      "column": "9",
+      "line": "698",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_SWO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47708@macro@SYSCTL_DC1_SWD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_SWD",
+    "location": {
+      "column": "9",
+      "line": "699",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_SWD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@47768@macro@SYSCTL_DC1_JTAG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC1_JTAG",
+    "location": {
+      "column": "9",
+      "line": "700",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC1_JTAG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48078@macro@SYSCTL_DC2_EPI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_EPI0",
+    "location": {
+      "column": "9",
+      "line": "707",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_EPI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48147@macro@SYSCTL_DC2_I2S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2S0",
+    "location": {
+      "column": "9",
+      "line": "708",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_I2S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48216@macro@SYSCTL_DC2_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP2",
+    "location": {
+      "column": "9",
+      "line": "709",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48292@macro@SYSCTL_DC2_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP1",
+    "location": {
+      "column": "9",
+      "line": "710",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48368@macro@SYSCTL_DC2_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_COMP0",
+    "location": {
+      "column": "9",
+      "line": "711",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48444@macro@SYSCTL_DC2_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "712",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48515@macro@SYSCTL_DC2_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "713",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48586@macro@SYSCTL_DC2_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "714",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48657@macro@SYSCTL_DC2_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "715",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48728@macro@SYSCTL_DC2_I2C1HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C1HS",
+    "location": {
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+      "line": "716",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_I2C1HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48795@macro@SYSCTL_DC2_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C1",
+    "location": {
+      "column": "9",
+      "line": "717",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48864@macro@SYSCTL_DC2_I2C0HS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C0HS",
+    "location": {
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+      "line": "718",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_I2C0HS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@48931@macro@SYSCTL_DC2_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_I2C0",
+    "location": {
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+      "line": "719",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49000@macro@SYSCTL_DC2_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_QEI1",
+    "location": {
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+      "line": "720",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49069@macro@SYSCTL_DC2_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_QEI0",
+    "location": {
+      "column": "9",
+      "line": "721",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49138@macro@SYSCTL_DC2_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_SSI1",
+    "location": {
+      "column": "9",
+      "line": "722",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49207@macro@SYSCTL_DC2_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_SSI0",
+    "location": {
+      "column": "9",
+      "line": "723",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49276@macro@SYSCTL_DC2_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART2",
+    "location": {
+      "column": "9",
+      "line": "724",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49346@macro@SYSCTL_DC2_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART1",
+    "location": {
+      "column": "9",
+      "line": "725",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49416@macro@SYSCTL_DC2_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC2_UART0",
+    "location": {
+      "column": "9",
+      "line": "726",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC2_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49735@macro@SYSCTL_DC3_32KHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_32KHZ",
+    "location": {
+      "column": "9",
+      "line": "733",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_32KHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49811@macro@SYSCTL_DC3_CCP5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP5",
+    "location": {
+      "column": "9",
+      "line": "734",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49878@macro@SYSCTL_DC3_CCP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP4",
+    "location": {
+      "column": "9",
+      "line": "735",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@49945@macro@SYSCTL_DC3_CCP3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP3",
+    "location": {
+      "column": "9",
+      "line": "736",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50012@macro@SYSCTL_DC3_CCP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP2",
+    "location": {
+      "column": "9",
+      "line": "737",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50079@macro@SYSCTL_DC3_CCP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP1",
+    "location": {
+      "column": "9",
+      "line": "738",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50146@macro@SYSCTL_DC3_CCP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_CCP0",
+    "location": {
+      "column": "9",
+      "line": "739",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_CCP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50213@macro@SYSCTL_DC3_ADC0AIN7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN7",
+    "location": {
+      "column": "9",
+      "line": "740",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50291@macro@SYSCTL_DC3_ADC0AIN6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN6",
+    "location": {
+      "column": "9",
+      "line": "741",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50369@macro@SYSCTL_DC3_ADC0AIN5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN5",
+    "location": {
+      "column": "9",
+      "line": "742",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50447@macro@SYSCTL_DC3_ADC0AIN4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN4",
+    "location": {
+      "column": "9",
+      "line": "743",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50525@macro@SYSCTL_DC3_ADC0AIN3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN3",
+    "location": {
+      "column": "9",
+      "line": "744",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50603@macro@SYSCTL_DC3_ADC0AIN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN2",
+    "location": {
+      "column": "9",
+      "line": "745",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50681@macro@SYSCTL_DC3_ADC0AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN1",
+    "location": {
+      "column": "9",
+      "line": "746",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50759@macro@SYSCTL_DC3_ADC0AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_ADC0AIN0",
+    "location": {
+      "column": "9",
+      "line": "747",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_ADC0AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50837@macro@SYSCTL_DC3_PWMFAULT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWMFAULT",
+    "location": {
+      "column": "9",
+      "line": "748",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWMFAULT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50907@macro@SYSCTL_DC3_C2O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2O",
+    "location": {
+      "column": "9",
+      "line": "749",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C2O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@50971@macro@SYSCTL_DC3_C2PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2PLUS",
+    "location": {
+      "column": "9",
+      "line": "750",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C2PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51035@macro@SYSCTL_DC3_C2MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C2MINUS",
+    "location": {
+      "column": "9",
+      "line": "751",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C2MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51099@macro@SYSCTL_DC3_C1O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1O",
+    "location": {
+      "column": "9",
+      "line": "752",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C1O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51163@macro@SYSCTL_DC3_C1PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1PLUS",
+    "location": {
+      "column": "9",
+      "line": "753",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C1PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51227@macro@SYSCTL_DC3_C1MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C1MINUS",
+    "location": {
+      "column": "9",
+      "line": "754",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C1MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51291@macro@SYSCTL_DC3_C0O",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0O",
+    "location": {
+      "column": "9",
+      "line": "755",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C0O",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51355@macro@SYSCTL_DC3_C0PLUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0PLUS",
+    "location": {
+      "column": "9",
+      "line": "756",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C0PLUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51419@macro@SYSCTL_DC3_C0MINUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_C0MINUS",
+    "location": {
+      "column": "9",
+      "line": "757",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_C0MINUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51483@macro@SYSCTL_DC3_PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM5",
+    "location": {
+      "column": "9",
+      "line": "758",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51548@macro@SYSCTL_DC3_PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM4",
+    "location": {
+      "column": "9",
+      "line": "759",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51613@macro@SYSCTL_DC3_PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM3",
+    "location": {
+      "column": "9",
+      "line": "760",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51678@macro@SYSCTL_DC3_PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM2",
+    "location": {
+      "column": "9",
+      "line": "761",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51743@macro@SYSCTL_DC3_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM1",
+    "location": {
+      "column": "9",
+      "line": "762",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@51808@macro@SYSCTL_DC3_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC3_PWM0",
+    "location": {
+      "column": "9",
+      "line": "763",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC3_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52122@macro@SYSCTL_DC4_EPHY0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_EPHY0",
+    "location": {
+      "column": "9",
+      "line": "770",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_EPHY0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52199@macro@SYSCTL_DC4_EMAC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_EMAC0",
+    "location": {
+      "column": "9",
+      "line": "771",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_EMAC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52276@macro@SYSCTL_DC4_E1588",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_E1588",
+    "location": {
+      "column": "9",
+      "line": "772",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_E1588",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52337@macro@SYSCTL_DC4_PICAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_PICAL",
+    "location": {
+      "column": "9",
+      "line": "773",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_PICAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52401@macro@SYSCTL_DC4_CCP7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_CCP7",
+    "location": {
+      "column": "9",
+      "line": "774",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_CCP7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52468@macro@SYSCTL_DC4_CCP6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_CCP6",
+    "location": {
+      "column": "9",
+      "line": "775",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_CCP6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52535@macro@SYSCTL_DC4_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_UDMA",
+    "location": {
+      "column": "9",
+      "line": "776",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52608@macro@SYSCTL_DC4_ROM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_ROM",
+    "location": {
+      "column": "9",
+      "line": "777",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_ROM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52682@macro@SYSCTL_DC4_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "778",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52750@macro@SYSCTL_DC4_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "779",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52818@macro@SYSCTL_DC4_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "780",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52886@macro@SYSCTL_DC4_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "781",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@52954@macro@SYSCTL_DC4_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "782",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53022@macro@SYSCTL_DC4_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "783",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53090@macro@SYSCTL_DC4_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "784",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53158@macro@SYSCTL_DC4_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "785",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53226@macro@SYSCTL_DC4_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC4_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "786",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC4_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53543@macro@SYSCTL_DC5_PWMFAULT3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT3",
+    "location": {
+      "column": "9",
+      "line": "793",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53615@macro@SYSCTL_DC5_PWMFAULT2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT2",
+    "location": {
+      "column": "9",
+      "line": "794",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53687@macro@SYSCTL_DC5_PWMFAULT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT1",
+    "location": {
+      "column": "9",
+      "line": "795",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53759@macro@SYSCTL_DC5_PWMFAULT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMFAULT0",
+    "location": {
+      "column": "9",
+      "line": "796",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMFAULT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53831@macro@SYSCTL_DC5_PWMEFLT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMEFLT",
+    "location": {
+      "column": "9",
+      "line": "797",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMEFLT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53905@macro@SYSCTL_DC5_PWMESYNC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWMESYNC",
+    "location": {
+      "column": "9",
+      "line": "798",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWMESYNC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@53978@macro@SYSCTL_DC5_PWM7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM7",
+    "location": {
+      "column": "9",
+      "line": "799",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54043@macro@SYSCTL_DC5_PWM6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM6",
+    "location": {
+      "column": "9",
+      "line": "800",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54108@macro@SYSCTL_DC5_PWM5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM5",
+    "location": {
+      "column": "9",
+      "line": "801",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54173@macro@SYSCTL_DC5_PWM4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM4",
+    "location": {
+      "column": "9",
+      "line": "802",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54238@macro@SYSCTL_DC5_PWM3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM3",
+    "location": {
+      "column": "9",
+      "line": "803",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54303@macro@SYSCTL_DC5_PWM2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM2",
+    "location": {
+      "column": "9",
+      "line": "804",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54368@macro@SYSCTL_DC5_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM1",
+    "location": {
+      "column": "9",
+      "line": "805",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54433@macro@SYSCTL_DC5_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC5_PWM0",
+    "location": {
+      "column": "9",
+      "line": "806",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC5_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54747@macro@SYSCTL_DC6_USB0PHY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0PHY",
+    "location": {
+      "column": "9",
+      "line": "813",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC6_USB0PHY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54820@macro@SYSCTL_DC6_USB0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_M",
+    "location": {
+      "column": "9",
+      "line": "814",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC6_USB0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54889@macro@SYSCTL_DC6_USB0_DEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_DEV",
+    "location": {
+      "column": "9",
+      "line": "815",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC6_USB0_DEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@54957@macro@SYSCTL_DC6_USB0_HOSTDEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_HOSTDEV",
+    "location": {
+      "column": "9",
+      "line": "816",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC6_USB0_HOSTDEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55027@macro@SYSCTL_DC6_USB0_OTG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC6_USB0_OTG",
+    "location": {
+      "column": "9",
+      "line": "817",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC6_USB0_OTG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55336@macro@SYSCTL_DC7_DMACH30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH30",
+    "location": {
+      "column": "9",
+      "line": "824",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55399@macro@SYSCTL_DC7_DMACH29",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH29",
+    "location": {
+      "column": "9",
+      "line": "825",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH29",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55462@macro@SYSCTL_DC7_DMACH28",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH28",
+    "location": {
+      "column": "9",
+      "line": "826",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH28",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55525@macro@SYSCTL_DC7_DMACH27",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH27",
+    "location": {
+      "column": "9",
+      "line": "827",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH27",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55588@macro@SYSCTL_DC7_DMACH26",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH26",
+    "location": {
+      "column": "9",
+      "line": "828",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH26",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55651@macro@SYSCTL_DC7_DMACH25",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH25",
+    "location": {
+      "column": "9",
+      "line": "829",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH25",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55714@macro@SYSCTL_DC7_DMACH24",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH24",
+    "location": {
+      "column": "9",
+      "line": "830",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH24",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55777@macro@SYSCTL_DC7_DMACH23",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH23",
+    "location": {
+      "column": "9",
+      "line": "831",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH23",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55840@macro@SYSCTL_DC7_DMACH22",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH22",
+    "location": {
+      "column": "9",
+      "line": "832",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC7_DMACH22",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@55903@macro@SYSCTL_DC7_DMACH21",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC7_DMACH21",
+    "location": {
+      "column": "9",
+      "line": "833",
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+    },
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+    },
+    "name": "SYSCTL_DC8_ADC0AIN11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59177@macro@SYSCTL_DC8_ADC0AIN10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN10",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59256@macro@SYSCTL_DC8_ADC0AIN9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN9",
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+      "line": "883",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59334@macro@SYSCTL_DC8_ADC0AIN8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN8",
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+      "line": "884",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59412@macro@SYSCTL_DC8_ADC0AIN7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN7",
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+      "line": "885",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59490@macro@SYSCTL_DC8_ADC0AIN6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN6",
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+      "line": "886",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59568@macro@SYSCTL_DC8_ADC0AIN5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN5",
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+      "line": "887",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59646@macro@SYSCTL_DC8_ADC0AIN4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN4",
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+      "line": "888",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59724@macro@SYSCTL_DC8_ADC0AIN3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN3",
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+      "line": "889",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59802@macro@SYSCTL_DC8_ADC0AIN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN2",
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+      "line": "890",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59880@macro@SYSCTL_DC8_ADC0AIN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN1",
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+      "line": "891",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@59958@macro@SYSCTL_DC8_ADC0AIN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC8_ADC0AIN0",
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+      "line": "892",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC8_ADC0AIN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@60289@macro@SYSCTL_PBORCTL_BOR0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PBORCTL_BOR0",
+    "location": {
+      "column": "9",
+      "line": "899",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PBORCTL_BOR0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@60365@macro@SYSCTL_PBORCTL_BOR1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PBORCTL_BOR1",
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+      "line": "900",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PBORCTL_BOR1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@60694@macro@SYSCTL_PTBOCTL_VDDA_UBOR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDDA_UBOR_M",
+    "location": {
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+      "line": "907",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDDA_UBOR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@60851@macro@SYSCTL_PTBOCTL_VDDA_UBOR_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDDA_UBOR_NONE",
+    "location": {
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+      "line": "909",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDDA_UBOR_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@60990@macro@SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT",
+    "location": {
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+      "line": "911",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61144@macro@SYSCTL_PTBOCTL_VDDA_UBOR_NMI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDDA_UBOR_NMI",
+    "location": {
+      "column": "9",
+      "line": "913",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDDA_UBOR_NMI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61277@macro@SYSCTL_PTBOCTL_VDDA_UBOR_RST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDDA_UBOR_RST",
+    "location": {
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+      "line": "915",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDDA_UBOR_RST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61412@macro@SYSCTL_PTBOCTL_VDD_UBOR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDD_UBOR_M",
+    "location": {
+      "column": "9",
+      "line": "917",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDD_UBOR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61623@macro@SYSCTL_PTBOCTL_VDD_UBOR_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDD_UBOR_NONE",
+    "location": {
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+      "line": "920",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDD_UBOR_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61762@macro@SYSCTL_PTBOCTL_VDD_UBOR_SYSINT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDD_UBOR_SYSINT",
+    "location": {
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+      "line": "922",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDD_UBOR_SYSINT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@61916@macro@SYSCTL_PTBOCTL_VDD_UBOR_NMI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDD_UBOR_NMI",
+    "location": {
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+      "line": "924",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDD_UBOR_NMI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62049@macro@SYSCTL_PTBOCTL_VDD_UBOR_RST",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PTBOCTL_VDD_UBOR_RST",
+    "location": {
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+      "line": "926",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PTBOCTL_VDD_UBOR_RST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62435@macro@SYSCTL_SRCR0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_WDT1",
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+      "line": "934",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62502@macro@SYSCTL_SRCR0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_CAN1",
+    "location": {
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+      "line": "935",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62569@macro@SYSCTL_SRCR0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_CAN0",
+    "location": {
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+      "line": "936",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62636@macro@SYSCTL_SRCR0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_PWM0",
+    "location": {
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+      "line": "937",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62702@macro@SYSCTL_SRCR0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_ADC1",
+    "location": {
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+      "line": "938",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62769@macro@SYSCTL_SRCR0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "939",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62836@macro@SYSCTL_SRCR0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_HIB",
+    "location": {
+      "column": "9",
+      "line": "940",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@62902@macro@SYSCTL_SRCR0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "941",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63220@macro@SYSCTL_SRCR1_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_COMP2",
+    "location": {
+      "column": "9",
+      "line": "948",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63296@macro@SYSCTL_SRCR1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "949",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63372@macro@SYSCTL_SRCR1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "950",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63448@macro@SYSCTL_SRCR1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "951",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63518@macro@SYSCTL_SRCR1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "952",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63588@macro@SYSCTL_SRCR1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "953",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63658@macro@SYSCTL_SRCR1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_TIMER0",
+    "location": {
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+      "line": "954",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63728@macro@SYSCTL_SRCR1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_I2C1",
+    "location": {
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+      "line": "955",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63795@macro@SYSCTL_SRCR1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_I2C0",
+    "location": {
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+      "line": "956",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63862@macro@SYSCTL_SRCR1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "957",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63929@macro@SYSCTL_SRCR1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "958",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@63996@macro@SYSCTL_SRCR1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "959",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64063@macro@SYSCTL_SRCR1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "960",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64130@macro@SYSCTL_SRCR1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART2",
+    "location": {
+      "column": "9",
+      "line": "961",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64198@macro@SYSCTL_SRCR1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART1",
+    "location": {
+      "column": "9",
+      "line": "962",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64266@macro@SYSCTL_SRCR1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR1_UART0",
+    "location": {
+      "column": "9",
+      "line": "963",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64585@macro@SYSCTL_SRCR2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_USB0",
+    "location": {
+      "column": "9",
+      "line": "970",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64652@macro@SYSCTL_SRCR2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "971",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64724@macro@SYSCTL_SRCR2_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "972",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64793@macro@SYSCTL_SRCR2_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "973",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64862@macro@SYSCTL_SRCR2_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "974",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@64931@macro@SYSCTL_SRCR2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "975",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65000@macro@SYSCTL_SRCR2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "976",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65069@macro@SYSCTL_SRCR2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "977",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65138@macro@SYSCTL_SRCR2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "978",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65207@macro@SYSCTL_SRCR2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "979",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65276@macro@SYSCTL_SRCR2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCR2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "980",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCR2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65594@macro@SYSCTL_RIS_BOR0RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_BOR0RIS",
+    "location": {
+      "column": "9",
+      "line": "987",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_BOR0RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65726@macro@SYSCTL_RIS_VDDARIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_VDDARIS",
+    "location": {
+      "column": "9",
+      "line": "989",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_VDDARIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65863@macro@SYSCTL_RIS_MOSCPUPRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_MOSCPUPRIS",
+    "location": {
+      "column": "9",
+      "line": "991",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_MOSCPUPRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@65994@macro@SYSCTL_RIS_USBPLLLRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_USBPLLLRIS",
+    "location": {
+      "column": "9",
+      "line": "993",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_USBPLLLRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66124@macro@SYSCTL_RIS_PLLLRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_PLLLRIS",
+    "location": {
+      "column": "9",
+      "line": "995",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_PLLLRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66202@macro@SYSCTL_RIS_MOFRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_MOFRIS",
+    "location": {
+      "column": "9",
+      "line": "996",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_MOFRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66343@macro@SYSCTL_RIS_BOR1RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_BOR1RIS",
+    "location": {
+      "column": "9",
+      "line": "998",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_BOR1RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66475@macro@SYSCTL_RIS_BORRIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RIS_BORRIS",
+    "location": {
+      "column": "9",
+      "line": "1000",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RIS_BORRIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66857@macro@SYSCTL_IMC_BOR0IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_BOR0IM",
+    "location": {
+      "column": "9",
+      "line": "1008",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_BOR0IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@66935@macro@SYSCTL_IMC_VDDAIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_VDDAIM",
+    "location": {
+      "column": "9",
+      "line": "1009",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_VDDAIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67012@macro@SYSCTL_IMC_MOSCPUPIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_MOSCPUPIM",
+    "location": {
+      "column": "9",
+      "line": "1010",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_MOSCPUPIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67089@macro@SYSCTL_IMC_USBPLLLIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_USBPLLLIM",
+    "location": {
+      "column": "9",
+      "line": "1011",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_USBPLLLIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67165@macro@SYSCTL_IMC_PLLLIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_PLLLIM",
+    "location": {
+      "column": "9",
+      "line": "1012",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_PLLLIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67237@macro@SYSCTL_IMC_MOFIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_MOFIM",
+    "location": {
+      "column": "9",
+      "line": "1013",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_MOFIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67372@macro@SYSCTL_IMC_BORIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_BORIM",
+    "location": {
+      "column": "9",
+      "line": "1015",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_BORIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67451@macro@SYSCTL_IMC_BOR1IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_IMC_BOR1IM",
+    "location": {
+      "column": "9",
+      "line": "1016",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_IMC_BOR1IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67779@macro@SYSCTL_MISC_BOR0MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_BOR0MIS",
+    "location": {
+      "column": "9",
+      "line": "1023",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_BOR0MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@67914@macro@SYSCTL_MISC_VDDAMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_VDDAMIS",
+    "location": {
+      "column": "9",
+      "line": "1025",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_VDDAMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68048@macro@SYSCTL_MISC_MOSCPUPMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_MOSCPUPMIS",
+    "location": {
+      "column": "9",
+      "line": "1027",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_MOSCPUPMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68182@macro@SYSCTL_MISC_USBPLLLMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_USBPLLLMIS",
+    "location": {
+      "column": "9",
+      "line": "1029",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_USBPLLLMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68315@macro@SYSCTL_MISC_PLLLMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_PLLLMIS",
+    "location": {
+      "column": "9",
+      "line": "1031",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_PLLLMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68396@macro@SYSCTL_MISC_MOFMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_MOFMIS",
+    "location": {
+      "column": "9",
+      "line": "1032",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_MOFMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68540@macro@SYSCTL_MISC_BORMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_BORMIS",
+    "location": {
+      "column": "9",
+      "line": "1034",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_BORMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@68616@macro@SYSCTL_MISC_BOR1MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MISC_BOR1MIS",
+    "location": {
+      "column": "9",
+      "line": "1035",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MISC_BOR1MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69001@macro@SYSCTL_RESC_MOSCFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_MOSCFAIL",
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+      "line": "1043",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_MOSCFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69068@macro@SYSCTL_RESC_HSSR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_HSSR",
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+      "line": "1044",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_HSSR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69127@macro@SYSCTL_RESC_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_WDT1",
+    "location": {
+      "column": "9",
+      "line": "1045",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69198@macro@SYSCTL_RESC_SW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_SW",
+    "location": {
+      "column": "9",
+      "line": "1046",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_SW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69261@macro@SYSCTL_RESC_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_WDT0",
+    "location": {
+      "column": "9",
+      "line": "1047",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69332@macro@SYSCTL_RESC_BOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_BOR",
+    "location": {
+      "column": "9",
+      "line": "1048",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_BOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69396@macro@SYSCTL_RESC_POR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_POR",
+    "location": {
+      "column": "9",
+      "line": "1049",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_POR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69459@macro@SYSCTL_RESC_EXT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_EXT",
+    "location": {
+      "column": "9",
+      "line": "1050",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_EXT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69773@macro@SYSCTL_PWRTC_VDDA_UBOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWRTC_VDDA_UBOR",
+    "location": {
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+      "line": "1057",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PWRTC_VDDA_UBOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@69843@macro@SYSCTL_PWRTC_VDD_UBOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWRTC_VDD_UBOR",
+    "location": {
+      "column": "9",
+      "line": "1058",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PWRTC_VDD_UBOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70161@macro@SYSCTL_RCC_ACG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_ACG",
+    "location": {
+      "column": "9",
+      "line": "1065",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_ACG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70227@macro@SYSCTL_RCC_SYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_SYSDIV_M",
+    "location": {
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+      "line": "1066",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_SYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70296@macro@SYSCTL_RCC_USESYSDIV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_USESYSDIV",
+    "location": {
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+      "line": "1067",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_USESYSDIV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70372@macro@SYSCTL_RCC_USEPWMDIV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_USEPWMDIV",
+    "location": {
+      "column": "9",
+      "line": "1068",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_USEPWMDIV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70445@macro@SYSCTL_RCC_PWMDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_M",
+    "location": {
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+      "line": "1069",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70516@macro@SYSCTL_RCC_PWMDIV_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_2",
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+      "line": "1070",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70577@macro@SYSCTL_RCC_PWMDIV_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_4",
+    "location": {
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+      "line": "1071",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70638@macro@SYSCTL_RCC_PWMDIV_8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_8",
+    "location": {
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+      "line": "1072",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70699@macro@SYSCTL_RCC_PWMDIV_16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_16",
+    "location": {
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+      "line": "1073",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70761@macro@SYSCTL_RCC_PWMDIV_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_32",
+    "location": {
+      "column": "9",
+      "line": "1074",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70823@macro@SYSCTL_RCC_PWMDIV_64",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWMDIV_64",
+    "location": {
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+      "line": "1075",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWMDIV_64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70885@macro@SYSCTL_RCC_PWRDN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_PWRDN",
+    "location": {
+      "column": "9",
+      "line": "1076",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_PWRDN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@70948@macro@SYSCTL_RCC_BYPASS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_BYPASS",
+    "location": {
+      "column": "9",
+      "line": "1077",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_BYPASS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71007@macro@SYSCTL_RCC_XTAL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_M",
+    "location": {
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+      "line": "1078",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71069@macro@SYSCTL_RCC_XTAL_4MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_4MHZ",
+    "location": {
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+      "line": "1079",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_4MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71123@macro@SYSCTL_RCC_XTAL_4_09MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_4_09MHZ",
+    "location": {
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+      "line": "1080",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_4_09MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71181@macro@SYSCTL_RCC_XTAL_4_91MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_4_91MHZ",
+    "location": {
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+      "line": "1081",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_4_91MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71240@macro@SYSCTL_RCC_XTAL_5MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_5MHZ",
+    "location": {
+      "column": "9",
+      "line": "1082",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_5MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71294@macro@SYSCTL_RCC_XTAL_5_12MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_5_12MHZ",
+    "location": {
+      "column": "9",
+      "line": "1083",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_5_12MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71351@macro@SYSCTL_RCC_XTAL_6MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_6MHZ",
+    "location": {
+      "column": "9",
+      "line": "1084",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_6MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71405@macro@SYSCTL_RCC_XTAL_6_14MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_6_14MHZ",
+    "location": {
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+      "line": "1085",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_6_14MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71463@macro@SYSCTL_RCC_XTAL_7_37MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_7_37MHZ",
+    "location": {
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+      "line": "1086",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_7_37MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71522@macro@SYSCTL_RCC_XTAL_8MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_8MHZ",
+    "location": {
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+      "line": "1087",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_8MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71576@macro@SYSCTL_RCC_XTAL_8_19MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_8_19MHZ",
+    "location": {
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+      "line": "1088",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_8_19MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71634@macro@SYSCTL_RCC_XTAL_10MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_10MHZ",
+    "location": {
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+      "line": "1089",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_10MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71689@macro@SYSCTL_RCC_XTAL_12MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_12MHZ",
+    "location": {
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+      "line": "1090",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_12MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71744@macro@SYSCTL_RCC_XTAL_12_2MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_12_2MHZ",
+    "location": {
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+      "line": "1091",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_12_2MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71803@macro@SYSCTL_RCC_XTAL_13_5MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_13_5MHZ",
+    "location": {
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+      "line": "1092",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_13_5MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71861@macro@SYSCTL_RCC_XTAL_14_3MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_14_3MHZ",
+    "location": {
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+      "line": "1093",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_14_3MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71922@macro@SYSCTL_RCC_XTAL_16MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_16MHZ",
+    "location": {
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+      "line": "1094",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_16MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@71977@macro@SYSCTL_RCC_XTAL_16_3MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_16_3MHZ",
+    "location": {
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+      "line": "1095",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_16_3MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72036@macro@SYSCTL_RCC_XTAL_18MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_18MHZ",
+    "location": {
+      "column": "9",
+      "line": "1096",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_18MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72099@macro@SYSCTL_RCC_XTAL_20MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_20MHZ",
+    "location": {
+      "column": "9",
+      "line": "1097",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_20MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72162@macro@SYSCTL_RCC_XTAL_24MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_24MHZ",
+    "location": {
+      "column": "9",
+      "line": "1098",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_24MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72225@macro@SYSCTL_RCC_XTAL_25MHZ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_25MHZ",
+    "location": {
+      "column": "9",
+      "line": "1099",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_25MHZ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72288@macro@SYSCTL_RCC_OSCSRC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_OSCSRC_M",
+    "location": {
+      "column": "9",
+      "line": "1100",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_OSCSRC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72354@macro@SYSCTL_RCC_OSCSRC_MAIN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_OSCSRC_MAIN",
+    "location": {
+      "column": "9",
+      "line": "1101",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_OSCSRC_MAIN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72407@macro@SYSCTL_RCC_OSCSRC_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_OSCSRC_INT",
+    "location": {
+      "column": "9",
+      "line": "1102",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_OSCSRC_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72460@macro@SYSCTL_RCC_OSCSRC_INT4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_OSCSRC_INT4",
+    "location": {
+      "column": "9",
+      "line": "1103",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_OSCSRC_INT4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72515@macro@SYSCTL_RCC_OSCSRC_30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_OSCSRC_30",
+    "location": {
+      "column": "9",
+      "line": "1104",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_OSCSRC_30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72570@macro@SYSCTL_RCC_MOSCDIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_MOSCDIS",
+    "location": {
+      "column": "9",
+      "line": "1105",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_MOSCDIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72642@macro@SYSCTL_RCC_SYSDIV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_SYSDIV_S",
+    "location": {
+      "column": "9",
+      "line": "1106",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_SYSDIV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@72678@macro@SYSCTL_RCC_XTAL_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC_XTAL_S",
+    "location": {
+      "column": "9",
+      "line": "1107",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC_XTAL_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73000@macro@SYSCTL_NMIC_MOSCFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_MOSCFAIL",
+    "location": {
+      "column": "9",
+      "line": "1114",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_MOSCFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73065@macro@SYSCTL_NMIC_TAMPER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_TAMPER",
+    "location": {
+      "column": "9",
+      "line": "1115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_TAMPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73130@macro@SYSCTL_NMIC_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_WDT1",
+    "location": {
+      "column": "9",
+      "line": "1116",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73206@macro@SYSCTL_NMIC_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_WDT0",
+    "location": {
+      "column": "9",
+      "line": "1117",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73282@macro@SYSCTL_NMIC_POWER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_POWER",
+    "location": {
+      "column": "9",
+      "line": "1118",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_POWER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73356@macro@SYSCTL_NMIC_EXTERNAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMIC_EXTERNAL",
+    "location": {
+      "column": "9",
+      "line": "1119",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_NMIC_EXTERNAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73680@macro@SYSCTL_GPIOHBCTL_PORTJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTJ",
+    "location": {
+      "column": "9",
+      "line": "1127",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73813@macro@SYSCTL_GPIOHBCTL_PORTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTH",
+    "location": {
+      "column": "9",
+      "line": "1129",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@73946@macro@SYSCTL_GPIOHBCTL_PORTG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTG",
+    "location": {
+      "column": "9",
+      "line": "1131",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74079@macro@SYSCTL_GPIOHBCTL_PORTF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTF",
+    "location": {
+      "column": "9",
+      "line": "1133",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74212@macro@SYSCTL_GPIOHBCTL_PORTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTE",
+    "location": {
+      "column": "9",
+      "line": "1135",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74345@macro@SYSCTL_GPIOHBCTL_PORTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTD",
+    "location": {
+      "column": "9",
+      "line": "1137",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74478@macro@SYSCTL_GPIOHBCTL_PORTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTC",
+    "location": {
+      "column": "9",
+      "line": "1139",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74611@macro@SYSCTL_GPIOHBCTL_PORTB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTB",
+    "location": {
+      "column": "9",
+      "line": "1141",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@74744@macro@SYSCTL_GPIOHBCTL_PORTA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_GPIOHBCTL_PORTA",
+    "location": {
+      "column": "9",
+      "line": "1143",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_GPIOHBCTL_PORTA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75127@macro@SYSCTL_RCC2_USERCC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_USERCC2",
+    "location": {
+      "column": "9",
+      "line": "1151",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_USERCC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75184@macro@SYSCTL_RCC2_DIV400",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_DIV400",
+    "location": {
+      "column": "9",
+      "line": "1152",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_DIV400",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75314@macro@SYSCTL_RCC2_SYSDIV2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2_M",
+    "location": {
+      "column": "9",
+      "line": "1154",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75385@macro@SYSCTL_RCC2_SYSDIV2LSB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2LSB",
+    "location": {
+      "column": "9",
+      "line": "1155",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2LSB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75460@macro@SYSCTL_RCC2_USBPWRDN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_USBPWRDN",
+    "location": {
+      "column": "9",
+      "line": "1156",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_USBPWRDN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75527@macro@SYSCTL_RCC2_PWRDN2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_PWRDN2",
+    "location": {
+      "column": "9",
+      "line": "1157",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_PWRDN2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75592@macro@SYSCTL_RCC2_BYPASS2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_BYPASS2",
+    "location": {
+      "column": "9",
+      "line": "1158",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_BYPASS2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75653@macro@SYSCTL_RCC2_OSCSRC2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_M",
+    "location": {
+      "column": "9",
+      "line": "1159",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75721@macro@SYSCTL_RCC2_OSCSRC2_MO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_MO",
+    "location": {
+      "column": "9",
+      "line": "1160",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_MO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75774@macro@SYSCTL_RCC2_OSCSRC2_IO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_IO",
+    "location": {
+      "column": "9",
+      "line": "1161",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_IO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75828@macro@SYSCTL_RCC2_OSCSRC2_IO4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_IO4",
+    "location": {
+      "column": "9",
+      "line": "1162",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_IO4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75884@macro@SYSCTL_RCC2_OSCSRC2_30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_30",
+    "location": {
+      "column": "9",
+      "line": "1163",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75939@macro@SYSCTL_RCC2_OSCSRC2_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_OSCSRC2_32",
+    "location": {
+      "column": "9",
+      "line": "1164",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_OSCSRC2_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@75998@macro@SYSCTL_RCC2_SYSDIV2_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCC2_SYSDIV2_S",
+    "location": {
+      "column": "9",
+      "line": "1165",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCC2_SYSDIV2_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76287@macro@SYSCTL_MOSCCTL_OSCRNG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_OSCRNG",
+    "location": {
+      "column": "9",
+      "line": "1172",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL_OSCRNG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76352@macro@SYSCTL_MOSCCTL_PWRDN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_PWRDN",
+    "location": {
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+      "line": "1173",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL_PWRDN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76411@macro@SYSCTL_MOSCCTL_NOXTAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_NOXTAL",
+    "location": {
+      "column": "9",
+      "line": "1174",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL_NOXTAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76480@macro@SYSCTL_MOSCCTL_MOSCIM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_MOSCIM",
+    "location": {
+      "column": "9",
+      "line": "1175",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL_MOSCIM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76548@macro@SYSCTL_MOSCCTL_CVAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MOSCCTL_CVAL",
+    "location": {
+      "column": "9",
+      "line": "1176",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MOSCCTL_CVAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76880@macro@SYSCTL_RSCLKCFG_MEMTIMU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_MEMTIMU",
+    "location": {
+      "column": "9",
+      "line": "1184",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_MEMTIMU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@76958@macro@SYSCTL_RSCLKCFG_NEWFREQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_NEWFREQ",
+    "location": {
+      "column": "9",
+      "line": "1185",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_NEWFREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77025@macro@SYSCTL_RSCLKCFG_ACG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_ACG",
+    "location": {
+      "column": "9",
+      "line": "1186",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_ACG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77091@macro@SYSCTL_RSCLKCFG_USEPLL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_USEPLL",
+    "location": {
+      "column": "9",
+      "line": "1187",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_USEPLL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77147@macro@SYSCTL_RSCLKCFG_PLLSRC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_PLLSRC_M",
+    "location": {
+      "column": "9",
+      "line": "1188",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_PLLSRC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77287@macro@SYSCTL_RSCLKCFG_PLLSRC_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_PLLSRC_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "1190",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_PLLSRC_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77448@macro@SYSCTL_RSCLKCFG_PLLSRC_MOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_PLLSRC_MOSC",
+    "location": {
+      "column": "9",
+      "line": "1192",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_PLLSRC_MOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77660@macro@SYSCTL_RSCLKCFG_OSCSRC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSCSRC_M",
+    "location": {
+      "column": "9",
+      "line": "1195",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSCSRC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77807@macro@SYSCTL_RSCLKCFG_OSCSRC_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSCSRC_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "1197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSCSRC_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@77963@macro@SYSCTL_RSCLKCFG_OSCSRC_LFIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSCSRC_LFIOSC",
+    "location": {
+      "column": "9",
+      "line": "1199",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSCSRC_LFIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78120@macro@SYSCTL_RSCLKCFG_OSCSRC_MOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSCSRC_MOSC",
+    "location": {
+      "column": "9",
+      "line": "1201",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSCSRC_MOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78275@macro@SYSCTL_RSCLKCFG_OSCSRC_RTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSCSRC_RTC",
+    "location": {
+      "column": "9",
+      "line": "1203",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSCSRC_RTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78495@macro@SYSCTL_RSCLKCFG_OSYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSYSDIV_M",
+    "location": {
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+      "line": "1206",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78656@macro@SYSCTL_RSCLKCFG_PSYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_PSYSDIV_M",
+    "location": {
+      "column": "9",
+      "line": "1208",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_PSYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78810@macro@SYSCTL_RSCLKCFG_OSYSDIV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_OSYSDIV_S",
+    "location": {
+      "column": "9",
+      "line": "1210",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_OSYSDIV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@78927@macro@SYSCTL_RSCLKCFG_PSYSDIV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RSCLKCFG_PSYSDIV_S",
+    "location": {
+      "column": "9",
+      "line": "1212",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RSCLKCFG_PSYSDIV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79296@macro@SYSCTL_MEMTIM0_EBCHT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_M",
+    "location": {
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+      "line": "1220",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79367@macro@SYSCTL_MEMTIM0_EBCHT_0_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_0_5",
+    "location": {
+      "column": "9",
+      "line": "1221",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_0_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79520@macro@SYSCTL_MEMTIM0_EBCHT_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_1",
+    "location": {
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+      "line": "1223",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79590@macro@SYSCTL_MEMTIM0_EBCHT_1_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_1_5",
+    "location": {
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+      "line": "1224",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_1_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79744@macro@SYSCTL_MEMTIM0_EBCHT_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_2",
+    "location": {
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+      "line": "1226",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79815@macro@SYSCTL_MEMTIM0_EBCHT_2_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_2_5",
+    "location": {
+      "column": "9",
+      "line": "1227",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_2_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@79969@macro@SYSCTL_MEMTIM0_EBCHT_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_3",
+    "location": {
+      "column": "9",
+      "line": "1229",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80040@macro@SYSCTL_MEMTIM0_EBCHT_3_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_3_5",
+    "location": {
+      "column": "9",
+      "line": "1230",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_3_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80194@macro@SYSCTL_MEMTIM0_EBCHT_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_4",
+    "location": {
+      "column": "9",
+      "line": "1232",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80265@macro@SYSCTL_MEMTIM0_EBCHT_4_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCHT_4_5",
+    "location": {
+      "column": "9",
+      "line": "1233",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCHT_4_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80419@macro@SYSCTL_MEMTIM0_EBCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EBCE",
+    "location": {
+      "column": "9",
+      "line": "1235",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EBCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80490@macro@SYSCTL_MEMTIM0_MB1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_MB1",
+    "location": {
+      "column": "9",
+      "line": "1236",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_MB1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80550@macro@SYSCTL_MEMTIM0_EWS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EWS_M",
+    "location": {
+      "column": "9",
+      "line": "1237",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EWS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80617@macro@SYSCTL_MEMTIM0_FBCHT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_M",
+    "location": {
+      "column": "9",
+      "line": "1238",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80692@macro@SYSCTL_MEMTIM0_FBCHT_0_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_0_5",
+    "location": {
+      "column": "9",
+      "line": "1239",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_0_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80845@macro@SYSCTL_MEMTIM0_FBCHT_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_1",
+    "location": {
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+      "line": "1241",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@80915@macro@SYSCTL_MEMTIM0_FBCHT_1_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_1_5",
+    "location": {
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+      "line": "1242",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_1_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81069@macro@SYSCTL_MEMTIM0_FBCHT_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_2",
+    "location": {
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+      "line": "1244",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81140@macro@SYSCTL_MEMTIM0_FBCHT_2_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_2_5",
+    "location": {
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+      "line": "1245",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_2_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81294@macro@SYSCTL_MEMTIM0_FBCHT_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_3",
+    "location": {
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+      "line": "1247",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81365@macro@SYSCTL_MEMTIM0_FBCHT_3_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_3_5",
+    "location": {
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+      "line": "1248",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_3_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81519@macro@SYSCTL_MEMTIM0_FBCHT_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_4",
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+      "line": "1250",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81590@macro@SYSCTL_MEMTIM0_FBCHT_4_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCHT_4_5",
+    "location": {
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+      "line": "1251",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCHT_4_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81744@macro@SYSCTL_MEMTIM0_FBCE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FBCE",
+    "location": {
+      "column": "9",
+      "line": "1253",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FBCE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81814@macro@SYSCTL_MEMTIM0_FWS_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FWS_M",
+    "location": {
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+      "line": "1254",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FWS_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81879@macro@SYSCTL_MEMTIM0_EWS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_EWS_S",
+    "location": {
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+      "line": "1255",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_EWS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@81915@macro@SYSCTL_MEMTIM0_FWS_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_MEMTIM0_FWS_S",
+    "location": {
+      "column": "9",
+      "line": "1256",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_MEMTIM0_FWS_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82201@macro@SYSCTL_RCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_WDT1",
+    "location": {
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+      "line": "1263",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82275@macro@SYSCTL_RCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "1264",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82349@macro@SYSCTL_RCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "1265",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82423@macro@SYSCTL_RCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "1266",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82496@macro@SYSCTL_RCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "1267",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82570@macro@SYSCTL_RCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "1268",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82644@macro@SYSCTL_RCGC0_ADC1SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_M",
+    "location": {
+      "column": "9",
+      "line": "1269",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82710@macro@SYSCTL_RCGC0_ADC1SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "1270",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@82859@macro@SYSCTL_RCGC0_ADC1SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "1272",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83008@macro@SYSCTL_RCGC0_ADC1SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_500K",
+    "location": {
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+      "line": "1274",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83157@macro@SYSCTL_RCGC0_ADC1SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC1SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "1276",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC1SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83223@macro@SYSCTL_RCGC0_ADC0SPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_M",
+    "location": {
+      "column": "9",
+      "line": "1277",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83289@macro@SYSCTL_RCGC0_ADC0SPD_125K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_125K",
+    "location": {
+      "column": "9",
+      "line": "1278",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_125K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83438@macro@SYSCTL_RCGC0_ADC0SPD_250K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_250K",
+    "location": {
+      "column": "9",
+      "line": "1280",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_250K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83587@macro@SYSCTL_RCGC0_ADC0SPD_500K",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_500K",
+    "location": {
+      "column": "9",
+      "line": "1282",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_500K",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83736@macro@SYSCTL_RCGC0_ADC0SPD_1M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_ADC0SPD_1M",
+    "location": {
+      "column": "9",
+      "line": "1284",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_ADC0SPD_1M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83802@macro@SYSCTL_RCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "1285",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@83875@macro@SYSCTL_RCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "1286",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84200@macro@SYSCTL_RCGC1_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_COMP2",
+    "location": {
+      "column": "9",
+      "line": "1293",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84281@macro@SYSCTL_RCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "1294",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84362@macro@SYSCTL_RCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "1295",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84443@macro@SYSCTL_RCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "1296",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84520@macro@SYSCTL_RCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "1297",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84597@macro@SYSCTL_RCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "1298",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84674@macro@SYSCTL_RCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "1299",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84751@macro@SYSCTL_RCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "1300",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84825@macro@SYSCTL_RCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "1301",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84899@macro@SYSCTL_RCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "1302",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@84973@macro@SYSCTL_RCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "1303",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85047@macro@SYSCTL_RCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "1304",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85121@macro@SYSCTL_RCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "1305",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85195@macro@SYSCTL_RCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "1306",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85270@macro@SYSCTL_RCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "1307",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85345@macro@SYSCTL_RCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "1308",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85671@macro@SYSCTL_RCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "1315",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85745@macro@SYSCTL_RCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "1316",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85824@macro@SYSCTL_RCGC2_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "1317",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85900@macro@SYSCTL_RCGC2_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "1318",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@85976@macro@SYSCTL_RCGC2_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "1319",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86052@macro@SYSCTL_RCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "1320",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86128@macro@SYSCTL_RCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "1321",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86204@macro@SYSCTL_RCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "1322",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86280@macro@SYSCTL_RCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "1323",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86356@macro@SYSCTL_RCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "1324",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86432@macro@SYSCTL_RCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "1325",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86759@macro@SYSCTL_SCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "1332",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86833@macro@SYSCTL_SCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "1333",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86907@macro@SYSCTL_SCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "1334",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@86981@macro@SYSCTL_SCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "1335",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87054@macro@SYSCTL_SCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "1336",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87128@macro@SYSCTL_SCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "1337",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87202@macro@SYSCTL_SCGC0_ADCSPD_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_ADCSPD_M",
+    "location": {
+      "column": "9",
+      "line": "1338",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_ADCSPD_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87267@macro@SYSCTL_SCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "1339",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87340@macro@SYSCTL_SCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "1340",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87665@macro@SYSCTL_SCGC1_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_COMP2",
+    "location": {
+      "column": "9",
+      "line": "1347",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87746@macro@SYSCTL_SCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "1348",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87827@macro@SYSCTL_SCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "1349",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87908@macro@SYSCTL_SCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "1350",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@87985@macro@SYSCTL_SCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "1351",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88062@macro@SYSCTL_SCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "1352",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88139@macro@SYSCTL_SCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "1353",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88216@macro@SYSCTL_SCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "1354",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88290@macro@SYSCTL_SCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "1355",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88364@macro@SYSCTL_SCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "1356",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88438@macro@SYSCTL_SCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "1357",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88512@macro@SYSCTL_SCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "1358",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88586@macro@SYSCTL_SCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "1359",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88660@macro@SYSCTL_SCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "1360",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88735@macro@SYSCTL_SCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "1361",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@88810@macro@SYSCTL_SCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "1362",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89136@macro@SYSCTL_SCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "1369",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89210@macro@SYSCTL_SCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "1370",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89289@macro@SYSCTL_SCGC2_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "1371",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89365@macro@SYSCTL_SCGC2_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "1372",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89441@macro@SYSCTL_SCGC2_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "1373",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89517@macro@SYSCTL_SCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "1374",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89593@macro@SYSCTL_SCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "1375",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89669@macro@SYSCTL_SCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "1376",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89745@macro@SYSCTL_SCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "1377",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89821@macro@SYSCTL_SCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "1378",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@89897@macro@SYSCTL_SCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "1379",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90224@macro@SYSCTL_DCGC0_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_WDT1",
+    "location": {
+      "column": "9",
+      "line": "1386",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90298@macro@SYSCTL_DCGC0_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_CAN1",
+    "location": {
+      "column": "9",
+      "line": "1387",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90372@macro@SYSCTL_DCGC0_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_CAN0",
+    "location": {
+      "column": "9",
+      "line": "1388",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90446@macro@SYSCTL_DCGC0_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_PWM0",
+    "location": {
+      "column": "9",
+      "line": "1389",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90519@macro@SYSCTL_DCGC0_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_ADC1",
+    "location": {
+      "column": "9",
+      "line": "1390",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90593@macro@SYSCTL_DCGC0_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_ADC0",
+    "location": {
+      "column": "9",
+      "line": "1391",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90667@macro@SYSCTL_DCGC0_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_HIB",
+    "location": {
+      "column": "9",
+      "line": "1392",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@90740@macro@SYSCTL_DCGC0_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC0_WDT0",
+    "location": {
+      "column": "9",
+      "line": "1393",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC0_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91065@macro@SYSCTL_DCGC1_COMP2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_COMP2",
+    "location": {
+      "column": "9",
+      "line": "1400",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_COMP2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91146@macro@SYSCTL_DCGC1_COMP1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_COMP1",
+    "location": {
+      "column": "9",
+      "line": "1401",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_COMP1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91227@macro@SYSCTL_DCGC1_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_COMP0",
+    "location": {
+      "column": "9",
+      "line": "1402",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91308@macro@SYSCTL_DCGC1_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "1403",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91385@macro@SYSCTL_DCGC1_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "1404",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91462@macro@SYSCTL_DCGC1_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "1405",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91539@macro@SYSCTL_DCGC1_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "1406",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91616@macro@SYSCTL_DCGC1_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_I2C1",
+    "location": {
+      "column": "9",
+      "line": "1407",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91690@macro@SYSCTL_DCGC1_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_I2C0",
+    "location": {
+      "column": "9",
+      "line": "1408",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91764@macro@SYSCTL_DCGC1_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_QEI1",
+    "location": {
+      "column": "9",
+      "line": "1409",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91838@macro@SYSCTL_DCGC1_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_QEI0",
+    "location": {
+      "column": "9",
+      "line": "1410",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91912@macro@SYSCTL_DCGC1_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_SSI1",
+    "location": {
+      "column": "9",
+      "line": "1411",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@91986@macro@SYSCTL_DCGC1_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_SSI0",
+    "location": {
+      "column": "9",
+      "line": "1412",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92060@macro@SYSCTL_DCGC1_UART2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART2",
+    "location": {
+      "column": "9",
+      "line": "1413",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_UART2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92135@macro@SYSCTL_DCGC1_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART1",
+    "location": {
+      "column": "9",
+      "line": "1414",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92210@macro@SYSCTL_DCGC1_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC1_UART0",
+    "location": {
+      "column": "9",
+      "line": "1415",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC1_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92536@macro@SYSCTL_DCGC2_USB0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_USB0",
+    "location": {
+      "column": "9",
+      "line": "1422",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92610@macro@SYSCTL_DCGC2_UDMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_UDMA",
+    "location": {
+      "column": "9",
+      "line": "1423",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92689@macro@SYSCTL_DCGC2_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "1424",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92765@macro@SYSCTL_DCGC2_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "1425",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92841@macro@SYSCTL_DCGC2_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "1426",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92917@macro@SYSCTL_DCGC2_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "1427",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@92993@macro@SYSCTL_DCGC2_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "1428",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93069@macro@SYSCTL_DCGC2_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "1429",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93145@macro@SYSCTL_DCGC2_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "1430",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93221@macro@SYSCTL_DCGC2_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "1431",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93297@macro@SYSCTL_DCGC2_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGC2_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "1432",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGC2_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93632@macro@SYSCTL_ALTCLKCFG_ALTCLK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLKCFG_ALTCLK_M",
+    "location": {
+      "column": "9",
+      "line": "1440",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLKCFG_ALTCLK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93784@macro@SYSCTL_ALTCLKCFG_ALTCLK_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLKCFG_ALTCLK_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "1442",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLKCFG_ALTCLK_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@93919@macro@SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC",
+    "location": {
+      "column": "9",
+      "line": "1444",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94147@macro@SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC",
+    "location": {
+      "column": "9",
+      "line": "1447",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94627@macro@SYSCTL_DSLPCLKCFG_D_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_D_M",
+    "location": {
+      "column": "9",
+      "line": "1457",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_D_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94698@macro@SYSCTL_DSLPCLKCFG_O_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_M",
+    "location": {
+      "column": "9",
+      "line": "1458",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94759@macro@SYSCTL_DSLPCLKCFG_O_IGN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_IGN",
+    "location": {
+      "column": "9",
+      "line": "1459",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_IGN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94812@macro@SYSCTL_DSLPCLKCFG_O_IO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_IO",
+    "location": {
+      "column": "9",
+      "line": "1460",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_IO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94866@macro@SYSCTL_DSLPCLKCFG_O_30",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_30",
+    "location": {
+      "column": "9",
+      "line": "1461",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_30",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94921@macro@SYSCTL_DSLPCLKCFG_O_32",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_O_32",
+    "location": {
+      "column": "9",
+      "line": "1462",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_O_32",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@94980@macro@SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "location": {
+      "column": "9",
+      "line": "1463",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_PIOSCPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95134@macro@SYSCTL_DSLPCLKCFG_D_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPCLKCFG_D_S",
+    "location": {
+      "column": "9",
+      "line": "1465",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPCLKCFG_D_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95428@macro@SYSCTL_DSCLKCFG_PIOSCPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_PIOSCPD",
+    "location": {
+      "column": "9",
+      "line": "1473",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_PIOSCPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95493@macro@SYSCTL_DSCLKCFG_MOSCDPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_MOSCDPD",
+    "location": {
+      "column": "9",
+      "line": "1474",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_MOSCDPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95565@macro@SYSCTL_DSCLKCFG_DSOSCSRC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSOSCSRC_M",
+    "location": {
+      "column": "9",
+      "line": "1475",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSOSCSRC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95723@macro@SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "1477",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95858@macro@SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC",
+    "location": {
+      "column": "9",
+      "line": "1479",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@95994@macro@SYSCTL_DSCLKCFG_DSOSCSRC_MOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSOSCSRC_MOSC",
+    "location": {
+      "column": "9",
+      "line": "1481",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSOSCSRC_MOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96128@macro@SYSCTL_DSCLKCFG_DSOSCSRC_RTC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSOSCSRC_RTC",
+    "location": {
+      "column": "9",
+      "line": "1483",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSOSCSRC_RTC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96283@macro@SYSCTL_DSCLKCFG_DSSYSDIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSSYSDIV_M",
+    "location": {
+      "column": "9",
+      "line": "1485",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSSYSDIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96437@macro@SYSCTL_DSCLKCFG_DSSYSDIV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSCLKCFG_DSSYSDIV_S",
+    "location": {
+      "column": "9",
+      "line": "1487",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSCLKCFG_DSSYSDIV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96806@macro@SYSCTL_DIVSCLK_EN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_EN",
+    "location": {
+      "column": "9",
+      "line": "1495",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_EN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96869@macro@SYSCTL_DIVSCLK_SRC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_SRC_M",
+    "location": {
+      "column": "9",
+      "line": "1496",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_SRC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@96930@macro@SYSCTL_DIVSCLK_SRC_SYSCLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_SRC_SYSCLK",
+    "location": {
+      "column": "9",
+      "line": "1497",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_SRC_SYSCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97072@macro@SYSCTL_DIVSCLK_SRC_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_SRC_PIOSC",
+    "location": {
+      "column": "9",
+      "line": "1499",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_SRC_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97207@macro@SYSCTL_DIVSCLK_SRC_MOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_SRC_MOSC",
+    "location": {
+      "column": "9",
+      "line": "1501",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_SRC_MOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97260@macro@SYSCTL_DIVSCLK_DIV_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_DIV_M",
+    "location": {
+      "column": "9",
+      "line": "1502",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_DIV_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97322@macro@SYSCTL_DIVSCLK_DIV_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DIVSCLK_DIV_S",
+    "location": {
+      "column": "9",
+      "line": "1503",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DIVSCLK_DIV_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97610@macro@SYSCTL_SYSPROP_FPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SYSPROP_FPU",
+    "location": {
+      "column": "9",
+      "line": "1510",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SYSPROP_FPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97928@macro@SYSCTL_PIOSCCAL_UTEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UTEN",
+    "location": {
+      "column": "9",
+      "line": "1518",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UTEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@97996@macro@SYSCTL_PIOSCCAL_CAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_CAL",
+    "location": {
+      "column": "9",
+      "line": "1519",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_CAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98062@macro@SYSCTL_PIOSCCAL_UPDATE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UPDATE",
+    "location": {
+      "column": "9",
+      "line": "1520",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UPDATE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98122@macro@SYSCTL_PIOSCCAL_UT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UT_M",
+    "location": {
+      "column": "9",
+      "line": "1521",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98186@macro@SYSCTL_PIOSCCAL_UT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCCAL_UT_S",
+    "location": {
+      "column": "9",
+      "line": "1522",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCCAL_UT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98480@macro@SYSCTL_PIOSCSTAT_DT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_DT_M",
+    "location": {
+      "column": "9",
+      "line": "1530",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_DT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98547@macro@SYSCTL_PIOSCSTAT_CR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CR_M",
+    "location": {
+      "column": "9",
+      "line": "1531",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98614@macro@SYSCTL_PIOSCSTAT_CRNONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRNONE",
+    "location": {
+      "column": "9",
+      "line": "1532",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRNONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98745@macro@SYSCTL_PIOSCSTAT_CRPASS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRPASS",
+    "location": {
+      "column": "9",
+      "line": "1534",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRPASS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@98902@macro@SYSCTL_PIOSCSTAT_CRFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CRFAIL",
+    "location": {
+      "column": "9",
+      "line": "1536",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CRFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99056@macro@SYSCTL_PIOSCSTAT_CT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CT_M",
+    "location": {
+      "column": "9",
+      "line": "1538",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99127@macro@SYSCTL_PIOSCSTAT_DT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_DT_S",
+    "location": {
+      "column": "9",
+      "line": "1539",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_DT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99163@macro@SYSCTL_PIOSCSTAT_CT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PIOSCSTAT_CT_S",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PIOSCSTAT_CT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99456@macro@SYSCTL_PLLFREQ0_PLLPWR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_PLLPWR",
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+      "line": "1548",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_PLLPWR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99514@macro@SYSCTL_PLLFREQ0_MFRAC_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MFRAC_M",
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+      "line": "1549",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MFRAC_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99585@macro@SYSCTL_PLLFREQ0_MINT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MINT_M",
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+      "line": "1550",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MINT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99653@macro@SYSCTL_PLLFREQ0_MFRAC_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MFRAC_S",
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+      "line": "1551",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MFRAC_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99689@macro@SYSCTL_PLLFREQ0_MINT_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ0_MINT_S",
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+      "line": "1552",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ0_MINT_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@99982@macro@SYSCTL_PLLFREQ1_Q_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_Q_M",
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+      "line": "1560",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_Q_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100042@macro@SYSCTL_PLLFREQ1_N_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_N_M",
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+      "line": "1561",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_N_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100102@macro@SYSCTL_PLLFREQ1_Q_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_Q_S",
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+      "line": "1562",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_Q_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100137@macro@SYSCTL_PLLFREQ1_N_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLFREQ1_N_S",
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+      "line": "1563",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLFREQ1_N_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100425@macro@SYSCTL_PLLSTAT_LOCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PLLSTAT_LOCK",
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+      "line": "1570",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PLLSTAT_LOCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100741@macro@SYSCTL_SLPPWRCFG_FLASHPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_M",
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+      "line": "1578",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@100888@macro@SYSCTL_SLPPWRCFG_FLASHPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_NRM",
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+      "line": "1580",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@101029@macro@SYSCTL_SLPPWRCFG_FLASHPM_SLP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_FLASHPM_SLP",
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+      "line": "1582",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_FLASHPM_SLP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@101173@macro@SYSCTL_SLPPWRCFG_SRAMPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_M",
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+      "line": "1584",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@101319@macro@SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "location": {
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+      "line": "1586",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@101460@macro@SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "location": {
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+      "line": "1588",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_SBY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@101602@macro@SYSCTL_SLPPWRCFG_SRAMPM_LP",
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+    "display": "SYSCTL_SLPPWRCFG_SRAMPM_LP",
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+      "line": "1590",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SLPPWRCFG_SRAMPM_LP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102006@macro@SYSCTL_DSLPPWRCFG_LDOSM",
+    "What": "MacroDef",
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+    "display": "SYSCTL_DSLPPWRCFG_LDOSM",
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+      "line": "1599",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_LDOSM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102069@macro@SYSCTL_DSLPPWRCFG_TSPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_TSPD",
+    "location": {
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+      "line": "1600",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_TSPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102146@macro@SYSCTL_DSLPPWRCFG_FLASHPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_M",
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+      "line": "1601",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102293@macro@SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "location": {
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+      "line": "1603",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102434@macro@SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "location": {
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+      "line": "1605",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_FLASHPM_SLP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102578@macro@SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "location": {
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+      "line": "1607",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102724@macro@SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "location": {
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+      "line": "1609",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_NRM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@102865@macro@SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "location": {
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+      "line": "1611",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_SBY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103007@macro@SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "location": {
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+      "line": "1613",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DSLPPWRCFG_SRAMPM_LP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103400@macro@SYSCTL_DC9_ADC1DC7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC7",
+    "location": {
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+      "line": "1621",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103465@macro@SYSCTL_DC9_ADC1DC6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC6",
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+      "line": "1622",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103530@macro@SYSCTL_DC9_ADC1DC5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC5",
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+      "line": "1623",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103595@macro@SYSCTL_DC9_ADC1DC4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC4",
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+      "line": "1624",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103660@macro@SYSCTL_DC9_ADC1DC3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC3",
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+      "line": "1625",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103725@macro@SYSCTL_DC9_ADC1DC2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC2",
+    "location": {
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+      "line": "1626",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103790@macro@SYSCTL_DC9_ADC1DC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC1",
+    "location": {
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+      "line": "1627",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103855@macro@SYSCTL_DC9_ADC1DC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC1DC0",
+    "location": {
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+      "line": "1628",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC1DC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103920@macro@SYSCTL_DC9_ADC0DC7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC7",
+    "location": {
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+      "line": "1629",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@103985@macro@SYSCTL_DC9_ADC0DC6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC6",
+    "location": {
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+      "line": "1630",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@104050@macro@SYSCTL_DC9_ADC0DC5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC5",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@104115@macro@SYSCTL_DC9_ADC0DC4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC4",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DC9_ADC0DC4",
+    "origin": "user_include",
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+  },
+  {
+    "ID": "c:hw_sysctl.h@104180@macro@SYSCTL_DC9_ADC0DC3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DC9_ADC0DC3",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_HSSR_CDOFF_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@111929@macro@SYSCTL_HSSR_KEY_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_HSSR_KEY_S",
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+      "line": "1756",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_HSSR_KEY_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@111965@macro@SYSCTL_HSSR_CDOFF_S",
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+    "defdec": "Def",
+    "display": "SYSCTL_HSSR_CDOFF_S",
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+      "line": "1757",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_HSSR_CDOFF_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112252@macro@SYSCTL_USBPDS_MEMSTAT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_MEMSTAT_M",
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+      "line": "1764",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_MEMSTAT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112326@macro@SYSCTL_USBPDS_MEMSTAT_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_MEMSTAT_OFF",
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+      "line": "1765",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_MEMSTAT_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112465@macro@SYSCTL_USBPDS_MEMSTAT_RETAIN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_MEMSTAT_RETAIN",
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+      "line": "1767",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_MEMSTAT_RETAIN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112609@macro@SYSCTL_USBPDS_MEMSTAT_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_MEMSTAT_ON",
+    "location": {
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+      "line": "1769",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_MEMSTAT_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112747@macro@SYSCTL_USBPDS_PWRSTAT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_PWRSTAT_M",
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+      "line": "1771",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_PWRSTAT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112815@macro@SYSCTL_USBPDS_PWRSTAT_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_PWRSTAT_OFF",
+    "location": {
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+      "line": "1772",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_PWRSTAT_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@112948@macro@SYSCTL_USBPDS_PWRSTAT_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBPDS_PWRSTAT_ON",
+    "location": {
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+      "line": "1774",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBPDS_PWRSTAT_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@113332@macro@SYSCTL_USBMPC_PWRCTL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBMPC_PWRCTL_M",
+    "location": {
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+      "line": "1782",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBMPC_PWRCTL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@113407@macro@SYSCTL_USBMPC_PWRCTL_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBMPC_PWRCTL_OFF",
+    "location": {
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+      "line": "1783",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBMPC_PWRCTL_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@113546@macro@SYSCTL_USBMPC_PWRCTL_RETAIN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBMPC_PWRCTL_RETAIN",
+    "location": {
+      "column": "9",
+      "line": "1785",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBMPC_PWRCTL_RETAIN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@113690@macro@SYSCTL_USBMPC_PWRCTL_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_USBMPC_PWRCTL_ON",
+    "location": {
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+      "line": "1787",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_USBMPC_PWRCTL_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114000@macro@SYSCTL_EMACPDS_MEMSTAT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_MEMSTAT_M",
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+      "line": "1794",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_MEMSTAT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114155@macro@SYSCTL_EMACPDS_MEMSTAT_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_MEMSTAT_OFF",
+    "location": {
+      "column": "9",
+      "line": "1796",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_MEMSTAT_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114294@macro@SYSCTL_EMACPDS_MEMSTAT_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_MEMSTAT_ON",
+    "location": {
+      "column": "9",
+      "line": "1798",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_MEMSTAT_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114432@macro@SYSCTL_EMACPDS_PWRSTAT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_PWRSTAT_M",
+    "location": {
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+      "line": "1800",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_PWRSTAT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114581@macro@SYSCTL_EMACPDS_PWRSTAT_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_PWRSTAT_OFF",
+    "location": {
+      "column": "9",
+      "line": "1802",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_PWRSTAT_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@114714@macro@SYSCTL_EMACPDS_PWRSTAT_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACPDS_PWRSTAT_ON",
+    "location": {
+      "column": "9",
+      "line": "1804",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACPDS_PWRSTAT_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115099@macro@SYSCTL_EMACMPC_PWRCTL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACMPC_PWRCTL_M",
+    "location": {
+      "column": "9",
+      "line": "1812",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACMPC_PWRCTL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115174@macro@SYSCTL_EMACMPC_PWRCTL_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACMPC_PWRCTL_OFF",
+    "location": {
+      "column": "9",
+      "line": "1813",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACMPC_PWRCTL_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115313@macro@SYSCTL_EMACMPC_PWRCTL_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_EMACMPC_PWRCTL_ON",
+    "location": {
+      "column": "9",
+      "line": "1815",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_EMACMPC_PWRCTL_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115703@macro@SYSCTL_LCDMPC_PWRCTL_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LCDMPC_PWRCTL_M",
+    "location": {
+      "column": "9",
+      "line": "1823",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LCDMPC_PWRCTL_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115778@macro@SYSCTL_LCDMPC_PWRCTL_OFF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LCDMPC_PWRCTL_OFF",
+    "location": {
+      "column": "9",
+      "line": "1824",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LCDMPC_PWRCTL_OFF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@115917@macro@SYSCTL_LCDMPC_PWRCTL_ON",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_LCDMPC_PWRCTL_ON",
+    "location": {
+      "column": "9",
+      "line": "1826",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_LCDMPC_PWRCTL_ON",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@116224@macro@SYSCTL_PPWD_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD_P1",
+    "location": {
+      "column": "9",
+      "line": "1833",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWD_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@116297@macro@SYSCTL_PPWD_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWD_P0",
+    "location": {
+      "column": "9",
+      "line": "1834",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWD_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@116623@macro@SYSCTL_PPTIMER_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P7",
+    "location": {
+      "column": "9",
+      "line": "1841",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@116761@macro@SYSCTL_PPTIMER_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P6",
+    "location": {
+      "column": "9",
+      "line": "1843",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@116899@macro@SYSCTL_PPTIMER_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P5",
+    "location": {
+      "column": "9",
+      "line": "1845",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117037@macro@SYSCTL_PPTIMER_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P4",
+    "location": {
+      "column": "9",
+      "line": "1847",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117175@macro@SYSCTL_PPTIMER_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P3",
+    "location": {
+      "column": "9",
+      "line": "1849",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117313@macro@SYSCTL_PPTIMER_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P2",
+    "location": {
+      "column": "9",
+      "line": "1851",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117451@macro@SYSCTL_PPTIMER_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P1",
+    "location": {
+      "column": "9",
+      "line": "1853",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117589@macro@SYSCTL_PPTIMER_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPTIMER_P0",
+    "location": {
+      "column": "9",
+      "line": "1855",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPTIMER_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@117979@macro@SYSCTL_PPGPIO_P17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P17",
+    "location": {
+      "column": "9",
+      "line": "1863",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118047@macro@SYSCTL_PPGPIO_P16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P16",
+    "location": {
+      "column": "9",
+      "line": "1864",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118115@macro@SYSCTL_PPGPIO_P15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P15",
+    "location": {
+      "column": "9",
+      "line": "1865",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118183@macro@SYSCTL_PPGPIO_P14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P14",
+    "location": {
+      "column": "9",
+      "line": "1866",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118251@macro@SYSCTL_PPGPIO_P13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P13",
+    "location": {
+      "column": "9",
+      "line": "1867",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118319@macro@SYSCTL_PPGPIO_P12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P12",
+    "location": {
+      "column": "9",
+      "line": "1868",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118387@macro@SYSCTL_PPGPIO_P11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P11",
+    "location": {
+      "column": "9",
+      "line": "1869",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118455@macro@SYSCTL_PPGPIO_P10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P10",
+    "location": {
+      "column": "9",
+      "line": "1870",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118523@macro@SYSCTL_PPGPIO_P9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P9",
+    "location": {
+      "column": "9",
+      "line": "1871",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118591@macro@SYSCTL_PPGPIO_P8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P8",
+    "location": {
+      "column": "9",
+      "line": "1872",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118659@macro@SYSCTL_PPGPIO_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P7",
+    "location": {
+      "column": "9",
+      "line": "1873",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118727@macro@SYSCTL_PPGPIO_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P6",
+    "location": {
+      "column": "9",
+      "line": "1874",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118795@macro@SYSCTL_PPGPIO_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P5",
+    "location": {
+      "column": "9",
+      "line": "1875",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118863@macro@SYSCTL_PPGPIO_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P4",
+    "location": {
+      "column": "9",
+      "line": "1876",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118931@macro@SYSCTL_PPGPIO_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P3",
+    "location": {
+      "column": "9",
+      "line": "1877",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@118999@macro@SYSCTL_PPGPIO_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P2",
+    "location": {
+      "column": "9",
+      "line": "1878",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@119067@macro@SYSCTL_PPGPIO_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P1",
+    "location": {
+      "column": "9",
+      "line": "1879",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@119135@macro@SYSCTL_PPGPIO_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPGPIO_P0",
+    "location": {
+      "column": "9",
+      "line": "1880",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPGPIO_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@119454@macro@SYSCTL_PPDMA_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPDMA_P0",
+    "location": {
+      "column": "9",
+      "line": "1887",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPDMA_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@119773@macro@SYSCTL_PPEPI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEPI_P0",
+    "location": {
+      "column": "9",
+      "line": "1894",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEPI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120091@macro@SYSCTL_PPHIB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIB_P0",
+    "location": {
+      "column": "9",
+      "line": "1901",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPHIB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120418@macro@SYSCTL_PPUART_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P7",
+    "location": {
+      "column": "9",
+      "line": "1908",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120488@macro@SYSCTL_PPUART_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P6",
+    "location": {
+      "column": "9",
+      "line": "1909",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120558@macro@SYSCTL_PPUART_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P5",
+    "location": {
+      "column": "9",
+      "line": "1910",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120628@macro@SYSCTL_PPUART_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P4",
+    "location": {
+      "column": "9",
+      "line": "1911",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120698@macro@SYSCTL_PPUART_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P3",
+    "location": {
+      "column": "9",
+      "line": "1912",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120768@macro@SYSCTL_PPUART_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P2",
+    "location": {
+      "column": "9",
+      "line": "1913",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120838@macro@SYSCTL_PPUART_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P1",
+    "location": {
+      "column": "9",
+      "line": "1914",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@120908@macro@SYSCTL_PPUART_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUART_P0",
+    "location": {
+      "column": "9",
+      "line": "1915",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUART_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121229@macro@SYSCTL_PPSSI_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P3",
+    "location": {
+      "column": "9",
+      "line": "1922",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPSSI_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121298@macro@SYSCTL_PPSSI_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P2",
+    "location": {
+      "column": "9",
+      "line": "1923",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPSSI_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121367@macro@SYSCTL_PPSSI_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P1",
+    "location": {
+      "column": "9",
+      "line": "1924",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPSSI_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121436@macro@SYSCTL_PPSSI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPSSI_P0",
+    "location": {
+      "column": "9",
+      "line": "1925",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPSSI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121756@macro@SYSCTL_PPI2C_P9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P9",
+    "location": {
+      "column": "9",
+      "line": "1932",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121825@macro@SYSCTL_PPI2C_P8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P8",
+    "location": {
+      "column": "9",
+      "line": "1933",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121894@macro@SYSCTL_PPI2C_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P7",
+    "location": {
+      "column": "9",
+      "line": "1934",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@121963@macro@SYSCTL_PPI2C_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P6",
+    "location": {
+      "column": "9",
+      "line": "1935",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122032@macro@SYSCTL_PPI2C_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P5",
+    "location": {
+      "column": "9",
+      "line": "1936",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122101@macro@SYSCTL_PPI2C_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P4",
+    "location": {
+      "column": "9",
+      "line": "1937",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122170@macro@SYSCTL_PPI2C_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P3",
+    "location": {
+      "column": "9",
+      "line": "1938",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122239@macro@SYSCTL_PPI2C_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P2",
+    "location": {
+      "column": "9",
+      "line": "1939",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122308@macro@SYSCTL_PPI2C_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P1",
+    "location": {
+      "column": "9",
+      "line": "1940",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122377@macro@SYSCTL_PPI2C_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPI2C_P0",
+    "location": {
+      "column": "9",
+      "line": "1941",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPI2C_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@122697@macro@SYSCTL_PPUSB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPUSB_P0",
+    "location": {
+      "column": "9",
+      "line": "1948",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPUSB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@123016@macro@SYSCTL_PPEPHY_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEPHY_P0",
+    "location": {
+      "column": "9",
+      "line": "1955",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEPHY_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@123343@macro@SYSCTL_PPCAN_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN_P1",
+    "location": {
+      "column": "9",
+      "line": "1962",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPCAN_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@123412@macro@SYSCTL_PPCAN_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCAN_P0",
+    "location": {
+      "column": "9",
+      "line": "1963",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPCAN_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@123732@macro@SYSCTL_PPADC_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC_P1",
+    "location": {
+      "column": "9",
+      "line": "1970",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPADC_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@123801@macro@SYSCTL_PPADC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPADC_P0",
+    "location": {
+      "column": "9",
+      "line": "1971",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPADC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@124122@macro@SYSCTL_PPACMP_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPACMP_P0",
+    "location": {
+      "column": "9",
+      "line": "1978",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPACMP_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@124454@macro@SYSCTL_PPPWM_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM_P1",
+    "location": {
+      "column": "9",
+      "line": "1985",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPPWM_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@124523@macro@SYSCTL_PPPWM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPWM_P0",
+    "location": {
+      "column": "9",
+      "line": "1986",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPPWM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@124843@macro@SYSCTL_PPQEI_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI_P1",
+    "location": {
+      "column": "9",
+      "line": "1993",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPQEI_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@124912@macro@SYSCTL_PPQEI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPQEI_P0",
+    "location": {
+      "column": "9",
+      "line": "1994",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPQEI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@125232@macro@SYSCTL_PPLPC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPLPC_P0",
+    "location": {
+      "column": "9",
+      "line": "2001",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPLPC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@125551@macro@SYSCTL_PPPECI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPPECI_P0",
+    "location": {
+      "column": "9",
+      "line": "2008",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPPECI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@125870@macro@SYSCTL_PPFAN_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPFAN_P0",
+    "location": {
+      "column": "9",
+      "line": "2015",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPFAN_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@126197@macro@SYSCTL_PPEEPROM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEEPROM_P0",
+    "location": {
+      "column": "9",
+      "line": "2023",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEEPROM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@126525@macro@SYSCTL_PPWTIMER_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P5",
+    "location": {
+      "column": "9",
+      "line": "2031",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@126668@macro@SYSCTL_PPWTIMER_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P4",
+    "location": {
+      "column": "9",
+      "line": "2033",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@126811@macro@SYSCTL_PPWTIMER_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P3",
+    "location": {
+      "column": "9",
+      "line": "2035",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@126954@macro@SYSCTL_PPWTIMER_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P2",
+    "location": {
+      "column": "9",
+      "line": "2037",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@127097@macro@SYSCTL_PPWTIMER_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P1",
+    "location": {
+      "column": "9",
+      "line": "2039",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@127240@macro@SYSCTL_PPWTIMER_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPWTIMER_P0",
+    "location": {
+      "column": "9",
+      "line": "2041",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPWTIMER_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@127634@macro@SYSCTL_PPRTS_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPRTS_P0",
+    "location": {
+      "column": "9",
+      "line": "2049",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPRTS_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@127952@macro@SYSCTL_PPCCM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPCCM_P0",
+    "location": {
+      "column": "9",
+      "line": "2056",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPCCM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@128337@macro@SYSCTL_PPLCD_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPLCD_P0",
+    "location": {
+      "column": "9",
+      "line": "2064",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPLCD_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@128657@macro@SYSCTL_PPOWIRE_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPOWIRE_P0",
+    "location": {
+      "column": "9",
+      "line": "2071",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPOWIRE_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@128979@macro@SYSCTL_PPEMAC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPEMAC_P0",
+    "location": {
+      "column": "9",
+      "line": "2078",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPEMAC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@129361@macro@SYSCTL_PPHIM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PPHIM_P0",
+    "location": {
+      "column": "9",
+      "line": "2086",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PPHIM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@129678@macro@SYSCTL_SRWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD_R1",
+    "location": {
+      "column": "9",
+      "line": "2093",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@129758@macro@SYSCTL_SRWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWD_R0",
+    "location": {
+      "column": "9",
+      "line": "2094",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130091@macro@SYSCTL_SRTIMER_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R7",
+    "location": {
+      "column": "9",
+      "line": "2101",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130236@macro@SYSCTL_SRTIMER_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R6",
+    "location": {
+      "column": "9",
+      "line": "2103",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130381@macro@SYSCTL_SRTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "2105",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130526@macro@SYSCTL_SRTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "2107",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130671@macro@SYSCTL_SRTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "2109",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130816@macro@SYSCTL_SRTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "2111",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@130961@macro@SYSCTL_SRTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "2113",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131106@macro@SYSCTL_SRTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "2115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131503@macro@SYSCTL_SRGPIO_R17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R17",
+    "location": {
+      "column": "9",
+      "line": "2123",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131578@macro@SYSCTL_SRGPIO_R16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R16",
+    "location": {
+      "column": "9",
+      "line": "2124",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131653@macro@SYSCTL_SRGPIO_R15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R15",
+    "location": {
+      "column": "9",
+      "line": "2125",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131728@macro@SYSCTL_SRGPIO_R14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R14",
+    "location": {
+      "column": "9",
+      "line": "2126",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131803@macro@SYSCTL_SRGPIO_R13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R13",
+    "location": {
+      "column": "9",
+      "line": "2127",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131878@macro@SYSCTL_SRGPIO_R12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R12",
+    "location": {
+      "column": "9",
+      "line": "2128",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@131953@macro@SYSCTL_SRGPIO_R11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R11",
+    "location": {
+      "column": "9",
+      "line": "2129",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132028@macro@SYSCTL_SRGPIO_R10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R10",
+    "location": {
+      "column": "9",
+      "line": "2130",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132103@macro@SYSCTL_SRGPIO_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R9",
+    "location": {
+      "column": "9",
+      "line": "2131",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132178@macro@SYSCTL_SRGPIO_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R8",
+    "location": {
+      "column": "9",
+      "line": "2132",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132253@macro@SYSCTL_SRGPIO_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R7",
+    "location": {
+      "column": "9",
+      "line": "2133",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132328@macro@SYSCTL_SRGPIO_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R6",
+    "location": {
+      "column": "9",
+      "line": "2134",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132403@macro@SYSCTL_SRGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "2135",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132478@macro@SYSCTL_SRGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "2136",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132553@macro@SYSCTL_SRGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "2137",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132628@macro@SYSCTL_SRGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "2138",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132703@macro@SYSCTL_SRGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "2139",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@132778@macro@SYSCTL_SRGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "2140",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@133104@macro@SYSCTL_SRDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "2147",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@133430@macro@SYSCTL_SREPI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREPI_R0",
+    "location": {
+      "column": "9",
+      "line": "2154",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREPI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@133755@macro@SYSCTL_SRHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "2161",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134137@macro@SYSCTL_SRUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R7",
+    "location": {
+      "column": "9",
+      "line": "2169",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134214@macro@SYSCTL_SRUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R6",
+    "location": {
+      "column": "9",
+      "line": "2170",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134291@macro@SYSCTL_SRUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R5",
+    "location": {
+      "column": "9",
+      "line": "2171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134368@macro@SYSCTL_SRUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R4",
+    "location": {
+      "column": "9",
+      "line": "2172",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134445@macro@SYSCTL_SRUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R3",
+    "location": {
+      "column": "9",
+      "line": "2173",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134522@macro@SYSCTL_SRUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R2",
+    "location": {
+      "column": "9",
+      "line": "2174",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134599@macro@SYSCTL_SRUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R1",
+    "location": {
+      "column": "9",
+      "line": "2175",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@134676@macro@SYSCTL_SRUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUART_R0",
+    "location": {
+      "column": "9",
+      "line": "2176",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135004@macro@SYSCTL_SRSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "2183",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135080@macro@SYSCTL_SRSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "2184",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135156@macro@SYSCTL_SRSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "2185",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135232@macro@SYSCTL_SRSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "2186",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135559@macro@SYSCTL_SRI2C_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R9",
+    "location": {
+      "column": "9",
+      "line": "2193",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135635@macro@SYSCTL_SRI2C_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R8",
+    "location": {
+      "column": "9",
+      "line": "2194",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135711@macro@SYSCTL_SRI2C_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R7",
+    "location": {
+      "column": "9",
+      "line": "2195",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135787@macro@SYSCTL_SRI2C_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R6",
+    "location": {
+      "column": "9",
+      "line": "2196",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135863@macro@SYSCTL_SRI2C_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R5",
+    "location": {
+      "column": "9",
+      "line": "2197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@135939@macro@SYSCTL_SRI2C_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R4",
+    "location": {
+      "column": "9",
+      "line": "2198",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136015@macro@SYSCTL_SRI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "2199",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136091@macro@SYSCTL_SRI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "2200",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136167@macro@SYSCTL_SRI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "2201",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136243@macro@SYSCTL_SRI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "2202",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136570@macro@SYSCTL_SRUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "2209",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@136896@macro@SYSCTL_SREPHY_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREPHY_R0",
+    "location": {
+      "column": "9",
+      "line": "2216",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREPHY_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@137278@macro@SYSCTL_SRCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "2224",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@137354@macro@SYSCTL_SRCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "2225",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@137681@macro@SYSCTL_SRADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC_R1",
+    "location": {
+      "column": "9",
+      "line": "2232",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@137757@macro@SYSCTL_SRADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRADC_R0",
+    "location": {
+      "column": "9",
+      "line": "2233",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@138085@macro@SYSCTL_SRACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "2240",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@138474@macro@SYSCTL_SRPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "2248",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@138550@macro@SYSCTL_SRPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "2249",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@138877@macro@SYSCTL_SRQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "2256",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@138953@macro@SYSCTL_SRQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "2257",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@139287@macro@SYSCTL_SREEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "2265",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@139622@macro@SYSCTL_SRWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "2273",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@139772@macro@SYSCTL_SRWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "2275",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@139922@macro@SYSCTL_SRWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "2277",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@140072@macro@SYSCTL_SRWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "2279",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@140222@macro@SYSCTL_SRWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "2281",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@140372@macro@SYSCTL_SRWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "2283",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@140773@macro@SYSCTL_SRCCM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRCCM_R0",
+    "location": {
+      "column": "9",
+      "line": "2291",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRCCM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@141165@macro@SYSCTL_SRLCD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SRLCD_R0",
+    "location": {
+      "column": "9",
+      "line": "2299",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SRLCD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@141494@macro@SYSCTL_SROWIRE_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SROWIRE_R0",
+    "location": {
+      "column": "9",
+      "line": "2306",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SROWIRE_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@141823@macro@SYSCTL_SREMAC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SREMAC_R0",
+    "location": {
+      "column": "9",
+      "line": "2313",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SREMAC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@142219@macro@SYSCTL_RCGCWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD_R1",
+    "location": {
+      "column": "9",
+      "line": "2321",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@142362@macro@SYSCTL_RCGCWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWD_R0",
+    "location": {
+      "column": "9",
+      "line": "2323",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@142764@macro@SYSCTL_RCGCTIMER_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R7",
+    "location": {
+      "column": "9",
+      "line": "2332",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@142924@macro@SYSCTL_RCGCTIMER_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R6",
+    "location": {
+      "column": "9",
+      "line": "2334",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143084@macro@SYSCTL_RCGCTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "2336",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143244@macro@SYSCTL_RCGCTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "2338",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143404@macro@SYSCTL_RCGCTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "2340",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143564@macro@SYSCTL_RCGCTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "2342",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143724@macro@SYSCTL_RCGCTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "2344",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@143884@macro@SYSCTL_RCGCTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "2346",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144302@macro@SYSCTL_RCGCGPIO_R17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R17",
+    "location": {
+      "column": "9",
+      "line": "2355",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144440@macro@SYSCTL_RCGCGPIO_R16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R16",
+    "location": {
+      "column": "9",
+      "line": "2357",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144578@macro@SYSCTL_RCGCGPIO_R15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R15",
+    "location": {
+      "column": "9",
+      "line": "2359",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144716@macro@SYSCTL_RCGCGPIO_R14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R14",
+    "location": {
+      "column": "9",
+      "line": "2361",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144854@macro@SYSCTL_RCGCGPIO_R13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R13",
+    "location": {
+      "column": "9",
+      "line": "2363",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@144992@macro@SYSCTL_RCGCGPIO_R12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R12",
+    "location": {
+      "column": "9",
+      "line": "2365",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145130@macro@SYSCTL_RCGCGPIO_R11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R11",
+    "location": {
+      "column": "9",
+      "line": "2367",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145268@macro@SYSCTL_RCGCGPIO_R10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R10",
+    "location": {
+      "column": "9",
+      "line": "2369",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145406@macro@SYSCTL_RCGCGPIO_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R9",
+    "location": {
+      "column": "9",
+      "line": "2371",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145544@macro@SYSCTL_RCGCGPIO_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R8",
+    "location": {
+      "column": "9",
+      "line": "2373",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145682@macro@SYSCTL_RCGCGPIO_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R7",
+    "location": {
+      "column": "9",
+      "line": "2375",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145820@macro@SYSCTL_RCGCGPIO_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R6",
+    "location": {
+      "column": "9",
+      "line": "2377",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@145958@macro@SYSCTL_RCGCGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "2379",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@146096@macro@SYSCTL_RCGCGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "2381",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@146234@macro@SYSCTL_RCGCGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "2383",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@146372@macro@SYSCTL_RCGCGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "2385",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@146510@macro@SYSCTL_RCGCGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "2387",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@146648@macro@SYSCTL_RCGCGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "2389",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@147039@macro@SYSCTL_RCGCDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "2397",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@147430@macro@SYSCTL_RCGCEPI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEPI_R0",
+    "location": {
+      "column": "9",
+      "line": "2405",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEPI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@147820@macro@SYSCTL_RCGCHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "2413",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148223@macro@SYSCTL_RCGCUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R7",
+    "location": {
+      "column": "9",
+      "line": "2422",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148363@macro@SYSCTL_RCGCUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R6",
+    "location": {
+      "column": "9",
+      "line": "2424",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148503@macro@SYSCTL_RCGCUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R5",
+    "location": {
+      "column": "9",
+      "line": "2426",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148643@macro@SYSCTL_RCGCUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R4",
+    "location": {
+      "column": "9",
+      "line": "2428",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148783@macro@SYSCTL_RCGCUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R3",
+    "location": {
+      "column": "9",
+      "line": "2430",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@148923@macro@SYSCTL_RCGCUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R2",
+    "location": {
+      "column": "9",
+      "line": "2432",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@149063@macro@SYSCTL_RCGCUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R1",
+    "location": {
+      "column": "9",
+      "line": "2434",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@149203@macro@SYSCTL_RCGCUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUART_R0",
+    "location": {
+      "column": "9",
+      "line": "2436",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@149596@macro@SYSCTL_RCGCSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "2444",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@149735@macro@SYSCTL_RCGCSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "2446",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@149874@macro@SYSCTL_RCGCSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "2448",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150013@macro@SYSCTL_RCGCSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "2450",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150405@macro@SYSCTL_RCGCI2C_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R9",
+    "location": {
+      "column": "9",
+      "line": "2458",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150544@macro@SYSCTL_RCGCI2C_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R8",
+    "location": {
+      "column": "9",
+      "line": "2460",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150683@macro@SYSCTL_RCGCI2C_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R7",
+    "location": {
+      "column": "9",
+      "line": "2462",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150822@macro@SYSCTL_RCGCI2C_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R6",
+    "location": {
+      "column": "9",
+      "line": "2464",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@150961@macro@SYSCTL_RCGCI2C_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R5",
+    "location": {
+      "column": "9",
+      "line": "2466",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@151100@macro@SYSCTL_RCGCI2C_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R4",
+    "location": {
+      "column": "9",
+      "line": "2468",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@151239@macro@SYSCTL_RCGCI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "2470",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@151378@macro@SYSCTL_RCGCI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "2472",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@151517@macro@SYSCTL_RCGCI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "2474",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@151656@macro@SYSCTL_RCGCI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "2476",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@152048@macro@SYSCTL_RCGCUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "2484",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@152443@macro@SYSCTL_RCGCEPHY_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEPHY_R0",
+    "location": {
+      "column": "9",
+      "line": "2493",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEPHY_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@152842@macro@SYSCTL_RCGCCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "2501",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@152981@macro@SYSCTL_RCGCCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "2503",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@153373@macro@SYSCTL_RCGCADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC_R1",
+    "location": {
+      "column": "9",
+      "line": "2511",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@153512@macro@SYSCTL_RCGCADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCADC_R0",
+    "location": {
+      "column": "9",
+      "line": "2513",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@153909@macro@SYSCTL_RCGCACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "2522",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@154315@macro@SYSCTL_RCGCPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "2530",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@154454@macro@SYSCTL_RCGCPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "2532",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@154846@macro@SYSCTL_RCGCQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "2540",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@154985@macro@SYSCTL_RCGCQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "2542",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@155384@macro@SYSCTL_RCGCEEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "2551",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@155784@macro@SYSCTL_RCGCWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "2560",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@155997@macro@SYSCTL_RCGCWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "2563",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@156210@macro@SYSCTL_RCGCWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "2566",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@156423@macro@SYSCTL_RCGCWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "2569",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@156636@macro@SYSCTL_RCGCWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "2572",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@156849@macro@SYSCTL_RCGCWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "2575",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@157315@macro@SYSCTL_RCGCCCM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCCCM_R0",
+    "location": {
+      "column": "9",
+      "line": "2584",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCCCM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@157724@macro@SYSCTL_RCGCLCD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCLCD_R0",
+    "location": {
+      "column": "9",
+      "line": "2592",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCLCD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@158133@macro@SYSCTL_RCGCOWIRE_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCOWIRE_R0",
+    "location": {
+      "column": "9",
+      "line": "2601",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCOWIRE_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@158533@macro@SYSCTL_RCGCEMAC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RCGCEMAC_R0",
+    "location": {
+      "column": "9",
+      "line": "2610",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RCGCEMAC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@158933@macro@SYSCTL_SCGCWD_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD_S1",
+    "location": {
+      "column": "9",
+      "line": "2618",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWD_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@159078@macro@SYSCTL_SCGCWD_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWD_S0",
+    "location": {
+      "column": "9",
+      "line": "2620",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWD_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@159482@macro@SYSCTL_SCGCTIMER_S7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S7",
+    "location": {
+      "column": "9",
+      "line": "2629",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@159692@macro@SYSCTL_SCGCTIMER_S6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S6",
+    "location": {
+      "column": "9",
+      "line": "2632",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@159902@macro@SYSCTL_SCGCTIMER_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S5",
+    "location": {
+      "column": "9",
+      "line": "2635",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@160112@macro@SYSCTL_SCGCTIMER_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S4",
+    "location": {
+      "column": "9",
+      "line": "2638",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@160322@macro@SYSCTL_SCGCTIMER_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S3",
+    "location": {
+      "column": "9",
+      "line": "2641",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@160532@macro@SYSCTL_SCGCTIMER_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S2",
+    "location": {
+      "column": "9",
+      "line": "2644",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@160742@macro@SYSCTL_SCGCTIMER_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S1",
+    "location": {
+      "column": "9",
+      "line": "2647",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@160952@macro@SYSCTL_SCGCTIMER_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCTIMER_S0",
+    "location": {
+      "column": "9",
+      "line": "2650",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCTIMER_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@161420@macro@SYSCTL_SCGCGPIO_S17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S17",
+    "location": {
+      "column": "9",
+      "line": "2660",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@161560@macro@SYSCTL_SCGCGPIO_S16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S16",
+    "location": {
+      "column": "9",
+      "line": "2662",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@161700@macro@SYSCTL_SCGCGPIO_S15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S15",
+    "location": {
+      "column": "9",
+      "line": "2664",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@161840@macro@SYSCTL_SCGCGPIO_S14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S14",
+    "location": {
+      "column": "9",
+      "line": "2666",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@161980@macro@SYSCTL_SCGCGPIO_S13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S13",
+    "location": {
+      "column": "9",
+      "line": "2668",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162120@macro@SYSCTL_SCGCGPIO_S12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S12",
+    "location": {
+      "column": "9",
+      "line": "2670",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162260@macro@SYSCTL_SCGCGPIO_S11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S11",
+    "location": {
+      "column": "9",
+      "line": "2672",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162400@macro@SYSCTL_SCGCGPIO_S10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S10",
+    "location": {
+      "column": "9",
+      "line": "2674",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162540@macro@SYSCTL_SCGCGPIO_S9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S9",
+    "location": {
+      "column": "9",
+      "line": "2676",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162680@macro@SYSCTL_SCGCGPIO_S8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S8",
+    "location": {
+      "column": "9",
+      "line": "2678",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162820@macro@SYSCTL_SCGCGPIO_S7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S7",
+    "location": {
+      "column": "9",
+      "line": "2680",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@162960@macro@SYSCTL_SCGCGPIO_S6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S6",
+    "location": {
+      "column": "9",
+      "line": "2682",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163100@macro@SYSCTL_SCGCGPIO_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S5",
+    "location": {
+      "column": "9",
+      "line": "2684",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163240@macro@SYSCTL_SCGCGPIO_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S4",
+    "location": {
+      "column": "9",
+      "line": "2686",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163380@macro@SYSCTL_SCGCGPIO_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S3",
+    "location": {
+      "column": "9",
+      "line": "2688",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163520@macro@SYSCTL_SCGCGPIO_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S2",
+    "location": {
+      "column": "9",
+      "line": "2690",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163660@macro@SYSCTL_SCGCGPIO_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S1",
+    "location": {
+      "column": "9",
+      "line": "2692",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@163800@macro@SYSCTL_SCGCGPIO_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCGPIO_S0",
+    "location": {
+      "column": "9",
+      "line": "2694",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCGPIO_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@164193@macro@SYSCTL_SCGCDMA_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCDMA_S0",
+    "location": {
+      "column": "9",
+      "line": "2702",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCDMA_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@164586@macro@SYSCTL_SCGCEPI_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEPI_S0",
+    "location": {
+      "column": "9",
+      "line": "2710",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEPI_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@164978@macro@SYSCTL_SCGCHIB_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCHIB_S0",
+    "location": {
+      "column": "9",
+      "line": "2718",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCHIB_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@165383@macro@SYSCTL_SCGCUART_S7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S7",
+    "location": {
+      "column": "9",
+      "line": "2727",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@165525@macro@SYSCTL_SCGCUART_S6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S6",
+    "location": {
+      "column": "9",
+      "line": "2729",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@165667@macro@SYSCTL_SCGCUART_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S5",
+    "location": {
+      "column": "9",
+      "line": "2731",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@165809@macro@SYSCTL_SCGCUART_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S4",
+    "location": {
+      "column": "9",
+      "line": "2733",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@165951@macro@SYSCTL_SCGCUART_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S3",
+    "location": {
+      "column": "9",
+      "line": "2735",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@166093@macro@SYSCTL_SCGCUART_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S2",
+    "location": {
+      "column": "9",
+      "line": "2737",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@166235@macro@SYSCTL_SCGCUART_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S1",
+    "location": {
+      "column": "9",
+      "line": "2739",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@166377@macro@SYSCTL_SCGCUART_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUART_S0",
+    "location": {
+      "column": "9",
+      "line": "2741",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUART_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@166772@macro@SYSCTL_SCGCSSI_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S3",
+    "location": {
+      "column": "9",
+      "line": "2749",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@166913@macro@SYSCTL_SCGCSSI_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S2",
+    "location": {
+      "column": "9",
+      "line": "2751",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@167054@macro@SYSCTL_SCGCSSI_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S1",
+    "location": {
+      "column": "9",
+      "line": "2753",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@167195@macro@SYSCTL_SCGCSSI_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCSSI_S0",
+    "location": {
+      "column": "9",
+      "line": "2755",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCSSI_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@167589@macro@SYSCTL_SCGCI2C_S9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S9",
+    "location": {
+      "column": "9",
+      "line": "2763",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@167730@macro@SYSCTL_SCGCI2C_S8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S8",
+    "location": {
+      "column": "9",
+      "line": "2765",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@167871@macro@SYSCTL_SCGCI2C_S7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S7",
+    "location": {
+      "column": "9",
+      "line": "2767",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168012@macro@SYSCTL_SCGCI2C_S6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S6",
+    "location": {
+      "column": "9",
+      "line": "2769",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168153@macro@SYSCTL_SCGCI2C_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S5",
+    "location": {
+      "column": "9",
+      "line": "2771",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168294@macro@SYSCTL_SCGCI2C_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S4",
+    "location": {
+      "column": "9",
+      "line": "2773",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168435@macro@SYSCTL_SCGCI2C_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S3",
+    "location": {
+      "column": "9",
+      "line": "2775",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168576@macro@SYSCTL_SCGCI2C_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S2",
+    "location": {
+      "column": "9",
+      "line": "2777",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168717@macro@SYSCTL_SCGCI2C_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S1",
+    "location": {
+      "column": "9",
+      "line": "2779",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@168858@macro@SYSCTL_SCGCI2C_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCI2C_S0",
+    "location": {
+      "column": "9",
+      "line": "2781",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCI2C_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@169252@macro@SYSCTL_SCGCUSB_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCUSB_S0",
+    "location": {
+      "column": "9",
+      "line": "2789",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCUSB_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@169649@macro@SYSCTL_SCGCEPHY_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEPHY_S0",
+    "location": {
+      "column": "9",
+      "line": "2798",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEPHY_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@170041@macro@SYSCTL_SCGCCAN_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN_S1",
+    "location": {
+      "column": "9",
+      "line": "2806",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCCAN_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@170182@macro@SYSCTL_SCGCCAN_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCAN_S0",
+    "location": {
+      "column": "9",
+      "line": "2808",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCCAN_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@170576@macro@SYSCTL_SCGCADC_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC_S1",
+    "location": {
+      "column": "9",
+      "line": "2816",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCADC_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@170717@macro@SYSCTL_SCGCADC_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCADC_S0",
+    "location": {
+      "column": "9",
+      "line": "2818",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCADC_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@171116@macro@SYSCTL_SCGCACMP_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCACMP_S0",
+    "location": {
+      "column": "9",
+      "line": "2827",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCACMP_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@171524@macro@SYSCTL_SCGCPWM_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM_S1",
+    "location": {
+      "column": "9",
+      "line": "2835",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCPWM_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@171665@macro@SYSCTL_SCGCPWM_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCPWM_S0",
+    "location": {
+      "column": "9",
+      "line": "2837",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCPWM_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@172059@macro@SYSCTL_SCGCQEI_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI_S1",
+    "location": {
+      "column": "9",
+      "line": "2845",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCQEI_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@172200@macro@SYSCTL_SCGCQEI_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCQEI_S0",
+    "location": {
+      "column": "9",
+      "line": "2847",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCQEI_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@172601@macro@SYSCTL_SCGCEEPROM_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEEPROM_S0",
+    "location": {
+      "column": "9",
+      "line": "2856",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEEPROM_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@173003@macro@SYSCTL_SCGCWTIMER_S5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S5",
+    "location": {
+      "column": "9",
+      "line": "2865",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@173218@macro@SYSCTL_SCGCWTIMER_S4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S4",
+    "location": {
+      "column": "9",
+      "line": "2868",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@173433@macro@SYSCTL_SCGCWTIMER_S3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S3",
+    "location": {
+      "column": "9",
+      "line": "2871",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@173648@macro@SYSCTL_SCGCWTIMER_S2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S2",
+    "location": {
+      "column": "9",
+      "line": "2874",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@173863@macro@SYSCTL_SCGCWTIMER_S1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S1",
+    "location": {
+      "column": "9",
+      "line": "2877",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@174078@macro@SYSCTL_SCGCWTIMER_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCWTIMER_S0",
+    "location": {
+      "column": "9",
+      "line": "2880",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCWTIMER_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@174546@macro@SYSCTL_SCGCCCM_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCCCM_S0",
+    "location": {
+      "column": "9",
+      "line": "2889",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCCCM_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@174957@macro@SYSCTL_SCGCLCD_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCLCD_S0",
+    "location": {
+      "column": "9",
+      "line": "2897",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCLCD_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@175368@macro@SYSCTL_SCGCOWIRE_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCOWIRE_S0",
+    "location": {
+      "column": "9",
+      "line": "2906",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCOWIRE_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@175770@macro@SYSCTL_SCGCEMAC_S0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_SCGCEMAC_S0",
+    "location": {
+      "column": "9",
+      "line": "2915",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_SCGCEMAC_S0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@176172@macro@SYSCTL_DCGCWD_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD_D1",
+    "location": {
+      "column": "9",
+      "line": "2923",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWD_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@176322@macro@SYSCTL_DCGCWD_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWD_D0",
+    "location": {
+      "column": "9",
+      "line": "2925",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWD_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@176731@macro@SYSCTL_DCGCTIMER_D7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D7",
+    "location": {
+      "column": "9",
+      "line": "2934",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@176946@macro@SYSCTL_DCGCTIMER_D6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D6",
+    "location": {
+      "column": "9",
+      "line": "2937",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@177161@macro@SYSCTL_DCGCTIMER_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D5",
+    "location": {
+      "column": "9",
+      "line": "2940",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@177376@macro@SYSCTL_DCGCTIMER_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D4",
+    "location": {
+      "column": "9",
+      "line": "2943",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@177591@macro@SYSCTL_DCGCTIMER_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D3",
+    "location": {
+      "column": "9",
+      "line": "2946",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@177806@macro@SYSCTL_DCGCTIMER_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D2",
+    "location": {
+      "column": "9",
+      "line": "2949",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@178021@macro@SYSCTL_DCGCTIMER_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D1",
+    "location": {
+      "column": "9",
+      "line": "2952",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@178236@macro@SYSCTL_DCGCTIMER_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCTIMER_D0",
+    "location": {
+      "column": "9",
+      "line": "2955",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCTIMER_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@178709@macro@SYSCTL_DCGCGPIO_D17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D17",
+    "location": {
+      "column": "9",
+      "line": "2965",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@178854@macro@SYSCTL_DCGCGPIO_D16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D16",
+    "location": {
+      "column": "9",
+      "line": "2967",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@178999@macro@SYSCTL_DCGCGPIO_D15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D15",
+    "location": {
+      "column": "9",
+      "line": "2969",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179144@macro@SYSCTL_DCGCGPIO_D14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D14",
+    "location": {
+      "column": "9",
+      "line": "2971",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179289@macro@SYSCTL_DCGCGPIO_D13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D13",
+    "location": {
+      "column": "9",
+      "line": "2973",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179434@macro@SYSCTL_DCGCGPIO_D12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D12",
+    "location": {
+      "column": "9",
+      "line": "2975",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179579@macro@SYSCTL_DCGCGPIO_D11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D11",
+    "location": {
+      "column": "9",
+      "line": "2977",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179724@macro@SYSCTL_DCGCGPIO_D10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D10",
+    "location": {
+      "column": "9",
+      "line": "2979",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@179869@macro@SYSCTL_DCGCGPIO_D9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D9",
+    "location": {
+      "column": "9",
+      "line": "2981",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180014@macro@SYSCTL_DCGCGPIO_D8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D8",
+    "location": {
+      "column": "9",
+      "line": "2983",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180159@macro@SYSCTL_DCGCGPIO_D7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D7",
+    "location": {
+      "column": "9",
+      "line": "2985",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180304@macro@SYSCTL_DCGCGPIO_D6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D6",
+    "location": {
+      "column": "9",
+      "line": "2987",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180449@macro@SYSCTL_DCGCGPIO_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D5",
+    "location": {
+      "column": "9",
+      "line": "2989",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180594@macro@SYSCTL_DCGCGPIO_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D4",
+    "location": {
+      "column": "9",
+      "line": "2991",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180739@macro@SYSCTL_DCGCGPIO_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D3",
+    "location": {
+      "column": "9",
+      "line": "2993",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@180884@macro@SYSCTL_DCGCGPIO_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D2",
+    "location": {
+      "column": "9",
+      "line": "2995",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@181029@macro@SYSCTL_DCGCGPIO_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D1",
+    "location": {
+      "column": "9",
+      "line": "2997",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@181174@macro@SYSCTL_DCGCGPIO_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCGPIO_D0",
+    "location": {
+      "column": "9",
+      "line": "2999",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCGPIO_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@181572@macro@SYSCTL_DCGCDMA_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCDMA_D0",
+    "location": {
+      "column": "9",
+      "line": "3007",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCDMA_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@181970@macro@SYSCTL_DCGCEPI_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEPI_D0",
+    "location": {
+      "column": "9",
+      "line": "3015",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEPI_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@182367@macro@SYSCTL_DCGCHIB_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCHIB_D0",
+    "location": {
+      "column": "9",
+      "line": "3023",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCHIB_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@182777@macro@SYSCTL_DCGCUART_D7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D7",
+    "location": {
+      "column": "9",
+      "line": "3032",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@182924@macro@SYSCTL_DCGCUART_D6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D6",
+    "location": {
+      "column": "9",
+      "line": "3034",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183071@macro@SYSCTL_DCGCUART_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D5",
+    "location": {
+      "column": "9",
+      "line": "3036",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183218@macro@SYSCTL_DCGCUART_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D4",
+    "location": {
+      "column": "9",
+      "line": "3038",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183365@macro@SYSCTL_DCGCUART_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D3",
+    "location": {
+      "column": "9",
+      "line": "3040",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183512@macro@SYSCTL_DCGCUART_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D2",
+    "location": {
+      "column": "9",
+      "line": "3042",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183659@macro@SYSCTL_DCGCUART_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D1",
+    "location": {
+      "column": "9",
+      "line": "3044",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@183806@macro@SYSCTL_DCGCUART_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUART_D0",
+    "location": {
+      "column": "9",
+      "line": "3046",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUART_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@184206@macro@SYSCTL_DCGCSSI_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D3",
+    "location": {
+      "column": "9",
+      "line": "3054",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@184352@macro@SYSCTL_DCGCSSI_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D2",
+    "location": {
+      "column": "9",
+      "line": "3056",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@184498@macro@SYSCTL_DCGCSSI_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D1",
+    "location": {
+      "column": "9",
+      "line": "3058",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@184644@macro@SYSCTL_DCGCSSI_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCSSI_D0",
+    "location": {
+      "column": "9",
+      "line": "3060",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCSSI_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185043@macro@SYSCTL_DCGCI2C_D9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D9",
+    "location": {
+      "column": "9",
+      "line": "3068",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185189@macro@SYSCTL_DCGCI2C_D8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D8",
+    "location": {
+      "column": "9",
+      "line": "3070",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185335@macro@SYSCTL_DCGCI2C_D7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D7",
+    "location": {
+      "column": "9",
+      "line": "3072",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185481@macro@SYSCTL_DCGCI2C_D6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D6",
+    "location": {
+      "column": "9",
+      "line": "3074",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185627@macro@SYSCTL_DCGCI2C_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D5",
+    "location": {
+      "column": "9",
+      "line": "3076",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185773@macro@SYSCTL_DCGCI2C_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D4",
+    "location": {
+      "column": "9",
+      "line": "3078",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@185919@macro@SYSCTL_DCGCI2C_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D3",
+    "location": {
+      "column": "9",
+      "line": "3080",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@186065@macro@SYSCTL_DCGCI2C_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D2",
+    "location": {
+      "column": "9",
+      "line": "3082",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@186211@macro@SYSCTL_DCGCI2C_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D1",
+    "location": {
+      "column": "9",
+      "line": "3084",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@186357@macro@SYSCTL_DCGCI2C_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCI2C_D0",
+    "location": {
+      "column": "9",
+      "line": "3086",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCI2C_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@186756@macro@SYSCTL_DCGCUSB_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCUSB_D0",
+    "location": {
+      "column": "9",
+      "line": "3094",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCUSB_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@187158@macro@SYSCTL_DCGCEPHY_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEPHY_D0",
+    "location": {
+      "column": "9",
+      "line": "3103",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEPHY_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@187555@macro@SYSCTL_DCGCCAN_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN_D1",
+    "location": {
+      "column": "9",
+      "line": "3111",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCCAN_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@187701@macro@SYSCTL_DCGCCAN_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCAN_D0",
+    "location": {
+      "column": "9",
+      "line": "3113",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCCAN_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@188100@macro@SYSCTL_DCGCADC_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC_D1",
+    "location": {
+      "column": "9",
+      "line": "3121",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCADC_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@188246@macro@SYSCTL_DCGCADC_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCADC_D0",
+    "location": {
+      "column": "9",
+      "line": "3123",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCADC_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@188650@macro@SYSCTL_DCGCACMP_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCACMP_D0",
+    "location": {
+      "column": "9",
+      "line": "3132",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCACMP_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@189111@macro@SYSCTL_DCGCPWM_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM_D1",
+    "location": {
+      "column": "9",
+      "line": "3141",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCPWM_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@189257@macro@SYSCTL_DCGCPWM_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCPWM_D0",
+    "location": {
+      "column": "9",
+      "line": "3143",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCPWM_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@189656@macro@SYSCTL_DCGCQEI_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI_D1",
+    "location": {
+      "column": "9",
+      "line": "3151",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCQEI_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@189802@macro@SYSCTL_DCGCQEI_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCQEI_D0",
+    "location": {
+      "column": "9",
+      "line": "3153",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCQEI_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@190208@macro@SYSCTL_DCGCEEPROM_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEEPROM_D0",
+    "location": {
+      "column": "9",
+      "line": "3162",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEEPROM_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@190615@macro@SYSCTL_DCGCWTIMER_D5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D5",
+    "location": {
+      "column": "9",
+      "line": "3171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@190835@macro@SYSCTL_DCGCWTIMER_D4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D4",
+    "location": {
+      "column": "9",
+      "line": "3174",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@191055@macro@SYSCTL_DCGCWTIMER_D3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D3",
+    "location": {
+      "column": "9",
+      "line": "3177",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@191275@macro@SYSCTL_DCGCWTIMER_D2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D2",
+    "location": {
+      "column": "9",
+      "line": "3180",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@191495@macro@SYSCTL_DCGCWTIMER_D1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D1",
+    "location": {
+      "column": "9",
+      "line": "3183",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@191715@macro@SYSCTL_DCGCWTIMER_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCWTIMER_D0",
+    "location": {
+      "column": "9",
+      "line": "3186",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCWTIMER_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@192188@macro@SYSCTL_DCGCCCM_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCCCM_D0",
+    "location": {
+      "column": "9",
+      "line": "3195",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCCCM_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@192652@macro@SYSCTL_DCGCLCD_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCLCD_D0",
+    "location": {
+      "column": "9",
+      "line": "3204",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCLCD_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@193116@macro@SYSCTL_DCGCOWIRE_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCOWIRE_D0",
+    "location": {
+      "column": "9",
+      "line": "3214",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCOWIRE_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@193523@macro@SYSCTL_DCGCEMAC_D0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DCGCEMAC_D0",
+    "location": {
+      "column": "9",
+      "line": "3223",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DCGCEMAC_D0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@193928@macro@SYSCTL_PCWD_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCWD_P1",
+    "location": {
+      "column": "9",
+      "line": "3231",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCWD_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194007@macro@SYSCTL_PCWD_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCWD_P0",
+    "location": {
+      "column": "9",
+      "line": "3232",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCWD_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194339@macro@SYSCTL_PCTIMER_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P7",
+    "location": {
+      "column": "9",
+      "line": "3239",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194473@macro@SYSCTL_PCTIMER_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P6",
+    "location": {
+      "column": "9",
+      "line": "3241",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194607@macro@SYSCTL_PCTIMER_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P5",
+    "location": {
+      "column": "9",
+      "line": "3243",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194741@macro@SYSCTL_PCTIMER_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P4",
+    "location": {
+      "column": "9",
+      "line": "3245",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@194875@macro@SYSCTL_PCTIMER_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P3",
+    "location": {
+      "column": "9",
+      "line": "3247",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195009@macro@SYSCTL_PCTIMER_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P2",
+    "location": {
+      "column": "9",
+      "line": "3249",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195143@macro@SYSCTL_PCTIMER_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P1",
+    "location": {
+      "column": "9",
+      "line": "3251",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195277@macro@SYSCTL_PCTIMER_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCTIMER_P0",
+    "location": {
+      "column": "9",
+      "line": "3253",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCTIMER_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195663@macro@SYSCTL_PCGPIO_P17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P17",
+    "location": {
+      "column": "9",
+      "line": "3261",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195737@macro@SYSCTL_PCGPIO_P16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P16",
+    "location": {
+      "column": "9",
+      "line": "3262",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195811@macro@SYSCTL_PCGPIO_P15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P15",
+    "location": {
+      "column": "9",
+      "line": "3263",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195885@macro@SYSCTL_PCGPIO_P14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P14",
+    "location": {
+      "column": "9",
+      "line": "3264",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@195959@macro@SYSCTL_PCGPIO_P13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P13",
+    "location": {
+      "column": "9",
+      "line": "3265",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196033@macro@SYSCTL_PCGPIO_P12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P12",
+    "location": {
+      "column": "9",
+      "line": "3266",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196107@macro@SYSCTL_PCGPIO_P11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P11",
+    "location": {
+      "column": "9",
+      "line": "3267",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196181@macro@SYSCTL_PCGPIO_P10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P10",
+    "location": {
+      "column": "9",
+      "line": "3268",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196255@macro@SYSCTL_PCGPIO_P9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P9",
+    "location": {
+      "column": "9",
+      "line": "3269",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196329@macro@SYSCTL_PCGPIO_P8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P8",
+    "location": {
+      "column": "9",
+      "line": "3270",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196403@macro@SYSCTL_PCGPIO_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P7",
+    "location": {
+      "column": "9",
+      "line": "3271",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196477@macro@SYSCTL_PCGPIO_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P6",
+    "location": {
+      "column": "9",
+      "line": "3272",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196551@macro@SYSCTL_PCGPIO_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P5",
+    "location": {
+      "column": "9",
+      "line": "3273",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196625@macro@SYSCTL_PCGPIO_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P4",
+    "location": {
+      "column": "9",
+      "line": "3274",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196699@macro@SYSCTL_PCGPIO_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P3",
+    "location": {
+      "column": "9",
+      "line": "3275",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196773@macro@SYSCTL_PCGPIO_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P2",
+    "location": {
+      "column": "9",
+      "line": "3276",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196847@macro@SYSCTL_PCGPIO_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P1",
+    "location": {
+      "column": "9",
+      "line": "3277",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@196921@macro@SYSCTL_PCGPIO_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCGPIO_P0",
+    "location": {
+      "column": "9",
+      "line": "3278",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCGPIO_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@197246@macro@SYSCTL_PCDMA_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCDMA_P0",
+    "location": {
+      "column": "9",
+      "line": "3285",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCDMA_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@197571@macro@SYSCTL_PCEPI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEPI_P0",
+    "location": {
+      "column": "9",
+      "line": "3292",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEPI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@197895@macro@SYSCTL_PCHIB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCHIB_P0",
+    "location": {
+      "column": "9",
+      "line": "3299",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCHIB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198228@macro@SYSCTL_PCUART_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P7",
+    "location": {
+      "column": "9",
+      "line": "3306",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198304@macro@SYSCTL_PCUART_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P6",
+    "location": {
+      "column": "9",
+      "line": "3307",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198380@macro@SYSCTL_PCUART_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P5",
+    "location": {
+      "column": "9",
+      "line": "3308",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198456@macro@SYSCTL_PCUART_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P4",
+    "location": {
+      "column": "9",
+      "line": "3309",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198532@macro@SYSCTL_PCUART_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P3",
+    "location": {
+      "column": "9",
+      "line": "3310",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198608@macro@SYSCTL_PCUART_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P2",
+    "location": {
+      "column": "9",
+      "line": "3311",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198684@macro@SYSCTL_PCUART_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P1",
+    "location": {
+      "column": "9",
+      "line": "3312",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@198760@macro@SYSCTL_PCUART_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUART_P0",
+    "location": {
+      "column": "9",
+      "line": "3313",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUART_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199087@macro@SYSCTL_PCSSI_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCSSI_P3",
+    "location": {
+      "column": "9",
+      "line": "3320",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCSSI_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199162@macro@SYSCTL_PCSSI_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCSSI_P2",
+    "location": {
+      "column": "9",
+      "line": "3321",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCSSI_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199237@macro@SYSCTL_PCSSI_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCSSI_P1",
+    "location": {
+      "column": "9",
+      "line": "3322",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCSSI_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199312@macro@SYSCTL_PCSSI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCSSI_P0",
+    "location": {
+      "column": "9",
+      "line": "3323",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCSSI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199638@macro@SYSCTL_PCI2C_P9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P9",
+    "location": {
+      "column": "9",
+      "line": "3330",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199713@macro@SYSCTL_PCI2C_P8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P8",
+    "location": {
+      "column": "9",
+      "line": "3331",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199788@macro@SYSCTL_PCI2C_P7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P7",
+    "location": {
+      "column": "9",
+      "line": "3332",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199863@macro@SYSCTL_PCI2C_P6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P6",
+    "location": {
+      "column": "9",
+      "line": "3333",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@199938@macro@SYSCTL_PCI2C_P5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P5",
+    "location": {
+      "column": "9",
+      "line": "3334",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200013@macro@SYSCTL_PCI2C_P4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P4",
+    "location": {
+      "column": "9",
+      "line": "3335",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200088@macro@SYSCTL_PCI2C_P3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P3",
+    "location": {
+      "column": "9",
+      "line": "3336",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200163@macro@SYSCTL_PCI2C_P2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P2",
+    "location": {
+      "column": "9",
+      "line": "3337",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200238@macro@SYSCTL_PCI2C_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P1",
+    "location": {
+      "column": "9",
+      "line": "3338",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200313@macro@SYSCTL_PCI2C_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCI2C_P0",
+    "location": {
+      "column": "9",
+      "line": "3339",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCI2C_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200639@macro@SYSCTL_PCUSB_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCUSB_P0",
+    "location": {
+      "column": "9",
+      "line": "3346",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCUSB_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@200964@macro@SYSCTL_PCEPHY_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEPHY_P0",
+    "location": {
+      "column": "9",
+      "line": "3353",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEPHY_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@201345@macro@SYSCTL_PCCAN_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCCAN_P1",
+    "location": {
+      "column": "9",
+      "line": "3361",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCCAN_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@201420@macro@SYSCTL_PCCAN_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCCAN_P0",
+    "location": {
+      "column": "9",
+      "line": "3362",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCCAN_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@201746@macro@SYSCTL_PCADC_P1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCADC_P1",
+    "location": {
+      "column": "9",
+      "line": "3369",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCADC_P1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@201821@macro@SYSCTL_PCADC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCADC_P0",
+    "location": {
+      "column": "9",
+      "line": "3370",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCADC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@202148@macro@SYSCTL_PCACMP_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCACMP_P0",
+    "location": {
+      "column": "9",
+      "line": "3377",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCACMP_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@202536@macro@SYSCTL_PCPWM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCPWM_P0",
+    "location": {
+      "column": "9",
+      "line": "3385",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCPWM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@202862@macro@SYSCTL_PCQEI_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCQEI_P0",
+    "location": {
+      "column": "9",
+      "line": "3392",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCQEI_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@203195@macro@SYSCTL_PCEEPROM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEEPROM_P0",
+    "location": {
+      "column": "9",
+      "line": "3400",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEEPROM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@203524@macro@SYSCTL_PCCCM_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCCCM_P0",
+    "location": {
+      "column": "9",
+      "line": "3407",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCCCM_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@203915@macro@SYSCTL_PCLCD_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCLCD_P0",
+    "location": {
+      "column": "9",
+      "line": "3415",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCLCD_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@204302@macro@SYSCTL_PCOWIRE_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCOWIRE_P0",
+    "location": {
+      "column": "9",
+      "line": "3423",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCOWIRE_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@204632@macro@SYSCTL_PCEMAC_P0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PCEMAC_P0",
+    "location": {
+      "column": "9",
+      "line": "3430",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PCEMAC_P0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205014@macro@SYSCTL_PRWD_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD_R1",
+    "location": {
+      "column": "9",
+      "line": "3438",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWD_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205144@macro@SYSCTL_PRWD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWD_R0",
+    "location": {
+      "column": "9",
+      "line": "3440",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205527@macro@SYSCTL_PRTIMER_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R7",
+    "location": {
+      "column": "9",
+      "line": "3448",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205674@macro@SYSCTL_PRTIMER_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R6",
+    "location": {
+      "column": "9",
+      "line": "3450",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205821@macro@SYSCTL_PRTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "3452",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@205968@macro@SYSCTL_PRTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "3454",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@206115@macro@SYSCTL_PRTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "3456",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@206262@macro@SYSCTL_PRTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "3458",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@206409@macro@SYSCTL_PRTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "3460",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@206556@macro@SYSCTL_PRTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "3462",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@206955@macro@SYSCTL_PRGPIO_R17",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R17",
+    "location": {
+      "column": "9",
+      "line": "3470",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R17",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207032@macro@SYSCTL_PRGPIO_R16",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R16",
+    "location": {
+      "column": "9",
+      "line": "3471",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R16",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207109@macro@SYSCTL_PRGPIO_R15",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R15",
+    "location": {
+      "column": "9",
+      "line": "3472",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R15",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207186@macro@SYSCTL_PRGPIO_R14",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R14",
+    "location": {
+      "column": "9",
+      "line": "3473",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R14",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207263@macro@SYSCTL_PRGPIO_R13",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R13",
+    "location": {
+      "column": "9",
+      "line": "3474",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R13",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207340@macro@SYSCTL_PRGPIO_R12",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R12",
+    "location": {
+      "column": "9",
+      "line": "3475",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R12",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207417@macro@SYSCTL_PRGPIO_R11",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R11",
+    "location": {
+      "column": "9",
+      "line": "3476",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R11",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207494@macro@SYSCTL_PRGPIO_R10",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R10",
+    "location": {
+      "column": "9",
+      "line": "3477",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R10",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207571@macro@SYSCTL_PRGPIO_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R9",
+    "location": {
+      "column": "9",
+      "line": "3478",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207648@macro@SYSCTL_PRGPIO_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R8",
+    "location": {
+      "column": "9",
+      "line": "3479",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207725@macro@SYSCTL_PRGPIO_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R7",
+    "location": {
+      "column": "9",
+      "line": "3480",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207802@macro@SYSCTL_PRGPIO_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R6",
+    "location": {
+      "column": "9",
+      "line": "3481",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207879@macro@SYSCTL_PRGPIO_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R5",
+    "location": {
+      "column": "9",
+      "line": "3482",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@207956@macro@SYSCTL_PRGPIO_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R4",
+    "location": {
+      "column": "9",
+      "line": "3483",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208033@macro@SYSCTL_PRGPIO_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R3",
+    "location": {
+      "column": "9",
+      "line": "3484",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208110@macro@SYSCTL_PRGPIO_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R2",
+    "location": {
+      "column": "9",
+      "line": "3485",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208187@macro@SYSCTL_PRGPIO_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R1",
+    "location": {
+      "column": "9",
+      "line": "3486",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208264@macro@SYSCTL_PRGPIO_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRGPIO_R0",
+    "location": {
+      "column": "9",
+      "line": "3487",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRGPIO_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208592@macro@SYSCTL_PRDMA_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRDMA_R0",
+    "location": {
+      "column": "9",
+      "line": "3494",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRDMA_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@208920@macro@SYSCTL_PREPI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREPI_R0",
+    "location": {
+      "column": "9",
+      "line": "3501",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREPI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209247@macro@SYSCTL_PRHIB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRHIB_R0",
+    "location": {
+      "column": "9",
+      "line": "3508",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRHIB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209631@macro@SYSCTL_PRUART_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R7",
+    "location": {
+      "column": "9",
+      "line": "3516",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209710@macro@SYSCTL_PRUART_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R6",
+    "location": {
+      "column": "9",
+      "line": "3517",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209789@macro@SYSCTL_PRUART_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R5",
+    "location": {
+      "column": "9",
+      "line": "3518",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209868@macro@SYSCTL_PRUART_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R4",
+    "location": {
+      "column": "9",
+      "line": "3519",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@209947@macro@SYSCTL_PRUART_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R3",
+    "location": {
+      "column": "9",
+      "line": "3520",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210026@macro@SYSCTL_PRUART_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R2",
+    "location": {
+      "column": "9",
+      "line": "3521",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210105@macro@SYSCTL_PRUART_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R1",
+    "location": {
+      "column": "9",
+      "line": "3522",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210184@macro@SYSCTL_PRUART_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUART_R0",
+    "location": {
+      "column": "9",
+      "line": "3523",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUART_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210514@macro@SYSCTL_PRSSI_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R3",
+    "location": {
+      "column": "9",
+      "line": "3530",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRSSI_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210592@macro@SYSCTL_PRSSI_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R2",
+    "location": {
+      "column": "9",
+      "line": "3531",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRSSI_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210670@macro@SYSCTL_PRSSI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R1",
+    "location": {
+      "column": "9",
+      "line": "3532",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRSSI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@210748@macro@SYSCTL_PRSSI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRSSI_R0",
+    "location": {
+      "column": "9",
+      "line": "3533",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRSSI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211077@macro@SYSCTL_PRI2C_R9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R9",
+    "location": {
+      "column": "9",
+      "line": "3540",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211155@macro@SYSCTL_PRI2C_R8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R8",
+    "location": {
+      "column": "9",
+      "line": "3541",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211233@macro@SYSCTL_PRI2C_R7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R7",
+    "location": {
+      "column": "9",
+      "line": "3542",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211311@macro@SYSCTL_PRI2C_R6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R6",
+    "location": {
+      "column": "9",
+      "line": "3543",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211389@macro@SYSCTL_PRI2C_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R5",
+    "location": {
+      "column": "9",
+      "line": "3544",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211467@macro@SYSCTL_PRI2C_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R4",
+    "location": {
+      "column": "9",
+      "line": "3545",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211545@macro@SYSCTL_PRI2C_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R3",
+    "location": {
+      "column": "9",
+      "line": "3546",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211623@macro@SYSCTL_PRI2C_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R2",
+    "location": {
+      "column": "9",
+      "line": "3547",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211701@macro@SYSCTL_PRI2C_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R1",
+    "location": {
+      "column": "9",
+      "line": "3548",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@211779@macro@SYSCTL_PRI2C_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRI2C_R0",
+    "location": {
+      "column": "9",
+      "line": "3549",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRI2C_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@212108@macro@SYSCTL_PRUSB_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRUSB_R0",
+    "location": {
+      "column": "9",
+      "line": "3556",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRUSB_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@212436@macro@SYSCTL_PREPHY_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREPHY_R0",
+    "location": {
+      "column": "9",
+      "line": "3563",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREPHY_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@212820@macro@SYSCTL_PRCAN_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN_R1",
+    "location": {
+      "column": "9",
+      "line": "3571",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRCAN_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@212898@macro@SYSCTL_PRCAN_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCAN_R0",
+    "location": {
+      "column": "9",
+      "line": "3572",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRCAN_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@213227@macro@SYSCTL_PRADC_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC_R1",
+    "location": {
+      "column": "9",
+      "line": "3579",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRADC_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@213305@macro@SYSCTL_PRADC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRADC_R0",
+    "location": {
+      "column": "9",
+      "line": "3580",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRADC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@213635@macro@SYSCTL_PRACMP_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRACMP_R0",
+    "location": {
+      "column": "9",
+      "line": "3587",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRACMP_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@214026@macro@SYSCTL_PRPWM_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM_R1",
+    "location": {
+      "column": "9",
+      "line": "3595",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRPWM_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@214104@macro@SYSCTL_PRPWM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRPWM_R0",
+    "location": {
+      "column": "9",
+      "line": "3596",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRPWM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@214433@macro@SYSCTL_PRQEI_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI_R1",
+    "location": {
+      "column": "9",
+      "line": "3603",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRQEI_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@214511@macro@SYSCTL_PRQEI_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRQEI_R0",
+    "location": {
+      "column": "9",
+      "line": "3604",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRQEI_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@214847@macro@SYSCTL_PREEPROM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREEPROM_R0",
+    "location": {
+      "column": "9",
+      "line": "3612",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREEPROM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215184@macro@SYSCTL_PRWTIMER_R5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R5",
+    "location": {
+      "column": "9",
+      "line": "3620",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215336@macro@SYSCTL_PRWTIMER_R4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R4",
+    "location": {
+      "column": "9",
+      "line": "3622",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215488@macro@SYSCTL_PRWTIMER_R3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R3",
+    "location": {
+      "column": "9",
+      "line": "3624",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215640@macro@SYSCTL_PRWTIMER_R2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R2",
+    "location": {
+      "column": "9",
+      "line": "3626",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215792@macro@SYSCTL_PRWTIMER_R1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R1",
+    "location": {
+      "column": "9",
+      "line": "3628",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@215944@macro@SYSCTL_PRWTIMER_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRWTIMER_R0",
+    "location": {
+      "column": "9",
+      "line": "3630",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRWTIMER_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@216347@macro@SYSCTL_PRCCM_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRCCM_R0",
+    "location": {
+      "column": "9",
+      "line": "3638",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRCCM_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@216741@macro@SYSCTL_PRLCD_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PRLCD_R0",
+    "location": {
+      "column": "9",
+      "line": "3646",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PRLCD_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@217131@macro@SYSCTL_PROWIRE_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PROWIRE_R0",
+    "location": {
+      "column": "9",
+      "line": "3654",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PROWIRE_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@217464@macro@SYSCTL_PREMAC_R0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PREMAC_R0",
+    "location": {
+      "column": "9",
+      "line": "3661",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PREMAC_R0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@217858@macro@SYSCTL_UNIQUEID0_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID0_ID_M",
+    "location": {
+      "column": "9",
+      "line": "3670",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID0_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@217916@macro@SYSCTL_UNIQUEID0_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID0_ID_S",
+    "location": {
+      "column": "9",
+      "line": "3671",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID0_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218210@macro@SYSCTL_UNIQUEID1_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID1_ID_M",
+    "location": {
+      "column": "9",
+      "line": "3679",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID1_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218268@macro@SYSCTL_UNIQUEID1_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID1_ID_S",
+    "location": {
+      "column": "9",
+      "line": "3680",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID1_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218562@macro@SYSCTL_UNIQUEID2_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID2_ID_M",
+    "location": {
+      "column": "9",
+      "line": "3688",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID2_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218620@macro@SYSCTL_UNIQUEID2_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID2_ID_S",
+    "location": {
+      "column": "9",
+      "line": "3689",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID2_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218914@macro@SYSCTL_UNIQUEID3_ID_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID3_ID_M",
+    "location": {
+      "column": "9",
+      "line": "3697",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID3_ID_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@218972@macro@SYSCTL_UNIQUEID3_ID_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_UNIQUEID3_ID_S",
+    "location": {
+      "column": "9",
+      "line": "3698",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_UNIQUEID3_ID_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@219265@macro@SYSCTL_CCMCGREQ_DESCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CCMCGREQ_DESCFG",
+    "location": {
+      "column": "9",
+      "line": "3706",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_CCMCGREQ_DESCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@219338@macro@SYSCTL_CCMCGREQ_AESCFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CCMCGREQ_AESCFG",
+    "location": {
+      "column": "9",
+      "line": "3707",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_CCMCGREQ_AESCFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@219411@macro@SYSCTL_CCMCGREQ_SHACFG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CCMCGREQ_SHACFG",
+    "location": {
+      "column": "9",
+      "line": "3708",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_CCMCGREQ_SHACFG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@219991@macro@SYSCTL_DID0_CLASS_BLIZZARD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_BLIZZARD",
+    "location": {
+      "column": "9",
+      "line": "3723",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_BLIZZARD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@220217@macro@SYSCTL_DID0_CLASS_SNOWFLAKE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_DID0_CLASS_SNOWFLAKE",
+    "location": {
+      "column": "9",
+      "line": "3726",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_DID0_CLASS_SNOWFLAKE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@220708@macro@SYSCTL_RESC_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_RESC_HIB",
+    "location": {
+      "column": "9",
+      "line": "3736",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_RESC_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@221032@macro@SYSCTL_PWRTC_VDDA_UBOR0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWRTC_VDDA_UBOR0",
+    "location": {
+      "column": "9",
+      "line": "3744",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PWRTC_VDDA_UBOR0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_sysctl.h@221103@macro@SYSCTL_PWRTC_VDD_UBOR0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWRTC_VDD_UBOR0",
+    "location": {
+      "column": "9",
+      "line": "3745",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_sysctl.h"
+    },
+    "name": "SYSCTL_PWRTC_VDD_UBOR0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@2036@macro@__DRIVERLIB_SYSCTL_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__DRIVERLIB_SYSCTL_H__",
+    "location": {
+      "column": "9",
+      "line": "41",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "__DRIVERLIB_SYSCTL_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@2888@macro@SYSCTL_PERIPH_ADC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_ADC0",
+    "location": {
+      "column": "9",
+      "line": "63",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_ADC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@2942@macro@SYSCTL_PERIPH_ADC1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_ADC1",
+    "location": {
+      "column": "9",
+      "line": "64",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_ADC1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@2996@macro@SYSCTL_PERIPH_CAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_CAN0",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_CAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3050@macro@SYSCTL_PERIPH_CAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_CAN1",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_CAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3104@macro@SYSCTL_PERIPH_COMP0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_COMP0",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_COMP0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3179@macro@SYSCTL_PERIPH_EMAC0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_EMAC0",
+    "location": {
+      "column": "9",
+      "line": "68",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_EMAC0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3241@macro@SYSCTL_PERIPH_EPHY0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_EPHY0",
+    "location": {
+      "column": "9",
+      "line": "69",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_EPHY0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3303@macro@SYSCTL_PERIPH_EPI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_EPI0",
+    "location": {
+      "column": "9",
+      "line": "70",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_EPI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3356@macro@SYSCTL_PERIPH_GPIOA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOA",
+    "location": {
+      "column": "9",
+      "line": "71",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3411@macro@SYSCTL_PERIPH_GPIOB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOB",
+    "location": {
+      "column": "9",
+      "line": "72",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3466@macro@SYSCTL_PERIPH_GPIOC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOC",
+    "location": {
+      "column": "9",
+      "line": "73",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3521@macro@SYSCTL_PERIPH_GPIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOD",
+    "location": {
+      "column": "9",
+      "line": "74",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3576@macro@SYSCTL_PERIPH_GPIOE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOE",
+    "location": {
+      "column": "9",
+      "line": "75",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3631@macro@SYSCTL_PERIPH_GPIOF",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOF",
+    "location": {
+      "column": "9",
+      "line": "76",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOF",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3686@macro@SYSCTL_PERIPH_GPIOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOG",
+    "location": {
+      "column": "9",
+      "line": "77",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3741@macro@SYSCTL_PERIPH_GPIOH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOH",
+    "location": {
+      "column": "9",
+      "line": "78",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3796@macro@SYSCTL_PERIPH_GPIOJ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOJ",
+    "location": {
+      "column": "9",
+      "line": "79",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOJ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3851@macro@SYSCTL_PERIPH_HIBERNATE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_HIBERNATE",
+    "location": {
+      "column": "9",
+      "line": "80",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_HIBERNATE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3918@macro@SYSCTL_PERIPH_CCM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_CCM0",
+    "location": {
+      "column": "9",
+      "line": "81",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_CCM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@3972@macro@SYSCTL_PERIPH_EEPROM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_EEPROM0",
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+      "line": "82",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_EEPROM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4029@macro@SYSCTL_PERIPH_FAN0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_FAN0",
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+      "line": "83",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_FAN0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4083@macro@SYSCTL_PERIPH_FAN1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_FAN1",
+    "location": {
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+      "line": "84",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_FAN1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4137@macro@SYSCTL_PERIPH_GPIOK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOK",
+    "location": {
+      "column": "9",
+      "line": "85",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4192@macro@SYSCTL_PERIPH_GPIOL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOL",
+    "location": {
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+      "line": "86",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4247@macro@SYSCTL_PERIPH_GPIOM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOM",
+    "location": {
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+      "line": "87",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4302@macro@SYSCTL_PERIPH_GPION",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPION",
+    "location": {
+      "column": "9",
+      "line": "88",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPION",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4357@macro@SYSCTL_PERIPH_GPIOP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOP",
+    "location": {
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+      "line": "89",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4412@macro@SYSCTL_PERIPH_GPIOQ",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOQ",
+    "location": {
+      "column": "9",
+      "line": "90",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4467@macro@SYSCTL_PERIPH_GPIOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOR",
+    "location": {
+      "column": "9",
+      "line": "91",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4522@macro@SYSCTL_PERIPH_GPIOS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOS",
+    "location": {
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+      "line": "92",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4577@macro@SYSCTL_PERIPH_GPIOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_GPIOT",
+    "location": {
+      "column": "9",
+      "line": "93",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_GPIOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4632@macro@SYSCTL_PERIPH_I2C0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C0",
+    "location": {
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+      "line": "94",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4686@macro@SYSCTL_PERIPH_I2C1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C1",
+    "location": {
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+      "line": "95",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4740@macro@SYSCTL_PERIPH_I2C2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C2",
+    "location": {
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+      "line": "96",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4794@macro@SYSCTL_PERIPH_I2C3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C3",
+    "location": {
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+      "line": "97",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4848@macro@SYSCTL_PERIPH_I2C4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C4",
+    "location": {
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+      "line": "98",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4902@macro@SYSCTL_PERIPH_I2C5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C5",
+    "location": {
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+      "line": "99",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@4956@macro@SYSCTL_PERIPH_I2C6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C6",
+    "location": {
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+      "line": "100",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5010@macro@SYSCTL_PERIPH_I2C7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C7",
+    "location": {
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+      "line": "101",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5064@macro@SYSCTL_PERIPH_I2C8",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C8",
+    "location": {
+      "column": "9",
+      "line": "102",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C8",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5118@macro@SYSCTL_PERIPH_I2C9",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_I2C9",
+    "location": {
+      "column": "9",
+      "line": "103",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_I2C9",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5172@macro@SYSCTL_PERIPH_LCD0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_LCD0",
+    "location": {
+      "column": "9",
+      "line": "104",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_LCD0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5226@macro@SYSCTL_PERIPH_ONEWIRE0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_ONEWIRE0",
+    "location": {
+      "column": "9",
+      "line": "105",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_ONEWIRE0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5285@macro@SYSCTL_PERIPH_PWM0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_PWM0",
+    "location": {
+      "column": "9",
+      "line": "106",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_PWM0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5339@macro@SYSCTL_PERIPH_PWM1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_PWM1",
+    "location": {
+      "column": "9",
+      "line": "107",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_PWM1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5393@macro@SYSCTL_PERIPH_QEI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_QEI0",
+    "location": {
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+      "line": "108",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_QEI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5447@macro@SYSCTL_PERIPH_QEI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_QEI1",
+    "location": {
+      "column": "9",
+      "line": "109",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_QEI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5501@macro@SYSCTL_PERIPH_SSI0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_SSI0",
+    "location": {
+      "column": "9",
+      "line": "110",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_SSI0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5555@macro@SYSCTL_PERIPH_SSI1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_SSI1",
+    "location": {
+      "column": "9",
+      "line": "111",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_SSI1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5609@macro@SYSCTL_PERIPH_SSI2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_SSI2",
+    "location": {
+      "column": "9",
+      "line": "112",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_SSI2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5663@macro@SYSCTL_PERIPH_SSI3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_SSI3",
+    "location": {
+      "column": "9",
+      "line": "113",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_SSI3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5717@macro@SYSCTL_PERIPH_TIMER0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER0",
+    "location": {
+      "column": "9",
+      "line": "114",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5773@macro@SYSCTL_PERIPH_TIMER1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER1",
+    "location": {
+      "column": "9",
+      "line": "115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5829@macro@SYSCTL_PERIPH_TIMER2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER2",
+    "location": {
+      "column": "9",
+      "line": "116",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5885@macro@SYSCTL_PERIPH_TIMER3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER3",
+    "location": {
+      "column": "9",
+      "line": "117",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5941@macro@SYSCTL_PERIPH_TIMER4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER4",
+    "location": {
+      "column": "9",
+      "line": "118",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@5997@macro@SYSCTL_PERIPH_TIMER5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER5",
+    "location": {
+      "column": "9",
+      "line": "119",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@6053@macro@SYSCTL_PERIPH_TIMER6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER6",
+    "location": {
+      "column": "9",
+      "line": "120",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@6109@macro@SYSCTL_PERIPH_TIMER7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_TIMER7",
+    "location": {
+      "column": "9",
+      "line": "121",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_TIMER7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@6165@macro@SYSCTL_PERIPH_UART0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_UART0",
+    "location": {
+      "column": "9",
+      "line": "122",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_UART0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@6220@macro@SYSCTL_PERIPH_UART1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PERIPH_UART1",
+    "location": {
+      "column": "9",
+      "line": "123",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PERIPH_UART1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@6275@macro@SYSCTL_PERIPH_UART2",
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+    },
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+  },
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+    },
+    "name": "SYSCTL_PERIPH_UART3",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_PERIPH_UART4",
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+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_PERIPH_UART5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_PERIPH_UART6",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_PERIPH_UART7",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_PERIPH_UDMA",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_PERIPH_USB0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_PERIPH_WDOG0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    },
+    "name": "SYSCTL_PERIPH_WTIMER0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
+    "name": "SYSCTL_PERIPH_WTIMER1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "What": "MacroDef",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_LDO_0_95V",
+    "origin": "user_include",
+    "scope": null
+  },
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    "What": "MacroDef",
+    "defdec": "Def",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_LDO_1_05V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_LDO_1_10V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    "display": "SYSCTL_LDO_1_15V",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_LDO_1_15V",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
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+    "display": "SYSCTL_LDO_1_20V",
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+      "line": "154",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_LDO_1_20V",
+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_INT_BOR0",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_VDDA_OK",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_VDDA_OK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
+    "display": "SYSCTL_INT_MOSC_PUP",
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+      "line": "165",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_MOSC_PUP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@8615@macro@SYSCTL_INT_USBPLL_LOCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_USBPLL_LOCK",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_USBPLL_LOCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@8686@macro@SYSCTL_INT_PLL_LOCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_PLL_LOCK",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_PLL_LOCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_MOSC_FAIL",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_MOSC_FAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@8829@macro@SYSCTL_INT_BOR1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_BOR1",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_BOR1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@8892@macro@SYSCTL_INT_BOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_INT_BOR",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_INT_BOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "What": "MacroDef",
+    "defdec": "Def",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_HSRVREQ",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9345@macro@SYSCTL_CAUSE_HIB",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_HIB",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_HIB",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9409@macro@SYSCTL_CAUSE_WDOG1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_WDOG1",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_WDOG1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9474@macro@SYSCTL_CAUSE_SW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_SW",
+    "location": {
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+      "line": "181",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_SW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9537@macro@SYSCTL_CAUSE_WDOG0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_WDOG0",
+    "location": {
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+      "line": "182",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_WDOG0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9622@macro@SYSCTL_CAUSE_WDOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_WDOG",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_WDOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9757@macro@SYSCTL_CAUSE_BOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_BOR",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_BOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9821@macro@SYSCTL_CAUSE_POR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_POR",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_POR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@9884@macro@SYSCTL_CAUSE_EXT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CAUSE_EXT",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CAUSE_EXT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@10237@macro@SYSCTL_BOR_RESET",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_BOR_RESET",
+    "location": {
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+      "line": "197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_BOR_RESET",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@10315@macro@SYSCTL_BOR_RESAMPLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_BOR_RESAMPLE",
+    "location": {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_BOR_RESAMPLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@10733@macro@SYSCTL_PWMDIV_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_PWMDIV_1",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_PWMDIV_1",
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+  },
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+    "origin": "user_include",
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+  },
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+    },
+    "name": "SYSCTL_ONRST_WDOG0_SYS",
+    "origin": "user_include",
+    "scope": null
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+    },
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+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "SYSCTL_ONRST_WDOG1_SYS",
+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
+    "name": "SYSCTL_ONRST_BOR_SYS",
+    "origin": "user_include",
+    "scope": null
+  },
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+    "defdec": "Def",
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+    },
+    "name": "SYSCTL_ONRST_EXT_POR",
+    "origin": "user_include",
+    "scope": null
+  },
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_ONRST_EXT_SYS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
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+    "origin": "user_include",
+    "scope": null
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+      "line": "539",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@34119@macro@SYSCTL_VEVENT_VDDABO_NMI",
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+    },
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+    "origin": "user_include",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_VEVENT_VDDABO_RST",
+    "origin": "user_include",
+    "scope": null
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+    },
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+    "origin": "user_include",
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+    },
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+    "origin": "user_include",
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+  {
+    "ID": "c:sysctl.h@34538@macro@SYSCTL_VEVENT_VDDBO_NMI",
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
+  {
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+    "defdec": "Def",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_VEVENT_VDDBO_RST",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@34890@macro@SYSCTL_VESTAT_VDDBOR",
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+    },
+    "name": "SYSCTL_VESTAT_VDDBOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@34934@macro@SYSCTL_VESTAT_VDDABOR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_VESTAT_VDDABOR",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_VESTAT_VDDABOR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35198@macro@SYSCTL_NMI_MOSCFAIL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMI_MOSCFAIL",
+    "location": {
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+      "line": "565",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_MOSCFAIL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35242@macro@SYSCTL_NMI_TAMPER",
+    "What": "MacroDef",
+    "defdec": "Def",
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+      "line": "566",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_TAMPER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35286@macro@SYSCTL_NMI_WDT1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMI_WDT1",
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+      "line": "567",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_WDT1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35330@macro@SYSCTL_NMI_WDT0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMI_WDT0",
+    "location": {
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+      "line": "568",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_WDT0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35374@macro@SYSCTL_NMI_POWER",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMI_POWER",
+    "location": {
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+      "line": "569",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_POWER",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35418@macro@SYSCTL_NMI_EXTERNAL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_NMI_EXTERNAL",
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+      "line": "570",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_NMI_EXTERNAL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35686@macro@SYSCTL_CLKOUT_EN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CLKOUT_EN",
+    "location": {
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+      "line": "577",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CLKOUT_EN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35730@macro@SYSCTL_CLKOUT_DIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CLKOUT_DIS",
+    "location": {
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+      "line": "578",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CLKOUT_DIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35774@macro@SYSCTL_CLKOUT_SYSCLK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CLKOUT_SYSCLK",
+    "location": {
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+      "line": "579",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CLKOUT_SYSCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35818@macro@SYSCTL_CLKOUT_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CLKOUT_PIOSC",
+    "location": {
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+      "line": "580",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CLKOUT_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@35862@macro@SYSCTL_CLKOUT_MOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_CLKOUT_MOSC",
+    "location": {
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+      "line": "581",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_CLKOUT_MOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@36153@macro@SYSCTL_ALTCLK_PIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLK_PIOSC",
+    "location": {
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+      "line": "588",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLK_PIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@36197@macro@SYSCTL_ALTCLK_RTCOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLK_RTCOSC",
+    "location": {
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+      "line": "589",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLK_RTCOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:sysctl.h@36241@macro@SYSCTL_ALTCLK_LFIOSC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SYSCTL_ALTCLK_LFIOSC",
+    "location": {
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+      "line": "590",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SYSCTL_ALTCLK_LFIOSC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlSRAMSizeGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlSRAMSizeGet(void)",
+    "location": {
+      "column": "17",
+      "line": "597",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlSRAMSizeGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlFlashSizeGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlFlashSizeGet(void)",
+    "location": {
+      "column": "17",
+      "line": "598",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlFlashSizeGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlFlashSectorSizeGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlFlashSectorSizeGet(void)",
+    "location": {
+      "column": "17",
+      "line": "599",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlFlashSectorSizeGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralPresent",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "bool SysCtlPeripheralPresent(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "600",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralPresent",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralReady",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "bool SysCtlPeripheralReady(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "601",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralReady",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralPowerOn",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralPowerOn(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "602",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralPowerOn",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralPowerOff",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralPowerOff(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "603",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralPowerOff",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralReset",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralReset(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "604",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralReset",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "605",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "606",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralSleepEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralSleepEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "607",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralSleepEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralSleepDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralSleepDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "608",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralSleepDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralDeepSleepEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralDeepSleepEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "609",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralDeepSleepEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralDeepSleepDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralDeepSleepDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "610",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralDeepSleepDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPeripheralClockGating",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPeripheralClockGating(bool)",
+    "location": {
+      "column": "13",
+      "line": "611",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPeripheralClockGating",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntRegister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIntRegister(void (*)(void))",
+    "location": {
+      "column": "13",
+      "line": "612",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntRegister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntUnregister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIntUnregister(void)",
+    "location": {
+      "column": "13",
+      "line": "613",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntUnregister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIntEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "614",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIntDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "615",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntClear",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIntClear(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "616",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntClear",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIntStatus",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlIntStatus(bool)",
+    "location": {
+      "column": "17",
+      "line": "617",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIntStatus",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlLDOSleepSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlLDOSleepSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "618",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlLDOSleepSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlLDOSleepGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlLDOSleepGet(void)",
+    "location": {
+      "column": "17",
+      "line": "619",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlLDOSleepGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlLDODeepSleepSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlLDODeepSleepSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "620",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlLDODeepSleepSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlLDODeepSleepGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlLDODeepSleepGet(void)",
+    "location": {
+      "column": "17",
+      "line": "621",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlLDODeepSleepGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlSleepPowerSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlSleepPowerSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "622",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlSleepPowerSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlDeepSleepPowerSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlDeepSleepPowerSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "623",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlDeepSleepPowerSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlReset",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlReset(void)",
+    "location": {
+      "column": "13",
+      "line": "624",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlReset",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlSleep",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlSleep(void)",
+    "location": {
+      "column": "13",
+      "line": "625",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlSleep",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlDeepSleep",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlDeepSleep(void)",
+    "location": {
+      "column": "13",
+      "line": "626",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlDeepSleep",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlResetCauseGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlResetCauseGet(void)",
+    "location": {
+      "column": "17",
+      "line": "627",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlResetCauseGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlResetCauseClear",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlResetCauseClear(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "628",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlResetCauseClear",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlBrownOutConfigSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlBrownOutConfigSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "629",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlBrownOutConfigSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlDelay",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlDelay(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "631",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlDelay",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlMOSCConfigSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlMOSCConfigSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "632",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlMOSCConfigSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPIOSCCalibrate",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlPIOSCCalibrate(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "633",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPIOSCCalibrate",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlClockSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlClockSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "634",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlClockSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlClockGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlClockGet(void)",
+    "location": {
+      "column": "17",
+      "line": "635",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlClockGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlDeepSleepClockSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlDeepSleepClockSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "636",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlDeepSleepClockSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlDeepSleepClockConfigSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlDeepSleepClockConfigSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "637",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlDeepSleepClockConfigSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPWMClockSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPWMClockSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "639",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPWMClockSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPWMClockGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlPWMClockGet(void)",
+    "location": {
+      "column": "17",
+      "line": "640",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPWMClockGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlIOSCVerificationSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlIOSCVerificationSet(bool)",
+    "location": {
+      "column": "13",
+      "line": "641",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlIOSCVerificationSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlMOSCVerificationSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlMOSCVerificationSet(bool)",
+    "location": {
+      "column": "13",
+      "line": "642",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlMOSCVerificationSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlPLLVerificationSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlPLLVerificationSet(bool)",
+    "location": {
+      "column": "13",
+      "line": "643",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlPLLVerificationSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlClkVerificationClear",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlClkVerificationClear(void)",
+    "location": {
+      "column": "13",
+      "line": "644",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlClkVerificationClear",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlGPIOAHBEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlGPIOAHBEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "645",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlGPIOAHBEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlGPIOAHBDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlGPIOAHBDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "646",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlGPIOAHBDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlUSBPLLEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlUSBPLLEnable(void)",
+    "location": {
+      "column": "13",
+      "line": "647",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlUSBPLLEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlUSBPLLDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlUSBPLLDisable(void)",
+    "location": {
+      "column": "13",
+      "line": "648",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlUSBPLLDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlClockFreqSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlClockFreqSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "649",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlClockFreqSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlResetBehaviorSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlResetBehaviorSet(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "651",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlResetBehaviorSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlResetBehaviorGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t SysCtlResetBehaviorGet(void)",
+    "location": {
+      "column": "17",
+      "line": "652",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlResetBehaviorGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlClockOutConfig",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void SysCtlClockOutConfig(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "653",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\sysctl.h"
+    },
+    "name": "SysCtlClockOutConfig",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@SysCtlAltClkConfig",
+    "What": "Function",
+    "defdec": "Dec",
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+    "name": "TimerEnable",
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+    "name": "TimerConfigure",
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+    "name": "TimerControlLevel",
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+    "display": "void TimerControlTrigger(uint32_t, uint32_t, bool)",
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+    "name": "TimerControlTrigger",
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+    },
+    "name": "ui32Val",
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+    "display": "void TimerControlEvent(uint32_t, uint32_t, uint32_t)",
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+    },
+    "name": "TimerControlEvent",
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+    "display": "void TimerControlStall(uint32_t, uint32_t, bool)",
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+    },
+    "name": "TimerControlStall",
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+    "display": "void TimerControlWaitOnTrigger(uint32_t, uint32_t, bool)",
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+    },
+    "name": "TimerControlWaitOnTrigger",
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+    "What": "Function",
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+    "display": "void TimerRTCEnable(uint32_t)",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerRTCEnable",
+    "origin": "project_file",
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+    "What": "Function",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerRTCDisable",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
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+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerClockSourceSet(uint32_t, uint32_t)",
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+    },
+    "name": "TimerClockSourceSet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerClockSourceGet",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerClockSourceGet(uint32_t)",
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+      "line": "758",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerClockSourceGet",
+    "origin": "project_file",
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+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerPrescaleSet(uint32_t, uint32_t, uint32_t)",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerPrescaleSet",
+    "origin": "project_file",
+    "scope": null
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+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerPrescaleGet(uint32_t, uint32_t)",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerPrescaleGet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleMatchSet",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerPrescaleMatchSet(uint32_t, uint32_t, uint32_t)",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerPrescaleMatchSet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleMatchGet",
+    "What": "Function",
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+    "display": "uint32_t TimerPrescaleMatchGet(uint32_t, uint32_t)",
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+      "line": "938",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerPrescaleMatchGet",
+    "origin": "project_file",
+    "scope": null
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+    "defdec": "Def",
+    "display": "void TimerLoadSet(uint32_t, uint32_t, uint32_t)",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerLoadSet",
+    "origin": "project_file",
+    "scope": null
+  },
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+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerLoadGet(uint32_t, uint32_t)",
+    "location": {
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+      "line": "1021",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerLoadGet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadSet64",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerLoadSet64(uint32_t, uint64_t)",
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+      "line": "1050",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerLoadSet64",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadGet64",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint64_t TimerLoadGet64(uint32_t)",
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+      "line": "1079",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerLoadGet64",
+    "origin": "project_file",
+    "scope": null
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High1",
+    "origin": "project_file",
+    "scope": null
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+  {
+    "ID": "c:timer.c@39634@F@TimerLoadGet64@ui32High2",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32High2",
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+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High2",
+    "origin": "project_file",
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+  {
+    "ID": "c:timer.c@39634@F@TimerLoadGet64@ui32Low",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32Low",
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+      "line": "1081",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32Low",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerValueGet",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerValueGet(uint32_t, uint32_t)",
+    "location": {
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+      "line": "1128",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerValueGet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerValueGet64",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint64_t TimerValueGet64(uint32_t)",
+    "location": {
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+      "line": "1155",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerValueGet64",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@42124@F@TimerValueGet64@ui32High1",
+    "What": "Variable",
+    "defdec": "Def",
+    "display": "ui32High1",
+    "location": {
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+      "line": "1157",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High1",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@42124@F@TimerValueGet64@ui32High2",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32High2",
+    "location": {
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+      "line": "1157",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High2",
+    "origin": "project_file",
+    "scope": null
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+  {
+    "ID": "c:timer.c@42124@F@TimerValueGet64@ui32Low",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32Low",
+    "location": {
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+      "line": "1157",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32Low",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
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+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerMatchSet(uint32_t, uint32_t, uint32_t)",
+    "location": {
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+      "line": "1209",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerMatchSet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchGet",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerMatchGet(uint32_t, uint32_t)",
+    "location": {
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+      "line": "1255",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerMatchGet",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchSet64",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerMatchSet64(uint32_t, uint64_t)",
+    "location": {
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+      "line": "1285",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerMatchSet64",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchGet64",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint64_t TimerMatchGet64(uint32_t)",
+    "location": {
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+      "line": "1313",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerMatchGet64",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@47404@F@TimerMatchGet64@ui32High1",
+    "What": "Variable",
+    "defdec": "Def",
+    "display": "ui32High1",
+    "location": {
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+      "line": "1315",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High1",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@47404@F@TimerMatchGet64@ui32High2",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32High2",
+    "location": {
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+      "line": "1315",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32High2",
+    "origin": "project_file",
+    "scope": null
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+  {
+    "ID": "c:timer.c@47404@F@TimerMatchGet64@ui32Low",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "ui32Low",
+    "location": {
+      "column": "36",
+      "line": "1315",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32Low",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntRegister",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerIntRegister(uint32_t, uint32_t, void (*)(void))",
+    "location": {
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+      "line": "1366",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntRegister",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@49347@F@TimerIntRegister@ui32Int",
+    "What": "Variable",
+    "defdec": "Def",
+    "display": "ui32Int",
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+      "line": "1369",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32Int",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntUnregister",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerIntUnregister(uint32_t, uint32_t)",
+    "location": {
+      "column": "1",
+      "line": "1415",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntUnregister",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:timer.c@50717@F@TimerIntUnregister@ui32Int",
+    "What": "Variable",
+    "defdec": "Def",
+    "display": "ui32Int",
+    "location": {
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+      "line": "1417",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "ui32Int",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntEnable",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerIntEnable(uint32_t, uint32_t)",
+    "location": {
+      "column": "1",
+      "line": "1472",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntEnable",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntDisable",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerIntDisable(uint32_t, uint32_t)",
+    "location": {
+      "column": "1",
+      "line": "1504",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntDisable",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntStatus",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "uint32_t TimerIntStatus(uint32_t, bool)",
+    "location": {
+      "column": "1",
+      "line": "1534",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntStatus",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntClear",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerIntClear(uint32_t, uint32_t)",
+    "location": {
+      "column": "1",
+      "line": "1576",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.c"
+    },
+    "name": "TimerIntClear",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerSynchronize",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void TimerSynchronize(uint32_t, uint32_t)",
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+    "ID": "c:@elapsed_time_2",
+    "What": "Variable",
+    "defdec": "Dec",
+    "display": "elapsed_time_2",
+    "location": {
+      "column": "15",
+      "line": "23",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "elapsed_time_2",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer0_handler",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer0_handler(void)",
+    "location": {
+      "column": "6",
+      "line": "27",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer0_handler",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer1_handler",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer1_handler(void)",
+    "location": {
+      "column": "6",
+      "line": "77",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer1_handler",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer0_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer0_init(int_32)",
+    "location": {
+      "column": "6",
+      "line": "125",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer0_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer1_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer1_init(int_32)",
+    "location": {
+      "column": "6",
+      "line": "148",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer1_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTA_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTA_init(void)",
+    "location": {
+      "column": "6",
+      "line": "176",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTA_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTB_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTB_init(void)",
+    "location": {
+      "column": "6",
+      "line": "194",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTB_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTC_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTC_init(void)",
+    "location": {
+      "column": "6",
+      "line": "211",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTC_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTD_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTD_init(void)",
+    "location": {
+      "column": "6",
+      "line": "230",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTD_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTE_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTE_init(void)",
+    "location": {
+      "column": "6",
+      "line": "255",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTE_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@PORTF_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void PORTF_init(void)",
+    "location": {
+      "column": "6",
+      "line": "272",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "PORTF_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@switch_handler",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void switch_handler(void)",
+    "location": {
+      "column": "6",
+      "line": "298",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "switch_handler",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@switch1_handler",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void switch1_handler(void)",
+    "location": {
+      "column": "6",
+      "line": "319",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "switch1_handler",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@switch2_handler",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void switch2_handler(void)",
+    "location": {
+      "column": "6",
+      "line": "327",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "switch2_handler",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer0_dsiable",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer0_dsiable(void)",
+    "location": {
+      "column": "6",
+      "line": "337",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer0_dsiable",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Timer1_disable",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Timer1_disable(void)",
+    "location": {
+      "column": "6",
+      "line": "343",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Timer1_disable",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Traffic_light_init",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Traffic_light_init(void)",
+    "location": {
+      "column": "6",
+      "line": "350",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Traffic_light_init",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Ticks_to_time",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "int_32 Ticks_to_time(int_32)",
+    "location": {
+      "column": "8",
+      "line": "361",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Ticks_to_time",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@Delay",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void Delay(unsigned long)",
+    "location": {
+      "column": "6",
+      "line": "368",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "Delay",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:Traffic_light.C@13018@F@Delay@i",
+    "What": "Variable",
+    "defdec": "Def",
+    "display": "i",
+    "location": {
+      "column": "16",
+      "line": "370",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "i",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@reset_traffic_1",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void reset_traffic_1(void)",
+    "location": {
+      "column": "6",
+      "line": "377",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "reset_traffic_1",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@reset_traffic_2",
+    "What": "Function",
+    "defdec": "Def",
+    "display": "void reset_traffic_2(void)",
+    "location": {
+      "column": "6",
+      "line": "387",
+      "path": "G:\\Semester 7\\Embedded\\FinalProject\\CESS_Team4_Trafficlight\\Traffic_light.C"
+    },
+    "name": "reset_traffic_2",
+    "origin": "project_file",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2023@macro@__DRIVERLIB_GPIO_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__DRIVERLIB_GPIO_H__",
+    "location": {
+      "column": "9",
+      "line": "41",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "__DRIVERLIB_GPIO_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2641@macro@GPIO_PIN_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_0",
+    "location": {
+      "column": "9",
+      "line": "60",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2700@macro@GPIO_PIN_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_1",
+    "location": {
+      "column": "9",
+      "line": "61",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2759@macro@GPIO_PIN_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_2",
+    "location": {
+      "column": "9",
+      "line": "62",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2818@macro@GPIO_PIN_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_3",
+    "location": {
+      "column": "9",
+      "line": "63",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2877@macro@GPIO_PIN_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_4",
+    "location": {
+      "column": "9",
+      "line": "64",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2936@macro@GPIO_PIN_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_5",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@2995@macro@GPIO_PIN_6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_6",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3054@macro@GPIO_PIN_7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_7",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3399@macro@GPIO_DIR_MODE_IN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DIR_MODE_IN",
+    "location": {
+      "column": "9",
+      "line": "75",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_DIR_MODE_IN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3467@macro@GPIO_DIR_MODE_OUT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DIR_MODE_OUT",
+    "location": {
+      "column": "9",
+      "line": "76",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_DIR_MODE_OUT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3536@macro@GPIO_DIR_MODE_HW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DIR_MODE_HW",
+    "location": {
+      "column": "9",
+      "line": "77",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_DIR_MODE_HW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3901@macro@GPIO_FALLING_EDGE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_FALLING_EDGE",
+    "location": {
+      "column": "9",
+      "line": "85",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_FALLING_EDGE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@3975@macro@GPIO_RISING_EDGE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_RISING_EDGE",
+    "location": {
+      "column": "9",
+      "line": "86",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_RISING_EDGE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4048@macro@GPIO_BOTH_EDGES",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_BOTH_EDGES",
+    "location": {
+      "column": "9",
+      "line": "87",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_BOTH_EDGES",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4120@macro@GPIO_LOW_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_LOW_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "88",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_LOW_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4191@macro@GPIO_HIGH_LEVEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_HIGH_LEVEL",
+    "location": {
+      "column": "9",
+      "line": "89",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_HIGH_LEVEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4263@macro@GPIO_DISCRETE_INT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DISCRETE_INT",
+    "location": {
+      "column": "9",
+      "line": "90",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_DISCRETE_INT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4664@macro@GPIO_STRENGTH_2MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_2MA",
+    "location": {
+      "column": "9",
+      "line": "98",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_2MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4731@macro@GPIO_STRENGTH_4MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_4MA",
+    "location": {
+      "column": "9",
+      "line": "99",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_4MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4798@macro@GPIO_STRENGTH_6MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_6MA",
+    "location": {
+      "column": "9",
+      "line": "100",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_6MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4865@macro@GPIO_STRENGTH_8MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_8MA",
+    "location": {
+      "column": "9",
+      "line": "101",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_8MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@4932@macro@GPIO_STRENGTH_8MA_SC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_8MA_SC",
+    "location": {
+      "column": "9",
+      "line": "102",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_8MA_SC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5013@macro@GPIO_STRENGTH_10MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_10MA",
+    "location": {
+      "column": "9",
+      "line": "103",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_10MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5081@macro@GPIO_STRENGTH_12MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_STRENGTH_12MA",
+    "location": {
+      "column": "9",
+      "line": "104",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_STRENGTH_12MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5470@macro@GPIO_PIN_TYPE_STD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_STD",
+    "location": {
+      "column": "9",
+      "line": "112",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_STD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5528@macro@GPIO_PIN_TYPE_STD_WPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_STD_WPU",
+    "location": {
+      "column": "9",
+      "line": "113",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_STD_WPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5604@macro@GPIO_PIN_TYPE_STD_WPD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_STD_WPD",
+    "location": {
+      "column": "9",
+      "line": "114",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_STD_WPD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5682@macro@GPIO_PIN_TYPE_OD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_OD",
+    "location": {
+      "column": "9",
+      "line": "115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_OD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5741@macro@GPIO_PIN_TYPE_ANALOG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_ANALOG",
+    "location": {
+      "column": "9",
+      "line": "116",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_ANALOG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5807@macro@GPIO_PIN_TYPE_WAKE_HIGH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_WAKE_HIGH",
+    "location": {
+      "column": "9",
+      "line": "117",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_WAKE_HIGH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@5876@macro@GPIO_PIN_TYPE_WAKE_LOW",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PIN_TYPE_WAKE_LOW",
+    "location": {
+      "column": "9",
+      "line": "118",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_PIN_TYPE_WAKE_LOW",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6231@macro@GPIO_INT_PIN_0",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_0",
+    "location": {
+      "column": "9",
+      "line": "126",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_0",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6275@macro@GPIO_INT_PIN_1",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_1",
+    "location": {
+      "column": "9",
+      "line": "127",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_1",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6319@macro@GPIO_INT_PIN_2",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_2",
+    "location": {
+      "column": "9",
+      "line": "128",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_2",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6363@macro@GPIO_INT_PIN_3",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_3",
+    "location": {
+      "column": "9",
+      "line": "129",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_3",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6407@macro@GPIO_INT_PIN_4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_4",
+    "location": {
+      "column": "9",
+      "line": "130",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6451@macro@GPIO_INT_PIN_5",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_5",
+    "location": {
+      "column": "9",
+      "line": "131",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_5",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6495@macro@GPIO_INT_PIN_6",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_6",
+    "location": {
+      "column": "9",
+      "line": "132",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_6",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6539@macro@GPIO_INT_PIN_7",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_PIN_7",
+    "location": {
+      "column": "9",
+      "line": "133",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_PIN_7",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:gpio.h@6583@macro@GPIO_INT_DMA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_INT_DMA",
+    "location": {
+      "column": "9",
+      "line": "134",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIO_INT_DMA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIODirModeSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIODirModeSet(uint32_t, uint8_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "141",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIODirModeSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIODirModeGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t GPIODirModeGet(uint32_t, uint8_t)",
+    "location": {
+      "column": "17",
+      "line": "143",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIODirModeGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntTypeSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntTypeSet(uint32_t, uint8_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "144",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntTypeSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntTypeGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t GPIOIntTypeGet(uint32_t, uint8_t)",
+    "location": {
+      "column": "17",
+      "line": "146",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntTypeGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPadConfigSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPadConfigSet(uint32_t, uint8_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "147",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPadConfigSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPadConfigGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPadConfigGet(uint32_t, uint8_t, uint32_t *, uint32_t *)",
+    "location": {
+      "column": "13",
+      "line": "149",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPadConfigGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntEnable(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "151",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntDisable(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "152",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntStatus",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t GPIOIntStatus(uint32_t, bool)",
+    "location": {
+      "column": "17",
+      "line": "153",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntStatus",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntClear",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntClear(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "154",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntClear",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntRegister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntRegister(uint32_t, void (*)(void))",
+    "location": {
+      "column": "13",
+      "line": "155",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntRegister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntUnregister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntUnregister(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "156",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntUnregister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntRegisterPin",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntRegisterPin(uint32_t, uint32_t, void (*)(void))",
+    "location": {
+      "column": "13",
+      "line": "157",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntRegisterPin",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOIntUnregisterPin",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOIntUnregisterPin(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "159",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOIntUnregisterPin",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinRead",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "int32_t GPIOPinRead(uint32_t, uint8_t)",
+    "location": {
+      "column": "16",
+      "line": "160",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinRead",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinWrite",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinWrite(uint32_t, uint8_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "161",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinWrite",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinConfigure",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinConfigure(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "162",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinConfigure",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeADC",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeADC(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "163",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeADC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeCAN",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeCAN(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "164",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeCAN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeComparator",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeComparator(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "165",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeComparator",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeComparatorOutput",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeComparatorOutput(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "166",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeComparatorOutput",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeDIVSCLK",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeDIVSCLK(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "167",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeDIVSCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeEPI",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeEPI(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "168",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeEPI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeEthernetLED",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeEthernetLED(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "169",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeEthernetLED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeEthernetMII",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeEthernetMII(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "170",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeEthernetMII",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeGPIOInput",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeGPIOInput(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeGPIOInput",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeGPIOOutput",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeGPIOOutput(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "172",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeGPIOOutput",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeGPIOOutputOD",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeGPIOOutputOD(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "173",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeGPIOOutputOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeHibernateRTCCLK",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeHibernateRTCCLK(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "174",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeHibernateRTCCLK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeI2C",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeI2C(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "175",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeI2C",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeI2CSCL",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeI2CSCL(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "176",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeI2CSCL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeLCD",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeLCD(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "177",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeLCD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeOneWire",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeOneWire(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "178",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeOneWire",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypePWM",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypePWM(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "179",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypePWM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeQEI",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeQEI(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "180",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeQEI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeSSI",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeSSI(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "181",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeSSI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeTimer",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeTimer(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "182",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeTimer",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeTrace",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeTrace(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "183",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeTrace",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeUART",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeUART(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "184",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeUART",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeUSBAnalog",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeUSBAnalog(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "185",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeUSBAnalog",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeUSBDigital",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeUSBDigital(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "186",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeUSBDigital",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeWakeHigh",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeWakeHigh(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "187",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeWakeHigh",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinTypeWakeLow",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOPinTypeWakeLow(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "188",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinTypeWakeLow",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOPinWakeStatus",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t GPIOPinWakeStatus(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "189",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOPinWakeStatus",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIODMATriggerEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIODMATriggerEnable(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "190",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIODMATriggerEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIODMATriggerDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIODMATriggerDisable(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "191",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIODMATriggerDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOADCTriggerEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOADCTriggerEnable(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "192",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOADCTriggerEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOADCTriggerDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOADCTriggerDisable(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "193",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOADCTriggerDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@GPIOUnlockPin",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void GPIOUnlockPin(uint32_t, uint8_t)",
+    "location": {
+      "column": "13",
+      "line": "194",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\gpio.h"
+    },
+    "name": "GPIOUnlockPin",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2060@macro@__HW_INTS_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__HW_INTS_H__",
+    "location": {
+      "column": "9",
+      "line": "42",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "__HW_INTS_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2312@macro@FAULT_NMI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_NMI",
+    "location": {
+      "column": "9",
+      "line": "49",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_NMI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2370@macro@FAULT_HARD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_HARD",
+    "location": {
+      "column": "9",
+      "line": "50",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_HARD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2429@macro@FAULT_MPU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_MPU",
+    "location": {
+      "column": "9",
+      "line": "51",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_MPU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2487@macro@FAULT_BUS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_BUS",
+    "location": {
+      "column": "9",
+      "line": "52",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_BUS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2545@macro@FAULT_USAGE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_USAGE",
+    "location": {
+      "column": "9",
+      "line": "53",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_USAGE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2605@macro@FAULT_SVCALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_SVCALL",
+    "location": {
+      "column": "9",
+      "line": "54",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_SVCALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2660@macro@FAULT_DEBUG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_DEBUG",
+    "location": {
+      "column": "9",
+      "line": "55",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_DEBUG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2722@macro@FAULT_PENDSV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_PENDSV",
+    "location": {
+      "column": "9",
+      "line": "56",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_PENDSV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@2777@macro@FAULT_SYSTICK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FAULT_SYSTICK",
+    "location": {
+      "column": "9",
+      "line": "57",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "FAULT_SYSTICK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3038@macro@INT_GPIOA_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOA_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "64",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_GPIOA_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3098@macro@INT_GPIOB_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOB_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_GPIOB_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3158@macro@INT_GPIOC_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOC_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_GPIOC_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3218@macro@INT_GPIOD_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOD_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_GPIOD_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3278@macro@INT_GPIOE_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_GPIOE_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "68",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_GPIOE_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3338@macro@INT_UART0_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART0_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "69",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_UART0_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3392@macro@INT_UART1_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_UART1_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "70",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_UART1_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3446@macro@INT_SSI0_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_SSI0_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "71",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_SSI0_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3499@macro@INT_I2C0_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_I2C0_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "72",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_I2C0_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3552@macro@INT_PWM0_FAULT_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_FAULT_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "73",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_PWM0_FAULT_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3611@macro@INT_PWM0_0_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_0_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "74",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_PWM0_0_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3676@macro@INT_PWM0_1_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_1_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "75",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
+    "name": "INT_PWM0_1_TM4C123",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_ints.h@3741@macro@INT_PWM0_2_TM4C123",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "INT_PWM0_2_TM4C123",
+    "location": {
+      "column": "9",
+      "line": "76",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_ints.h"
+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
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+  },
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+    },
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+    },
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+    },
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+    },
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+    },
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+  },
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+    },
+    "name": "INT_COMP0_TM4C129",
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+  },
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+    },
+    "name": "INT_COMP1_TM4C129",
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+  },
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+    },
+    "name": "INT_COMP2_TM4C129",
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+  },
+  {
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+    },
+    "name": "INT_SYSCTL_TM4C129",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "INT_FLASH_TM4C129",
+    "origin": "user_include",
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+  },
+  {
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+    },
+    "name": "INT_GPIOF_TM4C129",
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+  },
+  {
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+    "display": "INT_GPIOG_TM4C129",
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+    },
+    "name": "INT_GPIOG_TM4C129",
+    "origin": "user_include",
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+  },
+  {
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+    "defdec": "Def",
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+    },
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+    },
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+    },
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+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+    "What": "MacroDef",
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+    },
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+    "origin": "user_include",
+    "scope": null
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+    "What": "MacroDef",
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+    },
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+    "origin": "user_include",
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+    },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+  },
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+    },
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+    "origin": "user_include",
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+  },
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+    },
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+    "origin": "user_include",
+    "scope": null
+  },
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+    },
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+  {
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+    },
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+    "scope": null
+  },
+  {
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+    "scope": null
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+    },
+    "name": "INT_I2C2",
+    "origin": "user_include",
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+  },
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+    "What": "MacroDef",
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+    "display": "TIMER_TBMR_TCACT_NONE",
+    "location": {
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+      "line": "146",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@8762@macro@TIMER_TBMR_TCACT_TOGGLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_TOGGLE",
+    "location": {
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+      "line": "147",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_TOGGLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@8835@macro@TIMER_TBMR_TCACT_CLRTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_CLRTO",
+    "location": {
+      "column": "9",
+      "line": "148",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_CLRTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@8905@macro@TIMER_TBMR_TCACT_SETTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_SETTO",
+    "location": {
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+      "line": "149",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_SETTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@8973@macro@TIMER_TBMR_TCACT_SETTOGTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_SETTOGTO",
+    "location": {
+      "column": "9",
+      "line": "150",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_SETTOGTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@9193@macro@TIMER_TBMR_TCACT_CLRTOGTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_CLRTOGTO",
+    "location": {
+      "column": "9",
+      "line": "153",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_CLRTOGTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@9415@macro@TIMER_TBMR_TCACT_SETCLRTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_SETCLRTO",
+    "location": {
+      "column": "9",
+      "line": "156",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_SETCLRTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@9634@macro@TIMER_TBMR_TCACT_CLRSETTO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TCACT_CLRSETTO",
+    "location": {
+      "column": "9",
+      "line": "159",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TCACT_CLRSETTO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@9853@macro@TIMER_TBMR_TBCINTD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBCINTD",
+    "location": {
+      "column": "9",
+      "line": "162",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBCINTD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@9985@macro@TIMER_TBMR_TBPLO",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBPLO",
+    "location": {
+      "column": "9",
+      "line": "164",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBPLO",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10115@macro@TIMER_TBMR_TBMRSU",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMRSU",
+    "location": {
+      "column": "9",
+      "line": "166",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMRSU",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10246@macro@TIMER_TBMR_TBPWMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBPWMIE",
+    "location": {
+      "column": "9",
+      "line": "168",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBPWMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10376@macro@TIMER_TBMR_TBILD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBILD",
+    "location": {
+      "column": "9",
+      "line": "170",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBILD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10457@macro@TIMER_TBMR_TBSNAPS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBSNAPS",
+    "location": {
+      "column": "9",
+      "line": "171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBSNAPS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10533@macro@TIMER_TBMR_TBWOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBWOT",
+    "location": {
+      "column": "9",
+      "line": "172",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBWOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10610@macro@TIMER_TBMR_TBMIE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMIE",
+    "location": {
+      "column": "9",
+      "line": "173",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMIE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10742@macro@TIMER_TBMR_TBCDIR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBCDIR",
+    "location": {
+      "column": "9",
+      "line": "175",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBCDIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10819@macro@TIMER_TBMR_TBAMS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBAMS",
+    "location": {
+      "column": "9",
+      "line": "176",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBAMS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@10950@macro@TIMER_TBMR_TBCMR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBCMR",
+    "location": {
+      "column": "9",
+      "line": "178",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBCMR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11024@macro@TIMER_TBMR_TBMR_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_M",
+    "location": {
+      "column": "9",
+      "line": "179",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMR_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11090@macro@TIMER_TBMR_TBMR_1_SHOT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_1_SHOT",
+    "location": {
+      "column": "9",
+      "line": "180",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMR_1_SHOT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11158@macro@TIMER_TBMR_TBMR_PERIOD",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_PERIOD",
+    "location": {
+      "column": "9",
+      "line": "181",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMR_PERIOD",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11226@macro@TIMER_TBMR_TBMR_CAP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_TBMR_TBMR_CAP",
+    "location": {
+      "column": "9",
+      "line": "182",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_TBMR_TBMR_CAP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11537@macro@TIMER_CTL_TBPWML",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBPWML",
+    "location": {
+      "column": "9",
+      "line": "189",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBPWML",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11615@macro@TIMER_CTL_TBOTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBOTE",
+    "location": {
+      "column": "9",
+      "line": "190",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBOTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11746@macro@TIMER_CTL_TBEVENT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_M",
+    "location": {
+      "column": "9",
+      "line": "192",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11818@macro@TIMER_CTL_TBEVENT_POS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_POS",
+    "location": {
+      "column": "9",
+      "line": "193",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_POS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11880@macro@TIMER_CTL_TBEVENT_NEG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_NEG",
+    "location": {
+      "column": "9",
+      "line": "194",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_NEG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@11942@macro@TIMER_CTL_TBEVENT_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEVENT_BOTH",
+    "location": {
+      "column": "9",
+      "line": "195",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBEVENT_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12001@macro@TIMER_CTL_TBSTALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBSTALL",
+    "location": {
+      "column": "9",
+      "line": "196",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBSTALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12075@macro@TIMER_CTL_TBEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TBEN",
+    "location": {
+      "column": "9",
+      "line": "197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TBEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12143@macro@TIMER_CTL_TAPWML",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAPWML",
+    "location": {
+      "column": "9",
+      "line": "198",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAPWML",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12221@macro@TIMER_CTL_TAOTE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAOTE",
+    "location": {
+      "column": "9",
+      "line": "199",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAOTE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12352@macro@TIMER_CTL_RTCEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_RTCEN",
+    "location": {
+      "column": "9",
+      "line": "201",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_RTCEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12422@macro@TIMER_CTL_TAEVENT_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_M",
+    "location": {
+      "column": "9",
+      "line": "202",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12494@macro@TIMER_CTL_TAEVENT_POS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_POS",
+    "location": {
+      "column": "9",
+      "line": "203",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_POS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12556@macro@TIMER_CTL_TAEVENT_NEG",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_NEG",
+    "location": {
+      "column": "9",
+      "line": "204",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_NEG",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12618@macro@TIMER_CTL_TAEVENT_BOTH",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEVENT_BOTH",
+    "location": {
+      "column": "9",
+      "line": "205",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAEVENT_BOTH",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12677@macro@TIMER_CTL_TASTALL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TASTALL",
+    "location": {
+      "column": "9",
+      "line": "206",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TASTALL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@12751@macro@TIMER_CTL_TAEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_CTL_TAEN",
+    "location": {
+      "column": "9",
+      "line": "207",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_CTL_TAEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@13070@macro@TIMER_SYNC_SYNCWT5_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_M",
+    "location": {
+      "column": "9",
+      "line": "214",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@13201@macro@TIMER_SYNC_SYNCWT5_NONE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "TIMER_SYNC_SYNCWT5_NONE",
+    "location": {
+      "column": "9",
+      "line": "216",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_timer.h"
+    },
+    "name": "TIMER_SYNC_SYNCWT5_NONE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_timer.h@13336@macro@TIMER_SYNC_SYNCWT5_TA",
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+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerConfigure(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "247",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerConfigure",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerControlLevel",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerControlLevel(uint32_t, uint32_t, bool)",
+    "location": {
+      "column": "13",
+      "line": "248",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerControlLevel",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerControlTrigger",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerControlTrigger(uint32_t, uint32_t, bool)",
+    "location": {
+      "column": "13",
+      "line": "250",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerControlTrigger",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerControlEvent",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerControlEvent(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "252",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerControlEvent",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerControlStall",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerControlStall(uint32_t, uint32_t, bool)",
+    "location": {
+      "column": "13",
+      "line": "254",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerControlStall",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerControlWaitOnTrigger",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerControlWaitOnTrigger(uint32_t, uint32_t, bool)",
+    "location": {
+      "column": "13",
+      "line": "256",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerControlWaitOnTrigger",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerRTCEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerRTCEnable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "258",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerRTCEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerRTCDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerRTCDisable(uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "259",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerRTCDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerPrescaleSet(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "260",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerPrescaleSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerPrescaleGet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "262",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerPrescaleGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleMatchSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerPrescaleMatchSet(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "263",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerPrescaleMatchSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerPrescaleMatchGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerPrescaleMatchGet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "265",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerPrescaleMatchGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerLoadSet(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "266",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerLoadSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerLoadGet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "268",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerLoadGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadSet64",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerLoadSet64(uint32_t, uint64_t)",
+    "location": {
+      "column": "13",
+      "line": "269",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerLoadSet64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerLoadGet64",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint64_t TimerLoadGet64(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "270",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerLoadGet64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerValueGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerValueGet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "271",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerValueGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerValueGet64",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint64_t TimerValueGet64(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "272",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerValueGet64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerMatchSet(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "273",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerMatchSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerMatchGet(uint32_t, uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "275",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerMatchGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchSet64",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerMatchSet64(uint32_t, uint64_t)",
+    "location": {
+      "column": "13",
+      "line": "276",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerMatchSet64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerMatchGet64",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint64_t TimerMatchGet64(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "277",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerMatchGet64",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntRegister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerIntRegister(uint32_t, uint32_t, void (*)(void))",
+    "location": {
+      "column": "13",
+      "line": "278",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntRegister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntUnregister",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerIntUnregister(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "280",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntUnregister",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntEnable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerIntEnable(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "281",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntEnable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntDisable",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerIntDisable(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "282",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntDisable",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntStatus",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerIntStatus(uint32_t, bool)",
+    "location": {
+      "column": "17",
+      "line": "283",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntStatus",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerIntClear",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerIntClear(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "284",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerIntClear",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerSynchronize",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerSynchronize(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "285",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerSynchronize",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerClockSourceGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerClockSourceGet(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "286",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerClockSourceGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerClockSourceSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerClockSourceSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "287",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerClockSourceSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerADCEventGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerADCEventGet(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "288",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerADCEventGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerADCEventSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerADCEventSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "289",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerADCEventSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerDMAEventGet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "uint32_t TimerDMAEventGet(uint32_t)",
+    "location": {
+      "column": "17",
+      "line": "290",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerDMAEventGet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerDMAEventSet",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerDMAEventSet(uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "291",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerDMAEventSet",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@TimerUpdateMode",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void TimerUpdateMode(uint32_t, uint32_t, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "292",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\timer.h"
+    },
+    "name": "TimerUpdateMode",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2039@macro@__HW_MEMMAP_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__HW_MEMMAP_H__",
+    "location": {
+      "column": "9",
+      "line": "41",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "__HW_MEMMAP_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2324@macro@FLASH_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "FLASH_BASE",
+    "location": {
+      "column": "9",
+      "line": "49",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "FLASH_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2385@macro@SRAM_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SRAM_BASE",
+    "location": {
+      "column": "9",
+      "line": "50",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "SRAM_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2445@macro@WATCHDOG0_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WATCHDOG0_BASE",
+    "location": {
+      "column": "9",
+      "line": "51",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "WATCHDOG0_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2503@macro@WATCHDOG1_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "WATCHDOG1_BASE",
+    "location": {
+      "column": "9",
+      "line": "52",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "WATCHDOG1_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2561@macro@GPIO_PORTA_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTA_BASE",
+    "location": {
+      "column": "9",
+      "line": "53",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "GPIO_PORTA_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2621@macro@GPIO_PORTB_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTB_BASE",
+    "location": {
+      "column": "9",
+      "line": "54",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "GPIO_PORTB_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2681@macro@GPIO_PORTC_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTC_BASE",
+    "location": {
+      "column": "9",
+      "line": "55",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "GPIO_PORTC_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2741@macro@GPIO_PORTD_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PORTD_BASE",
+    "location": {
+      "column": "9",
+      "line": "56",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "GPIO_PORTD_BASE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_memmap.h@2801@macro@SSI0_BASE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "SSI0_BASE",
+    "location": {
+      "column": "9",
+      "line": "57",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_memmap.h"
+    },
+    "name": "SSI0_BASE",
+    "origin": "user_include",
+    "scope": null
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+      "column": "9",
+      "line": "49",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DIR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2404@macro@GPIO_O_IS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_IS",
+    "location": {
+      "column": "9",
+      "line": "50",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_IS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2473@macro@GPIO_O_IBE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_IBE",
+    "location": {
+      "column": "9",
+      "line": "51",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_IBE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2547@macro@GPIO_O_IEV",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_IEV",
+    "location": {
+      "column": "9",
+      "line": "52",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_IEV",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2616@macro@GPIO_O_IM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_IM",
+    "location": {
+      "column": "9",
+      "line": "53",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_IM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2684@macro@GPIO_O_RIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_RIS",
+    "location": {
+      "column": "9",
+      "line": "54",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_RIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2758@macro@GPIO_O_MIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_MIS",
+    "location": {
+      "column": "9",
+      "line": "55",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_MIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2835@macro@GPIO_O_ICR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_ICR",
+    "location": {
+      "column": "9",
+      "line": "56",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_ICR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2904@macro@GPIO_O_AFSEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_AFSEL",
+    "location": {
+      "column": "9",
+      "line": "57",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_AFSEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@2983@macro@GPIO_O_DR2R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DR2R",
+    "location": {
+      "column": "9",
+      "line": "58",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DR2R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3054@macro@GPIO_O_DR4R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DR4R",
+    "location": {
+      "column": "9",
+      "line": "59",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DR4R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3125@macro@GPIO_O_DR8R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DR8R",
+    "location": {
+      "column": "9",
+      "line": "60",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DR8R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3196@macro@GPIO_O_ODR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_ODR",
+    "location": {
+      "column": "9",
+      "line": "61",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_ODR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3267@macro@GPIO_O_PUR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_PUR",
+    "location": {
+      "column": "9",
+      "line": "62",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_PUR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3335@macro@GPIO_O_PDR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_PDR",
+    "location": {
+      "column": "9",
+      "line": "63",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_PDR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3405@macro@GPIO_O_SLR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_SLR",
+    "location": {
+      "column": "9",
+      "line": "64",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_SLR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3483@macro@GPIO_O_DEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DEN",
+    "location": {
+      "column": "9",
+      "line": "65",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3551@macro@GPIO_O_LOCK",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_LOCK",
+    "location": {
+      "column": "9",
+      "line": "66",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_LOCK",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3609@macro@GPIO_O_CR",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_CR",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_CR",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3669@macro@GPIO_O_AMSEL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_AMSEL",
+    "location": {
+      "column": "9",
+      "line": "68",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_AMSEL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3741@macro@GPIO_O_PCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_PCTL",
+    "location": {
+      "column": "9",
+      "line": "69",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_PCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3807@macro@GPIO_O_ADCCTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_ADCCTL",
+    "location": {
+      "column": "9",
+      "line": "70",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_ADCCTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3872@macro@GPIO_O_DMACTL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DMACTL",
+    "location": {
+      "column": "9",
+      "line": "71",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DMACTL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@3937@macro@GPIO_O_SI",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_SI",
+    "location": {
+      "column": "9",
+      "line": "72",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_SI",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4007@macro@GPIO_O_DR12R",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_DR12R",
+    "location": {
+      "column": "9",
+      "line": "73",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_DR12R",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4079@macro@GPIO_O_WAKEPEN",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_WAKEPEN",
+    "location": {
+      "column": "9",
+      "line": "74",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_WAKEPEN",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4148@macro@GPIO_O_WAKELVL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_WAKELVL",
+    "location": {
+      "column": "9",
+      "line": "75",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_WAKELVL",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4212@macro@GPIO_O_WAKESTAT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_WAKESTAT",
+    "location": {
+      "column": "9",
+      "line": "76",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_WAKESTAT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4277@macro@GPIO_O_PP",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_PP",
+    "location": {
+      "column": "9",
+      "line": "77",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_PP",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4350@macro@GPIO_O_PC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_O_PC",
+    "location": {
+      "column": "9",
+      "line": "78",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_O_PC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4676@macro@GPIO_IM_DMAIME",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_IM_DMAIME",
+    "location": {
+      "column": "9",
+      "line": "85",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_IM_DMAIME",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4809@macro@GPIO_IM_GPIO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_IM_GPIO_M",
+    "location": {
+      "column": "9",
+      "line": "87",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_IM_GPIO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@4884@macro@GPIO_IM_GPIO_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_IM_GPIO_S",
+    "location": {
+      "column": "9",
+      "line": "88",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_IM_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5168@macro@GPIO_RIS_DMARIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_RIS_DMARIS",
+    "location": {
+      "column": "9",
+      "line": "95",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_RIS_DMARIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5300@macro@GPIO_RIS_GPIO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_RIS_GPIO_M",
+    "location": {
+      "column": "9",
+      "line": "97",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_RIS_GPIO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5374@macro@GPIO_RIS_GPIO_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_RIS_GPIO_S",
+    "location": {
+      "column": "9",
+      "line": "98",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_RIS_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5658@macro@GPIO_MIS_DMAMIS",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_MIS_DMAMIS",
+    "location": {
+      "column": "9",
+      "line": "105",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_MIS_DMAMIS",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5793@macro@GPIO_MIS_GPIO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_MIS_GPIO_M",
+    "location": {
+      "column": "9",
+      "line": "107",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_MIS_GPIO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@5870@macro@GPIO_MIS_GPIO_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_MIS_GPIO_S",
+    "location": {
+      "column": "9",
+      "line": "108",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_MIS_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6154@macro@GPIO_ICR_DMAIC",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_ICR_DMAIC",
+    "location": {
+      "column": "9",
+      "line": "115",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_ICR_DMAIC",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6228@macro@GPIO_ICR_GPIO_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_ICR_GPIO_M",
+    "location": {
+      "column": "9",
+      "line": "116",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_ICR_GPIO_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6297@macro@GPIO_ICR_GPIO_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_ICR_GPIO_S",
+    "location": {
+      "column": "9",
+      "line": "117",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_ICR_GPIO_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6582@macro@GPIO_LOCK_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_LOCK_M",
+    "location": {
+      "column": "9",
+      "line": "124",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_LOCK_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6640@macro@GPIO_LOCK_UNLOCKED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_LOCK_UNLOCKED",
+    "location": {
+      "column": "9",
+      "line": "125",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_LOCK_UNLOCKED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6788@macro@GPIO_LOCK_LOCKED",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_LOCK_LOCKED",
+    "location": {
+      "column": "9",
+      "line": "127",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_LOCK_LOCKED",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@6938@macro@GPIO_LOCK_KEY",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_LOCK_KEY",
+    "location": {
+      "column": "9",
+      "line": "129",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_LOCK_KEY",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@7263@macro@GPIO_SI_SUM",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_SI_SUM",
+    "location": {
+      "column": "9",
+      "line": "136",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_SI_SUM",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@7580@macro@GPIO_DR12R_DRV12_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DR12R_DRV12_M",
+    "location": {
+      "column": "9",
+      "line": "143",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_DR12R_DRV12_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@7658@macro@GPIO_DR12R_DRV12_12MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_DR12R_DRV12_12MA",
+    "location": {
+      "column": "9",
+      "line": "144",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_DR12R_DRV12_12MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@8362@macro@GPIO_WAKEPEN_WAKEP4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_WAKEPEN_WAKEP4",
+    "location": {
+      "column": "9",
+      "line": "156",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_WAKEPEN_WAKEP4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@8680@macro@GPIO_WAKELVL_WAKELVL4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_WAKELVL_WAKELVL4",
+    "location": {
+      "column": "9",
+      "line": "163",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_WAKELVL_WAKELVL4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9002@macro@GPIO_WAKESTAT_STAT4",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_WAKESTAT_STAT4",
+    "location": {
+      "column": "9",
+      "line": "171",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_WAKESTAT_STAT4",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9315@macro@GPIO_PP_EDE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PP_EDE",
+    "location": {
+      "column": "9",
+      "line": "178",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PP_EDE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9633@macro@GPIO_PC_EDM7_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM7_M",
+    "location": {
+      "column": "9",
+      "line": "185",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM7_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9707@macro@GPIO_PC_EDM6_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM6_M",
+    "location": {
+      "column": "9",
+      "line": "186",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM6_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9781@macro@GPIO_PC_EDM5_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM5_M",
+    "location": {
+      "column": "9",
+      "line": "187",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM5_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9855@macro@GPIO_PC_EDM4_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM4_M",
+    "location": {
+      "column": "9",
+      "line": "188",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM4_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@9929@macro@GPIO_PC_EDM3_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM3_M",
+    "location": {
+      "column": "9",
+      "line": "189",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM3_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10003@macro@GPIO_PC_EDM2_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM2_M",
+    "location": {
+      "column": "9",
+      "line": "190",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM2_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10077@macro@GPIO_PC_EDM1_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM1_M",
+    "location": {
+      "column": "9",
+      "line": "191",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM1_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10151@macro@GPIO_PC_EDM0_M",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM0_M",
+    "location": {
+      "column": "9",
+      "line": "192",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM0_M",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10225@macro@GPIO_PC_EDM0_DISABLE",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM0_DISABLE",
+    "location": {
+      "column": "9",
+      "line": "193",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM0_DISABLE",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10523@macro@GPIO_PC_EDM0_6MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM0_6MA",
+    "location": {
+      "column": "9",
+      "line": "197",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM0_6MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@10657@macro@GPIO_PC_EDM0_PLUS2MA",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM0_PLUS2MA",
+    "location": {
+      "column": "9",
+      "line": "199",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM0_PLUS2MA",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11125@macro@GPIO_PC_EDM7_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM7_S",
+    "location": {
+      "column": "9",
+      "line": "205",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM7_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11161@macro@GPIO_PC_EDM6_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM6_S",
+    "location": {
+      "column": "9",
+      "line": "206",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM6_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11197@macro@GPIO_PC_EDM5_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM5_S",
+    "location": {
+      "column": "9",
+      "line": "207",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM5_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11233@macro@GPIO_PC_EDM4_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM4_S",
+    "location": {
+      "column": "9",
+      "line": "208",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM4_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11268@macro@GPIO_PC_EDM3_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM3_S",
+    "location": {
+      "column": "9",
+      "line": "209",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM3_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11303@macro@GPIO_PC_EDM2_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM2_S",
+    "location": {
+      "column": "9",
+      "line": "210",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM2_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:hw_gpio.h@11338@macro@GPIO_PC_EDM1_S",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "GPIO_PC_EDM1_S",
+    "location": {
+      "column": "9",
+      "line": "211",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\inc\\hw_gpio.h"
+    },
+    "name": "GPIO_PC_EDM1_S",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:debug.h@2042@macro@__DRIVERLIB_DEBUG_H__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__DRIVERLIB_DEBUG_H__",
+    "location": {
+      "column": "9",
+      "line": "41",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\debug.h"
+    },
+    "name": "__DRIVERLIB_DEBUG_H__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:@F@__error__",
+    "What": "Function",
+    "defdec": "Dec",
+    "display": "void __error__(char *, uint32_t)",
+    "location": {
+      "column": "13",
+      "line": "49",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\debug.h"
+    },
+    "name": "__error__",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:debug.h@3356@macro@ASSERT",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "ASSERT",
+    "location": {
+      "column": "9",
+      "line": "67",
+      "path": "C:\\ti\\TivaWare_C_Series-2.2.0.295\\driverlib\\debug.h"
+    },
+    "name": "ASSERT",
+    "origin": "user_include",
+    "scope": null
+  },
+  {
+    "ID": "c:stdbool.h@96@macro@_STDBOOL",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "_STDBOOL",
+    "location": {
+      "column": "9",
+      "line": "5",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\stdbool.h"
+    },
+    "name": "_STDBOOL",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:stdbool.h@200@macro@bool",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "bool",
+    "location": {
+      "column": "11",
+      "line": "13",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\stdbool.h"
+    },
+    "name": "bool",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:stdbool.h@225@macro@true",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "true",
+    "location": {
+      "column": "11",
+      "line": "14",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\stdbool.h"
+    },
+    "name": "true",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:stdbool.h@246@macro@false",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "false",
+    "location": {
+      "column": "11",
+      "line": "15",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\stdbool.h"
+    },
+    "name": "false",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:stdbool.h@275@macro@__bool_true_false_are_defined",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__bool_true_false_are_defined",
+    "location": {
+      "column": "9",
+      "line": "18",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\stdbool.h"
+    },
+    "name": "__bool_true_false_are_defined",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@111@macro@_YSIZET_H",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "_YSIZET_H",
+    "location": {
+      "column": "9",
+      "line": "5",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "_YSIZET_H",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@277@macro@_SIZE_T",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "_SIZE_T",
+    "location": {
+      "column": "11",
+      "line": "16",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "_SIZE_T",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@296@macro@_STD_USING_SIZE_T",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "_STD_USING_SIZE_T",
+    "location": {
+      "column": "11",
+      "line": "17",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "_STD_USING_SIZE_T",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@T@size_t",
+    "What": "Typedef",
+    "defdec": "Def",
+    "display": "_Sizet",
+    "location": {
+      "column": "18",
+      "line": "18",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "size_t",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@359@macro@__DATA_PTR_MEM_HELPER1__",
+    "What": "MacroDef",
+    "defdec": "Def",
+    "display": "__DATA_PTR_MEM_HELPER1__",
+    "location": {
+      "column": "9",
+      "line": "21",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "__DATA_PTR_MEM_HELPER1__",
+    "origin": "system_include",
+    "scope": null
+  },
+  {
+    "ID": "c:ysizet.h@T@__data_size_t",
+    "What": "Typedef",
+    "defdec": "Def",
+    "display": "unsigned int",
+    "location": {
+      "column": "1",
+      "line": "23",
+      "path": "C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\ysizet.h"
+    },
+    "name": "__data_size_t",
+    "origin": "system_include",
+    "scope": null
+  }
+]
\ No newline at end of file
diff --git a/Debug/BrowseInfo/Traffic_light.pbi b/Debug/BrowseInfo/Traffic_light.pbi
new file mode 100644
index 0000000..d68c24d
Binary files /dev/null and b/Debug/BrowseInfo/Traffic_light.pbi differ
diff --git a/Debug/BrowseInfo/Traffic_light.pbi.dep b/Debug/BrowseInfo/Traffic_light.pbi.dep
new file mode 100644
index 0000000..0950ee3
--- /dev/null
+++ b/Debug/BrowseInfo/Traffic_light.pbi.dep
@@ -0,0 +1,26 @@
+G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi: \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\tm4c123gh6pm.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\timer.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\interrupt.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\debug.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_sysctl.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_timer.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\timer.c \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_ints.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_types.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\sysctl.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_memmap.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_gpio.h \
+  C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\gpio.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\stdbool.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\ycheck.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\ysizet.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\stdio.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Product.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Config_Normal.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\DLib_Defaults.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\yvals.h \
+  C:\Program\ Files\IAR\ Systems\Embedded\ Workbench\ 9.0\arm\inc\c\stdint.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\types.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.C
diff --git a/Debug/BrowseInfo/Traffic_light.xcl b/Debug/BrowseInfo/Traffic_light.xcl
new file mode 100644
index 0000000..b42f56d
--- /dev/null
+++ b/Debug/BrowseInfo/Traffic_light.xcl
@@ -0,0 +1,368 @@
+"G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.C"
+-std=c11
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+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi.dep
+-o
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi
+-I
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight
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+C:\ti\TivaWare_C_Series-2.2.0.295
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diff --git a/Debug/BrowseInfo/build.ninja b/Debug/BrowseInfo/build.ninja
new file mode 100644
index 0000000..b6da3a0
--- /dev/null
+++ b/Debug/BrowseInfo/build.ninja
@@ -0,0 +1,61 @@
+##IAR Ninja build file
+
+
+#Rules
+rule COMPILER_XCL
+  command = C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\XclFileGenerator.exe $xclcommand -f "$rspfile_name"
+  description = IAR_NEW_TOOL+++COMPILER_XCL+++$in+++"C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\XclFileGenerator.exe" $flags
+  rspfile = $rspfile_name
+  rspfile_content = $flags
+
+rule INDEXER
+  command = C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\SourceIndexer.exe $flags
+  depfile = $out.dep
+  description = IAR_NEW_TOOL+++INDEXER+++$out+++"C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\SourceIndexer.exe" $flags
+
+rule MAKEBROWSE
+  command = C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\makeBrowseData.exe $flags
+  description = IAR_NEW_TOOL+++MAKEBROWSE+++$out+++"C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\makeBrowseData.exe" $flags
+
+rule PDBLINK
+  command = C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\PbdLink.exe $flags
+  description = IAR_NEW_TOOL+++PDBLINK+++$out+++"C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\common\bin\PbdLink.exe" $flags
+
+
+
+#Build steps
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.xcl : COMPILER_XCL 
+  xclcommand = -source_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.C" -xcl_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.xcl" -macro_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.tmp" -icc_path "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\bin\iccarm.exe"
+  flags = "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.C" -D ewarm -D PART_TM4C123GH6PM -D TARGET_IS_TM4C123_RB1 -o "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\\" --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa --no_clustering --no_scheduling --debug --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp --dlib_config "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\inc\c\DLib_Config_Normal.h" -I C$:\ti\TivaWare_C_Series-2.2.0.295\ -Ol --predef_macros "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.tmp"
+  rspfile_name = G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.xcl.rsp
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.xcl : COMPILER_XCL 
+  xclcommand = -source_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\main.c" -xcl_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.xcl" -macro_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.tmp" -icc_path "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\bin\iccarm.exe"
+  flags = "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\main.c" -D ewarm -D PART_TM4C123GH6PM -D TARGET_IS_TM4C123_RB1 -o "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\\" --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa --no_clustering --no_scheduling --debug --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp --dlib_config "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\inc\c\DLib_Config_Normal.h" -I C$:\ti\TivaWare_C_Series-2.2.0.295\ -Ol --predef_macros "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.tmp"
+  rspfile_name = G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.xcl.rsp
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.xcl : COMPILER_XCL 
+  xclcommand = -source_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.C" -xcl_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.xcl" -macro_file "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.tmp" -icc_path "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\bin\iccarm.exe"
+  flags = "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.C" -D ewarm -D PART_TM4C123GH6PM -D TARGET_IS_TM4C123_RB1 -o "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\\" --no_cse --no_unroll --no_inline --no_code_motion --no_tbaa --no_clustering --no_scheduling --debug --endian=little --cpu=Cortex-M4 -e --fpu=VFPv4_sp --dlib_config "C$:\Program$ Files\IAR$ Systems\Embedded$ Workbench$ 9.0\arm\inc\c\DLib_Config_Normal.h" -I C$:\ti\TivaWare_C_Series-2.2.0.295\ -Ol --predef_macros "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.tmp"
+  rspfile_name = G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.xcl.rsp
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi : INDEXER G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.xcl |  $
+G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\DIO.C
+  flags = "-out=G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi" -f "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.xcl"
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi : INDEXER G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.xcl |  $
+G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\main.c
+  flags = "-out=G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi" -f "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.xcl"
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi : INDEXER G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.xcl |  $
+G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.C
+  flags = "-out=G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi" -f "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.xcl"
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbw : MAKEBROWSE G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbd
+  flags = "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbd" -output "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbw"
+
+build G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbd : PDBLINK G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi |  $
+G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi $
+G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi
+  flags = -M "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\TrafficLight.pbd" "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\DIO.pbi" "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi" "G$:\Semester$ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\Traffic_light.pbi"
+
diff --git a/Debug/BrowseInfo/main.pbi b/Debug/BrowseInfo/main.pbi
new file mode 100644
index 0000000..707af93
Binary files /dev/null and b/Debug/BrowseInfo/main.pbi differ
diff --git a/Debug/BrowseInfo/main.pbi.dep b/Debug/BrowseInfo/main.pbi.dep
new file mode 100644
index 0000000..37e7a33
--- /dev/null
+++ b/Debug/BrowseInfo/main.pbi.dep
@@ -0,0 +1,4 @@
+G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi: \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\types.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Traffic_light.h \
+  G:\Semester\ 7\Embedded\FinalProject\CESS_Team4_Trafficlight\main.c
diff --git a/Debug/BrowseInfo/main.xcl b/Debug/BrowseInfo/main.xcl
new file mode 100644
index 0000000..3c9fb24
--- /dev/null
+++ b/Debug/BrowseInfo/main.xcl
@@ -0,0 +1,368 @@
+"G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\main.c"
+-std=c11
+-ferror-limit=0
+-fbracket-depth=512
+-funsigned-char
+-MD
+-MF
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi.dep
+-o
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\BrowseInfo\main.pbi
+-I
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight
+-I
+C:\ti\TivaWare_C_Series-2.2.0.295
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\aarch32
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc
+-I
+C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c
+-I
+C:\ti\TivaWare_C_Series-2.2.0.295
+-D__CHAR_BITS__=8
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+-D__UINT64_T_TYPE__=unsigned long long int
+-D__UINT64_T_MAX__=0xffffffffffffffffULL
+-D__INT64_SIZE_PREFIX__="ll"
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+-D__INT_LEAST64_T_TYPE__=signed long long int
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+-D__cpp_hex_float=201603L
+-D__cpp_unicode_literals=200710L
+-D__cpp_static_assert=200410L
+-D__EDG__=1
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+-D__EDG_IA64_ABI_USE_VARIANT_ARRAY_COOKIES=1
+-D__EDG_ABI_COMPATIBILITY_VERSION=9999
+-D__EDG_ABI_CHANGES_FOR_RTTI=1
+-D__EDG_ABI_CHANGES_FOR_ARRAY_NEW_AND_DELETE=1
+-D__EDG_ABI_CHANGES_FOR_PLACEMENT_DELETE=1
+-D__EDG_BSD=0
+-D__EDG_SYSV=0
+-D__EDG_ANSIC=1
+-D__EDG_CPP11_IL_EXTENSIONS_SUPPORTED=1
+-D__EDG_FLOAT80_ENABLING_POSSIBLE=0
+-D__EDG_FLOAT128_ENABLING_POSSIBLE=0
+-D__EDG_INT128_EXTENSIONS_ALLOWED=0
+-Dewarm=1
+-DPART_TM4C123GH6PM=1
+-DTARGET_IS_TM4C123_RB1=1
+-D_DLIB_CONFIG_FILE_HEADER_NAME="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h"
+-D_DLIB_CONFIG_FILE_STRING="C:\\Program Files\\IAR Systems\\Embedded Workbench 9.0\\arm\\inc\\c\\DLib_Config_Normal.h"
+-D__VERSION__="IAR ANSI C/C++ Compiler V9.10.2.313/W64 for ARM"
+-D_VA_DEFINED=
+-D_VA_LIST=struct __va_list
+-D__ICCARM_OLD_DEFINED_VAARGS__=1
+-D__VA_STACK_ALIGN__=8
+-D__CODE_MEMORY_LIST1__()=__CODE_MEM_HELPER1__(__code, 0 )
+-D__CODE_MEMORY_LIST2__(_P1)=__CODE_MEM_HELPER2__(__code, 0 ,  _P1 )
+-D__CODE_MEMORY_LIST3__(_P1,_P2)=__CODE_MEM_HELPER3__(__code, 0 ,  _P1 ,  _P2 )
+-D__DATA_MEMORY_LIST1__()=__DATA_MEM_HELPER1__(__data, 0 )
+-D__DATA_MEMORY_LIST2__(_P1)=__DATA_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__DATA_MEMORY_LIST3__(_P1,_P2)=__DATA_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__CODE_PTR_MEMORY_LIST1__()=__CODE_PTR_MEM_HELPER1__(__code, 0 )
+-D__CODE_PTR_MEMORY_LIST2__(_P1)=__CODE_PTR_MEM_HELPER2__(__code, 0 ,  _P1 )
+-D__CODE_PTR_MEMORY_LIST3__(_P1,_P2)=__CODE_PTR_MEM_HELPER3__(__code, 0 ,  _P1 ,  _P2 )
+-D__DATA_PTR_MEMORY_LIST1__()=__DATA_PTR_MEM_HELPER1__(__data, 0 )
+-D__DATA_PTR_MEMORY_LIST2__(_P1)=__DATA_PTR_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__DATA_PTR_MEMORY_LIST3__(_P1,_P2)=__DATA_PTR_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__VAR_MEMORY_LIST1__()=__VAR_MEM_HELPER1__(__data, 0 )
+-D__VAR_MEMORY_LIST2__(_P1)=__VAR_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__VAR_MEMORY_LIST3__(_P1,_P2)=__VAR_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__VARD_MEMORY_LIST1__()=__VARD_MEM_HELPER1__(__data, 0, _ )
+-D__HEAP_MEMORY_LIST1__()=__HEAP_MEM_HELPER1__(__data, 0 )
+-D__HEAP_MEMORY_LIST2__(_P1)=__HEAP_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__HEAP_MEMORY_LIST3__(_P1,_P2)=__HEAP_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__HVAR_MEMORY_LIST1__()=__HVAR_MEM_HELPER1__(__data, 0 )
+-D__HEAPD_MEMORY_LIST1__()=__HEAPD_MEM_HELPER1__(__data, 0, _ )
+-D__HEAPU_MEMORY_LIST1__()=__HEAPU_MEM_HELPER1__(__data, 0 )
+-D__TOPM_DATA_MEMORY_LIST1__()=
+-D__TOPM_DATA_MEMORY_LIST2__(_P1)=
+-D__TOPM_DATA_MEMORY_LIST3__(_P1,_P2)=
+-D__TOPP_DATA_MEMORY_LIST1__()=__TOPP_DATA_MEM_HELPER1__(__data, 0 )
+-D__TOPP_DATA_MEMORY_LIST2__(_P1)=__TOPP_DATA_MEM_HELPER2__(__data, 0 ,  _P1 )
+-D__TOPP_DATA_MEMORY_LIST3__(_P1,_P2)=__TOPP_DATA_MEM_HELPER3__(__data, 0 ,  _P1 ,  _P2 )
+-D__DATA_MEM0_SIZE_TYPE__=unsigned int
+-D__DATA_MEM0_INDEX_TYPE__=signed int
+-D__iar_fp2bits32(x)=0
+-D__iar_fp2bits64(x)=0
+-D__iar_fpgethi64(x)=0
+-D__iar_atomic_add_fetch(x,y,z)=0
+-D__iar_atomic_sub_fetch(x,y,z)=0
+-D__iar_atomic_load(x,y)=0ULL
+-D__iar_atomic_compare_exchange_weak(a,b,c,d,e)=0
diff --git a/Debug/Exe/TrafficLight.out b/Debug/Exe/TrafficLight.out
new file mode 100644
index 0000000..ae1d55f
Binary files /dev/null and b/Debug/Exe/TrafficLight.out differ
diff --git a/Debug/Exe/TrafficLight.sim b/Debug/Exe/TrafficLight.sim
new file mode 100644
index 0000000..da04c30
Binary files /dev/null and b/Debug/Exe/TrafficLight.sim differ
diff --git a/Debug/List/TrafficLight.map b/Debug/List/TrafficLight.map
new file mode 100644
index 0000000..cddf64d
--- /dev/null
+++ b/Debug/List/TrafficLight.map
@@ -0,0 +1,321 @@
+###############################################################################
+#
+# IAR ELF Linker V9.10.2.313/W64 for ARM                  13/Jan/2022  21:15:39
+# Copyright 2007-2021 IAR Systems AB.
+#
+#    Output file  =
+#        G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Exe\TrafficLight.out
+#    Map file     =
+#        G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\List\TrafficLight.map
+#    Command line =
+#        -f "G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Exe\TrafficLight.out.rsp"
+#        ("G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\DIO.o"
+#        "G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\main.o"
+#        "G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj\Traffic_light.o"
+#        --no_out_extension -o "G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Exe\TrafficLight.out"
+#        --redirect _Printf=_PrintfFullNoMb --redirect _Scanf=_ScanfFullNoMb
+#        --map "G:\Semester
+#        7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\List\TrafficLight.map"
+#        --config "C:\Program Files\IAR Systems\Embedded Workbench
+#        9.0\arm\config\linker\TexasInstruments\TM4C123GH6.icf" --semihosting
+#        C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\ewarm\Exe\driverlib.a
+#        --entry __iar_program_start --vfe --text_out locale)
+#
+###############################################################################
+
+*******************************************************************************
+*** MESSAGES
+***
+
+Warning[Lt009]: Inconsistent wchar_t size
+            sysctl.o(driverlib.a) and 3 other objects in driverlib.a have
+                      wchar_t size 16 bits
+            DIO.o and 15 other objects, some of them in dl7M_tln.a and 11 other
+                      libraries have wchar_t size 32 bits
+
+
+*******************************************************************************
+*** RUNTIME MODEL ATTRIBUTES
+***
+
+CppFlavor       = *
+__SystemLibrary = DLib
+__dlib_version  = 6
+
+
+*******************************************************************************
+*** HEAP SELECTION
+***
+
+The basic heap was selected because some modules are built with
+size limitations (and not runtime checking), and --advanced_heap
+was not specified.
+
+
+*******************************************************************************
+*** PLACEMENT SUMMARY
+***
+
+"A0":  place at address 0x0 { ro section .intvec };
+"P1":  place in [from 0x0 to 0x3'ffff] { ro };
+define block CSTACK with size = 4K, alignment = 8 { };
+define block HEAP with size = 8K, alignment = 8 { };
+"P2":  place in [from 0x2000'0000 to 0x2000'7fff] {
+          rw, block CSTACK, block HEAP };
+initialize by copy { rw };
+
+  Section            Kind         Address    Size  Object
+  -------            ----         -------    ----  ------
+"A0":                                        0x40
+  .intvec            ro code          0x0    0x40  vector_table_M.o [5]
+                                   - 0x40    0x40
+
+"P1":                                       0xf60
+  .text              ro code         0x40   0x850  Traffic_light.o [1]
+  .text              ro code        0x890    0xb0  interrupt.o [3]
+  .text              ro code        0x940   0x3fc  gpio.o [3]
+  .text              ro code        0xd3c    0x48  sysctl.o [3]
+  .text              ro code        0xd84     0xc  cpu.o [3]
+  .rodata            const          0xd90    0x60  Traffic_light.o [1]
+  .rodata            const          0xdf0    0x40  Traffic_light.o [1]
+  .text              ro code        0xe30    0x38  zero_init3.o [5]
+  .text              ro code        0xe68    0x2a  main.o [1]
+  .text              ro code        0xe92    0x2a  copy_init3.o [5]
+  .text              ro code        0xebc    0x28  data_init.o [5]
+  .text              ro code        0xee4    0x22  fpinit_M.o [4]
+  .iar.init_table    const          0xf08    0x24  - Linker created -
+  .text              ro code        0xf2c     0x2  vectortrap_M.o [5]
+  .text              ro code        0xf30    0x1e  cmain.o [5]
+  .text              ro code        0xf4e     0x4  low_level_init.o [2]
+  .text              ro code        0xf52     0x4  exit.o [2]
+  .text              ro code        0xf58     0xa  cexit.o [5]
+  .text              ro code        0xf64    0x14  exit.o [6]
+  .text              ro code        0xf78    0x1c  cstartup_M.o [5]
+  .rodata            const          0xf94     0x4  Traffic_light.o [1]
+  .rodata            const          0xf98     0x4  Traffic_light.o [1]
+  Initializer bytes  const          0xf9c     0x4  <for P2-1>
+  .rodata            const          0xfa0     0x0  zero_init3.o [5]
+  .rodata            const          0xfa0     0x0  copy_init3.o [5]
+                                  - 0xfa0   0xf60
+
+"P2", part 1 of 3:                            0x4
+  P2-1                        0x2000'0000     0x4  <Init block>
+    .data            inited   0x2000'0000     0x4  main.o [1]
+                            - 0x2000'0004     0x4
+
+"P2", part 2 of 3:                          0x674
+  VTABLE             zero     0x2000'0400   0x26c  interrupt.o [3]
+  .bss               zero     0x2000'066c     0x4  main.o [1]
+  .bss               zero     0x2000'0670     0x4  main.o [1]
+  .bss               zero     0x2000'0674     0x4  main.o [1]
+                            - 0x2000'0678   0x674
+
+"P2", part 3 of 3:                         0x1000
+  CSTACK                      0x2000'0678  0x1000  <Block>
+    CSTACK           uninit   0x2000'0678  0x1000  <Block tail>
+                            - 0x2000'1678  0x1000
+
+Unused ranges:
+
+         From           To      Size
+         ----           --      ----
+        0xfa0     0x3'ffff  0x3'f060
+  0x2000'1678  0x2000'7fff    0x6988
+
+
+*******************************************************************************
+*** INIT TABLE
+***
+
+          Address      Size
+          -------      ----
+Zero (__iar_zero_init3)
+    1 destination range, total size 0x278:
+          0x2000'0400  0x278
+
+Copy (__iar_copy_init3)
+    1 source range, total size 0x4:
+                0xf9c    0x4
+    1 destination range, total size 0x4:
+          0x2000'0000    0x4
+
+
+
+*******************************************************************************
+*** MODULE SUMMARY
+***
+
+    Module            ro code  ro data  rw data
+    ------            -------  -------  -------
+command line/config:
+    -------------------------------------------
+    Total:
+
+G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj: [1]
+    Traffic_light.o     2'128      168
+    main.o                 42        4       16
+    -------------------------------------------
+    Total:              2'170      172       16
+
+dl7M_tln.a: [2]
+    exit.o                  4
+    low_level_init.o        4
+    -------------------------------------------
+    Total:                  8
+
+driverlib.a: [3]
+    cpu.o                  12
+    gpio.o              1'020
+    interrupt.o           176               620
+    sysctl.o               72
+    -------------------------------------------
+    Total:              1'280               620
+
+m7M_tls.a: [4]
+    fpinit_M.o             34
+    -------------------------------------------
+    Total:                 34
+
+rt7M_tl.a: [5]
+    cexit.o                10
+    cmain.o                30
+    copy_init3.o           42
+    cstartup_M.o           28
+    data_init.o            40
+    vector_table_M.o       64
+    vectortrap_M.o          2
+    zero_init3.o           56
+    -------------------------------------------
+    Total:                272
+
+shb_l.a: [6]
+    exit.o                 20
+    -------------------------------------------
+    Total:                 20
+
+    Gaps                    6        2    1'020
+    Linker created                  36    4'096
+-----------------------------------------------
+    Grand Total:        3'790      210    5'752
+
+
+*******************************************************************************
+*** ENTRY LIST
+***
+
+Entry                       Address   Size  Type      Object
+-----                       -------   ----  ----      ------
+.iar.init_table$$Base         0xf08          --   Gb  - Linker created -
+.iar.init_table$$Limit        0xf2c          --   Gb  - Linker created -
+?main                         0xf31         Code  Gb  cmain.o [5]
+BusFault_Handler              0xf2d         Code  Wk  vectortrap_M.o [5]
+CPUcpsie                      0xd85    0x8  Code  Gb  cpu.o [3]
+CPUwfi                        0xd8d    0x4  Code  Gb  cpu.o [3]
+CSTACK$$Base            0x2000'0678          --   Gb  - Linker created -
+CSTACK$$Limit           0x2000'1678          --   Gb  - Linker created -
+DebugMon_Handler              0xf2d         Code  Wk  vectortrap_M.o [5]
+Delay                         0x78d    0xe  Code  Gb  Traffic_light.o [1]
+GPIODirModeSet                0x981   0x28  Code  Gb  gpio.o [3]
+GPIOIntClear                  0xb23    0x6  Code  Gb  gpio.o [3]
+GPIOIntEnable                 0xb1d    0x6  Code  Gb  gpio.o [3]
+GPIOIntRegister               0xb29   0x14  Code  Gb  gpio.o [3]
+GPIOPadConfigSet              0x9a9  0x174  Code  Gb  gpio.o [3]
+GPIOPinRead                   0xb45    0x6  Code  Gb  gpio.o [3]
+GPIOPinTypeGPIOInput          0xb55   0x14  Code  Gb  gpio.o [3]
+GPIOPinTypeGPIOOutput         0xb69    0xa  Code  Gb  gpio.o [3]
+GPIOPinWrite                  0xb4b    0x6  Code  Gb  gpio.o [3]
+HardFault_Handler             0xf2d         Code  Wk  vectortrap_M.o [5]
+IntEnable                     0x8c7   0x56  Code  Gb  interrupt.o [3]
+IntMasterEnable               0x891    0x8  Code  Gb  interrupt.o [3]
+IntRegister                   0x8a1   0x26  Code  Gb  interrupt.o [3]
+MemManage_Handler             0xf2d         Code  Wk  vectortrap_M.o [5]
+NMI_Handler                   0xf2d         Code  Wk  vectortrap_M.o [5]
+PORTA_init                    0x523   0x4a  Code  Gb  Traffic_light.o [1]
+PORTC_init                    0x56d   0x3a  Code  Gb  Traffic_light.o [1]
+PORTD_init                    0x5a7   0x5e  Code  Gb  Traffic_light.o [1]
+PORTE_init                    0x605   0x3a  Code  Gb  Traffic_light.o [1]
+PORTF_init                    0x63f   0x5e  Code  Gb  Traffic_light.o [1]
+PendSV_Handler                0xf2d         Code  Wk  vectortrap_M.o [5]
+Region$$Table$$Base           0xf08          --   Gb  - Linker created -
+Region$$Table$$Limit          0xf2c          --   Gb  - Linker created -
+SVC_Handler                   0xf2d         Code  Wk  vectortrap_M.o [5]
+SysCtlPeripheralEnable        0xd5d    0x8  Code  Gb  sysctl.o [3]
+SysCtlPeripheralReady         0xd3d    0x8  Code  Gb  sysctl.o [3]
+SysCtlSleep                   0xd79    0x4  Code  Gb  sysctl.o [3]
+SysTick_Handler               0xf2d         Code  Wk  vectortrap_M.o [5]
+Ticks_to_time                 0x785    0x8  Code  Gb  Traffic_light.o [1]
+Timer0_dsiable                0x735    0xe  Code  Gb  Traffic_light.o [1]
+Timer0_handler                0x185  0x162  Code  Gb  Traffic_light.o [1]
+Timer0_init                   0x43b   0x74  Code  Gb  Traffic_light.o [1]
+Timer1_disable                0x743    0xe  Code  Gb  Traffic_light.o [1]
+Timer1_handler                0x2e7  0x154  Code  Gb  Traffic_light.o [1]
+Timer1_init                   0x4af   0x74  Code  Gb  Traffic_light.o [1]
+TimerConfigure                 0xbd   0x74  Code  Gb  Traffic_light.o [1]
+TimerDisable                   0xa7   0x16  Code  Gb  Traffic_light.o [1]
+TimerEnable                    0x93   0x14  Code  Gb  Traffic_light.o [1]
+TimerIntClear                 0x17f    0x6  Code  Gb  Traffic_light.o [1]
+TimerIntEnable                0x171    0xe  Code  Gb  Traffic_light.o [1]
+TimerIntRegister              0x157   0x1a  Code  Gb  Traffic_light.o [1]
+TimerLoadSet                  0x131   0x16  Code  Gb  Traffic_light.o [1]
+TimerValueGet                 0x147   0x10  Code  Gb  Traffic_light.o [1]
+Traffic_light_init            0x751   0x34  Code  Gb  Traffic_light.o [1]
+UsageFault_Handler            0xf2d         Code  Wk  vectortrap_M.o [5]
+_GPIOIntNumberGet             0x941   0x40  Code  Lc  gpio.o [3]
+_TimerIntNumberGet             0x41   0x52  Code  Lc  Traffic_light.o [1]
+__cmain                       0xf31         Code  Gb  cmain.o [5]
+__exit                        0xf65   0x14  Code  Gb  exit.o [6]
+__iar_copy_init3              0xe93   0x2a  Code  Gb  copy_init3.o [5]
+__iar_data_init3              0xebd   0x28  Code  Gb  data_init.o [5]
+__iar_init_vfp                0xee5         Code  Gb  fpinit_M.o [4]
+__iar_program_start           0xf79         Code  Gb  cstartup_M.o [5]
+__iar_zero_init3              0xe31   0x38  Code  Gb  zero_init3.o [5]
+__low_level_init              0xf4f    0x4  Code  Gb  low_level_init.o [2]
+__vector_table                  0x0         Data  Gb  vector_table_M.o [5]
+_call_main                    0xf3d         Code  Gb  cmain.o [5]
+_exit                         0xf59         Code  Gb  cexit.o [5]
+elapsed_time_1          0x2000'0670    0x4  Data  Gb  main.o [1]
+elapsed_time_2          0x2000'0674    0x4  Data  Gb  main.o [1]
+exit                          0xf53    0x4  Code  Gb  exit.o [2]
+g_pfnRAMVectors         0x2000'0400  0x26c  Data  Lc  interrupt.o [3]
+g_ppui32GPIOIntMapBlizzard
+                              0xba4   0xc0  Data  Lc  gpio.o [3]
+g_ppui32GPIOIntMapSnowflake
+                              0xc64   0xd8  Data  Lc  gpio.o [3]
+g_ppui32TimerIntMap           0xd90   0x60  Data  Lc  Traffic_light.o [1]
+g_ppui32TimerIntMapSnowflake
+                              0xdf0   0x40  Data  Lc  Traffic_light.o [1]
+g_pui32EnRegs                 0x92c   0x14  Data  Lc  interrupt.o [3]
+g_ui8TimerIntMapRows          0xf94    0x4  Data  Lc  Traffic_light.o [1]
+g_ui8TimerIntMapRowsSnowflake
+                              0xf98    0x4  Data  Lc  Traffic_light.o [1]
+main                          0xe69   0x2a  Code  Gb  main.o [1]
+next_state              0x2000'066c    0x4  Data  Gb  main.o [1]
+next_state_2            0x2000'0000    0x4  Data  Gb  main.o [1]
+priority_config               0x733    0x2  Code  Gb  Traffic_light.o [1]
+reset_traffic_1               0x79b   0x2c  Code  Gb  Traffic_light.o [1]
+reset_traffic_2               0x7c7   0x26  Code  Gb  Traffic_light.o [1]
+switch1_handler               0x6ff   0x1a  Code  Gb  Traffic_light.o [1]
+switch2_handler               0x719   0x1a  Code  Gb  Traffic_light.o [1]
+switch_handler                0x69d   0x62  Code  Gb  Traffic_light.o [1]
+
+
+[1] = G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Obj
+[2] = dl7M_tln.a
+[3] = driverlib.a
+[4] = m7M_tls.a
+[5] = rt7M_tl.a
+[6] = shb_l.a
+
+  3'790 bytes of readonly  code memory
+    210 bytes of readonly  data memory
+  5'752 bytes of readwrite data memory
+
+Errors: none
+Warnings: 1
diff --git a/Debug/Obj/DIO.o b/Debug/Obj/DIO.o
new file mode 100644
index 0000000..4df009c
Binary files /dev/null and b/Debug/Obj/DIO.o differ
diff --git a/Debug/Obj/Traffic_light.o b/Debug/Obj/Traffic_light.o
new file mode 100644
index 0000000..8a6a469
Binary files /dev/null and b/Debug/Obj/Traffic_light.o differ
diff --git a/Debug/Obj/main.o b/Debug/Obj/main.o
new file mode 100644
index 0000000..2e33aff
Binary files /dev/null and b/Debug/Obj/main.o differ
diff --git a/TrafficLight.dep b/TrafficLight.dep
new file mode 100644
index 0000000..85493c2
--- /dev/null
+++ b/TrafficLight.dep
@@ -0,0 +1,137 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>5</fileVersion>
+    <fileChecksum>3509568517</fileChecksum>
+    <configuration>
+        <name>Debug</name>
+        <outputs>
+            <file>$TOOLKIT_DIR$\lib\rt7M_tl.a</file>
+            <file>$PROJ_DIR$\Debug\Obj\main.o</file>
+            <file>$PROJ_DIR$\Traffic_light.h</file>
+            <file>$PROJ_DIR$\tm4c123gh6pm.h</file>
+            <file>$PROJ_DIR$\Traffic_light.C</file>
+            <file>$PROJ_DIR$\types.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\debug.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\ewarm\Exe\driverlib.a</file>
+            <file>$TOOLKIT_DIR$\lib\shb_l.a</file>
+            <file>$TOOLKIT_DIR$\inc\c\ysizet.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_timer.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\sysctl.h</file>
+            <file>$PROJ_DIR$\Debug\Obj\DIO.o</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_memmap.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\timer.h</file>
+            <file>$PROJ_DIR$\DIO.h</file>
+            <file>$PROJ_DIR$\main.c</file>
+            <file>$PROJ_DIR$\DIO.C</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Product.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\yvals.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\timer.c</file>
+            <file>$TOOLKIT_DIR$\config\linker\TexasInstruments\TM4C123GH6.icf</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\gpio.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdbool.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\DLib_Defaults.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_sysctl.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\ycheck.h</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdint.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_types.h</file>
+            <file>$TOOLKIT_DIR$\lib\m7M_tls.a</file>
+            <file>$PROJ_DIR$\Debug\List\TrafficLight.map</file>
+            <file>$PROJ_DIR$\Debug\Obj\Traffic_light.o</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_ints.h</file>
+            <file>$PROJ_DIR$\Debug\Exe\TrafficLight.out</file>
+            <file>$TOOLKIT_DIR$\inc\c\stdio.h</file>
+            <file>$TOOLKIT_DIR$\lib\dl7M_tln.a</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\driverlib\interrupt.h</file>
+            <file>C:\ti\TivaWare_C_Series-2.2.0.295\inc\hw_gpio.h</file>
+        </outputs>
+        <file>
+            <name>$PROJ_DIR$\Traffic_light.C</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 32</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 7 25 19 24 28 35 27 10 20 6 23 37 12 21 15 38 33 14 26 11 29 2 3 5</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\main.c</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 1</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 2 5</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\DIO.C</name>
+            <outputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 13</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ICCARM</name>
+                    <file> 7 25 19 28 27 20 16 3 5</file>
+                </tool>
+            </inputs>
+        </file>
+        <file>
+            <name>[ROOT_NODE]</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 31 34</file>
+                </tool>
+            </outputs>
+        </file>
+        <file>
+            <name>$PROJ_DIR$\Debug\Exe\TrafficLight.out</name>
+            <outputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 31</file>
+                </tool>
+            </outputs>
+            <inputs>
+                <tool>
+                    <name>ILINK</name>
+                    <file> 22 36 30 0 9 8 13 32 1</file>
+                </tool>
+            </inputs>
+        </file>
+        <forcedrebuild>
+            <name>$PROJ_DIR$\main.c</name>
+            <tool>ICCARM</tool>
+        </forcedrebuild>
+        <forcedrebuild>
+            <name>[MULTI_TOOL]</name>
+            <tool>ILINK</tool>
+        </forcedrebuild>
+        <forcedrebuild>
+            <name>[REBUILD_ALL]</name>
+        </forcedrebuild>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <outputs />
+        <forcedrebuild>
+            <name>[MULTI_TOOL]</name>
+            <tool>ILINK</tool>
+        </forcedrebuild>
+    </configuration>
+</project>
diff --git a/TrafficLight.ewd b/TrafficLight.ewd
new file mode 100644
index 0000000..d325094
--- /dev/null
+++ b/TrafficLight.ewd
@@ -0,0 +1,3056 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>32</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state>$TOOLKIT_DIR$\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf</state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>9.10.2.39304</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>LMIFTDI_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state>9.10.2.39304</state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state>$TOOLKIT_DIR$\config\flashloader\TexasInstruments\FlashTC4_H6_o.board</state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
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+                    <state>0</state>
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+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
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+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
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+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
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+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
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+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
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+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
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+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>7</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+    <configuration>
+        <name>Release</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>0</debug>
+        <settings>
+            <name>C-SPY</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>32</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCVariant</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>MemOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MemFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>RunToEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RunToName</name>
+                    <state>main</state>
+                </option>
+                <option>
+                    <name>CExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDDFArgumentProducer</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadSuppressDownload</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDownloadVerifyAll</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProductVersion</name>
+                    <state>9.10.2.39304</state>
+                </option>
+                <option>
+                    <name>OCDynDriverList</name>
+                    <state>ARMSIM_ID</state>
+                </option>
+                <option>
+                    <name>OCLastSavedByProductVersion</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>UseFlashLoader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CLowLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CDevice</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>FlashLoadersV3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesSuppressCheck3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesPath3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OverrideDefFlashBoard</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesOffset1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesOffset3</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCImagesUse1</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCImagesUse3</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDeviceConfigMacroFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCDebuggerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAllMTBOptions</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCores</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreWorkspace</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveProject</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCMulticoreSlaveConfiguration</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCDownloadExtraImage</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCAttachSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MassEraseBeforeFlashing</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreNrOfCoresSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCMulticoreAMPConfigType</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCMulticoreSessionFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCTpiuBaseOption</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ARMSIM_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCSimDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCSimEnablePSP</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspOverrideConfig</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCSimPspConfigFile</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CADI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CCadiMemory</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Fast Model</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCADILogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCADILogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CMSISDAP_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>4</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>CMSISDAPHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>CMSISDAPDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CMSISDAPInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CMSISDAPProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CMSISDAPSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCMSISDAPUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>GDBSERVER_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJTagBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJTagUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IJET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>9</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OCIarProbeScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetResetList</name>
+                    <version>1</version>
+                    <state>10</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDuration</name>
+                    <state>300</state>
+                </option>
+                <option>
+                    <name>IjetHWResetDelay</name>
+                    <state>200</state>
+                </option>
+                <option>
+                    <name>IjetPowerFromProbe</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPowerRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTargetEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetJtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetProtocolRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSwoPin</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetSwoPrescalerList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetRestoreBreakpointsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetUpdateBreakpointsEdit</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>RDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchUndef</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchData</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchPrefetch</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchMMERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchNOCPERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchCHKERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSTATERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchBUSERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchINTERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchSFERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchHARDERR</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeCfgOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCProbeConfig</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IjetProbeConfigRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetMultiCPUNumber</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetSelectedCPUBehaviour</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ICpuName</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>OCJetEmuParams</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetPreferETB</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IjetTraceSettingsList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IjetTraceSizeList</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>FlashBoardPathSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIjetUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREREL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL1S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL2NS</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8AREEL3S</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CatchV8ARREL3S</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>JLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>16</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>JLinkSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCJLinkHWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>JLinkInitialSpeed</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCDoJlinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCScanChainNonARMDevices</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkMultiTarget</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkIRLength</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkCommRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTCPIP</name>
+                    <state>aaa.bbb.ccc.ddd</state>
+                </option>
+                <option>
+                    <name>CCJLinkSpeedRadioV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCUSBDevice</name>
+                    <version>1</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRDICatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCRDICatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkBreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkResetList</name>
+                    <version>6</version>
+                    <state>5</state>
+                </option>
+                <option>
+                    <name>CCJLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkScriptFile</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCTcpIpAlt</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCJLinkTcpIpSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkTraceSourceDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCJLinkDeviceName</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>LMIFTDI_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>LmiftdiSpeed</name>
+                    <state>500</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCLmiFtdiInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLmiftdiUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCLmiftdiResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>NULINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>PEMICRO_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>3</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCJPEMicroShowSettings</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>STLINK_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>7</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceRadio</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSTLinkInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkResetList</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSwoClockAuto</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCSwoClockEdit</name>
+                    <state>2000</state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkCatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkUsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkJtagSpeedList</name>
+                    <version>2</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkDAPNumber</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCSTLinkDebugAccessPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkUseServerSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSTLinkProbeList</name>
+                    <version>1</version>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>THIRDPARTY_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>CThirdPartyDriverDll</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CThirdPartyLogFileEditB</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>TIFET_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetInterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVccTypeDefault</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>CCMSPFetVCCDefault</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetTargetSettlingtime</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioJtagSpeedType</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCMSPFetConnection</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetUsbComPort</name>
+                    <state>Automatic</state>
+                </option>
+                <option>
+                    <name>CCMSPFetAllowAccessToBSL</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetDoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCMSPFetLogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCMSPFetRadioEraseFlash</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>XDS100_ID</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>8</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>OCDriverInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TIPackageOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TIPackage</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>BoardFile</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DoLogfile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>LogFile</name>
+                    <state>$PROJ_DIR$\cspycomm.log</state>
+                </option>
+                <option>
+                    <name>CCXds100BreakpointRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100DoUpdateBreakpoints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UpdateBreakpoints</name>
+                    <state>_call_main</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchReset</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchUndef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSWI</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchData</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchPrefetch</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchIRQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchFIQ</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCORERESET</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchMMERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchNOCPERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchCHRERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSTATERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchBUSERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchINTERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchSFERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchHARDERR</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CatchDummy</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100CpuClockEdit</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockAuto</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SwoClockEdit</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>CCXds100HWResetDelay</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ResetList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNo</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCXds100UsbSerialNoSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100JtagSpeedList</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceRadio</name>
+                    <state>2</state>
+                </option>
+                <option>
+                    <name>CCXds100InterfaceCmdLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100ProbeList</name>
+                    <version>0</version>
+                    <state>3</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPortRadio</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXds100SWOPort</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVccEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCXDSTargetVoltage</name>
+                    <state>###Uninitialized###</state>
+                </option>
+                <option>
+                    <name>OCXDSDigitalStatesConfigFile</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+        <debuggerPlugins>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\CMX\CmxTinyArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm9BE.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\Orti\Orti.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\TargetAccessServer\TargetAccessServer.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+            <plugin>
+                <file>$EW_DIR$\common\plugins\uCProbe\uCProbePlugin.ENU.ewplugin</file>
+                <loadFlag>0</loadFlag>
+            </plugin>
+        </debuggerPlugins>
+    </configuration>
+</project>
diff --git a/TrafficLight.ewp b/TrafficLight.ewp
new file mode 100644
index 0000000..24ad687
--- /dev/null
+++ b/TrafficLight.ewp
@@ -0,0 +1,2111 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>General</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <version>33</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>BrowseInfoPath</name>
+                    <state>Debug\BrowseInfo</state>
+                </option>
+                <option>
+                    <name>ExePath</name>
+                    <state>Debug\Exe</state>
+                </option>
+                <option>
+                    <name>ObjPath</name>
+                    <state>Debug\Obj</state>
+                </option>
+                <option>
+                    <name>ListPath</name>
+                    <state>Debug\List</state>
+                </option>
+                <option>
+                    <name>GEndianMode</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>Input description</name>
+                    <state>Full formatting, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>Output description</name>
+                    <state>Full formatting, without multibyte support.</state>
+                </option>
+                <option>
+                    <name>GOutputBinary</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGCoreOrChip</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelect</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibSelectSlave</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>RTDescription</name>
+                    <state>Use the normal configuration of the C/C++ runtime library. No locale interface, C locale, no file descriptor support, no multibytes in printf and scanf, and no hex floats in strtod.</state>
+                </option>
+                <option>
+                    <name>OGProductVersion</name>
+                    <state>5.10.0.159</state>
+                </option>
+                <option>
+                    <name>OGLastSavedByProductVersion</name>
+                    <state>9.10.2.39304</state>
+                </option>
+                <option>
+                    <name>OGChipSelectEditMenu</name>
+                    <state>TM4C123GH6PM	TexasInstruments TM4C123GH6PM</state>
+                </option>
+                <option>
+                    <name>GenLowLevelInterface</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GEndianModeBE</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGBufferedTerminalOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenStdoutInterface</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>RTConfigPath2</name>
+                    <state>$TOOLKIT_DIR$\inc\c\DLib_Config_Normal.h</state>
+                </option>
+                <option>
+                    <name>GBECoreSlave</name>
+                    <version>30</version>
+                    <state>38</state>
+                </option>
+                <option>
+                    <name>OGUseCmsis</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGUseCmsisDspLib</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GRuntimeLibThreads</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CoreVariant</name>
+                    <version>30</version>
+                    <state>39</state>
+                </option>
+                <option>
+                    <name>GFPUDeviceSlave</name>
+                    <state>TM4C123GH6PM	TexasInstruments TM4C123GH6PM</state>
+                </option>
+                <option>
+                    <name>FPU2</name>
+                    <version>0</version>
+                    <state>4</state>
+                </option>
+                <option>
+                    <name>NrRegs</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>NEON</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GFPUCoreSlave2</name>
+                    <version>30</version>
+                    <state>39</state>
+                </option>
+                <option>
+                    <name>OGCMSISPackSelectDevice</name>
+                </option>
+                <option>
+                    <name>OgLibHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGLibAdditionalLocale</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGPrintfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGPrintfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGScanfVariant</name>
+                    <version>0</version>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OGScanfMultibyteSupport</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenLocaleTags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>GenLocaleDisplayOnly</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>DSPExtension</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>TrustZone</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>TrustZoneModes</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OGAarch64Abi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OG_32_64Device</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>ICCARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>37</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>CCOptimizationNoSizeConstraints</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDefines</name>
+                    <state>ewarm </state>
+                    <state>PART_TM4C123GH6PM</state>
+                    <state>TARGET_IS_TM4C123_RB1</state>
+                </option>
+                <option>
+                    <name>CCPreprocFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocComments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPreprocLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMnemonics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListCMessages</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssFile</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCListAssSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagSuppress</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagRemark</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagWarning</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCDiagError</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCAllowList</name>
+                    <version>1</version>
+                    <state>00000000</state>
+                </option>
+                <option>
+                    <name>CCDebugInfo</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IEndianMode</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IExtraOptionsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCLangConformance</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCSignedPlainChar</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCRequirePrototypes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCDiagWarnAreErr</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCompilerRuntimeInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>CCLibConfigHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>CCIncludePath2</name>
+                    <state>C:\ti\TivaWare_C_Series-2.2.0.295</state>
+                </option>
+                <option>
+                    <name>CCStdIncCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCCodeSection</name>
+                    <state>.text</state>
+                </option>
+                <option>
+                    <name>IProcessorMode2</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptLevel</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCOptStrategy</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptLevelSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCPosIndRopi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndRwpi</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCPosIndNoDynInit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccLang</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCDialect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccAllowVLA</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccStaticDestr</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccCppInlineSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IccFloatSemantics</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCOptStrategySlave</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCGuardCalls</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncSource</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>CCEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccExceptions2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IccRTTI2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OICompilerExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CCStackProtection</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>AARM</name>
+            <archiveVersion>2</archiveVersion>
+            <data>
+                <version>11</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>AObjPrefix</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AEndian</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>ACaseSensitivity</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacroChars</name>
+                    <version>0</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnWhat</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AWarnOne</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange1</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AWarnRange2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>ADebug</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AltRegisterNames</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ADefines</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AList</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AListHeader</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AListing</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>Includes</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacDefs</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MacExps</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>MacExec</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OnlyAssed</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>MultiLine</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLengthCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PageLength</name>
+                    <state>80</state>
+                </option>
+                <option>
+                    <name>TabSpacing</name>
+                    <state>8</state>
+                </option>
+                <option>
+                    <name>AXRef</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDefines</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefInternal</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AXRefDual</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AFpuProcessor</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>AOutputFile</name>
+                    <state>$FILE_BNAME$.o</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsCheck</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>ALimitErrorsEdit</name>
+                    <state>100</state>
+                </option>
+                <option>
+                    <name>AIgnoreStdInclude</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AUserIncludes</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AExtraOptionsCheckV2</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>AExtraOptionsV2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>AsmNoLiteralPool</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>PreInclude</name>
+                    <state></state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>OBJCOPY</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>1</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>OOCOutputFormat</name>
+                    <version>3</version>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OCOutputOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>OOCOutputFile</name>
+                    <state>TrafficLight.srec</state>
+                </option>
+                <option>
+                    <name>OOCCommandLineProducer</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>OOCObjCopyEnable</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>1</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>25</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>1</debug>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>$PROJ_FNAME$.out</state>
+                </option>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
+                </option>
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+                    <state>0</state>
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+                    <state></state>
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+                </option>
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+            <archiveVersion>0</archiveVersion>
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+                <wantNonLocal>1</wantNonLocal>
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+                    <version>3</version>
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+                    <state>1</state>
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+                    <name>OOCObjCopyEnable</name>
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+                </option>
+            </data>
+        </settings>
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+            <name>CUSTOM</name>
+            <archiveVersion>3</archiveVersion>
+            <data>
+                <extensions></extensions>
+                <cmdline></cmdline>
+                <hasPrio>0</hasPrio>
+                <buildSequence>inputOutputBased</buildSequence>
+            </data>
+        </settings>
+        <settings>
+            <name>BUILDACTION</name>
+            <archiveVersion>1</archiveVersion>
+            <data>
+                <prebuild></prebuild>
+                <postbuild></postbuild>
+            </data>
+        </settings>
+        <settings>
+            <name>ILINK</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>25</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IlinkOutputFile</name>
+                    <state>$PROJ_FNAME$.out</state>
+                </option>
+                <option>
+                    <name>IlinkLibIOConfig</name>
+                    <state>1</state>
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+                <option>
+                    <name>IlinkInputFileSlave</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDebugInfoEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkKeepSymbols</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinaryFile</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinarySymbol</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySegment</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinaryAlign</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkDefines</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkConfigDefines</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkMapFile</name>
+                    <state>1</state>
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+                <option>
+                    <name>IlinkLogFile</name>
+                    <state>0</state>
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+                    <name>IlinkLogInitialization</name>
+                    <state>0</state>
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+                    <name>IlinkLogModule</name>
+                    <state>0</state>
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+                    <name>IlinkLogSection</name>
+                    <state>0</state>
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+                    <name>IlinkLogVeneer</name>
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+                    <name>IlinkIcfOverride</name>
+                    <state>0</state>
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+                <option>
+                    <name>IlinkIcfFile</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkIcfFileSlave</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkEnableRemarks</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkSuppressDiags</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkTreatAsRem</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkTreatAsWarn</name>
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+                <option>
+                    <name>IlinkTreatAsErr</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkWarningsAreErrors</name>
+                    <state>0</state>
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+                <option>
+                    <name>IlinkUseExtraOptions</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkExtraOptions</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLowLevelInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAutoLibEnable</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkAdditionalLibs</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkOverrideProgramEntryLabel</name>
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+                <option>
+                    <name>IlinkProgramEntryLabelSelect</name>
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+                <option>
+                    <name>IlinkProgramEntryLabel</name>
+                    <state></state>
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+                    <name>DoFill</name>
+                    <state>0</state>
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+                <option>
+                    <name>FillerByte</name>
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+                    <name>CrcBitOrder</name>
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+                </option>
+                <option>
+                    <name>CrcInitialValue</name>
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+                    <name>DoCrc</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkBE8Slave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkBufferedTerminalOutput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkStdoutInterfaceSlave</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>CrcFullSize</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkIElfToolPostProcess</name>
+                    <state>0</state>
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+                <option>
+                    <name>IlinkLogAutoLibSelect</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogRedirSymbols</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogUnusedFragments</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcReverseByteOrder</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCrcUseAsInput</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptInline</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsAllow</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptExceptionsForce</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkCmsis</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkOptMergeDuplSections</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkOptUseVfe</name>
+                    <state>1</state>
+                </option>
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+                    <name>IlinkOptForceVfe</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkStackAnalysisEnable</name>
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+                    <name>IlinkStackControlFile</name>
+                    <state></state>
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+                    <name>IlinkStackCallGraphFile</name>
+                    <state></state>
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+                <option>
+                    <name>CrcAlgorithm</name>
+                    <version>1</version>
+                    <state>1</state>
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+                <option>
+                    <name>CrcUnitSize</name>
+                    <version>0</version>
+                    <state>0</state>
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+                <option>
+                    <name>IlinkThreadsSlave</name>
+                    <state>1</state>
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+                <option>
+                    <name>IlinkLogCallGraph</name>
+                    <state>0</state>
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+                    <name>IlinkIcfFile_AltDefault</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkEncInput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutput</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkEncOutputBom</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkHeapSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkLocaleSelect</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkTrustzoneImportLibraryOut</name>
+                    <state>###Unitialized###</state>
+                </option>
+                <option>
+                    <name>OILinkExtraOption</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>IlinkRawBinaryFile2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkRawBinarySymbol2</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinarySegment2</name>
+                    <state></state>
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+                <option>
+                    <name>IlinkRawBinaryAlign2</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IlinkLogCrtRoutineSelection</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogFragmentInfo</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogInlining</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkLogMerging</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IlinkDemangle</name>
+                    <state>0</state>
+                </option>
+            </data>
+        </settings>
+        <settings>
+            <name>IARCHIVE</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>0</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>IarchiveInputs</name>
+                    <state></state>
+                </option>
+                <option>
+                    <name>IarchiveOverride</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>IarchiveOutput</name>
+                    <state>###Unitialized###</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+    <file>
+        <name>$PROJ_DIR$\DIO.C</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\DIO.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\main.c</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\tm4c123gh6pm.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\Traffic_light.C</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\Traffic_light.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\types.h</name>
+    </file>
+</project>
diff --git a/TrafficLight.ewt b/TrafficLight.ewt
new file mode 100644
index 0000000..012ee5a
--- /dev/null
+++ b/TrafficLight.ewt
@@ -0,0 +1,2863 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<project>
+    <fileVersion>3</fileVersion>
+    <configuration>
+        <name>Debug</name>
+        <toolchain>
+            <name>ARM</name>
+        </toolchain>
+        <debug>1</debug>
+        <settings>
+            <name>C-STAT</name>
+            <archiveVersion>515</archiveVersion>
+            <data>
+                <version>515</version>
+                <cstatargs>
+                    <useExtraArgs>0</useExtraArgs>
+                    <extraArgs></extraArgs>
+                    <analyzeTimeoutEnabled>1</analyzeTimeoutEnabled>
+                    <analyzeTimeout>600</analyzeTimeout>
+                    <enableParallel>1</enableParallel>
+                    <parallelThreads>2</parallelThreads>
+                    <enableFalsePositives>0</enableFalsePositives>
+                    <messagesLimitEnabled>1</messagesLimitEnabled>
+                    <messagesLimit>100</messagesLimit>
+                    <outputDir>Debug\C-STAT</outputDir>
+                </cstatargs>
+                <cstat_settings>
+                    <cstat_version>2.3.1</cstat_version>
+                    <checks_tree>
+                        <package name="STDCHECKS" enabled="true">
+                            <group enabled="true" name="ARR">
+                                <check name="ARR-inv-index-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr-pos" enabled="true" />
+                                <check name="ARR-inv-index-ptr" enabled="true" />
+                                <check name="ARR-inv-index" enabled="true" />
+                                <check name="ARR-neg-index" enabled="true" />
+                                <check name="ARR-uninit-index" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ATH">
+                                <check name="ATH-cmp-float" enabled="true" />
+                                <check name="ATH-cmp-unsign-neg" enabled="true" />
+                                <check name="ATH-cmp-unsign-pos" enabled="true" />
+                                <check name="ATH-div-0-assign" enabled="true" />
+                                <check name="ATH-div-0-cmp-aft" enabled="false" />
+                                <check name="ATH-div-0-cmp-bef" enabled="true" />
+                                <check name="ATH-div-0-interval" enabled="true" />
+                                <check name="ATH-div-0-pos" enabled="true" />
+                                <check name="ATH-div-0-unchk-global" enabled="true" />
+                                <check name="ATH-div-0-unchk-local" enabled="true" />
+                                <check name="ATH-div-0-unchk-param" enabled="true" />
+                                <check name="ATH-div-0" enabled="true" />
+                                <check name="ATH-inc-bool" enabled="true" />
+                                <check name="ATH-malloc-overrun" enabled="true" />
+                                <check name="ATH-neg-check-nonneg" enabled="true" />
+                                <check name="ATH-neg-check-pos" enabled="true" />
+                                <check name="ATH-new-overrun" enabled="true" />
+                                <check name="ATH-overflow-cast" enabled="false" />
+                                <check name="ATH-overflow" enabled="true" />
+                                <check name="ATH-shift-bounds" enabled="true" />
+                                <check name="ATH-shift-neg" enabled="true" />
+                                <check name="ATH-sizeof-by-sizeof" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CAST">
+                                <check name="CAST-old-style" enabled="false" />
+                            </group>
+                            <group enabled="true" name="CATCH">
+                                <check name="CATCH-object-slicing" enabled="true" />
+                                <check name="CATCH-xtor-bad-member" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMA">
+                                <check name="COMMA-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="COMMENT">
+                                <check name="COMMENT-nested" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CONST">
+                                <check name="CONST-member-ret" enabled="true" />
+                            </group>
+                            <group enabled="true" name="COP">
+                                <check name="COP-alloc-ctor" enabled="false" />
+                                <check name="COP-assign-op-ret" enabled="true" />
+                                <check name="COP-assign-op-self" enabled="true" />
+                                <check name="COP-assign-op" enabled="true" />
+                                <check name="COP-copy-ctor" enabled="true" />
+                                <check name="COP-dealloc-dtor" enabled="false" />
+                                <check name="COP-dtor-throw" enabled="true" />
+                                <check name="COP-dtor" enabled="true" />
+                                <check name="COP-init-order" enabled="false" />
+                                <check name="COP-init-uninit" enabled="true" />
+                                <check name="COP-member-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CPU">
+                                <check name="CPU-ctor-call-virt" enabled="true" />
+                                <check name="CPU-ctor-implicit" enabled="false" />
+                                <check name="CPU-delete-throw" enabled="true" />
+                                <check name="CPU-delete-void" enabled="true" />
+                                <check name="CPU-dtor-call-virt" enabled="true" />
+                                <check name="CPU-malloc-class" enabled="true" />
+                                <check name="CPU-nonvirt-dtor" enabled="true" />
+                                <check name="CPU-return-ref-to-class-data" enabled="true" />
+                            </group>
+                            <group enabled="true" name="DECL">
+                                <check name="DECL-implicit-int" enabled="false" />
+                            </group>
+                            <group enabled="true" name="DEFINE">
+                                <check name="DEFINE-hash-multiple" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ENUM">
+                                <check name="ENUM-bounds" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXP">
+                                <check name="EXP-cond-assign" enabled="true" />
+                                <check name="EXP-dangling-else" enabled="true" />
+                                <check name="EXP-loop-exit" enabled="true" />
+                                <check name="EXP-main-ret-int" enabled="false" />
+                                <check name="EXP-null-stmt" enabled="false" />
+                                <check name="EXP-stray-semicolon" enabled="false" />
+                            </group>
+                            <group enabled="true" name="EXPR">
+                                <check name="EXPR-const-overflow" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FPT">
+                                <check name="FPT-cmp-null" enabled="true" />
+                                <check name="FPT-literal" enabled="false" />
+                                <check name="FPT-misuse" enabled="true" />
+                            </group>
+                            <group enabled="true" name="FUNC">
+                                <check name="FUNC-implicit-decl" enabled="false" />
+                                <check name="FUNC-unprototyped-all" enabled="false" />
+                                <check name="FUNC-unprototyped-used" enabled="true" />
+                            </group>
+                            <group enabled="true" name="INCLUDE">
+                                <check name="INCLUDE-c-file" enabled="false" />
+                            </group>
+                            <group enabled="true" name="INT">
+                                <check name="INT-use-signed-as-unsigned-pos" enabled="false" />
+                                <check name="INT-use-signed-as-unsigned" enabled="true" />
+                            </group>
+                            <group enabled="true" name="ITR">
+                                <check name="ITR-end-cmp-aft" enabled="true" />
+                                <check name="ITR-end-cmp-bef" enabled="true" />
+                                <check name="ITR-invalidated" enabled="true" />
+                                <check name="ITR-mismatch-alg" enabled="false" />
+                                <check name="ITR-store" enabled="false" />
+                                <check name="ITR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LIB">
+                                <check name="LIB-bsearch-overrun-pos" enabled="false" />
+                                <check name="LIB-bsearch-overrun" enabled="false" />
+                                <check name="LIB-fn-unsafe" enabled="false" />
+                                <check name="LIB-fread-overrun-pos" enabled="false" />
+                                <check name="LIB-fread-overrun" enabled="true" />
+                                <check name="LIB-memchr-overrun-pos" enabled="false" />
+                                <check name="LIB-memchr-overrun" enabled="true" />
+                                <check name="LIB-memcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-memcpy-overrun" enabled="true" />
+                                <check name="LIB-memset-overrun-pos" enabled="false" />
+                                <check name="LIB-memset-overrun" enabled="true" />
+                                <check name="LIB-putenv" enabled="false" />
+                                <check name="LIB-qsort-overrun-pos" enabled="false" />
+                                <check name="LIB-qsort-overrun" enabled="false" />
+                                <check name="LIB-return-const" enabled="true" />
+                                <check name="LIB-return-error" enabled="true" />
+                                <check name="LIB-return-leak" enabled="true" />
+                                <check name="LIB-return-neg" enabled="true" />
+                                <check name="LIB-return-null" enabled="true" />
+                                <check name="LIB-sprintf-overrun" enabled="false" />
+                                <check name="LIB-std-sort-overrun-pos" enabled="false" />
+                                <check name="LIB-std-sort-overrun" enabled="true" />
+                                <check name="LIB-strcat-overrun-pos" enabled="false" />
+                                <check name="LIB-strcat-overrun" enabled="true" />
+                                <check name="LIB-strcpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strcpy-overrun" enabled="true" />
+                                <check name="LIB-strncat-overrun-pos" enabled="false" />
+                                <check name="LIB-strncat-overrun" enabled="true" />
+                                <check name="LIB-strncmp-overrun-pos" enabled="false" />
+                                <check name="LIB-strncmp-overrun" enabled="true" />
+                                <check name="LIB-strncpy-overrun-pos" enabled="false" />
+                                <check name="LIB-strncpy-overrun" enabled="true" />
+                            </group>
+                            <group enabled="true" name="LOGIC">
+                                <check name="LOGIC-overload" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MEM">
+                                <check name="MEM-delete-array-op" enabled="true" />
+                                <check name="MEM-delete-op" enabled="true" />
+                                <check name="MEM-double-free-alias" enabled="true" />
+                                <check name="MEM-double-free-some" enabled="true" />
+                                <check name="MEM-double-free" enabled="true" />
+                                <check name="MEM-free-field" enabled="true" />
+                                <check name="MEM-free-fptr" enabled="true" />
+                                <check name="MEM-free-no-alloc-struct" enabled="false" />
+                                <check name="MEM-free-no-alloc" enabled="false" />
+                                <check name="MEM-free-no-use" enabled="true" />
+                                <check name="MEM-free-op" enabled="true" />
+                                <check name="MEM-free-struct-field" enabled="true" />
+                                <check name="MEM-free-variable-alias" enabled="true" />
+                                <check name="MEM-free-variable" enabled="true" />
+                                <check name="MEM-leak-alias" enabled="true" />
+                                <check name="MEM-leak" enabled="false" />
+                                <check name="MEM-malloc-arith" enabled="false" />
+                                <check name="MEM-malloc-diff-type" enabled="true" />
+                                <check name="MEM-malloc-sizeof-ptr" enabled="true" />
+                                <check name="MEM-malloc-sizeof" enabled="true" />
+                                <check name="MEM-malloc-strlen" enabled="false" />
+                                <check name="MEM-realloc-diff-type" enabled="true" />
+                                <check name="MEM-return-free" enabled="true" />
+                                <check name="MEM-return-no-assign" enabled="true" />
+                                <check name="MEM-stack-global-field" enabled="true" />
+                                <check name="MEM-stack-global" enabled="true" />
+                                <check name="MEM-stack-param-ref" enabled="true" />
+                                <check name="MEM-stack-param" enabled="true" />
+                                <check name="MEM-stack-pos" enabled="true" />
+                                <check name="MEM-stack-ref" enabled="true" />
+                                <check name="MEM-stack" enabled="true" />
+                                <check name="MEM-use-free-all" enabled="true" />
+                                <check name="MEM-use-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check name="PTR-arith-field" enabled="true" />
+                                <check name="PTR-arith-stack" enabled="true" />
+                                <check name="PTR-arith-var" enabled="true" />
+                                <check name="PTR-cmp-str-lit" enabled="true" />
+                                <check name="PTR-null-assign-fun-pos" enabled="false" />
+                                <check name="PTR-null-assign-pos" enabled="false" />
+                                <check name="PTR-null-assign" enabled="true" />
+                                <check name="PTR-null-cmp-aft" enabled="true" />
+                                <check name="PTR-null-cmp-bef-fun" enabled="true" />
+                                <check name="PTR-null-cmp-bef" enabled="true" />
+                                <check name="PTR-null-fun-pos" enabled="true" />
+                                <check name="PTR-null-literal-pos" enabled="false" />
+                                <check name="PTR-overload" enabled="false" />
+                                <check name="PTR-singleton-arith-pos" enabled="false" />
+                                <check name="PTR-singleton-arith" enabled="true" />
+                                <check name="PTR-unchk-param-some" enabled="true" />
+                                <check name="PTR-unchk-param" enabled="false" />
+                                <check name="PTR-uninit-pos" enabled="false" />
+                                <check name="PTR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check name="RED-alloc-zero-bytes" enabled="false" />
+                                <check name="RED-case-reach" enabled="false" />
+                                <check name="RED-cmp-always" enabled="false" />
+                                <check name="RED-cmp-never" enabled="false" />
+                                <check name="RED-cond-always" enabled="false" />
+                                <check name="RED-cond-const-assign" enabled="true" />
+                                <check name="RED-cond-const-expr" enabled="false" />
+                                <check name="RED-cond-const" enabled="false" />
+                                <check name="RED-cond-never" enabled="false" />
+                                <check name="RED-dead" enabled="true" />
+                                <check name="RED-expr" enabled="false" />
+                                <check name="RED-func-no-effect" enabled="false" />
+                                <check name="RED-local-hides-global" enabled="true" />
+                                <check name="RED-local-hides-local" enabled="false" />
+                                <check name="RED-local-hides-member" enabled="false" />
+                                <check name="RED-local-hides-param" enabled="true" />
+                                <check name="RED-no-effect" enabled="false" />
+                                <check name="RED-self-assign" enabled="true" />
+                                <check name="RED-unused-assign" enabled="true" />
+                                <check name="RED-unused-param" enabled="false" />
+                                <check name="RED-unused-return-val" enabled="false" />
+                                <check name="RED-unused-val" enabled="false" />
+                                <check name="RED-unused-var-all" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check name="RESOURCE-deref-file" enabled="false" />
+                                <check name="RESOURCE-double-close" enabled="true" />
+                                <check name="RESOURCE-file-no-close-all" enabled="true" />
+                                <check name="RESOURCE-file-pos-neg" enabled="false" />
+                                <check name="RESOURCE-file-use-after-close" enabled="true" />
+                                <check name="RESOURCE-implicit-deref-file" enabled="false" />
+                                <check name="RESOURCE-write-ronly-file" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check name="SIZEOF-side-effect" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check name="SPC-order" enabled="true" />
+                                <check name="SPC-uninit-arr-all" enabled="false" />
+                                <check name="SPC-uninit-struct-field-heap" enabled="true" />
+                                <check name="SPC-uninit-struct-field" enabled="false" />
+                                <check name="SPC-uninit-struct" enabled="true" />
+                                <check name="SPC-uninit-var-all" enabled="true" />
+                                <check name="SPC-uninit-var-some" enabled="true" />
+                                <check name="SPC-volatile-reads" enabled="false" />
+                                <check name="SPC-volatile-writes" enabled="false" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check name="STRUCT-signed-bit" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check name="SWITCH-fall-through" enabled="true" />
+                            </group>
+                            <group enabled="true" name="THROW">
+                                <check name="THROW-empty" enabled="false" />
+                                <check name="THROW-main" enabled="false" />
+                                <check name="THROW-null" enabled="true" />
+                                <check name="THROW-ptr" enabled="true" />
+                                <check name="THROW-static" enabled="true" />
+                                <check name="THROW-unhandled" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="CERT" enabled="false">
+                            <group enabled="true" name="CERT-ARR">
+                                <check name="CERT-ARR30-C_a" enabled="true" />
+                                <check name="CERT-ARR30-C_b" enabled="true" />
+                                <check name="CERT-ARR30-C_c" enabled="true" />
+                                <check name="CERT-ARR30-C_d" enabled="true" />
+                                <check name="CERT-ARR30-C_e" enabled="true" />
+                                <check name="CERT-ARR30-C_f" enabled="true" />
+                                <check name="CERT-ARR30-C_g" enabled="true" />
+                                <check name="CERT-ARR30-C_h" enabled="true" />
+                                <check name="CERT-ARR30-C_i" enabled="true" />
+                                <check name="CERT-ARR30-C_j" enabled="true" />
+                                <check name="CERT-ARR32-C" enabled="true" />
+                                <check name="CERT-ARR36-C_a" enabled="true" />
+                                <check name="CERT-ARR36-C_b" enabled="true" />
+                                <check name="CERT-ARR37-C" enabled="true" />
+                                <check name="CERT-ARR38-C_a" enabled="true" />
+                                <check name="CERT-ARR38-C_b" enabled="true" />
+                                <check name="CERT-ARR38-C_c" enabled="true" />
+                                <check name="CERT-ARR38-C_d" enabled="true" />
+                                <check name="CERT-ARR38-C_e" enabled="true" />
+                                <check name="CERT-ARR38-C_f" enabled="true" />
+                                <check name="CERT-ARR39-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check name="CERT-DCL30-C_a" enabled="true" />
+                                <check name="CERT-DCL30-C_b" enabled="true" />
+                                <check name="CERT-DCL30-C_c" enabled="true" />
+                                <check name="CERT-DCL30-C_d" enabled="true" />
+                                <check name="CERT-DCL30-C_e" enabled="true" />
+                                <check name="CERT-DCL31-C" enabled="true" />
+                                <check name="CERT-DCL36-C" enabled="true" />
+                                <check name="CERT-DCL37-C_a" enabled="true" />
+                                <check name="CERT-DCL37-C_b" enabled="true" />
+                                <check name="CERT-DCL37-C_c" enabled="false" />
+                                <check name="CERT-DCL38-C" enabled="true" />
+                                <check name="CERT-DCL39-C" enabled="true" />
+                                <check name="CERT-DCL40-C" enabled="true" />
+                                <check name="CERT-DCL41-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check name="CERT-ENV30-C" enabled="true" />
+                                <check name="CERT-ENV31-C" enabled="true" />
+                                <check name="CERT-ENV32-C" enabled="true" />
+                                <check name="CERT-ENV33-C" enabled="true" />
+                                <check name="CERT-ENV34-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check name="CERT-ERR30-C_a" enabled="true" />
+                                <check name="CERT-ERR30-C_b" enabled="true" />
+                                <check name="CERT-ERR30-C_c" enabled="true" />
+                                <check name="CERT-ERR30-C_d" enabled="true" />
+                                <check name="CERT-ERR32-C" enabled="true" />
+                                <check name="CERT-ERR33-C_a" enabled="true" />
+                                <check name="CERT-ERR33-C_b" enabled="true" />
+                                <check name="CERT-ERR33-C_c" enabled="true" />
+                                <check name="CERT-ERR33-C_d" enabled="true" />
+                                <check name="CERT-ERR34-C_a" enabled="true" />
+                                <check name="CERT-ERR34-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                                <check name="CERT-EXP30-C_a" enabled="true" />
+                                <check name="CERT-EXP30-C_b" enabled="true" />
+                                <check name="CERT-EXP32-C" enabled="true" />
+                                <check name="CERT-EXP33-C_a" enabled="true" />
+                                <check name="CERT-EXP33-C_b" enabled="true" />
+                                <check name="CERT-EXP33-C_c" enabled="true" />
+                                <check name="CERT-EXP33-C_d" enabled="true" />
+                                <check name="CERT-EXP33-C_e" enabled="true" />
+                                <check name="CERT-EXP33-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_a" enabled="true" />
+                                <check name="CERT-EXP34-C_b" enabled="true" />
+                                <check name="CERT-EXP34-C_c" enabled="true" />
+                                <check name="CERT-EXP34-C_d" enabled="true" />
+                                <check name="CERT-EXP34-C_e" enabled="true" />
+                                <check name="CERT-EXP34-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_g" enabled="true" />
+                                <check name="CERT-EXP35-C" enabled="true" />
+                                <check name="CERT-EXP36-C_a" enabled="true" />
+                                <check name="CERT-EXP36-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_a" enabled="true" />
+                                <check name="CERT-EXP37-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_a" enabled="true" />
+                                <check name="CERT-EXP39-C_b" enabled="true" />
+                                <check name="CERT-EXP39-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_d" enabled="true" />
+                                <check name="CERT-EXP39-C_e" enabled="true" />
+                                <check name="CERT-EXP40-C_a" enabled="true" />
+                                <check name="CERT-EXP40-C_b" enabled="true" />
+                                <check name="CERT-EXP42-C" enabled="true" />
+                                <check name="CERT-EXP43-C_a" enabled="true" />
+                                <check name="CERT-EXP43-C_b" enabled="true" />
+                                <check name="CERT-EXP43-C_c" enabled="true" />
+                                <check name="CERT-EXP43-C_d" enabled="true" />
+                                <check name="CERT-EXP44-C" enabled="true" />
+                                <check name="CERT-EXP45-C" enabled="true" />
+                                <check name="CERT-EXP46-C" enabled="true" />
+                                <check name="CERT-EXP47-C_a" enabled="true" />
+                                <check name="CERT-EXP47-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO30-C" enabled="true" />
+                                <check name="CERT-FIO32-C" enabled="true" />
+                                <check name="CERT-FIO34-C" enabled="true" />
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                                <check name="CERT-FIO39-C" enabled="true" />
+                                <check name="CERT-FIO40-C" enabled="true" />
+                                <check name="CERT-FIO41-C" enabled="true" />
+                                <check name="CERT-FIO42-C_a" enabled="true" />
+                                <check name="CERT-FIO42-C_b" enabled="false" />
+                                <check name="CERT-FIO44-C" enabled="true" />
+                                <check name="CERT-FIO45-C" enabled="true" />
+                                <check name="CERT-FIO46-C_a" enabled="true" />
+                                <check name="CERT-FIO46-C_b" enabled="true" />
+                                <check name="CERT-FIO46-C_c" enabled="true" />
+                                <check name="CERT-FIO47-C_a" enabled="true" />
+                                <check name="CERT-FIO47-C_b" enabled="true" />
+                                <check name="CERT-FIO47-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check name="CERT-FLP30-C_a" enabled="true" />
+                                <check name="CERT-FLP30-C_b" enabled="true" />
+                                <check name="CERT-FLP32-C_a" enabled="true" />
+                                <check name="CERT-FLP32-C_b" enabled="true" />
+                                <check name="CERT-FLP34-C" enabled="true" />
+                                <check name="CERT-FLP36-C" enabled="true" />
+                                <check name="CERT-FLP37-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check name="CERT-INT30-C_a" enabled="true" />
+                                <check name="CERT-INT30-C_b" enabled="false" />
+                                <check name="CERT-INT31-C_a" enabled="true" />
+                                <check name="CERT-INT31-C_b" enabled="true" />
+                                <check name="CERT-INT31-C_c" enabled="true" />
+                                <check name="CERT-INT32-C_a" enabled="true" />
+                                <check name="CERT-INT32-C_b" enabled="false" />
+                                <check name="CERT-INT33-C_a" enabled="true" />
+                                <check name="CERT-INT33-C_b" enabled="true" />
+                                <check name="CERT-INT33-C_c" enabled="true" />
+                                <check name="CERT-INT33-C_d" enabled="true" />
+                                <check name="CERT-INT33-C_e" enabled="true" />
+                                <check name="CERT-INT33-C_f" enabled="true" />
+                                <check name="CERT-INT33-C_g" enabled="true" />
+                                <check name="CERT-INT33-C_h" enabled="true" />
+                                <check name="CERT-INT33-C_i" enabled="true" />
+                                <check name="CERT-INT34-C_a" enabled="true" />
+                                <check name="CERT-INT34-C_b" enabled="true" />
+                                <check name="CERT-INT34-C_c" enabled="true" />
+                                <check name="CERT-INT35-C" enabled="true" />
+                                <check name="CERT-INT36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check name="CERT-MEM30-C_a" enabled="true" />
+                                <check name="CERT-MEM30-C_b" enabled="true" />
+                                <check name="CERT-MEM30-C_c" enabled="true" />
+                                <check name="CERT-MEM31-C" enabled="true" />
+                                <check name="CERT-MEM33-C_a" enabled="true" />
+                                <check name="CERT-MEM33-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_a" enabled="true" />
+                                <check name="CERT-MEM34-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_c" enabled="true" />
+                                <check name="CERT-MEM35-C_a" enabled="true" />
+                                <check name="CERT-MEM35-C_b" enabled="true" />
+                                <check name="CERT-MEM35-C_c" enabled="true" />
+                                <check name="CERT-MEM36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check name="CERT-MSC30-C" enabled="true" />
+                                <check name="CERT-MSC32-C" enabled="true" />
+                                <check name="CERT-MSC33-C" enabled="false" />
+                                <check name="CERT-MSC37-C" enabled="true" />
+                                <check name="CERT-MSC38-C" enabled="true" />
+                                <check name="CERT-MSC39-C" enabled="true" />
+                                <check name="CERT-MSC40-C_a" enabled="true" />
+                                <check name="CERT-MSC40-C_b" enabled="true" />
+                                <check name="CERT-MSC40-C_c" enabled="true" />
+                                <check name="CERT-MSC40-C_d" enabled="true" />
+                                <check name="CERT-MSC40-C_e" enabled="false" />
+                                <check name="CERT-MSC41-C_a" enabled="true" />
+                                <check name="CERT-MSC41-C_b" enabled="true" />
+                                <check name="CERT-MSC41-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check name="CERT-PRE31-C" enabled="true" />
+                                <check name="CERT-PRE32-C_a" enabled="true" />
+                                <check name="CERT-PRE32-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG30-C" enabled="true" />
+                                <check name="CERT-SIG31-C" enabled="true" />
+                                <check name="CERT-SIG34-C" enabled="true" />
+                                <check name="CERT-SIG35-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check name="CERT-STR30-C" enabled="true" />
+                                <check name="CERT-STR31-C_a" enabled="true" />
+                                <check name="CERT-STR31-C_b" enabled="true" />
+                                <check name="CERT-STR31-C_c" enabled="true" />
+                                <check name="CERT-STR31-C_d" enabled="true" />
+                                <check name="CERT-STR31-C_e" enabled="true" />
+                                <check name="CERT-STR31-C_f" enabled="true" />
+                                <check name="CERT-STR31-C_g" enabled="true" />
+                                <check name="CERT-STR31-C_h" enabled="true" />
+                                <check name="CERT-STR32-C" enabled="true" />
+                                <check name="CERT-STR34-C" enabled="true" />
+                                <check name="CERT-STR37-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
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+                                <check name="MISRAC2004-1.2_a" enabled="true" />
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+                                <check name="MISRAC2004-1.2_i" enabled="true" />
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+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
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+                                <check name="MISRAC2004-7.1" enabled="true" />
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+                                <check name="MISRAC2004-8.10" enabled="true" />
+                                <check name="MISRAC2004-8.12" enabled="true" />
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+                                <check name="MISRAC2004-9.3" enabled="true" />
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+                                <check name="MISRAC2004-10.3" enabled="true" />
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+                                <check name="MISRAC2004-10.5" enabled="true" />
+                                <check name="MISRAC2004-10.6" enabled="true" />
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+                                <check name="MISRAC2004-11.5" enabled="true" />
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+                                <check name="MISRAC2004-12.13" enabled="false" />
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+                                <check name="MISRAC2004-13.6" enabled="true" />
+                                <check name="MISRAC2004-13.7_a" enabled="true" />
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+                                <check name="MISRAC2004-15.5" enabled="true" />
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+                                <check name="MISRAC2004-17.6_d" enabled="true" />
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+                                <check name="MISRAC2004-18.4" enabled="true" />
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+                                <check name="MISRAC2004-19.15" enabled="true" />
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+                                <check name="MEM-use-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="PTR">
+                                <check name="PTR-arith-field" enabled="true" />
+                                <check name="PTR-arith-stack" enabled="true" />
+                                <check name="PTR-arith-var" enabled="true" />
+                                <check name="PTR-cmp-str-lit" enabled="true" />
+                                <check name="PTR-null-assign-fun-pos" enabled="false" />
+                                <check name="PTR-null-assign-pos" enabled="false" />
+                                <check name="PTR-null-assign" enabled="true" />
+                                <check name="PTR-null-cmp-aft" enabled="true" />
+                                <check name="PTR-null-cmp-bef-fun" enabled="true" />
+                                <check name="PTR-null-cmp-bef" enabled="true" />
+                                <check name="PTR-null-fun-pos" enabled="true" />
+                                <check name="PTR-null-literal-pos" enabled="false" />
+                                <check name="PTR-overload" enabled="false" />
+                                <check name="PTR-singleton-arith-pos" enabled="false" />
+                                <check name="PTR-singleton-arith" enabled="true" />
+                                <check name="PTR-unchk-param-some" enabled="true" />
+                                <check name="PTR-unchk-param" enabled="false" />
+                                <check name="PTR-uninit-pos" enabled="false" />
+                                <check name="PTR-uninit" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RED">
+                                <check name="RED-alloc-zero-bytes" enabled="false" />
+                                <check name="RED-case-reach" enabled="false" />
+                                <check name="RED-cmp-always" enabled="false" />
+                                <check name="RED-cmp-never" enabled="false" />
+                                <check name="RED-cond-always" enabled="false" />
+                                <check name="RED-cond-const-assign" enabled="true" />
+                                <check name="RED-cond-const-expr" enabled="false" />
+                                <check name="RED-cond-const" enabled="false" />
+                                <check name="RED-cond-never" enabled="false" />
+                                <check name="RED-dead" enabled="true" />
+                                <check name="RED-expr" enabled="false" />
+                                <check name="RED-func-no-effect" enabled="false" />
+                                <check name="RED-local-hides-global" enabled="true" />
+                                <check name="RED-local-hides-local" enabled="false" />
+                                <check name="RED-local-hides-member" enabled="false" />
+                                <check name="RED-local-hides-param" enabled="true" />
+                                <check name="RED-no-effect" enabled="false" />
+                                <check name="RED-self-assign" enabled="true" />
+                                <check name="RED-unused-assign" enabled="true" />
+                                <check name="RED-unused-param" enabled="false" />
+                                <check name="RED-unused-return-val" enabled="false" />
+                                <check name="RED-unused-val" enabled="false" />
+                                <check name="RED-unused-var-all" enabled="true" />
+                            </group>
+                            <group enabled="true" name="RESOURCE">
+                                <check name="RESOURCE-deref-file" enabled="false" />
+                                <check name="RESOURCE-double-close" enabled="true" />
+                                <check name="RESOURCE-file-no-close-all" enabled="true" />
+                                <check name="RESOURCE-file-pos-neg" enabled="false" />
+                                <check name="RESOURCE-file-use-after-close" enabled="true" />
+                                <check name="RESOURCE-implicit-deref-file" enabled="false" />
+                                <check name="RESOURCE-write-ronly-file" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SIZEOF">
+                                <check name="SIZEOF-side-effect" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SPC">
+                                <check name="SPC-order" enabled="true" />
+                                <check name="SPC-uninit-arr-all" enabled="false" />
+                                <check name="SPC-uninit-struct-field-heap" enabled="true" />
+                                <check name="SPC-uninit-struct-field" enabled="false" />
+                                <check name="SPC-uninit-struct" enabled="true" />
+                                <check name="SPC-uninit-var-all" enabled="true" />
+                                <check name="SPC-uninit-var-some" enabled="true" />
+                                <check name="SPC-volatile-reads" enabled="false" />
+                                <check name="SPC-volatile-writes" enabled="false" />
+                            </group>
+                            <group enabled="true" name="STRUCT">
+                                <check name="STRUCT-signed-bit" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SWITCH">
+                                <check name="SWITCH-fall-through" enabled="true" />
+                            </group>
+                            <group enabled="true" name="THROW">
+                                <check name="THROW-empty" enabled="false" />
+                                <check name="THROW-main" enabled="false" />
+                                <check name="THROW-null" enabled="true" />
+                                <check name="THROW-ptr" enabled="true" />
+                                <check name="THROW-static" enabled="true" />
+                                <check name="THROW-unhandled" enabled="true" />
+                            </group>
+                            <group enabled="true" name="UNION">
+                                <check name="UNION-overlap-assign" enabled="true" />
+                                <check name="UNION-type-punning" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="CERT" enabled="false">
+                            <group enabled="true" name="CERT-ARR">
+                                <check name="CERT-ARR30-C_a" enabled="true" />
+                                <check name="CERT-ARR30-C_b" enabled="true" />
+                                <check name="CERT-ARR30-C_c" enabled="true" />
+                                <check name="CERT-ARR30-C_d" enabled="true" />
+                                <check name="CERT-ARR30-C_e" enabled="true" />
+                                <check name="CERT-ARR30-C_f" enabled="true" />
+                                <check name="CERT-ARR30-C_g" enabled="true" />
+                                <check name="CERT-ARR30-C_h" enabled="true" />
+                                <check name="CERT-ARR30-C_i" enabled="true" />
+                                <check name="CERT-ARR30-C_j" enabled="true" />
+                                <check name="CERT-ARR32-C" enabled="true" />
+                                <check name="CERT-ARR36-C_a" enabled="true" />
+                                <check name="CERT-ARR36-C_b" enabled="true" />
+                                <check name="CERT-ARR37-C" enabled="true" />
+                                <check name="CERT-ARR38-C_a" enabled="true" />
+                                <check name="CERT-ARR38-C_b" enabled="true" />
+                                <check name="CERT-ARR38-C_c" enabled="true" />
+                                <check name="CERT-ARR38-C_d" enabled="true" />
+                                <check name="CERT-ARR38-C_e" enabled="true" />
+                                <check name="CERT-ARR38-C_f" enabled="true" />
+                                <check name="CERT-ARR39-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-DCL">
+                                <check name="CERT-DCL30-C_a" enabled="true" />
+                                <check name="CERT-DCL30-C_b" enabled="true" />
+                                <check name="CERT-DCL30-C_c" enabled="true" />
+                                <check name="CERT-DCL30-C_d" enabled="true" />
+                                <check name="CERT-DCL30-C_e" enabled="true" />
+                                <check name="CERT-DCL31-C" enabled="true" />
+                                <check name="CERT-DCL36-C" enabled="true" />
+                                <check name="CERT-DCL37-C_a" enabled="true" />
+                                <check name="CERT-DCL37-C_b" enabled="true" />
+                                <check name="CERT-DCL37-C_c" enabled="false" />
+                                <check name="CERT-DCL38-C" enabled="true" />
+                                <check name="CERT-DCL39-C" enabled="true" />
+                                <check name="CERT-DCL40-C" enabled="true" />
+                                <check name="CERT-DCL41-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ENV">
+                                <check name="CERT-ENV30-C" enabled="true" />
+                                <check name="CERT-ENV31-C" enabled="true" />
+                                <check name="CERT-ENV32-C" enabled="true" />
+                                <check name="CERT-ENV33-C" enabled="true" />
+                                <check name="CERT-ENV34-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-ERR">
+                                <check name="CERT-ERR30-C_a" enabled="true" />
+                                <check name="CERT-ERR30-C_b" enabled="true" />
+                                <check name="CERT-ERR30-C_c" enabled="true" />
+                                <check name="CERT-ERR30-C_d" enabled="true" />
+                                <check name="CERT-ERR32-C" enabled="true" />
+                                <check name="CERT-ERR33-C_a" enabled="true" />
+                                <check name="CERT-ERR33-C_b" enabled="true" />
+                                <check name="CERT-ERR33-C_c" enabled="true" />
+                                <check name="CERT-ERR33-C_d" enabled="true" />
+                                <check name="CERT-ERR34-C_a" enabled="true" />
+                                <check name="CERT-ERR34-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-EXP">
+                                <check name="CERT-EXP19-C" enabled="true" />
+                                <check name="CERT-EXP30-C_a" enabled="true" />
+                                <check name="CERT-EXP30-C_b" enabled="true" />
+                                <check name="CERT-EXP32-C" enabled="true" />
+                                <check name="CERT-EXP33-C_a" enabled="true" />
+                                <check name="CERT-EXP33-C_b" enabled="true" />
+                                <check name="CERT-EXP33-C_c" enabled="true" />
+                                <check name="CERT-EXP33-C_d" enabled="true" />
+                                <check name="CERT-EXP33-C_e" enabled="true" />
+                                <check name="CERT-EXP33-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_a" enabled="true" />
+                                <check name="CERT-EXP34-C_b" enabled="true" />
+                                <check name="CERT-EXP34-C_c" enabled="true" />
+                                <check name="CERT-EXP34-C_d" enabled="true" />
+                                <check name="CERT-EXP34-C_e" enabled="true" />
+                                <check name="CERT-EXP34-C_f" enabled="true" />
+                                <check name="CERT-EXP34-C_g" enabled="true" />
+                                <check name="CERT-EXP35-C" enabled="true" />
+                                <check name="CERT-EXP36-C_a" enabled="true" />
+                                <check name="CERT-EXP36-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_a" enabled="true" />
+                                <check name="CERT-EXP37-C_b" enabled="true" />
+                                <check name="CERT-EXP37-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_a" enabled="true" />
+                                <check name="CERT-EXP39-C_b" enabled="true" />
+                                <check name="CERT-EXP39-C_c" enabled="true" />
+                                <check name="CERT-EXP39-C_d" enabled="true" />
+                                <check name="CERT-EXP39-C_e" enabled="true" />
+                                <check name="CERT-EXP40-C_a" enabled="true" />
+                                <check name="CERT-EXP40-C_b" enabled="true" />
+                                <check name="CERT-EXP42-C" enabled="true" />
+                                <check name="CERT-EXP43-C_a" enabled="true" />
+                                <check name="CERT-EXP43-C_b" enabled="true" />
+                                <check name="CERT-EXP43-C_c" enabled="true" />
+                                <check name="CERT-EXP43-C_d" enabled="true" />
+                                <check name="CERT-EXP44-C" enabled="true" />
+                                <check name="CERT-EXP45-C" enabled="true" />
+                                <check name="CERT-EXP46-C" enabled="true" />
+                                <check name="CERT-EXP47-C_a" enabled="true" />
+                                <check name="CERT-EXP47-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FIO">
+                                <check name="CERT-FIO30-C" enabled="true" />
+                                <check name="CERT-FIO32-C" enabled="true" />
+                                <check name="CERT-FIO34-C" enabled="true" />
+                                <check name="CERT-FIO37-C" enabled="true" />
+                                <check name="CERT-FIO38-C" enabled="true" />
+                                <check name="CERT-FIO39-C" enabled="true" />
+                                <check name="CERT-FIO40-C" enabled="true" />
+                                <check name="CERT-FIO41-C" enabled="true" />
+                                <check name="CERT-FIO42-C_a" enabled="true" />
+                                <check name="CERT-FIO42-C_b" enabled="false" />
+                                <check name="CERT-FIO44-C" enabled="true" />
+                                <check name="CERT-FIO45-C" enabled="true" />
+                                <check name="CERT-FIO46-C_a" enabled="true" />
+                                <check name="CERT-FIO46-C_b" enabled="true" />
+                                <check name="CERT-FIO46-C_c" enabled="true" />
+                                <check name="CERT-FIO47-C_a" enabled="true" />
+                                <check name="CERT-FIO47-C_b" enabled="true" />
+                                <check name="CERT-FIO47-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-FLP">
+                                <check name="CERT-FLP30-C_a" enabled="true" />
+                                <check name="CERT-FLP30-C_b" enabled="true" />
+                                <check name="CERT-FLP32-C_a" enabled="true" />
+                                <check name="CERT-FLP32-C_b" enabled="true" />
+                                <check name="CERT-FLP34-C" enabled="true" />
+                                <check name="CERT-FLP36-C" enabled="true" />
+                                <check name="CERT-FLP37-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-INT">
+                                <check name="CERT-INT30-C_a" enabled="true" />
+                                <check name="CERT-INT30-C_b" enabled="false" />
+                                <check name="CERT-INT31-C_a" enabled="true" />
+                                <check name="CERT-INT31-C_b" enabled="true" />
+                                <check name="CERT-INT31-C_c" enabled="true" />
+                                <check name="CERT-INT32-C_a" enabled="true" />
+                                <check name="CERT-INT32-C_b" enabled="false" />
+                                <check name="CERT-INT33-C_a" enabled="true" />
+                                <check name="CERT-INT33-C_b" enabled="true" />
+                                <check name="CERT-INT33-C_c" enabled="true" />
+                                <check name="CERT-INT33-C_d" enabled="true" />
+                                <check name="CERT-INT33-C_e" enabled="true" />
+                                <check name="CERT-INT33-C_f" enabled="true" />
+                                <check name="CERT-INT33-C_g" enabled="true" />
+                                <check name="CERT-INT33-C_h" enabled="true" />
+                                <check name="CERT-INT33-C_i" enabled="true" />
+                                <check name="CERT-INT34-C_a" enabled="true" />
+                                <check name="CERT-INT34-C_b" enabled="true" />
+                                <check name="CERT-INT34-C_c" enabled="true" />
+                                <check name="CERT-INT35-C" enabled="true" />
+                                <check name="CERT-INT36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MEM">
+                                <check name="CERT-MEM30-C_a" enabled="true" />
+                                <check name="CERT-MEM30-C_b" enabled="true" />
+                                <check name="CERT-MEM30-C_c" enabled="true" />
+                                <check name="CERT-MEM31-C" enabled="true" />
+                                <check name="CERT-MEM33-C_a" enabled="true" />
+                                <check name="CERT-MEM33-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_a" enabled="true" />
+                                <check name="CERT-MEM34-C_b" enabled="true" />
+                                <check name="CERT-MEM34-C_c" enabled="true" />
+                                <check name="CERT-MEM35-C_a" enabled="true" />
+                                <check name="CERT-MEM35-C_b" enabled="true" />
+                                <check name="CERT-MEM35-C_c" enabled="true" />
+                                <check name="CERT-MEM36-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-MSC">
+                                <check name="CERT-MSC30-C" enabled="true" />
+                                <check name="CERT-MSC32-C" enabled="true" />
+                                <check name="CERT-MSC33-C" enabled="false" />
+                                <check name="CERT-MSC37-C" enabled="true" />
+                                <check name="CERT-MSC38-C" enabled="true" />
+                                <check name="CERT-MSC39-C" enabled="true" />
+                                <check name="CERT-MSC40-C_a" enabled="true" />
+                                <check name="CERT-MSC40-C_b" enabled="true" />
+                                <check name="CERT-MSC40-C_c" enabled="true" />
+                                <check name="CERT-MSC40-C_d" enabled="true" />
+                                <check name="CERT-MSC40-C_e" enabled="false" />
+                                <check name="CERT-MSC41-C_a" enabled="true" />
+                                <check name="CERT-MSC41-C_b" enabled="true" />
+                                <check name="CERT-MSC41-C_c" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-PRE">
+                                <check name="CERT-PRE31-C" enabled="true" />
+                                <check name="CERT-PRE32-C_a" enabled="true" />
+                                <check name="CERT-PRE32-C_b" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-SIG">
+                                <check name="CERT-SIG30-C" enabled="true" />
+                                <check name="CERT-SIG31-C" enabled="true" />
+                                <check name="CERT-SIG34-C" enabled="true" />
+                                <check name="CERT-SIG35-C" enabled="true" />
+                            </group>
+                            <group enabled="true" name="CERT-STR">
+                                <check name="CERT-STR30-C" enabled="true" />
+                                <check name="CERT-STR31-C_a" enabled="true" />
+                                <check name="CERT-STR31-C_b" enabled="true" />
+                                <check name="CERT-STR31-C_c" enabled="true" />
+                                <check name="CERT-STR31-C_d" enabled="true" />
+                                <check name="CERT-STR31-C_e" enabled="true" />
+                                <check name="CERT-STR31-C_f" enabled="true" />
+                                <check name="CERT-STR31-C_g" enabled="true" />
+                                <check name="CERT-STR31-C_h" enabled="true" />
+                                <check name="CERT-STR32-C" enabled="true" />
+                                <check name="CERT-STR34-C" enabled="true" />
+                                <check name="CERT-STR37-C" enabled="true" />
+                            </group>
+                        </package>
+                        <package name="SECURITY" enabled="false">
+                            <group enabled="true" name="SEC-BUFFER">
+                                <check name="SEC-BUFFER-memory-leak-alias" enabled="true" />
+                                <check name="SEC-BUFFER-memory-leak" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-memset-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-qsort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-qsort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-sprintf-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-std-sort-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-std-sort-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strcpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strcpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncat-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncat-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncmp-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncmp-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-strncpy-overrun-pos" enabled="false" />
+                                <check name="SEC-BUFFER-strncpy-overrun" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-alloc-size" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy-length" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-copy" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-index" enabled="true" />
+                                <check name="SEC-BUFFER-tainted-offset" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-all" enabled="true" />
+                                <check name="SEC-BUFFER-use-after-free-some" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-DIV-0">
+                                <check name="SEC-DIV-0-compare-after" enabled="true" />
+                                <check name="SEC-DIV-0-compare-before" enabled="true" />
+                                <check name="SEC-DIV-0-tainted" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-FILEOP">
+                                <check name="SEC-FILEOP-open-no-close" enabled="true" />
+                                <check name="SEC-FILEOP-path-traversal" enabled="false" />
+                                <check name="SEC-FILEOP-use-after-close" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-INJECTION">
+                                <check name="SEC-INJECTION-sql" enabled="false" />
+                                <check name="SEC-INJECTION-xpath" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-LOOP">
+                                <check name="SEC-LOOP-tainted-bound" enabled="true" />
+                            </group>
+                            <group enabled="true" name="SEC-NULL">
+                                <check name="SEC-NULL-assignment-fun-pos" enabled="false" />
+                                <check name="SEC-NULL-assignment" enabled="true" />
+                                <check name="SEC-NULL-cmp-aft" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef-fun" enabled="true" />
+                                <check name="SEC-NULL-cmp-bef" enabled="true" />
+                                <check name="SEC-NULL-literal-pos" enabled="false" />
+                            </group>
+                            <group enabled="true" name="SEC-STRING">
+                                <check name="SEC-STRING-format-string" enabled="true" />
+                                <check name="SEC-STRING-hard-coded-credentials" enabled="false" />
+                            </group>
+                        </package>
+                        <package name="MISRAC2004" enabled="false">
+                            <group enabled="true" name="MISRAC2004-1">
+                                <check name="MISRAC2004-1.1" enabled="true" />
+                                <check name="MISRAC2004-1.2_a" enabled="true" />
+                                <check name="MISRAC2004-1.2_b" enabled="true" />
+                                <check name="MISRAC2004-1.2_c" enabled="true" />
+                                <check name="MISRAC2004-1.2_d" enabled="true" />
+                                <check name="MISRAC2004-1.2_e" enabled="true" />
+                                <check name="MISRAC2004-1.2_f" enabled="true" />
+                                <check name="MISRAC2004-1.2_g" enabled="true" />
+                                <check name="MISRAC2004-1.2_h" enabled="true" />
+                                <check name="MISRAC2004-1.2_i" enabled="true" />
+                                <check name="MISRAC2004-1.2_j" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC2004-2">
+                                <check name="MISRAC2004-2.1" enabled="true" />
+                                <check name="MISRAC2004-2.2" enabled="true" />
+                                <check name="MISRAC2004-2.3" enabled="true" />
+                                <check name="MISRAC2004-2.4" enabled="false" />
+                            </group>
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+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-3">
+                                <check name="MISRAC++2008-9-3-1" enabled="true" />
+                                <check name="MISRAC++2008-9-3-2" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-5">
+                                <check name="MISRAC++2008-9-5-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-9-6">
+                                <check name="MISRAC++2008-9-6-2" enabled="true" />
+                                <check name="MISRAC++2008-9-6-3" enabled="true" />
+                                <check name="MISRAC++2008-9-6-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-12-1">
+                                <check name="MISRAC++2008-12-1-1_a" enabled="true" />
+                                <check name="MISRAC++2008-12-1-1_b" enabled="true" />
+                                <check name="MISRAC++2008-12-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-0">
+                                <check name="MISRAC++2008-15-0-2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-1">
+                                <check name="MISRAC++2008-15-1-2" enabled="true" />
+                                <check name="MISRAC++2008-15-1-3" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-3">
+                                <check name="MISRAC++2008-15-3-1" enabled="true" />
+                                <check name="MISRAC++2008-15-3-2" enabled="false" />
+                                <check name="MISRAC++2008-15-3-3" enabled="true" />
+                                <check name="MISRAC++2008-15-3-4" enabled="true" />
+                                <check name="MISRAC++2008-15-3-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-15-5">
+                                <check name="MISRAC++2008-15-5-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-0">
+                                <check name="MISRAC++2008-16-0-3" enabled="true" />
+                                <check name="MISRAC++2008-16-0-4" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-2">
+                                <check name="MISRAC++2008-16-2-2" enabled="true" />
+                                <check name="MISRAC++2008-16-2-3" enabled="true" />
+                                <check name="MISRAC++2008-16-2-4" enabled="true" />
+                                <check name="MISRAC++2008-16-2-5" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-16-3">
+                                <check name="MISRAC++2008-16-3-1" enabled="true" />
+                                <check name="MISRAC++2008-16-3-2" enabled="false" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-17-0">
+                                <check name="MISRAC++2008-17-0-1" enabled="true" />
+                                <check name="MISRAC++2008-17-0-3" enabled="true" />
+                                <check name="MISRAC++2008-17-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-0">
+                                <check name="MISRAC++2008-18-0-1" enabled="true" />
+                                <check name="MISRAC++2008-18-0-2" enabled="true" />
+                                <check name="MISRAC++2008-18-0-3" enabled="true" />
+                                <check name="MISRAC++2008-18-0-4" enabled="true" />
+                                <check name="MISRAC++2008-18-0-5" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-2">
+                                <check name="MISRAC++2008-18-2-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-4">
+                                <check name="MISRAC++2008-18-4-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-18-7">
+                                <check name="MISRAC++2008-18-7-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-19-3">
+                                <check name="MISRAC++2008-19-3-1" enabled="true" />
+                            </group>
+                            <group enabled="true" name="MISRAC++2008-27-0">
+                                <check name="MISRAC++2008-27-0-1" enabled="true" />
+                            </group>
+                        </package>
+                    </checks_tree>
+                </cstat_settings>
+            </data>
+        </settings>
+        <settings>
+            <name>RuntimeChecking</name>
+            <archiveVersion>0</archiveVersion>
+            <data>
+                <version>2</version>
+                <wantNonLocal>1</wantNonLocal>
+                <debug>0</debug>
+                <option>
+                    <name>GenRtcDebugHeap</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnableBoundsChecking</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrMem</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcTrackPointerBounds</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckAccesses</name>
+                    <state>1</state>
+                </option>
+                <option>
+                    <name>GenRtcGenerateEntries</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcNrTrackedPointers</name>
+                    <state>1000</state>
+                </option>
+                <option>
+                    <name>GenRtcIntOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIncUnsigned</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntConversion</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclExplicit</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcIntShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcInclUnsignedShiftOverflow</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcUnhandledCase</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcDivByZero</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcEnable</name>
+                    <state>0</state>
+                </option>
+                <option>
+                    <name>GenRtcCheckPtrsNonInstrFunc</name>
+                    <state>1</state>
+                </option>
+            </data>
+        </settings>
+    </configuration>
+    <file>
+        <name>$PROJ_DIR$\DIO.C</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\DIO.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\main.c</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\tm4c123gh6pm.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\Traffic_light.C</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\Traffic_light.h</name>
+    </file>
+    <file>
+        <name>$PROJ_DIR$\types.h</name>
+    </file>
+</project>
diff --git a/Traffic_light.C b/Traffic_light.C
new file mode 100644
index 0000000..2baa1fc
--- /dev/null
+++ b/Traffic_light.C
@@ -0,0 +1,394 @@
+// Include used libraries
+#include "Traffic_light.h"
+#include "stdint.h"
+#include "stdio.h"
+#include "stdbool.h"
+#include "driverlib/gpio.h"
+#include "inc/hw_gpio.h"
+#include "inc/hw_memmap.h"
+#include "driverlib/sysctl.h"
+#include "inc/hw_types.h"
+#include "inc/hw_ints.h"
+#include "driverlib/timer.c"
+#include "driverlib/timer.h"
+#include "tm4c123gh6pm.h"
+
+// Global variables used in the main.c defined as extern 
+extern int_32 next_state;
+extern int_32 next_state_2;
+extern int_32 next_state_ps;
+extern int_32 ps_1;
+extern int_32 ps_2;
+extern int_32 elapsed_time_1;
+extern int_32 elapsed_time_2;
+
+
+// function handles the traffic light 1 interrupt
+void Timer0_handler() 
+{
+  TimerIntClear(TIMER0_BASE, TIMER_TIMA_TIMEOUT); //CLEAR THE FLAG 
+  switch(next_state)
+  {
+  case GREEN_1:
+	  Timer0_init(5-Ticks_to_time(elapsed_time_1));
+	  elapsed_time_1 = 0;
+	  next_state = YELLOW_1; // blue
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_5, GPIO_PIN_5); // RED_ps_1
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_4, 0); // GREEN_ps_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, 0); // RED_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, GPIO_PIN_4); // GREEN_1
+	  break; 
+  case YELLOW_1: 
+	  Timer0_init(2);
+	  next_state = RED_1;
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, 0); // GREEN_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, GPIO_PIN_3); // YELLOW_1
+	  break; 
+  case RED_1:
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); // YELLOW_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, 0); // GREEN_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_1
+	  next_state_2 = GREEN_2;
+	  Timer0_dsiable();	
+	  Timer1_init(1); 
+	  break;	
+  case GREEN_ps_1:
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); // YELLOW_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, 0); // GREEN_1
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_1
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_5, 0); // RED_ps_1
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_4, GPIO_PIN_4); // GREEN_ps_1
+	  Timer0_init(2); 
+	  next_state = RED_ps_1; 
+	break;
+  case RED_ps_1:
+	  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); // YELLOW_1
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_5, GPIO_PIN_5); // RED_ps_1
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_4, 0); // GREEN_ps_1
+	  next_state = GREEN_1;
+	  reset_traffic_2();
+	  Timer0_init(1); 
+
+	break; 
+	}
+}
+
+// function handles the traffic light 2 interrupt
+void Timer1_handler()
+{
+  TimerIntClear(TIMER1_BASE, TIMER_TIMA_TIMEOUT); //CLEAR THE FLAG 
+  switch(next_state_2)
+  {
+  case GREEN_2:
+	  Timer1_init(5 - Ticks_to_time(elapsed_time_2));
+	  elapsed_time_2 = 0; 
+	  next_state_2 = YELLOW_2;
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_ps_2
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0); // GREEN_ps_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, 0); // RED_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, GPIO_PIN_0); // GREEN_2
+	  break; 
+  case YELLOW_2: 
+	  Timer1_init(2);
+	  next_state_2 = RED_2;
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0); // GREEN_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, GPIO_PIN_2); // YELLOW_2
+	  break; 
+  case RED_2:
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, 0); // YELLOW_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3); // RED_2 
+	  next_state = GREEN_1;
+	  Timer1_disable();	
+	  Timer0_init(1); 
+	  break;	
+  case GREEN_ps_2:
+	  Timer1_init(2); 
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, 0); // YELLOW_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0); // GREEN_2
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3); // RED_2
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, 0); // RED_ps_2
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, GPIO_PIN_1); // GREEN_ps_2
+	  next_state_2 = RED_ps_2; 
+	break;
+  case RED_ps_2:
+	  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, 0); // YELLOW_2
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_ps_1
+	  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_1, 0); // GREEN_ps_1
+	  next_state_2 = GREEN_2;
+	  Timer1_init(1); 
+	  reset_traffic_1();
+	break; 
+	}
+}
+
+// This functions initialize Timer 0 with given time as parameter 
+void Timer0_init(int_32 time)
+{
+  
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER0); 
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER0))
+  {
+  }
+  TimerDisable(TIMER0_BASE, TIMER_BOTH); // DISABLE
+  // Configuration
+  TimerConfigure(TIMER0_BASE, (TIMER_CFG_PERIODIC | TIMER_CFG_A_ACT_TOINTD)); 
+  TimerLoadSet(TIMER0_BASE , TIMER_A, (time * 16000000)-1);
+  // Timer interrupt 
+  TimerIntRegister(TIMER0_BASE, TIMER_A, Timer0_handler);
+  TimerIntEnable(TIMER0_BASE, TIMER_TIMA_TIMEOUT);
+  // NVIC interrupt 
+  IntEnable(INT_TIMER0A_TM4C123);
+  // CPU interrupt
+  IntMasterEnable();
+  TimerEnable(TIMER0_BASE, TIMER_BOTH); // ENABLE
+  
+}
+
+// This functions initialize Timer 1 with given time as parameter 
+void Timer1_init(int_32 time)
+{
+  
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_TIMER1); 
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_TIMER1))
+  {
+  }
+  TimerDisable(TIMER1_BASE, TIMER_BOTH); // DISABLE
+  // Configuration
+  TimerConfigure(TIMER1_BASE, (TIMER_CFG_PERIODIC | TIMER_CFG_A_ACT_TOINTD)); 
+  TimerLoadSet(TIMER1_BASE , TIMER_A, (time * 16000000)-1);
+  // Timer interrupt 
+  TimerIntRegister(TIMER1_BASE, TIMER_A, Timer1_handler);
+  TimerIntEnable(TIMER1_BASE, TIMER_TIMA_TIMEOUT);
+  // NVIC interrupt 
+  IntEnable(INT_TIMER1A_TM4C123);
+  // CPU interrupt
+  IntMasterEnable();
+  TimerEnable(TIMER1_BASE, TIMER_BOTH); // ENABLE
+}
+
+
+
+
+
+// Function initializes the corresponding port A
+
+/* function initializes the corresponding port with all functionalities needed*/
+void PORTA_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOA);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOA)){ }
+  HWREG(GPIO_PORTA_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+  HWREG(GPIO_PORTA_BASE + GPIO_O_CR) |= GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
+  GPIOPinTypeGPIOOutput(GPIO_PORTA_BASE,GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+  GPIOPadConfigSet(GPIO_PORTA_BASE,GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+}
+
+
+
+// Function initializes the corresponding port B
+
+/* function initializes the corresponding port with all functionalities needed*/
+void PORTB_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOB);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOB)){ }
+  HWREG(GPIO_PORTB_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+  HWREG(GPIO_PORTB_BASE + GPIO_O_CR) |=  GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7; 
+  GPIOPinTypeGPIOOutput(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_4 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3);
+  GPIOPadConfigSet(GPIO_PORTB_BASE, GPIO_PIN_0 | GPIO_PIN_4 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+}
+
+
+
+// Function initializes the corresponding port C
+
+/* function initializes the corresponding port with all functionalities needed*/
+
+void PORTC_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOC);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOC)){ }
+  HWREG(GPIO_PORTC_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+   HWREG(GPIO_PORTC_BASE + GPIO_O_CR) |= GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 
+                                      | GPIO_PIN_7;
+  GPIOPinTypeGPIOOutput(GPIO_PORTC_BASE, GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 
+                                      | GPIO_PIN_7);
+  GPIOPadConfigSet(GPIO_PORTC_BASE,  GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 
+                                      | GPIO_PIN_7, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+}
+		
+
+
+// Function initializes the corresponding port D
+
+/* function initializes the corresponding port with all functionalities needed*/
+
+void PORTD_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOD);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOD)){ }
+  HWREG(GPIO_PORTD_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+ HWREG(GPIO_PORTD_BASE + GPIO_O_CR) |=  GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
+ GPIOPinTypeGPIOInput(GPIO_PORTD_BASE,GPIO_PIN_0);
+ GPIOPinTypeGPIOOutput(GPIO_PORTD_BASE,GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6);
+ GPIOPadConfigSet(GPIO_PORTD_BASE, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+  // **GPIO interrupt** 
+  GPIOIntRegister(GPIO_PORTD_BASE, switch2_handler); 
+  GPIOIntEnable(GPIO_PORTD_BASE, GPIO_INT_PIN_0);
+  // NVIC interrupt 
+  IntEnable(INT_GPIOD_TM4C123);
+  // CPU interrupt
+  IntMasterEnable();
+}
+		
+
+
+// Function initializes the corresponding port E
+
+/* function initializes the corresponding port with all functionalities needed*/
+
+void PORTE_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOE);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOE)){ }
+  HWREG(GPIO_PORTE_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+  HWREG(GPIO_PORTE_BASE + GPIO_O_CR) |=  GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
+ GPIOPinTypeGPIOOutput(GPIO_PORTE_BASE,GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+ GPIOPadConfigSet(GPIO_PORTE_BASE, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+}
+
+
+
+// Function initializes the corresponding port F
+
+/* function initializes the corresponding port with all functionalities needed*/
+
+void PORTF_init()
+{
+  SysCtlPeripheralEnable(SYSCTL_PERIPH_GPIOF);
+  while(!SysCtlPeripheralReady(SYSCTL_PERIPH_GPIOF)){ }
+  HWREG(GPIO_PORTF_BASE + GPIO_O_LOCK) = GPIO_LOCK_KEY;
+ HWREG(GPIO_PORTF_BASE + GPIO_O_CR) |=  GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4
+                                      | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7;
+ GPIOPinTypeGPIOInput(GPIO_PORTF_BASE,
+    GPIO_PIN_0 | GPIO_PIN_4);
+ GPIOPinTypeGPIOOutput(GPIO_PORTF_BASE,GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7);
+ GPIOPadConfigSet(GPIO_PORTF_BASE, GPIO_PIN_0 | GPIO_PIN_1| GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7, GPIO_STRENGTH_2MA, GPIO_PIN_TYPE_STD_WPU); 
+  
+  // **GPIO interrupt** 
+  GPIOIntRegister(GPIO_PORTF_BASE, switch_handler); 
+  GPIOIntEnable(GPIO_PORTF_BASE, GPIO_INT_PIN_0 | GPIO_INT_PIN_4);
+  // NVIC interrupt 
+  IntEnable(INT_GPIOF_TM4C123);
+  // CPU interrupt
+  IntMasterEnable();
+  
+
+}
+
+//This function check which switch has created the interruput
+
+/*This function check which switch has created the interrupt and move to the corresponding handler.*/
+void switch_handler()
+{
+   GPIOIntClear(GPIO_PORTF_BASE, GPIO_INT_PIN_0 | GPIO_INT_PIN_4);
+   Delay(DELAY_DEBOUNCE);
+   if (GPIOPinRead(GPIO_PORTF_BASE, (GPIO_PIN_0)) == 0) {
+    switch1_handler();
+  }
+  else if (GPIOPinRead(GPIO_PORTF_BASE, (GPIO_PIN_4)) == 0) {
+    switch2_handler();
+  }
+  else if (GPIOPinRead(GPIO_PORTF_BASE, (GPIO_PIN_0)) == 0 && GPIOPinRead(GPIO_PORTF_BASE, (GPIO_PIN_4)) == 0)
+  {
+	 next_state = GREEN_ps_1; 
+	 next_state_2 = GREEN_ps_2;
+	 switch1_handler();
+	 switch2_handler();
+	 
+  }
+}
+
+//function stores the elapsed time from the corresponding timer and calls its corresponding handler.
+void switch1_handler()
+{
+	elapsed_time_1 = TimerValueGet(TIMER0_BASE, TIMER_A);
+	next_state = GREEN_ps_1;
+	Timer0_handler();
+}
+
+//function stores the elapsed time from the corresponding timer and calls its corresponding handler.
+void switch2_handler()
+{
+	elapsed_time_2 = TimerValueGet(TIMER1_BASE, TIMER_A);
+	next_state_2 = GREEN_ps_2;
+	Timer1_handler();
+
+}
+
+
+// This function disables timer A 
+void Timer0_dsiable()
+{
+ TimerDisable(TIMER0_BASE, TIMER_BOTH); 
+}
+
+// This function disables timer B
+void Timer1_disable()
+{
+  TimerDisable(TIMER1_BASE, TIMER_BOTH);
+}
+
+
+// This function put the system into the start state
+void Traffic_light_init()
+{
+  
+  GPIOPinWrite(GPIO_PORTD_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_ps_2
+  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_5, GPIO_PIN_5); // RED_ps_1
+  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3); // RED_2
+  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, GPIO_PIN_4); // RED_2
+  Timer0_init(1);
+}
+
+// Convert ticks into time in seconds
+int_32 Ticks_to_time(int_32 elapsed_ticks)
+{
+  return (elapsed_ticks / 16000000);
+}
+
+
+// Delay is used to switch presses check 
+void Delay(unsigned long counter)
+{
+	unsigned long i = 0;
+	for(i = 0; i<counter; i++);	
+}
+
+
+// This function reset traffic light 1
+
+void reset_traffic_1()
+{
+  Timer0_dsiable();
+  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_3, 0); // YELLOW_1
+  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_4, 0); // GREEN_1
+  GPIOPinWrite(GPIO_PORTA_BASE, GPIO_PIN_2, GPIO_PIN_2); // RED_1
+}
+
+// This function reset traffic light 2
+
+void reset_traffic_2()
+{
+  Timer1_disable();
+  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_2, 0); // YELLOW_2
+  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_0, 0); // GREEN_2
+  GPIOPinWrite(GPIO_PORTE_BASE, GPIO_PIN_3, GPIO_PIN_3); // RED_2
+}
+
diff --git a/Traffic_light.h b/Traffic_light.h
new file mode 100644
index 0000000..bc38e49
--- /dev/null
+++ b/Traffic_light.h
@@ -0,0 +1,68 @@
+#include "types.h" // defined types from labs 
+
+// State definitions for each traffic light and pedstrains 
+
+// Traffic_light_1
+#define GREEN_1 0
+#define YELLOW_1 1
+#define RED_1 2 
+// Traffic_light_2/
+#define GREEN_2 3
+#define YELLOW_2 4
+#define RED_2 5 
+// WAIT states
+#define WAIT_1 6
+#define WAIT_2 7
+// Pedstrain 1
+#define GREEN_ps_1 8
+#define RED_ps_1 9
+#define IDLE 10
+// Pedstrain 2
+#define GREEN_ps_2 11
+#define RED_ps_2 12
+
+// 
+//#define PRESSED 20 
+//#define NOTPRESSED 21
+
+// delay for swithc press
+# define SYSTEM_CLOC_FREQUENCY  80000000
+#define DELAY_DEBOUNCE SYSTEM_CLOC_FREQUENCY/100
+
+// Port inizialization 
+void PORTA_init();
+void PORTB_init();
+void PORTC_init(); 
+void PORTD_init(); 
+void PORTE_init();
+void PORTF_init(); 
+
+// inizilize traffic light 
+void Traffic_light_init(); 
+
+// switch presses handlers 
+void switch1_handler();
+void switch2_handler();
+void switch_handler();
+
+// Timer inizializatio 
+void Timer0_init(int_32 time);
+void Timer1_init(int_32 time);
+
+// Timer handlers
+void Timer0_handler(); 
+void Timer1_handler(); 
+void Timer0_dsiable();
+void Timer1_disable(); 
+
+// Delay for switch presses check 
+void Delay();
+
+// Traffic lights reset 
+void reset_traffic_1();
+void reset_traffic_2();
+
+// Convert ticks into time in seconds 
+int_32 Ticks_to_time(int_32 time);
+
+
diff --git a/TrafficlightV2.eww b/TrafficlightV2.eww
new file mode 100644
index 0000000..95fdfea
--- /dev/null
+++ b/TrafficlightV2.eww
@@ -0,0 +1,7 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<workspace>
+    <project>
+        <path>G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\TrafficLight.ewp</path>
+    </project>
+    <batchBuild />
+</workspace>
diff --git a/main.c b/main.c
new file mode 100644
index 0000000..3ecc2ed
--- /dev/null
+++ b/main.c
@@ -0,0 +1,26 @@
+#include "Traffic_light.h"
+
+// global variables 
+
+int_32 next_state = GREEN_1; // Traffic light 1 state 
+int_32 next_state_2 = RED_2; // Traffic light 2 state 
+int_32 next_state_ps = GREEN_ps_1; // Pedstrain 1 state
+int_32 elapsed_time_1 = 0; // Elapsed time Green in traffic light 1
+int_32 elapsed_time_2 = 0; // Elapsed time Green in traffic light 2
+int main()
+{
+  // Port inizialization 
+  PORTA_init();
+  PORTC_init();
+  PORTE_init();
+  PORTF_init();
+  PORTD_init();
+  // Timer inizialization 
+  Timer0_init(1);
+  // START
+  Traffic_light_init();
+  while(1)
+  {
+	SysCtlSleep(); //Sleep
+  }
+}
diff --git a/settings/TrafficLight.Debug.cspy.bat b/settings/TrafficLight.Debug.cspy.bat
new file mode 100644
index 0000000..a298534
--- /dev/null
+++ b/settings/TrafficLight.Debug.cspy.bat
@@ -0,0 +1,40 @@
+@REM This batch file has been generated by the IAR Embedded Workbench
+@REM C-SPY Debugger, as an aid to preparing a command line for running
+@REM the cspybat command line utility using the appropriate settings.
+@REM
+@REM Note that this file is generated every time a new debug session
+@REM is initialized, so you may want to move or rename the file before
+@REM making changes.
+@REM
+@REM You can launch cspybat by typing the name of this batch file followed
+@REM by the name of the debug file (usually an ELF/DWARF or UBROF file).
+@REM
+@REM Read about available command line parameters in the C-SPY Debugging
+@REM Guide. Hints about additional command line parameters that may be
+@REM useful in specific cases:
+@REM   --download_only   Downloads a code image without starting a debug
+@REM                     session afterwards.
+@REM   --silent          Omits the sign-on message.
+@REM   --timeout         Limits the maximum allowed execution time.
+@REM 
+
+
+@echo off 
+
+if not "%~1" == "" goto debugFile 
+
+@echo on 
+
+"C:\Program Files\IAR Systems\Embedded Workbench 9.0\common\bin\cspybat" -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.general.xcl" --backend -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.driver.xcl" 
+
+@echo off 
+goto end 
+
+:debugFile 
+
+@echo on 
+
+"C:\Program Files\IAR Systems\Embedded Workbench 9.0\common\bin\cspybat" -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.general.xcl" "--debug_file=%~1" --backend -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.driver.xcl" 
+
+@echo off 
+:end
\ No newline at end of file
diff --git a/settings/TrafficLight.Debug.cspy.ps1 b/settings/TrafficLight.Debug.cspy.ps1
new file mode 100644
index 0000000..fb5f47e
--- /dev/null
+++ b/settings/TrafficLight.Debug.cspy.ps1
@@ -0,0 +1,31 @@
+param([String]$debugfile = "");
+
+# This powershell file has been generated by the IAR Embedded Workbench
+# C - SPY Debugger, as an aid to preparing a command line for running
+# the cspybat command line utility using the appropriate settings.
+#
+# Note that this file is generated every time a new debug session
+# is initialized, so you may want to move or rename the file before
+# making changes.
+#
+# You can launch cspybat by typing Powershell.exe -File followed by the name of this batch file, followed
+# by the name of the debug file (usually an ELF / DWARF or UBROF file).
+#
+# Read about available command line parameters in the C - SPY Debugging
+# Guide. Hints about additional command line parameters that may be
+# useful in specific cases :
+#   --download_only   Downloads a code image without starting a debug
+#                     session afterwards.
+#   --silent          Omits the sign - on message.
+#   --timeout         Limits the maximum allowed execution time.
+#
+
+
+if ($debugfile -eq "")
+{
+& "C:\Program Files\IAR Systems\Embedded Workbench 9.0\common\bin\cspybat" -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.general.xcl" --backend -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.driver.xcl" 
+}
+else
+{
+& "C:\Program Files\IAR Systems\Embedded Workbench 9.0\common\bin\cspybat" -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.general.xcl" --debug_file=$debugfile --backend -f "G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\settings\TrafficLight.Debug.driver.xcl" 
+}
diff --git a/settings/TrafficLight.Debug.driver.xcl b/settings/TrafficLight.Debug.driver.xcl
new file mode 100644
index 0000000..b3d4df8
--- /dev/null
+++ b/settings/TrafficLight.Debug.driver.xcl
@@ -0,0 +1,23 @@
+"--endian=little" 
+
+"--cpu=Cortex-M4" 
+
+"--fpu=VFPv4_SP" 
+
+"-p" 
+
+"C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf" 
+
+"--semihosting" 
+
+"--device=TM4C123GH6PM" 
+
+"--drv_interface_speed=500" 
+
+"--drv_interface=SWD" 
+
+"--lmiftdi_reset_strategy=0,0" 
+
+
+
+
diff --git a/settings/TrafficLight.Debug.general.xcl b/settings/TrafficLight.Debug.general.xcl
new file mode 100644
index 0000000..fe74485
--- /dev/null
+++ b/settings/TrafficLight.Debug.general.xcl
@@ -0,0 +1,15 @@
+"C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armPROC.dll" 
+
+"C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armLMIFTDI.dll" 
+
+"G:\Semester 7\Embedded\FinalProject\CESS_Team4_Trafficlight\Debug\Exe\TrafficLight.out" 
+
+--plugin="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\bin\armbat.dll" 
+
+--device_macro="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\config\debugger\TexasInstruments\TM4C123.dmac" 
+
+--flash_loader="C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\config\flashloader\TexasInstruments\FlashTC4_H6_o.board" 
+
+
+
+
diff --git a/settings/TrafficLight.crun b/settings/TrafficLight.crun
new file mode 100644
index 0000000..d71ea55
--- /dev/null
+++ b/settings/TrafficLight.crun
@@ -0,0 +1,13 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<crun>
+    <version>1</version>
+    <filter_entries>
+        <filter index="0" type="default">
+            <type>*</type>
+            <start_file>*</start_file>
+            <end_file>*</end_file>
+            <action_debugger>0</action_debugger>
+            <action_log>1</action_log>
+        </filter>
+    </filter_entries>
+</crun>
diff --git a/settings/TrafficLight.dbgdt b/settings/TrafficLight.dbgdt
new file mode 100644
index 0000000..405024e
--- /dev/null
+++ b/settings/TrafficLight.dbgdt
@@ -0,0 +1,1022 @@
+<?xml version="1.0"?>
+<Project>
+    <WindowStorage>
+        <ChildIdMap>
+            <TB_CMSISPACK>34048</TB_CMSISPACK>
+            <TB_DEBUG>34049</TB_DEBUG>
+            <TB_MAIN2>34050</TB_MAIN2>
+            <WIN_AUTO>34051</WIN_AUTO>
+            <WIN_BREAKPOINTS>34052</WIN_BREAKPOINTS>
+            <WIN_BUILD>34053</WIN_BUILD>
+            <WIN_CALL_GRAPH>34054</WIN_CALL_GRAPH>
+            <WIN_CALL_STACK>34055</WIN_CALL_STACK>
+            <WIN_CORES>34056</WIN_CORES>
+            <WIN_CUSTOM_SFR>34057</WIN_CUSTOM_SFR>
+            <WIN_C_STAT>34058</WIN_C_STAT>
+            <WIN_DEBUGGER_MACROS>34059</WIN_DEBUGGER_MACROS>
+            <WIN_DEBUG_LOG>34060</WIN_DEBUG_LOG>
+            <WIN_DISASSEMBLY>34061</WIN_DISASSEMBLY>
+            <WIN_EXCEPTION_VIEWER>34062</WIN_EXCEPTION_VIEWER>
+            <WIN_EXTRA_TRACE>34063</WIN_EXTRA_TRACE>
+            <WIN_FIND_ALL_DECLARATIONS>34064</WIN_FIND_ALL_DECLARATIONS>
+            <WIN_FIND_ALL_REFERENCES>34065</WIN_FIND_ALL_REFERENCES>
+            <WIN_FIND_IN_FILES>34066</WIN_FIND_IN_FILES>
+            <WIN_FIND_IN_SLIDING_TRACE>34067</WIN_FIND_IN_SLIDING_TRACE>
+            <WIN_FIND_IN_TRACE_EXTRA>34068</WIN_FIND_IN_TRACE_EXTRA>
+            <WIN_IMAGES>34069</WIN_IMAGES>
+            <WIN_LOCALS>34070</WIN_LOCALS>
+            <WIN_MACRO_EVAL>34071</WIN_MACRO_EVAL>
+            <WIN_MACRO_REGISTRATION>34072</WIN_MACRO_REGISTRATION>
+            <WIN_MEMORY_1>34073</WIN_MEMORY_1>
+            <WIN_MEMORY_2>34074</WIN_MEMORY_2>
+            <WIN_MEMORY_3>34075</WIN_MEMORY_3>
+            <WIN_MEMORY_4>34076</WIN_MEMORY_4>
+            <WIN_PHYSICAL_BREAKPOINTS>34077</WIN_PHYSICAL_BREAKPOINTS>
+            <WIN_QUICK_WATCH>34078</WIN_QUICK_WATCH>
+            <WIN_REGISTER_1>34079</WIN_REGISTER_1>
+            <WIN_REGISTER_2>34080</WIN_REGISTER_2>
+            <WIN_REGISTER_3>34081</WIN_REGISTER_3>
+            <WIN_REGISTER_4>34082</WIN_REGISTER_4>
+            <WIN_REGISTER_GROUPS>34083</WIN_REGISTER_GROUPS>
+            <WIN_SELECT_AMBIGUOUS_DEFINITIONS>34084</WIN_SELECT_AMBIGUOUS_DEFINITIONS>
+            <WIN_SLIDING_FUNCTION_TRACE>34085</WIN_SLIDING_FUNCTION_TRACE>
+            <WIN_SLIDING_TRACE_WINDOW>34086</WIN_SLIDING_TRACE_WINDOW>
+            <WIN_SOURCEBROWSE_LOG>34087</WIN_SOURCEBROWSE_LOG>
+            <WIN_SOURCE_BROWSE2>34088</WIN_SOURCE_BROWSE2>
+            <WIN_STACK_1>34089</WIN_STACK_1>
+            <WIN_STACK_2>34090</WIN_STACK_2>
+            <WIN_STATICS>34091</WIN_STATICS>
+            <WIN_STATIC_WATCH>34092</WIN_STATIC_WATCH>
+            <WIN_SYMBOLIC_MEMORY>34093</WIN_SYMBOLIC_MEMORY>
+            <WIN_SYMBOLS>34094</WIN_SYMBOLS>
+            <WIN_TERM_IO>34095</WIN_TERM_IO>
+            <WIN_TOOL_OUTPUT>34096</WIN_TOOL_OUTPUT>
+            <WIN_WATCH_1>34097</WIN_WATCH_1>
+            <WIN_WATCH_2>34098</WIN_WATCH_2>
+            <WIN_WATCH_3>34099</WIN_WATCH_3>
+            <WIN_WATCH_4>34100</WIN_WATCH_4>
+            <WIN_WORKSPACE>34101</WIN_WORKSPACE>
+        </ChildIdMap>
+        <Desktop>
+            <IarPane-34048>
+                <ToolBarCmdIds>
+                    <item>34001</item>
+                    <item>0</item>
+                </ToolBarCmdIds>
+            </IarPane-34048>
+            <IarPane-34049>
+                <ToolBarCmdIds>
+                    <item>34390</item>
+                    <item>34323</item>
+                    <item>34398</item>
+                    <item>34400</item>
+                    <item>34397</item>
+                    <item>34320</item>
+                    <item>34321</item>
+                    <item>34324</item>
+                    <item>0</item>
+                </ToolBarCmdIds>
+            </IarPane-34049>
+            <IarPane-34050>
+                <ToolBarCmdIds>
+                    <item>57600</item>
+                    <item>57601</item>
+                    <item>57603</item>
+                    <item>33024</item>
+                    <item>0</item>
+                    <item>57607</item>
+                    <item>0</item>
+                    <item>57635</item>
+                    <item>57634</item>
+                    <item>57637</item>
+                    <item>0</item>
+                    <item>57643</item>
+                    <item>57644</item>
+                    <item>0</item>
+                    <item>33090</item>
+                    <item>33057</item>
+                    <item>57636</item>
+                    <item>57640</item>
+                    <item>57641</item>
+                    <item>33026</item>
+                    <item>33065</item>
+                    <item>33063</item>
+                    <item>33064</item>
+                    <item>33053</item>
+                    <item>33054</item>
+                    <item>0</item>
+                    <item>33035</item>
+                    <item>33036</item>
+                    <item>34399</item>
+                    <item>0</item>
+                    <item>33055</item>
+                    <item>33056</item>
+                    <item>33094</item>
+                    <item>0</item>
+                </ToolBarCmdIds>
+            </IarPane-34050>
+            <IarPane-34061>
+                <kDisasmGotoHistoryKey />
+                <col-names>
+                    <item>Disassembly</item>
+                    <item>_I0</item>
+                </col-names>
+                <col-widths>
+                    <item>500</item>
+                    <item>20</item>
+                </col-widths>
+                <ShowCodeCoverage>1</ShowCodeCoverage>
+                <ShowInstrProfiling>1</ShowInstrProfiling>
+            </IarPane-34061>
+            <ControlBarVersion>
+                <Major>14</Major>
+                <Minor>29</Minor>
+            </ControlBarVersion>
+            <MFCToolBarParameters>
+                <Tooltips>1</Tooltips>
+                <ShortcutKeys>1</ShortcutKeys>
+                <LargeIcons>0</LargeIcons>
+                <MenuAnimation>0</MenuAnimation>
+                <RecentlyUsedMenus>1</RecentlyUsedMenus>
+                <MenuShadows>1</MenuShadows>
+                <ShowAllMenusAfterDelay>1</ShowAllMenusAfterDelay>
+                <CommandsUsage>910300001800138600000D00000010860000F40000000F810000010000002081000001000000A6800000020000000D800000010000000C81000002000000568600008A00000000840000010000000E84000003000000AB800000010000000E8100000E0000001F8100007A0000005E860000070000000B8100000100000014860000EA00000002840000010000002187000001000000118600008D000000468100001B000000AA800000010000005D86000001000000A780000001000000A480000001000000</CommandsUsage>
+            </MFCToolBarParameters>
+            <CommandManager>
+                <CommandsWithoutImages>2A00208700002187000019860000FFFFFFFF9C800000A1800000A2800000A3800000A4800000A5800000AF800000B2800000B3800000B7800000B8800000B9800000BA80000005DC0000AA800000AB800000AC800000AD800000AE800000A6800000A7800000A8800000A98000009D8000009E8000009F800000A08000001B8600001C8600001D8600001E8600005A8600005B86000053860000A4860000A38600007886000079860000</CommandsWithoutImages>
+                <MenuUserImages>1500158100004D000000239200000000000007E100006100000029E100006700000004E100005F0000000D8000003D00000001E100005C000000178100004F000000008400006E000000148100004C000000008100004200000003E100005E00000025E100006500000000E100005B00000022E100006200000041E100006B000000168100004E000000518400007C00000005E100006000000002E100005D00000024E1000064000000</MenuUserImages>
+            </CommandManager>
+            <Pane-59393>
+                <ID>0</ID>
+                <RectRecentFloat>0A0000000A0000006E0000006E000000</RectRecentFloat>
+                <RectRecentDocked>00000000D602000056050000E9020000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-59393>
+            <BasePane-59393>
+                <IsVisible>1</IsVisible>
+            </BasePane-59393>
+            <Pane--1>
+                <ID>4294967295</ID>
+                <RectRecentFloat>400100008601000065030000C8010000</RectRecentFloat>
+                <RectRecentDocked>400100006F01000065030000B1010000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane--1>
+            <BasePane--1>
+                <IsVisible>0</IsVisible>
+            </BasePane--1>
+            <Pane-34051>
+                <ID>34051</ID>
+                <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
+                <RectRecentDocked>540400004A00000052050000BC020000</RectRecentDocked>
+                <RecentFrameAlignment>16384</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34051>
+            <BasePane-34051>
+                <IsVisible>0</IsVisible>
+            </BasePane-34051>
+            <IarPane-34051 />
+            <Pane-34070>
+                <ID>34070</ID>
+                <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
+                <RectRecentDocked>540400004A00000052050000BC020000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34070>
+            <BasePane-34070>
+                <IsVisible>0</IsVisible>
+            </BasePane-34070>
+            <IarPane-34070>
+                <col-names>
+                    <item>Location</item>
+                    <item>Type</item>
+                    <item>Value</item>
+                    <item>Variable</item>
+                </col-names>
+                <col-widths>
+                    <item>150</item>
+                    <item>100</item>
+                    <item>100</item>
+                    <item>100</item>
+                </col-widths>
+                <right_justify>0</right_justify>
+            </IarPane-34070>
+            <Pane-34092>
+                <ID>34092</ID>
+                <RectRecentFloat>00000000170000000601000078010000</RectRecentFloat>
+                <RectRecentDocked>540400004A00000052050000BC020000</RectRecentDocked>
+                <RecentFrameAlignment>4096</RecentFrameAlignment>
+                <RecentRowIndex>0</RecentRowIndex>
+                <IsFloating>0</IsFloating>
+                <MRUWidth>32767</MRUWidth>
+                <PinState>0</PinState>
+            </Pane-34092>
+            <BasePane-34092>
+                <IsVisible>0</IsVisible>
+            </BasePane-34092>
+            <IarPane-34092 />
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diff --git a/settings/TrafficLight.dnx b/settings/TrafficLight.dnx
new file mode 100644
index 0000000..767582a
--- /dev/null
+++ b/settings/TrafficLight.dnx
@@ -0,0 +1,108 @@
+<?xml version="1.0"?>
+<settings>
+    <InterruptLog>
+        <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
+        <SumEnabled>0</SumEnabled>
+        <ShowTimeSum>1</ShowTimeSum>
+        <SumSortOrder>0</SumSortOrder>
+    </InterruptLog>
+    <DataLog>
+        <GraphEnabled>0</GraphEnabled>
+        <LogEnabled>0</LogEnabled>
+        <ShowTimeLog>1</ShowTimeLog>
+        <SumEnabled>0</SumEnabled>
+        <ShowTimeSum>1</ShowTimeSum>
+    </DataLog>
+    <Stack>
+        <FillEnabled>0</FillEnabled>
+        <OverflowWarningsEnabled>1</OverflowWarningsEnabled>
+        <WarningThreshold>90</WarningThreshold>
+        <SpWarningsEnabled>1</SpWarningsEnabled>
+        <WarnLogOnly>1</WarnLogOnly>
+        <UseTrigger>1</UseTrigger>
+        <TriggerName>main</TriggerName>
+        <LimitSize>0</LimitSize>
+        <ByteLimit>50</ByteLimit>
+    </Stack>
+    <Interrupts>
+        <Enabled>1</Enabled>
+    </Interrupts>
+    <MemConfig>
+        <Base>1</Base>
+        <Manual>0</Manual>
+        <Ddf>1</Ddf>
+        <TypeViol>0</TypeViol>
+        <Stop>1</Stop>
+    </MemConfig>
+    <Trace1>
+        <Enabled>0</Enabled>
+        <ShowSource>1</ShowSource>
+    </Trace1>
+    <Simulator>
+        <Freq>10000000</Freq>
+        <FreqHi>0</FreqHi>
+        <MultiCoreRunAll>1</MultiCoreRunAll>
+    </Simulator>
+    <PlDriver>
+        <FirstRun>0</FirstRun>
+        <MemConfigValue>C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\CONFIG\debugger\TexasInstruments\TM4C123GH6PM.ddf</MemConfigValue>
+    </PlDriver>
+    <ArmDriver>
+        <EnableCache>0</EnableCache>
+    </ArmDriver>
+    <LmiFtdiDriver>
+        <LMIFTDIserialNo>0E233CF3</LMIFTDIserialNo>
+        <LMIFTDIfoundProbes />
+        <LmiFtdiResetStyle>1</LmiFtdiResetStyle>
+        <LmiFtdiResetStrategy>0</LmiFtdiResetStrategy>
+        <LeaveTargetRunning>_ 0</LeaveTargetRunning>
+        <CStepIntDis>_ 0</CStepIntDis>
+    </LmiFtdiDriver>
+    <DebugChecksum>
+        <Checksum>321248604</Checksum>
+    </DebugChecksum>
+    <Exceptions>
+        <StopOnUncaught>_ 0</StopOnUncaught>
+        <StopOnThrow>_ 0</StopOnThrow>
+    </Exceptions>
+    <Disassembly>
+        <MixedMode>1</MixedMode>
+    </Disassembly>
+    <CallStack>
+        <ShowArgs>1</ShowArgs>
+    </CallStack>
+    <Trace2>
+        <Enabled>0</Enabled>
+        <ShowSource>0</ShowSource>
+    </Trace2>
+    <TermIOLog>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+    </TermIOLog>
+    <LogFile>
+        <LoggingEnabled>_ 0</LoggingEnabled>
+        <LogFile>_ ""</LogFile>
+        <Category>_ 0</Category>
+    </LogFile>
+    <CallStackLog>
+        <Enabled>0</Enabled>
+    </CallStackLog>
+    <CallStackStripe>
+        <ShowTiming>1</ShowTiming>
+    </CallStackStripe>
+    <DisassembleMode>
+        <mode>0</mode>
+    </DisassembleMode>
+    <Breakpoints2>
+        <Count>0</Count>
+    </Breakpoints2>
+    <Aliases>
+        <A0>_ "C:\Jenkins\workspace\TivaWare-Git-Release\DriverLib\build\DriverLib.test\driverlib\cpu.c" ""</A0>
+        <A1>_ "C:\Jenkins\workspace\TivaWare-Git-Release\DriverLib\build\DriverLib.test\driverlib\gpio.c" ""</A1>
+        <A2>_ "C:\Jenkins\workspace\TivaWare-Git-Release\DriverLib\build\DriverLib.test\driverlib\sysctl.c" ""</A2>
+        <Count>3</Count>
+        <SuppressDialog>0</SuppressDialog>
+    </Aliases>
+</settings>
diff --git a/settings/TrafficLight.reggroups b/settings/TrafficLight.reggroups
new file mode 100644
index 0000000..5f28270
--- /dev/null
+++ b/settings/TrafficLight.reggroups
@@ -0,0 +1 @@
+
\ No newline at end of file
diff --git a/tm4c123gh6pm.h b/tm4c123gh6pm.h
new file mode 100644
index 0000000..6cec6f0
--- /dev/null
+++ b/tm4c123gh6pm.h
@@ -0,0 +1,12867 @@
+//*****************************************************************************
+//
+// tm4c123gh6pm.h - TM4C123GH6PM Register Definitions
+//
+// Copyright (c) 2013-2017 Texas Instruments Incorporated.  All rights reserved.
+// Software License Agreement
+// 
+//   Redistribution and use in source and binary forms, with or without
+//   modification, are permitted provided that the following conditions
+//   are met:
+// 
+//   Redistributions of source code must retain the above copyright
+//   notice, this list of conditions and the following disclaimer.
+// 
+//   Redistributions in binary form must reproduce the above copyright
+//   notice, this list of conditions and the following disclaimer in the
+//   documentation and/or other materials provided with the  
+//   distribution.
+// 
+//   Neither the name of Texas Instruments Incorporated nor the names of
+//   its contributors may be used to endorse or promote products derived
+//   from this software without specific prior written permission.
+// 
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// 
+// This is part of revision 2.1.4.178 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __TM4C123GH6PM_H__
+#define __TM4C123GH6PM_H__
+
+//*****************************************************************************
+//
+// Interrupt assignments
+//
+//*****************************************************************************
+#define INT_GPIOA               16          // GPIO Port A
+#define INT_GPIOB               17          // GPIO Port B
+#define INT_GPIOC               18          // GPIO Port C
+#define INT_GPIOD               19          // GPIO Port D
+#define INT_GPIOE               20          // GPIO Port E
+#define INT_UART0               21          // UART0
+#define INT_UART1               22          // UART1
+#define INT_SSI0                23          // SSI0
+#define INT_I2C0                24          // I2C0
+#define INT_PWM0_FAULT          25          // PWM0 Fault
+#define INT_PWM0_0              26          // PWM0 Generator 0
+#define INT_PWM0_1              27          // PWM0 Generator 1
+#define INT_PWM0_2              28          // PWM0 Generator 2
+#define INT_QEI0                29          // QEI0
+#define INT_ADC0SS0             30          // ADC0 Sequence 0
+#define INT_ADC0SS1             31          // ADC0 Sequence 1
+#define INT_ADC0SS2             32          // ADC0 Sequence 2
+#define INT_ADC0SS3             33          // ADC0 Sequence 3
+#define INT_WATCHDOG            34          // Watchdog Timers 0 and 1
+#define INT_TIMER0A             35          // 16/32-Bit Timer 0A
+#define INT_TIMER0B             36          // 16/32-Bit Timer 0B
+#define INT_TIMER1A             37          // 16/32-Bit Timer 1A
+#define INT_TIMER1B             38          // 16/32-Bit Timer 1B
+#define INT_TIMER2A             39          // 16/32-Bit Timer 2A
+#define INT_TIMER2B             40          // 16/32-Bit Timer 2B
+#define INT_COMP0               41          // Analog Comparator 0
+#define INT_COMP1               42          // Analog Comparator 1
+#define INT_SYSCTL              44          // System Control
+#define INT_FLASH               45          // Flash Memory Control and EEPROM
+                                            // Control
+#define INT_GPIOF               46          // GPIO Port F
+#define INT_UART2               49          // UART2
+#define INT_SSI1                50          // SSI1
+#define INT_TIMER3A             51          // 16/32-Bit Timer 3A
+#define INT_TIMER3B             52          // Timer 3B
+#define INT_I2C1                53          // I2C1
+#define INT_QEI1                54          // QEI1
+#define INT_CAN0                55          // CAN0
+#define INT_CAN1                56          // CAN1
+#define INT_HIBERNATE           59          // Hibernation Module
+#define INT_USB0                60          // USB
+#define INT_PWM0_3              61          // PWM Generator 3
+#define INT_UDMA                62          // uDMA Software
+#define INT_UDMAERR             63          // uDMA Error
+#define INT_ADC1SS0             64          // ADC1 Sequence 0
+#define INT_ADC1SS1             65          // ADC1 Sequence 1
+#define INT_ADC1SS2             66          // ADC1 Sequence 2
+#define INT_ADC1SS3             67          // ADC1 Sequence 3
+#define INT_SSI2                73          // SSI2
+#define INT_SSI3                74          // SSI3
+#define INT_UART3               75          // UART3
+#define INT_UART4               76          // UART4
+#define INT_UART5               77          // UART5
+#define INT_UART6               78          // UART6
+#define INT_UART7               79          // UART7
+#define INT_I2C2                84          // I2C2
+#define INT_I2C3                85          // I2C3
+#define INT_TIMER4A             86          // 16/32-Bit Timer 4A
+#define INT_TIMER4B             87          // 16/32-Bit Timer 4B
+#define INT_TIMER5A             108         // 16/32-Bit Timer 5A
+#define INT_TIMER5B             109         // 16/32-Bit Timer 5B
+#define INT_WTIMER0A            110         // 32/64-Bit Timer 0A
+#define INT_WTIMER0B            111         // 32/64-Bit Timer 0B
+#define INT_WTIMER1A            112         // 32/64-Bit Timer 1A
+#define INT_WTIMER1B            113         // 32/64-Bit Timer 1B
+#define INT_WTIMER2A            114         // 32/64-Bit Timer 2A
+#define INT_WTIMER2B            115         // 32/64-Bit Timer 2B
+#define INT_WTIMER3A            116         // 32/64-Bit Timer 3A
+#define INT_WTIMER3B            117         // 32/64-Bit Timer 3B
+#define INT_WTIMER4A            118         // 32/64-Bit Timer 4A
+#define INT_WTIMER4B            119         // 32/64-Bit Timer 4B
+#define INT_WTIMER5A            120         // 32/64-Bit Timer 5A
+#define INT_WTIMER5B            121         // 32/64-Bit Timer 5B
+#define INT_SYSEXC              122         // System Exception (imprecise)
+#define INT_PWM1_0              150         // PWM1 Generator 0
+#define INT_PWM1_1              151         // PWM1 Generator 1
+#define INT_PWM1_2              152         // PWM1 Generator 2
+#define INT_PWM1_3              153         // PWM1 Generator 3
+#define INT_PWM1_FAULT          154         // PWM1 Fault
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG0)
+//
+//*****************************************************************************
+#define WATCHDOG0_LOAD_R        (*((volatile uint32_t *)0x40000000))
+#define WATCHDOG0_VALUE_R       (*((volatile uint32_t *)0x40000004))
+#define WATCHDOG0_CTL_R         (*((volatile uint32_t *)0x40000008))
+#define WATCHDOG0_ICR_R         (*((volatile uint32_t *)0x4000000C))
+#define WATCHDOG0_RIS_R         (*((volatile uint32_t *)0x40000010))
+#define WATCHDOG0_MIS_R         (*((volatile uint32_t *)0x40000014))
+#define WATCHDOG0_TEST_R        (*((volatile uint32_t *)0x40000418))
+#define WATCHDOG0_LOCK_R        (*((volatile uint32_t *)0x40000C00))
+
+//*****************************************************************************
+//
+// Watchdog Timer registers (WATCHDOG1)
+//
+//*****************************************************************************
+#define WATCHDOG1_LOAD_R        (*((volatile uint32_t *)0x40001000))
+#define WATCHDOG1_VALUE_R       (*((volatile uint32_t *)0x40001004))
+#define WATCHDOG1_CTL_R         (*((volatile uint32_t *)0x40001008))
+#define WATCHDOG1_ICR_R         (*((volatile uint32_t *)0x4000100C))
+#define WATCHDOG1_RIS_R         (*((volatile uint32_t *)0x40001010))
+#define WATCHDOG1_MIS_R         (*((volatile uint32_t *)0x40001014))
+#define WATCHDOG1_TEST_R        (*((volatile uint32_t *)0x40001418))
+#define WATCHDOG1_LOCK_R        (*((volatile uint32_t *)0x40001C00))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA)
+//
+//*****************************************************************************
+#define GPIO_PORTA_DATA_BITS_R  ((volatile uint32_t *)0x40004000)
+#define GPIO_PORTA_DATA_R       (*((volatile uint32_t *)0x400043FC))
+#define GPIO_PORTA_DIR_R        (*((volatile uint32_t *)0x40004400))
+#define GPIO_PORTA_IS_R         (*((volatile uint32_t *)0x40004404))
+#define GPIO_PORTA_IBE_R        (*((volatile uint32_t *)0x40004408))
+#define GPIO_PORTA_IEV_R        (*((volatile uint32_t *)0x4000440C))
+#define GPIO_PORTA_IM_R         (*((volatile uint32_t *)0x40004410))
+#define GPIO_PORTA_RIS_R        (*((volatile uint32_t *)0x40004414))
+#define GPIO_PORTA_MIS_R        (*((volatile uint32_t *)0x40004418))
+#define GPIO_PORTA_ICR_R        (*((volatile uint32_t *)0x4000441C))
+#define GPIO_PORTA_AFSEL_R      (*((volatile uint32_t *)0x40004420))
+#define GPIO_PORTA_DR2R_R       (*((volatile uint32_t *)0x40004500))
+#define GPIO_PORTA_DR4R_R       (*((volatile uint32_t *)0x40004504))
+#define GPIO_PORTA_DR8R_R       (*((volatile uint32_t *)0x40004508))
+#define GPIO_PORTA_ODR_R        (*((volatile uint32_t *)0x4000450C))
+#define GPIO_PORTA_PUR_R        (*((volatile uint32_t *)0x40004510))
+#define GPIO_PORTA_PDR_R        (*((volatile uint32_t *)0x40004514))
+#define GPIO_PORTA_SLR_R        (*((volatile uint32_t *)0x40004518))
+#define GPIO_PORTA_DEN_R        (*((volatile uint32_t *)0x4000451C))
+#define GPIO_PORTA_LOCK_R       (*((volatile uint32_t *)0x40004520))
+#define GPIO_PORTA_CR_R         (*((volatile uint32_t *)0x40004524))
+#define GPIO_PORTA_AMSEL_R      (*((volatile uint32_t *)0x40004528))
+#define GPIO_PORTA_PCTL_R       (*((volatile uint32_t *)0x4000452C))
+#define GPIO_PORTA_ADCCTL_R     (*((volatile uint32_t *)0x40004530))
+#define GPIO_PORTA_DMACTL_R     (*((volatile uint32_t *)0x40004534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_DATA_BITS_R  ((volatile uint32_t *)0x40005000)
+#define GPIO_PORTB_DATA_R       (*((volatile uint32_t *)0x400053FC))
+#define GPIO_PORTB_DIR_R        (*((volatile uint32_t *)0x40005400))
+#define GPIO_PORTB_IS_R         (*((volatile uint32_t *)0x40005404))
+#define GPIO_PORTB_IBE_R        (*((volatile uint32_t *)0x40005408))
+#define GPIO_PORTB_IEV_R        (*((volatile uint32_t *)0x4000540C))
+#define GPIO_PORTB_IM_R         (*((volatile uint32_t *)0x40005410))
+#define GPIO_PORTB_RIS_R        (*((volatile uint32_t *)0x40005414))
+#define GPIO_PORTB_MIS_R        (*((volatile uint32_t *)0x40005418))
+#define GPIO_PORTB_ICR_R        (*((volatile uint32_t *)0x4000541C))
+#define GPIO_PORTB_AFSEL_R      (*((volatile uint32_t *)0x40005420))
+#define GPIO_PORTB_DR2R_R       (*((volatile uint32_t *)0x40005500))
+#define GPIO_PORTB_DR4R_R       (*((volatile uint32_t *)0x40005504))
+#define GPIO_PORTB_DR8R_R       (*((volatile uint32_t *)0x40005508))
+#define GPIO_PORTB_ODR_R        (*((volatile uint32_t *)0x4000550C))
+#define GPIO_PORTB_PUR_R        (*((volatile uint32_t *)0x40005510))
+#define GPIO_PORTB_PDR_R        (*((volatile uint32_t *)0x40005514))
+#define GPIO_PORTB_SLR_R        (*((volatile uint32_t *)0x40005518))
+#define GPIO_PORTB_DEN_R        (*((volatile uint32_t *)0x4000551C))
+#define GPIO_PORTB_LOCK_R       (*((volatile uint32_t *)0x40005520))
+#define GPIO_PORTB_CR_R         (*((volatile uint32_t *)0x40005524))
+#define GPIO_PORTB_AMSEL_R      (*((volatile uint32_t *)0x40005528))
+#define GPIO_PORTB_PCTL_R       (*((volatile uint32_t *)0x4000552C))
+#define GPIO_PORTB_ADCCTL_R     (*((volatile uint32_t *)0x40005530))
+#define GPIO_PORTB_DMACTL_R     (*((volatile uint32_t *)0x40005534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC)
+//
+//*****************************************************************************
+#define GPIO_PORTC_DATA_BITS_R  ((volatile uint32_t *)0x40006000)
+#define GPIO_PORTC_DATA_R       (*((volatile uint32_t *)0x400063FC))
+#define GPIO_PORTC_DIR_R        (*((volatile uint32_t *)0x40006400))
+#define GPIO_PORTC_IS_R         (*((volatile uint32_t *)0x40006404))
+#define GPIO_PORTC_IBE_R        (*((volatile uint32_t *)0x40006408))
+#define GPIO_PORTC_IEV_R        (*((volatile uint32_t *)0x4000640C))
+#define GPIO_PORTC_IM_R         (*((volatile uint32_t *)0x40006410))
+#define GPIO_PORTC_RIS_R        (*((volatile uint32_t *)0x40006414))
+#define GPIO_PORTC_MIS_R        (*((volatile uint32_t *)0x40006418))
+#define GPIO_PORTC_ICR_R        (*((volatile uint32_t *)0x4000641C))
+#define GPIO_PORTC_AFSEL_R      (*((volatile uint32_t *)0x40006420))
+#define GPIO_PORTC_DR2R_R       (*((volatile uint32_t *)0x40006500))
+#define GPIO_PORTC_DR4R_R       (*((volatile uint32_t *)0x40006504))
+#define GPIO_PORTC_DR8R_R       (*((volatile uint32_t *)0x40006508))
+#define GPIO_PORTC_ODR_R        (*((volatile uint32_t *)0x4000650C))
+#define GPIO_PORTC_PUR_R        (*((volatile uint32_t *)0x40006510))
+#define GPIO_PORTC_PDR_R        (*((volatile uint32_t *)0x40006514))
+#define GPIO_PORTC_SLR_R        (*((volatile uint32_t *)0x40006518))
+#define GPIO_PORTC_DEN_R        (*((volatile uint32_t *)0x4000651C))
+#define GPIO_PORTC_LOCK_R       (*((volatile uint32_t *)0x40006520))
+#define GPIO_PORTC_CR_R         (*((volatile uint32_t *)0x40006524))
+#define GPIO_PORTC_AMSEL_R      (*((volatile uint32_t *)0x40006528))
+#define GPIO_PORTC_PCTL_R       (*((volatile uint32_t *)0x4000652C))
+#define GPIO_PORTC_ADCCTL_R     (*((volatile uint32_t *)0x40006530))
+#define GPIO_PORTC_DMACTL_R     (*((volatile uint32_t *)0x40006534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD)
+//
+//*****************************************************************************
+#define GPIO_PORTD_DATA_BITS_R  ((volatile uint32_t *)0x40007000)
+#define GPIO_PORTD_DATA_R       (*((volatile uint32_t *)0x400073FC))
+#define GPIO_PORTD_DIR_R        (*((volatile uint32_t *)0x40007400))
+#define GPIO_PORTD_IS_R         (*((volatile uint32_t *)0x40007404))
+#define GPIO_PORTD_IBE_R        (*((volatile uint32_t *)0x40007408))
+#define GPIO_PORTD_IEV_R        (*((volatile uint32_t *)0x4000740C))
+#define GPIO_PORTD_IM_R         (*((volatile uint32_t *)0x40007410))
+#define GPIO_PORTD_RIS_R        (*((volatile uint32_t *)0x40007414))
+#define GPIO_PORTD_MIS_R        (*((volatile uint32_t *)0x40007418))
+#define GPIO_PORTD_ICR_R        (*((volatile uint32_t *)0x4000741C))
+#define GPIO_PORTD_AFSEL_R      (*((volatile uint32_t *)0x40007420))
+#define GPIO_PORTD_DR2R_R       (*((volatile uint32_t *)0x40007500))
+#define GPIO_PORTD_DR4R_R       (*((volatile uint32_t *)0x40007504))
+#define GPIO_PORTD_DR8R_R       (*((volatile uint32_t *)0x40007508))
+#define GPIO_PORTD_ODR_R        (*((volatile uint32_t *)0x4000750C))
+#define GPIO_PORTD_PUR_R        (*((volatile uint32_t *)0x40007510))
+#define GPIO_PORTD_PDR_R        (*((volatile uint32_t *)0x40007514))
+#define GPIO_PORTD_SLR_R        (*((volatile uint32_t *)0x40007518))
+#define GPIO_PORTD_DEN_R        (*((volatile uint32_t *)0x4000751C))
+#define GPIO_PORTD_LOCK_R       (*((volatile uint32_t *)0x40007520))
+#define GPIO_PORTD_CR_R         (*((volatile uint32_t *)0x40007524))
+#define GPIO_PORTD_AMSEL_R      (*((volatile uint32_t *)0x40007528))
+#define GPIO_PORTD_PCTL_R       (*((volatile uint32_t *)0x4000752C))
+#define GPIO_PORTD_ADCCTL_R     (*((volatile uint32_t *)0x40007530))
+#define GPIO_PORTD_DMACTL_R     (*((volatile uint32_t *)0x40007534))
+
+//*****************************************************************************
+//
+// SSI registers (SSI0)
+//
+//*****************************************************************************
+#define SSI0_CR0_R              (*((volatile uint32_t *)0x40008000))
+#define SSI0_CR1_R              (*((volatile uint32_t *)0x40008004))
+#define SSI0_DR_R               (*((volatile uint32_t *)0x40008008))
+#define SSI0_SR_R               (*((volatile uint32_t *)0x4000800C))
+#define SSI0_CPSR_R             (*((volatile uint32_t *)0x40008010))
+#define SSI0_IM_R               (*((volatile uint32_t *)0x40008014))
+#define SSI0_RIS_R              (*((volatile uint32_t *)0x40008018))
+#define SSI0_MIS_R              (*((volatile uint32_t *)0x4000801C))
+#define SSI0_ICR_R              (*((volatile uint32_t *)0x40008020))
+#define SSI0_DMACTL_R           (*((volatile uint32_t *)0x40008024))
+#define SSI0_CC_R               (*((volatile uint32_t *)0x40008FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI1)
+//
+//*****************************************************************************
+#define SSI1_CR0_R              (*((volatile uint32_t *)0x40009000))
+#define SSI1_CR1_R              (*((volatile uint32_t *)0x40009004))
+#define SSI1_DR_R               (*((volatile uint32_t *)0x40009008))
+#define SSI1_SR_R               (*((volatile uint32_t *)0x4000900C))
+#define SSI1_CPSR_R             (*((volatile uint32_t *)0x40009010))
+#define SSI1_IM_R               (*((volatile uint32_t *)0x40009014))
+#define SSI1_RIS_R              (*((volatile uint32_t *)0x40009018))
+#define SSI1_MIS_R              (*((volatile uint32_t *)0x4000901C))
+#define SSI1_ICR_R              (*((volatile uint32_t *)0x40009020))
+#define SSI1_DMACTL_R           (*((volatile uint32_t *)0x40009024))
+#define SSI1_CC_R               (*((volatile uint32_t *)0x40009FC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI2)
+//
+//*****************************************************************************
+#define SSI2_CR0_R              (*((volatile uint32_t *)0x4000A000))
+#define SSI2_CR1_R              (*((volatile uint32_t *)0x4000A004))
+#define SSI2_DR_R               (*((volatile uint32_t *)0x4000A008))
+#define SSI2_SR_R               (*((volatile uint32_t *)0x4000A00C))
+#define SSI2_CPSR_R             (*((volatile uint32_t *)0x4000A010))
+#define SSI2_IM_R               (*((volatile uint32_t *)0x4000A014))
+#define SSI2_RIS_R              (*((volatile uint32_t *)0x4000A018))
+#define SSI2_MIS_R              (*((volatile uint32_t *)0x4000A01C))
+#define SSI2_ICR_R              (*((volatile uint32_t *)0x4000A020))
+#define SSI2_DMACTL_R           (*((volatile uint32_t *)0x4000A024))
+#define SSI2_CC_R               (*((volatile uint32_t *)0x4000AFC8))
+
+//*****************************************************************************
+//
+// SSI registers (SSI3)
+//
+//*****************************************************************************
+#define SSI3_CR0_R              (*((volatile uint32_t *)0x4000B000))
+#define SSI3_CR1_R              (*((volatile uint32_t *)0x4000B004))
+#define SSI3_DR_R               (*((volatile uint32_t *)0x4000B008))
+#define SSI3_SR_R               (*((volatile uint32_t *)0x4000B00C))
+#define SSI3_CPSR_R             (*((volatile uint32_t *)0x4000B010))
+#define SSI3_IM_R               (*((volatile uint32_t *)0x4000B014))
+#define SSI3_RIS_R              (*((volatile uint32_t *)0x4000B018))
+#define SSI3_MIS_R              (*((volatile uint32_t *)0x4000B01C))
+#define SSI3_ICR_R              (*((volatile uint32_t *)0x4000B020))
+#define SSI3_DMACTL_R           (*((volatile uint32_t *)0x4000B024))
+#define SSI3_CC_R               (*((volatile uint32_t *)0x4000BFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART0)
+//
+//*****************************************************************************
+#define UART0_DR_R              (*((volatile uint32_t *)0x4000C000))
+#define UART0_RSR_R             (*((volatile uint32_t *)0x4000C004))
+#define UART0_ECR_R             (*((volatile uint32_t *)0x4000C004))
+#define UART0_FR_R              (*((volatile uint32_t *)0x4000C018))
+#define UART0_ILPR_R            (*((volatile uint32_t *)0x4000C020))
+#define UART0_IBRD_R            (*((volatile uint32_t *)0x4000C024))
+#define UART0_FBRD_R            (*((volatile uint32_t *)0x4000C028))
+#define UART0_LCRH_R            (*((volatile uint32_t *)0x4000C02C))
+#define UART0_CTL_R             (*((volatile uint32_t *)0x4000C030))
+#define UART0_IFLS_R            (*((volatile uint32_t *)0x4000C034))
+#define UART0_IM_R              (*((volatile uint32_t *)0x4000C038))
+#define UART0_RIS_R             (*((volatile uint32_t *)0x4000C03C))
+#define UART0_MIS_R             (*((volatile uint32_t *)0x4000C040))
+#define UART0_ICR_R             (*((volatile uint32_t *)0x4000C044))
+#define UART0_DMACTL_R          (*((volatile uint32_t *)0x4000C048))
+#define UART0_9BITADDR_R        (*((volatile uint32_t *)0x4000C0A4))
+#define UART0_9BITAMASK_R       (*((volatile uint32_t *)0x4000C0A8))
+#define UART0_PP_R              (*((volatile uint32_t *)0x4000CFC0))
+#define UART0_CC_R              (*((volatile uint32_t *)0x4000CFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART1)
+//
+//*****************************************************************************
+#define UART1_DR_R              (*((volatile uint32_t *)0x4000D000))
+#define UART1_RSR_R             (*((volatile uint32_t *)0x4000D004))
+#define UART1_ECR_R             (*((volatile uint32_t *)0x4000D004))
+#define UART1_FR_R              (*((volatile uint32_t *)0x4000D018))
+#define UART1_ILPR_R            (*((volatile uint32_t *)0x4000D020))
+#define UART1_IBRD_R            (*((volatile uint32_t *)0x4000D024))
+#define UART1_FBRD_R            (*((volatile uint32_t *)0x4000D028))
+#define UART1_LCRH_R            (*((volatile uint32_t *)0x4000D02C))
+#define UART1_CTL_R             (*((volatile uint32_t *)0x4000D030))
+#define UART1_IFLS_R            (*((volatile uint32_t *)0x4000D034))
+#define UART1_IM_R              (*((volatile uint32_t *)0x4000D038))
+#define UART1_RIS_R             (*((volatile uint32_t *)0x4000D03C))
+#define UART1_MIS_R             (*((volatile uint32_t *)0x4000D040))
+#define UART1_ICR_R             (*((volatile uint32_t *)0x4000D044))
+#define UART1_DMACTL_R          (*((volatile uint32_t *)0x4000D048))
+#define UART1_9BITADDR_R        (*((volatile uint32_t *)0x4000D0A4))
+#define UART1_9BITAMASK_R       (*((volatile uint32_t *)0x4000D0A8))
+#define UART1_PP_R              (*((volatile uint32_t *)0x4000DFC0))
+#define UART1_CC_R              (*((volatile uint32_t *)0x4000DFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART2)
+//
+//*****************************************************************************
+#define UART2_DR_R              (*((volatile uint32_t *)0x4000E000))
+#define UART2_RSR_R             (*((volatile uint32_t *)0x4000E004))
+#define UART2_ECR_R             (*((volatile uint32_t *)0x4000E004))
+#define UART2_FR_R              (*((volatile uint32_t *)0x4000E018))
+#define UART2_ILPR_R            (*((volatile uint32_t *)0x4000E020))
+#define UART2_IBRD_R            (*((volatile uint32_t *)0x4000E024))
+#define UART2_FBRD_R            (*((volatile uint32_t *)0x4000E028))
+#define UART2_LCRH_R            (*((volatile uint32_t *)0x4000E02C))
+#define UART2_CTL_R             (*((volatile uint32_t *)0x4000E030))
+#define UART2_IFLS_R            (*((volatile uint32_t *)0x4000E034))
+#define UART2_IM_R              (*((volatile uint32_t *)0x4000E038))
+#define UART2_RIS_R             (*((volatile uint32_t *)0x4000E03C))
+#define UART2_MIS_R             (*((volatile uint32_t *)0x4000E040))
+#define UART2_ICR_R             (*((volatile uint32_t *)0x4000E044))
+#define UART2_DMACTL_R          (*((volatile uint32_t *)0x4000E048))
+#define UART2_9BITADDR_R        (*((volatile uint32_t *)0x4000E0A4))
+#define UART2_9BITAMASK_R       (*((volatile uint32_t *)0x4000E0A8))
+#define UART2_PP_R              (*((volatile uint32_t *)0x4000EFC0))
+#define UART2_CC_R              (*((volatile uint32_t *)0x4000EFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART3)
+//
+//*****************************************************************************
+#define UART3_DR_R              (*((volatile uint32_t *)0x4000F000))
+#define UART3_RSR_R             (*((volatile uint32_t *)0x4000F004))
+#define UART3_ECR_R             (*((volatile uint32_t *)0x4000F004))
+#define UART3_FR_R              (*((volatile uint32_t *)0x4000F018))
+#define UART3_ILPR_R            (*((volatile uint32_t *)0x4000F020))
+#define UART3_IBRD_R            (*((volatile uint32_t *)0x4000F024))
+#define UART3_FBRD_R            (*((volatile uint32_t *)0x4000F028))
+#define UART3_LCRH_R            (*((volatile uint32_t *)0x4000F02C))
+#define UART3_CTL_R             (*((volatile uint32_t *)0x4000F030))
+#define UART3_IFLS_R            (*((volatile uint32_t *)0x4000F034))
+#define UART3_IM_R              (*((volatile uint32_t *)0x4000F038))
+#define UART3_RIS_R             (*((volatile uint32_t *)0x4000F03C))
+#define UART3_MIS_R             (*((volatile uint32_t *)0x4000F040))
+#define UART3_ICR_R             (*((volatile uint32_t *)0x4000F044))
+#define UART3_DMACTL_R          (*((volatile uint32_t *)0x4000F048))
+#define UART3_9BITADDR_R        (*((volatile uint32_t *)0x4000F0A4))
+#define UART3_9BITAMASK_R       (*((volatile uint32_t *)0x4000F0A8))
+#define UART3_PP_R              (*((volatile uint32_t *)0x4000FFC0))
+#define UART3_CC_R              (*((volatile uint32_t *)0x4000FFC8))
+
+//*****************************************************************************
+//
+// UART registers (UART4)
+//
+//*****************************************************************************
+#define UART4_DR_R              (*((volatile uint32_t *)0x40010000))
+#define UART4_RSR_R             (*((volatile uint32_t *)0x40010004))
+#define UART4_ECR_R             (*((volatile uint32_t *)0x40010004))
+#define UART4_FR_R              (*((volatile uint32_t *)0x40010018))
+#define UART4_ILPR_R            (*((volatile uint32_t *)0x40010020))
+#define UART4_IBRD_R            (*((volatile uint32_t *)0x40010024))
+#define UART4_FBRD_R            (*((volatile uint32_t *)0x40010028))
+#define UART4_LCRH_R            (*((volatile uint32_t *)0x4001002C))
+#define UART4_CTL_R             (*((volatile uint32_t *)0x40010030))
+#define UART4_IFLS_R            (*((volatile uint32_t *)0x40010034))
+#define UART4_IM_R              (*((volatile uint32_t *)0x40010038))
+#define UART4_RIS_R             (*((volatile uint32_t *)0x4001003C))
+#define UART4_MIS_R             (*((volatile uint32_t *)0x40010040))
+#define UART4_ICR_R             (*((volatile uint32_t *)0x40010044))
+#define UART4_DMACTL_R          (*((volatile uint32_t *)0x40010048))
+#define UART4_9BITADDR_R        (*((volatile uint32_t *)0x400100A4))
+#define UART4_9BITAMASK_R       (*((volatile uint32_t *)0x400100A8))
+#define UART4_PP_R              (*((volatile uint32_t *)0x40010FC0))
+#define UART4_CC_R              (*((volatile uint32_t *)0x40010FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART5)
+//
+//*****************************************************************************
+#define UART5_DR_R              (*((volatile uint32_t *)0x40011000))
+#define UART5_RSR_R             (*((volatile uint32_t *)0x40011004))
+#define UART5_ECR_R             (*((volatile uint32_t *)0x40011004))
+#define UART5_FR_R              (*((volatile uint32_t *)0x40011018))
+#define UART5_ILPR_R            (*((volatile uint32_t *)0x40011020))
+#define UART5_IBRD_R            (*((volatile uint32_t *)0x40011024))
+#define UART5_FBRD_R            (*((volatile uint32_t *)0x40011028))
+#define UART5_LCRH_R            (*((volatile uint32_t *)0x4001102C))
+#define UART5_CTL_R             (*((volatile uint32_t *)0x40011030))
+#define UART5_IFLS_R            (*((volatile uint32_t *)0x40011034))
+#define UART5_IM_R              (*((volatile uint32_t *)0x40011038))
+#define UART5_RIS_R             (*((volatile uint32_t *)0x4001103C))
+#define UART5_MIS_R             (*((volatile uint32_t *)0x40011040))
+#define UART5_ICR_R             (*((volatile uint32_t *)0x40011044))
+#define UART5_DMACTL_R          (*((volatile uint32_t *)0x40011048))
+#define UART5_9BITADDR_R        (*((volatile uint32_t *)0x400110A4))
+#define UART5_9BITAMASK_R       (*((volatile uint32_t *)0x400110A8))
+#define UART5_PP_R              (*((volatile uint32_t *)0x40011FC0))
+#define UART5_CC_R              (*((volatile uint32_t *)0x40011FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART6)
+//
+//*****************************************************************************
+#define UART6_DR_R              (*((volatile uint32_t *)0x40012000))
+#define UART6_RSR_R             (*((volatile uint32_t *)0x40012004))
+#define UART6_ECR_R             (*((volatile uint32_t *)0x40012004))
+#define UART6_FR_R              (*((volatile uint32_t *)0x40012018))
+#define UART6_ILPR_R            (*((volatile uint32_t *)0x40012020))
+#define UART6_IBRD_R            (*((volatile uint32_t *)0x40012024))
+#define UART6_FBRD_R            (*((volatile uint32_t *)0x40012028))
+#define UART6_LCRH_R            (*((volatile uint32_t *)0x4001202C))
+#define UART6_CTL_R             (*((volatile uint32_t *)0x40012030))
+#define UART6_IFLS_R            (*((volatile uint32_t *)0x40012034))
+#define UART6_IM_R              (*((volatile uint32_t *)0x40012038))
+#define UART6_RIS_R             (*((volatile uint32_t *)0x4001203C))
+#define UART6_MIS_R             (*((volatile uint32_t *)0x40012040))
+#define UART6_ICR_R             (*((volatile uint32_t *)0x40012044))
+#define UART6_DMACTL_R          (*((volatile uint32_t *)0x40012048))
+#define UART6_9BITADDR_R        (*((volatile uint32_t *)0x400120A4))
+#define UART6_9BITAMASK_R       (*((volatile uint32_t *)0x400120A8))
+#define UART6_PP_R              (*((volatile uint32_t *)0x40012FC0))
+#define UART6_CC_R              (*((volatile uint32_t *)0x40012FC8))
+
+//*****************************************************************************
+//
+// UART registers (UART7)
+//
+//*****************************************************************************
+#define UART7_DR_R              (*((volatile uint32_t *)0x40013000))
+#define UART7_RSR_R             (*((volatile uint32_t *)0x40013004))
+#define UART7_ECR_R             (*((volatile uint32_t *)0x40013004))
+#define UART7_FR_R              (*((volatile uint32_t *)0x40013018))
+#define UART7_ILPR_R            (*((volatile uint32_t *)0x40013020))
+#define UART7_IBRD_R            (*((volatile uint32_t *)0x40013024))
+#define UART7_FBRD_R            (*((volatile uint32_t *)0x40013028))
+#define UART7_LCRH_R            (*((volatile uint32_t *)0x4001302C))
+#define UART7_CTL_R             (*((volatile uint32_t *)0x40013030))
+#define UART7_IFLS_R            (*((volatile uint32_t *)0x40013034))
+#define UART7_IM_R              (*((volatile uint32_t *)0x40013038))
+#define UART7_RIS_R             (*((volatile uint32_t *)0x4001303C))
+#define UART7_MIS_R             (*((volatile uint32_t *)0x40013040))
+#define UART7_ICR_R             (*((volatile uint32_t *)0x40013044))
+#define UART7_DMACTL_R          (*((volatile uint32_t *)0x40013048))
+#define UART7_9BITADDR_R        (*((volatile uint32_t *)0x400130A4))
+#define UART7_9BITAMASK_R       (*((volatile uint32_t *)0x400130A8))
+#define UART7_PP_R              (*((volatile uint32_t *)0x40013FC0))
+#define UART7_CC_R              (*((volatile uint32_t *)0x40013FC8))
+
+//*****************************************************************************
+//
+// I2C registers (I2C0)
+//
+//*****************************************************************************
+#define I2C0_MSA_R              (*((volatile uint32_t *)0x40020000))
+#define I2C0_MCS_R              (*((volatile uint32_t *)0x40020004))
+#define I2C0_MDR_R              (*((volatile uint32_t *)0x40020008))
+#define I2C0_MTPR_R             (*((volatile uint32_t *)0x4002000C))
+#define I2C0_MIMR_R             (*((volatile uint32_t *)0x40020010))
+#define I2C0_MRIS_R             (*((volatile uint32_t *)0x40020014))
+#define I2C0_MMIS_R             (*((volatile uint32_t *)0x40020018))
+#define I2C0_MICR_R             (*((volatile uint32_t *)0x4002001C))
+#define I2C0_MCR_R              (*((volatile uint32_t *)0x40020020))
+#define I2C0_MCLKOCNT_R         (*((volatile uint32_t *)0x40020024))
+#define I2C0_MBMON_R            (*((volatile uint32_t *)0x4002002C))
+#define I2C0_MCR2_R             (*((volatile uint32_t *)0x40020038))
+#define I2C0_SOAR_R             (*((volatile uint32_t *)0x40020800))
+#define I2C0_SCSR_R             (*((volatile uint32_t *)0x40020804))
+#define I2C0_SDR_R              (*((volatile uint32_t *)0x40020808))
+#define I2C0_SIMR_R             (*((volatile uint32_t *)0x4002080C))
+#define I2C0_SRIS_R             (*((volatile uint32_t *)0x40020810))
+#define I2C0_SMIS_R             (*((volatile uint32_t *)0x40020814))
+#define I2C0_SICR_R             (*((volatile uint32_t *)0x40020818))
+#define I2C0_SOAR2_R            (*((volatile uint32_t *)0x4002081C))
+#define I2C0_SACKCTL_R          (*((volatile uint32_t *)0x40020820))
+#define I2C0_PP_R               (*((volatile uint32_t *)0x40020FC0))
+#define I2C0_PC_R               (*((volatile uint32_t *)0x40020FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C1)
+//
+//*****************************************************************************
+#define I2C1_MSA_R              (*((volatile uint32_t *)0x40021000))
+#define I2C1_MCS_R              (*((volatile uint32_t *)0x40021004))
+#define I2C1_MDR_R              (*((volatile uint32_t *)0x40021008))
+#define I2C1_MTPR_R             (*((volatile uint32_t *)0x4002100C))
+#define I2C1_MIMR_R             (*((volatile uint32_t *)0x40021010))
+#define I2C1_MRIS_R             (*((volatile uint32_t *)0x40021014))
+#define I2C1_MMIS_R             (*((volatile uint32_t *)0x40021018))
+#define I2C1_MICR_R             (*((volatile uint32_t *)0x4002101C))
+#define I2C1_MCR_R              (*((volatile uint32_t *)0x40021020))
+#define I2C1_MCLKOCNT_R         (*((volatile uint32_t *)0x40021024))
+#define I2C1_MBMON_R            (*((volatile uint32_t *)0x4002102C))
+#define I2C1_MCR2_R             (*((volatile uint32_t *)0x40021038))
+#define I2C1_SOAR_R             (*((volatile uint32_t *)0x40021800))
+#define I2C1_SCSR_R             (*((volatile uint32_t *)0x40021804))
+#define I2C1_SDR_R              (*((volatile uint32_t *)0x40021808))
+#define I2C1_SIMR_R             (*((volatile uint32_t *)0x4002180C))
+#define I2C1_SRIS_R             (*((volatile uint32_t *)0x40021810))
+#define I2C1_SMIS_R             (*((volatile uint32_t *)0x40021814))
+#define I2C1_SICR_R             (*((volatile uint32_t *)0x40021818))
+#define I2C1_SOAR2_R            (*((volatile uint32_t *)0x4002181C))
+#define I2C1_SACKCTL_R          (*((volatile uint32_t *)0x40021820))
+#define I2C1_PP_R               (*((volatile uint32_t *)0x40021FC0))
+#define I2C1_PC_R               (*((volatile uint32_t *)0x40021FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C2)
+//
+//*****************************************************************************
+#define I2C2_MSA_R              (*((volatile uint32_t *)0x40022000))
+#define I2C2_MCS_R              (*((volatile uint32_t *)0x40022004))
+#define I2C2_MDR_R              (*((volatile uint32_t *)0x40022008))
+#define I2C2_MTPR_R             (*((volatile uint32_t *)0x4002200C))
+#define I2C2_MIMR_R             (*((volatile uint32_t *)0x40022010))
+#define I2C2_MRIS_R             (*((volatile uint32_t *)0x40022014))
+#define I2C2_MMIS_R             (*((volatile uint32_t *)0x40022018))
+#define I2C2_MICR_R             (*((volatile uint32_t *)0x4002201C))
+#define I2C2_MCR_R              (*((volatile uint32_t *)0x40022020))
+#define I2C2_MCLKOCNT_R         (*((volatile uint32_t *)0x40022024))
+#define I2C2_MBMON_R            (*((volatile uint32_t *)0x4002202C))
+#define I2C2_MCR2_R             (*((volatile uint32_t *)0x40022038))
+#define I2C2_SOAR_R             (*((volatile uint32_t *)0x40022800))
+#define I2C2_SCSR_R             (*((volatile uint32_t *)0x40022804))
+#define I2C2_SDR_R              (*((volatile uint32_t *)0x40022808))
+#define I2C2_SIMR_R             (*((volatile uint32_t *)0x4002280C))
+#define I2C2_SRIS_R             (*((volatile uint32_t *)0x40022810))
+#define I2C2_SMIS_R             (*((volatile uint32_t *)0x40022814))
+#define I2C2_SICR_R             (*((volatile uint32_t *)0x40022818))
+#define I2C2_SOAR2_R            (*((volatile uint32_t *)0x4002281C))
+#define I2C2_SACKCTL_R          (*((volatile uint32_t *)0x40022820))
+#define I2C2_PP_R               (*((volatile uint32_t *)0x40022FC0))
+#define I2C2_PC_R               (*((volatile uint32_t *)0x40022FC4))
+
+//*****************************************************************************
+//
+// I2C registers (I2C3)
+//
+//*****************************************************************************
+#define I2C3_MSA_R              (*((volatile uint32_t *)0x40023000))
+#define I2C3_MCS_R              (*((volatile uint32_t *)0x40023004))
+#define I2C3_MDR_R              (*((volatile uint32_t *)0x40023008))
+#define I2C3_MTPR_R             (*((volatile uint32_t *)0x4002300C))
+#define I2C3_MIMR_R             (*((volatile uint32_t *)0x40023010))
+#define I2C3_MRIS_R             (*((volatile uint32_t *)0x40023014))
+#define I2C3_MMIS_R             (*((volatile uint32_t *)0x40023018))
+#define I2C3_MICR_R             (*((volatile uint32_t *)0x4002301C))
+#define I2C3_MCR_R              (*((volatile uint32_t *)0x40023020))
+#define I2C3_MCLKOCNT_R         (*((volatile uint32_t *)0x40023024))
+#define I2C3_MBMON_R            (*((volatile uint32_t *)0x4002302C))
+#define I2C3_MCR2_R             (*((volatile uint32_t *)0x40023038))
+#define I2C3_SOAR_R             (*((volatile uint32_t *)0x40023800))
+#define I2C3_SCSR_R             (*((volatile uint32_t *)0x40023804))
+#define I2C3_SDR_R              (*((volatile uint32_t *)0x40023808))
+#define I2C3_SIMR_R             (*((volatile uint32_t *)0x4002380C))
+#define I2C3_SRIS_R             (*((volatile uint32_t *)0x40023810))
+#define I2C3_SMIS_R             (*((volatile uint32_t *)0x40023814))
+#define I2C3_SICR_R             (*((volatile uint32_t *)0x40023818))
+#define I2C3_SOAR2_R            (*((volatile uint32_t *)0x4002381C))
+#define I2C3_SACKCTL_R          (*((volatile uint32_t *)0x40023820))
+#define I2C3_PP_R               (*((volatile uint32_t *)0x40023FC0))
+#define I2C3_PC_R               (*((volatile uint32_t *)0x40023FC4))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE)
+//
+//*****************************************************************************
+#define GPIO_PORTE_DATA_BITS_R  ((volatile uint32_t *)0x40024000)
+#define GPIO_PORTE_DATA_R       (*((volatile uint32_t *)0x400243FC))
+#define GPIO_PORTE_DIR_R        (*((volatile uint32_t *)0x40024400))
+#define GPIO_PORTE_IS_R         (*((volatile uint32_t *)0x40024404))
+#define GPIO_PORTE_IBE_R        (*((volatile uint32_t *)0x40024408))
+#define GPIO_PORTE_IEV_R        (*((volatile uint32_t *)0x4002440C))
+#define GPIO_PORTE_IM_R         (*((volatile uint32_t *)0x40024410))
+#define GPIO_PORTE_RIS_R        (*((volatile uint32_t *)0x40024414))
+#define GPIO_PORTE_MIS_R        (*((volatile uint32_t *)0x40024418))
+#define GPIO_PORTE_ICR_R        (*((volatile uint32_t *)0x4002441C))
+#define GPIO_PORTE_AFSEL_R      (*((volatile uint32_t *)0x40024420))
+#define GPIO_PORTE_DR2R_R       (*((volatile uint32_t *)0x40024500))
+#define GPIO_PORTE_DR4R_R       (*((volatile uint32_t *)0x40024504))
+#define GPIO_PORTE_DR8R_R       (*((volatile uint32_t *)0x40024508))
+#define GPIO_PORTE_ODR_R        (*((volatile uint32_t *)0x4002450C))
+#define GPIO_PORTE_PUR_R        (*((volatile uint32_t *)0x40024510))
+#define GPIO_PORTE_PDR_R        (*((volatile uint32_t *)0x40024514))
+#define GPIO_PORTE_SLR_R        (*((volatile uint32_t *)0x40024518))
+#define GPIO_PORTE_DEN_R        (*((volatile uint32_t *)0x4002451C))
+#define GPIO_PORTE_LOCK_R       (*((volatile uint32_t *)0x40024520))
+#define GPIO_PORTE_CR_R         (*((volatile uint32_t *)0x40024524))
+#define GPIO_PORTE_AMSEL_R      (*((volatile uint32_t *)0x40024528))
+#define GPIO_PORTE_PCTL_R       (*((volatile uint32_t *)0x4002452C))
+#define GPIO_PORTE_ADCCTL_R     (*((volatile uint32_t *)0x40024530))
+#define GPIO_PORTE_DMACTL_R     (*((volatile uint32_t *)0x40024534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF)
+//
+//*****************************************************************************
+#define GPIO_PORTF_DATA_BITS_R  ((volatile uint32_t *)0x40025000)
+#define GPIO_PORTF_DATA_R       (*((volatile uint32_t *)0x400253FC))
+#define GPIO_PORTF_DIR_R        (*((volatile uint32_t *)0x40025400))
+#define GPIO_PORTF_IS_R         (*((volatile uint32_t *)0x40025404))
+#define GPIO_PORTF_IBE_R        (*((volatile uint32_t *)0x40025408))
+#define GPIO_PORTF_IEV_R        (*((volatile uint32_t *)0x4002540C))
+#define GPIO_PORTF_IM_R         (*((volatile uint32_t *)0x40025410))
+#define GPIO_PORTF_RIS_R        (*((volatile uint32_t *)0x40025414))
+#define GPIO_PORTF_MIS_R        (*((volatile uint32_t *)0x40025418))
+#define GPIO_PORTF_ICR_R        (*((volatile uint32_t *)0x4002541C))
+#define GPIO_PORTF_AFSEL_R      (*((volatile uint32_t *)0x40025420))
+#define GPIO_PORTF_DR2R_R       (*((volatile uint32_t *)0x40025500))
+#define GPIO_PORTF_DR4R_R       (*((volatile uint32_t *)0x40025504))
+#define GPIO_PORTF_DR8R_R       (*((volatile uint32_t *)0x40025508))
+#define GPIO_PORTF_ODR_R        (*((volatile uint32_t *)0x4002550C))
+#define GPIO_PORTF_PUR_R        (*((volatile uint32_t *)0x40025510))
+#define GPIO_PORTF_PDR_R        (*((volatile uint32_t *)0x40025514))
+#define GPIO_PORTF_SLR_R        (*((volatile uint32_t *)0x40025518))
+#define GPIO_PORTF_DEN_R        (*((volatile uint32_t *)0x4002551C))
+#define GPIO_PORTF_LOCK_R       (*((volatile uint32_t *)0x40025520))
+#define GPIO_PORTF_CR_R         (*((volatile uint32_t *)0x40025524))
+#define GPIO_PORTF_AMSEL_R      (*((volatile uint32_t *)0x40025528))
+#define GPIO_PORTF_PCTL_R       (*((volatile uint32_t *)0x4002552C))
+#define GPIO_PORTF_ADCCTL_R     (*((volatile uint32_t *)0x40025530))
+#define GPIO_PORTF_DMACTL_R     (*((volatile uint32_t *)0x40025534))
+
+//*****************************************************************************
+//
+// PWM registers (PWM0)
+//
+//*****************************************************************************
+#define PWM0_CTL_R              (*((volatile uint32_t *)0x40028000))
+#define PWM0_SYNC_R             (*((volatile uint32_t *)0x40028004))
+#define PWM0_ENABLE_R           (*((volatile uint32_t *)0x40028008))
+#define PWM0_INVERT_R           (*((volatile uint32_t *)0x4002800C))
+#define PWM0_FAULT_R            (*((volatile uint32_t *)0x40028010))
+#define PWM0_INTEN_R            (*((volatile uint32_t *)0x40028014))
+#define PWM0_RIS_R              (*((volatile uint32_t *)0x40028018))
+#define PWM0_ISC_R              (*((volatile uint32_t *)0x4002801C))
+#define PWM0_STATUS_R           (*((volatile uint32_t *)0x40028020))
+#define PWM0_FAULTVAL_R         (*((volatile uint32_t *)0x40028024))
+#define PWM0_ENUPD_R            (*((volatile uint32_t *)0x40028028))
+#define PWM0_0_CTL_R            (*((volatile uint32_t *)0x40028040))
+#define PWM0_0_INTEN_R          (*((volatile uint32_t *)0x40028044))
+#define PWM0_0_RIS_R            (*((volatile uint32_t *)0x40028048))
+#define PWM0_0_ISC_R            (*((volatile uint32_t *)0x4002804C))
+#define PWM0_0_LOAD_R           (*((volatile uint32_t *)0x40028050))
+#define PWM0_0_COUNT_R          (*((volatile uint32_t *)0x40028054))
+#define PWM0_0_CMPA_R           (*((volatile uint32_t *)0x40028058))
+#define PWM0_0_CMPB_R           (*((volatile uint32_t *)0x4002805C))
+#define PWM0_0_GENA_R           (*((volatile uint32_t *)0x40028060))
+#define PWM0_0_GENB_R           (*((volatile uint32_t *)0x40028064))
+#define PWM0_0_DBCTL_R          (*((volatile uint32_t *)0x40028068))
+#define PWM0_0_DBRISE_R         (*((volatile uint32_t *)0x4002806C))
+#define PWM0_0_DBFALL_R         (*((volatile uint32_t *)0x40028070))
+#define PWM0_0_FLTSRC0_R        (*((volatile uint32_t *)0x40028074))
+#define PWM0_0_FLTSRC1_R        (*((volatile uint32_t *)0x40028078))
+#define PWM0_0_MINFLTPER_R      (*((volatile uint32_t *)0x4002807C))
+#define PWM0_1_CTL_R            (*((volatile uint32_t *)0x40028080))
+#define PWM0_1_INTEN_R          (*((volatile uint32_t *)0x40028084))
+#define PWM0_1_RIS_R            (*((volatile uint32_t *)0x40028088))
+#define PWM0_1_ISC_R            (*((volatile uint32_t *)0x4002808C))
+#define PWM0_1_LOAD_R           (*((volatile uint32_t *)0x40028090))
+#define PWM0_1_COUNT_R          (*((volatile uint32_t *)0x40028094))
+#define PWM0_1_CMPA_R           (*((volatile uint32_t *)0x40028098))
+#define PWM0_1_CMPB_R           (*((volatile uint32_t *)0x4002809C))
+#define PWM0_1_GENA_R           (*((volatile uint32_t *)0x400280A0))
+#define PWM0_1_GENB_R           (*((volatile uint32_t *)0x400280A4))
+#define PWM0_1_DBCTL_R          (*((volatile uint32_t *)0x400280A8))
+#define PWM0_1_DBRISE_R         (*((volatile uint32_t *)0x400280AC))
+#define PWM0_1_DBFALL_R         (*((volatile uint32_t *)0x400280B0))
+#define PWM0_1_FLTSRC0_R        (*((volatile uint32_t *)0x400280B4))
+#define PWM0_1_FLTSRC1_R        (*((volatile uint32_t *)0x400280B8))
+#define PWM0_1_MINFLTPER_R      (*((volatile uint32_t *)0x400280BC))
+#define PWM0_2_CTL_R            (*((volatile uint32_t *)0x400280C0))
+#define PWM0_2_INTEN_R          (*((volatile uint32_t *)0x400280C4))
+#define PWM0_2_RIS_R            (*((volatile uint32_t *)0x400280C8))
+#define PWM0_2_ISC_R            (*((volatile uint32_t *)0x400280CC))
+#define PWM0_2_LOAD_R           (*((volatile uint32_t *)0x400280D0))
+#define PWM0_2_COUNT_R          (*((volatile uint32_t *)0x400280D4))
+#define PWM0_2_CMPA_R           (*((volatile uint32_t *)0x400280D8))
+#define PWM0_2_CMPB_R           (*((volatile uint32_t *)0x400280DC))
+#define PWM0_2_GENA_R           (*((volatile uint32_t *)0x400280E0))
+#define PWM0_2_GENB_R           (*((volatile uint32_t *)0x400280E4))
+#define PWM0_2_DBCTL_R          (*((volatile uint32_t *)0x400280E8))
+#define PWM0_2_DBRISE_R         (*((volatile uint32_t *)0x400280EC))
+#define PWM0_2_DBFALL_R         (*((volatile uint32_t *)0x400280F0))
+#define PWM0_2_FLTSRC0_R        (*((volatile uint32_t *)0x400280F4))
+#define PWM0_2_FLTSRC1_R        (*((volatile uint32_t *)0x400280F8))
+#define PWM0_2_MINFLTPER_R      (*((volatile uint32_t *)0x400280FC))
+#define PWM0_3_CTL_R            (*((volatile uint32_t *)0x40028100))
+#define PWM0_3_INTEN_R          (*((volatile uint32_t *)0x40028104))
+#define PWM0_3_RIS_R            (*((volatile uint32_t *)0x40028108))
+#define PWM0_3_ISC_R            (*((volatile uint32_t *)0x4002810C))
+#define PWM0_3_LOAD_R           (*((volatile uint32_t *)0x40028110))
+#define PWM0_3_COUNT_R          (*((volatile uint32_t *)0x40028114))
+#define PWM0_3_CMPA_R           (*((volatile uint32_t *)0x40028118))
+#define PWM0_3_CMPB_R           (*((volatile uint32_t *)0x4002811C))
+#define PWM0_3_GENA_R           (*((volatile uint32_t *)0x40028120))
+#define PWM0_3_GENB_R           (*((volatile uint32_t *)0x40028124))
+#define PWM0_3_DBCTL_R          (*((volatile uint32_t *)0x40028128))
+#define PWM0_3_DBRISE_R         (*((volatile uint32_t *)0x4002812C))
+#define PWM0_3_DBFALL_R         (*((volatile uint32_t *)0x40028130))
+#define PWM0_3_FLTSRC0_R        (*((volatile uint32_t *)0x40028134))
+#define PWM0_3_FLTSRC1_R        (*((volatile uint32_t *)0x40028138))
+#define PWM0_3_MINFLTPER_R      (*((volatile uint32_t *)0x4002813C))
+#define PWM0_0_FLTSEN_R         (*((volatile uint32_t *)0x40028800))
+#define PWM0_0_FLTSTAT0_R       (*((volatile uint32_t *)0x40028804))
+#define PWM0_0_FLTSTAT1_R       (*((volatile uint32_t *)0x40028808))
+#define PWM0_1_FLTSEN_R         (*((volatile uint32_t *)0x40028880))
+#define PWM0_1_FLTSTAT0_R       (*((volatile uint32_t *)0x40028884))
+#define PWM0_1_FLTSTAT1_R       (*((volatile uint32_t *)0x40028888))
+#define PWM0_2_FLTSTAT0_R       (*((volatile uint32_t *)0x40028904))
+#define PWM0_2_FLTSTAT1_R       (*((volatile uint32_t *)0x40028908))
+#define PWM0_3_FLTSTAT0_R       (*((volatile uint32_t *)0x40028984))
+#define PWM0_3_FLTSTAT1_R       (*((volatile uint32_t *)0x40028988))
+#define PWM0_PP_R               (*((volatile uint32_t *)0x40028FC0))
+
+//*****************************************************************************
+//
+// PWM registers (PWM1)
+//
+//*****************************************************************************
+#define PWM1_CTL_R              (*((volatile uint32_t *)0x40029000))
+#define PWM1_SYNC_R             (*((volatile uint32_t *)0x40029004))
+#define PWM1_ENABLE_R           (*((volatile uint32_t *)0x40029008))
+#define PWM1_INVERT_R           (*((volatile uint32_t *)0x4002900C))
+#define PWM1_FAULT_R            (*((volatile uint32_t *)0x40029010))
+#define PWM1_INTEN_R            (*((volatile uint32_t *)0x40029014))
+#define PWM1_RIS_R              (*((volatile uint32_t *)0x40029018))
+#define PWM1_ISC_R              (*((volatile uint32_t *)0x4002901C))
+#define PWM1_STATUS_R           (*((volatile uint32_t *)0x40029020))
+#define PWM1_FAULTVAL_R         (*((volatile uint32_t *)0x40029024))
+#define PWM1_ENUPD_R            (*((volatile uint32_t *)0x40029028))
+#define PWM1_0_CTL_R            (*((volatile uint32_t *)0x40029040))
+#define PWM1_0_INTEN_R          (*((volatile uint32_t *)0x40029044))
+#define PWM1_0_RIS_R            (*((volatile uint32_t *)0x40029048))
+#define PWM1_0_ISC_R            (*((volatile uint32_t *)0x4002904C))
+#define PWM1_0_LOAD_R           (*((volatile uint32_t *)0x40029050))
+#define PWM1_0_COUNT_R          (*((volatile uint32_t *)0x40029054))
+#define PWM1_0_CMPA_R           (*((volatile uint32_t *)0x40029058))
+#define PWM1_0_CMPB_R           (*((volatile uint32_t *)0x4002905C))
+#define PWM1_0_GENA_R           (*((volatile uint32_t *)0x40029060))
+#define PWM1_0_GENB_R           (*((volatile uint32_t *)0x40029064))
+#define PWM1_0_DBCTL_R          (*((volatile uint32_t *)0x40029068))
+#define PWM1_0_DBRISE_R         (*((volatile uint32_t *)0x4002906C))
+#define PWM1_0_DBFALL_R         (*((volatile uint32_t *)0x40029070))
+#define PWM1_0_FLTSRC0_R        (*((volatile uint32_t *)0x40029074))
+#define PWM1_0_FLTSRC1_R        (*((volatile uint32_t *)0x40029078))
+#define PWM1_0_MINFLTPER_R      (*((volatile uint32_t *)0x4002907C))
+#define PWM1_1_CTL_R            (*((volatile uint32_t *)0x40029080))
+#define PWM1_1_INTEN_R          (*((volatile uint32_t *)0x40029084))
+#define PWM1_1_RIS_R            (*((volatile uint32_t *)0x40029088))
+#define PWM1_1_ISC_R            (*((volatile uint32_t *)0x4002908C))
+#define PWM1_1_LOAD_R           (*((volatile uint32_t *)0x40029090))
+#define PWM1_1_COUNT_R          (*((volatile uint32_t *)0x40029094))
+#define PWM1_1_CMPA_R           (*((volatile uint32_t *)0x40029098))
+#define PWM1_1_CMPB_R           (*((volatile uint32_t *)0x4002909C))
+#define PWM1_1_GENA_R           (*((volatile uint32_t *)0x400290A0))
+#define PWM1_1_GENB_R           (*((volatile uint32_t *)0x400290A4))
+#define PWM1_1_DBCTL_R          (*((volatile uint32_t *)0x400290A8))
+#define PWM1_1_DBRISE_R         (*((volatile uint32_t *)0x400290AC))
+#define PWM1_1_DBFALL_R         (*((volatile uint32_t *)0x400290B0))
+#define PWM1_1_FLTSRC0_R        (*((volatile uint32_t *)0x400290B4))
+#define PWM1_1_FLTSRC1_R        (*((volatile uint32_t *)0x400290B8))
+#define PWM1_1_MINFLTPER_R      (*((volatile uint32_t *)0x400290BC))
+#define PWM1_2_CTL_R            (*((volatile uint32_t *)0x400290C0))
+#define PWM1_2_INTEN_R          (*((volatile uint32_t *)0x400290C4))
+#define PWM1_2_RIS_R            (*((volatile uint32_t *)0x400290C8))
+#define PWM1_2_ISC_R            (*((volatile uint32_t *)0x400290CC))
+#define PWM1_2_LOAD_R           (*((volatile uint32_t *)0x400290D0))
+#define PWM1_2_COUNT_R          (*((volatile uint32_t *)0x400290D4))
+#define PWM1_2_CMPA_R           (*((volatile uint32_t *)0x400290D8))
+#define PWM1_2_CMPB_R           (*((volatile uint32_t *)0x400290DC))
+#define PWM1_2_GENA_R           (*((volatile uint32_t *)0x400290E0))
+#define PWM1_2_GENB_R           (*((volatile uint32_t *)0x400290E4))
+#define PWM1_2_DBCTL_R          (*((volatile uint32_t *)0x400290E8))
+#define PWM1_2_DBRISE_R         (*((volatile uint32_t *)0x400290EC))
+#define PWM1_2_DBFALL_R         (*((volatile uint32_t *)0x400290F0))
+#define PWM1_2_FLTSRC0_R        (*((volatile uint32_t *)0x400290F4))
+#define PWM1_2_FLTSRC1_R        (*((volatile uint32_t *)0x400290F8))
+#define PWM1_2_MINFLTPER_R      (*((volatile uint32_t *)0x400290FC))
+#define PWM1_3_CTL_R            (*((volatile uint32_t *)0x40029100))
+#define PWM1_3_INTEN_R          (*((volatile uint32_t *)0x40029104))
+#define PWM1_3_RIS_R            (*((volatile uint32_t *)0x40029108))
+#define PWM1_3_ISC_R            (*((volatile uint32_t *)0x4002910C))
+#define PWM1_3_LOAD_R           (*((volatile uint32_t *)0x40029110))
+#define PWM1_3_COUNT_R          (*((volatile uint32_t *)0x40029114))
+#define PWM1_3_CMPA_R           (*((volatile uint32_t *)0x40029118))
+#define PWM1_3_CMPB_R           (*((volatile uint32_t *)0x4002911C))
+#define PWM1_3_GENA_R           (*((volatile uint32_t *)0x40029120))
+#define PWM1_3_GENB_R           (*((volatile uint32_t *)0x40029124))
+#define PWM1_3_DBCTL_R          (*((volatile uint32_t *)0x40029128))
+#define PWM1_3_DBRISE_R         (*((volatile uint32_t *)0x4002912C))
+#define PWM1_3_DBFALL_R         (*((volatile uint32_t *)0x40029130))
+#define PWM1_3_FLTSRC0_R        (*((volatile uint32_t *)0x40029134))
+#define PWM1_3_FLTSRC1_R        (*((volatile uint32_t *)0x40029138))
+#define PWM1_3_MINFLTPER_R      (*((volatile uint32_t *)0x4002913C))
+#define PWM1_0_FLTSEN_R         (*((volatile uint32_t *)0x40029800))
+#define PWM1_0_FLTSTAT0_R       (*((volatile uint32_t *)0x40029804))
+#define PWM1_0_FLTSTAT1_R       (*((volatile uint32_t *)0x40029808))
+#define PWM1_1_FLTSEN_R         (*((volatile uint32_t *)0x40029880))
+#define PWM1_1_FLTSTAT0_R       (*((volatile uint32_t *)0x40029884))
+#define PWM1_1_FLTSTAT1_R       (*((volatile uint32_t *)0x40029888))
+#define PWM1_2_FLTSTAT0_R       (*((volatile uint32_t *)0x40029904))
+#define PWM1_2_FLTSTAT1_R       (*((volatile uint32_t *)0x40029908))
+#define PWM1_3_FLTSTAT0_R       (*((volatile uint32_t *)0x40029984))
+#define PWM1_3_FLTSTAT1_R       (*((volatile uint32_t *)0x40029988))
+#define PWM1_PP_R               (*((volatile uint32_t *)0x40029FC0))
+
+//*****************************************************************************
+//
+// QEI registers (QEI0)
+//
+//*****************************************************************************
+#define QEI0_CTL_R              (*((volatile uint32_t *)0x4002C000))
+#define QEI0_STAT_R             (*((volatile uint32_t *)0x4002C004))
+#define QEI0_POS_R              (*((volatile uint32_t *)0x4002C008))
+#define QEI0_MAXPOS_R           (*((volatile uint32_t *)0x4002C00C))
+#define QEI0_LOAD_R             (*((volatile uint32_t *)0x4002C010))
+#define QEI0_TIME_R             (*((volatile uint32_t *)0x4002C014))
+#define QEI0_COUNT_R            (*((volatile uint32_t *)0x4002C018))
+#define QEI0_SPEED_R            (*((volatile uint32_t *)0x4002C01C))
+#define QEI0_INTEN_R            (*((volatile uint32_t *)0x4002C020))
+#define QEI0_RIS_R              (*((volatile uint32_t *)0x4002C024))
+#define QEI0_ISC_R              (*((volatile uint32_t *)0x4002C028))
+
+//*****************************************************************************
+//
+// QEI registers (QEI1)
+//
+//*****************************************************************************
+#define QEI1_CTL_R              (*((volatile uint32_t *)0x4002D000))
+#define QEI1_STAT_R             (*((volatile uint32_t *)0x4002D004))
+#define QEI1_POS_R              (*((volatile uint32_t *)0x4002D008))
+#define QEI1_MAXPOS_R           (*((volatile uint32_t *)0x4002D00C))
+#define QEI1_LOAD_R             (*((volatile uint32_t *)0x4002D010))
+#define QEI1_TIME_R             (*((volatile uint32_t *)0x4002D014))
+#define QEI1_COUNT_R            (*((volatile uint32_t *)0x4002D018))
+#define QEI1_SPEED_R            (*((volatile uint32_t *)0x4002D01C))
+#define QEI1_INTEN_R            (*((volatile uint32_t *)0x4002D020))
+#define QEI1_RIS_R              (*((volatile uint32_t *)0x4002D024))
+#define QEI1_ISC_R              (*((volatile uint32_t *)0x4002D028))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER0)
+//
+//*****************************************************************************
+#define TIMER0_CFG_R            (*((volatile uint32_t *)0x40030000))
+#define TIMER0_TAMR_R           (*((volatile uint32_t *)0x40030004))
+#define TIMER0_TBMR_R           (*((volatile uint32_t *)0x40030008))
+#define TIMER0_CTL_R            (*((volatile uint32_t *)0x4003000C))
+#define TIMER0_SYNC_R           (*((volatile uint32_t *)0x40030010))
+#define TIMER0_IMR_R            (*((volatile uint32_t *)0x40030018))
+#define TIMER0_RIS_R            (*((volatile uint32_t *)0x4003001C))
+#define TIMER0_MIS_R            (*((volatile uint32_t *)0x40030020))
+#define TIMER0_ICR_R            (*((volatile uint32_t *)0x40030024))
+#define TIMER0_TAILR_R          (*((volatile uint32_t *)0x40030028))
+#define TIMER0_TBILR_R          (*((volatile uint32_t *)0x4003002C))
+#define TIMER0_TAMATCHR_R       (*((volatile uint32_t *)0x40030030))
+#define TIMER0_TBMATCHR_R       (*((volatile uint32_t *)0x40030034))
+#define TIMER0_TAPR_R           (*((volatile uint32_t *)0x40030038))
+#define TIMER0_TBPR_R           (*((volatile uint32_t *)0x4003003C))
+#define TIMER0_TAPMR_R          (*((volatile uint32_t *)0x40030040))
+#define TIMER0_TBPMR_R          (*((volatile uint32_t *)0x40030044))
+#define TIMER0_TAR_R            (*((volatile uint32_t *)0x40030048))
+#define TIMER0_TBR_R            (*((volatile uint32_t *)0x4003004C))
+#define TIMER0_TAV_R            (*((volatile uint32_t *)0x40030050))
+#define TIMER0_TBV_R            (*((volatile uint32_t *)0x40030054))
+#define TIMER0_RTCPD_R          (*((volatile uint32_t *)0x40030058))
+#define TIMER0_TAPS_R           (*((volatile uint32_t *)0x4003005C))
+#define TIMER0_TBPS_R           (*((volatile uint32_t *)0x40030060))
+#define TIMER0_TAPV_R           (*((volatile uint32_t *)0x40030064))
+#define TIMER0_TBPV_R           (*((volatile uint32_t *)0x40030068))
+#define TIMER0_PP_R             (*((volatile uint32_t *)0x40030FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER1)
+//
+//*****************************************************************************
+#define TIMER1_CFG_R            (*((volatile uint32_t *)0x40031000))
+#define TIMER1_TAMR_R           (*((volatile uint32_t *)0x40031004))
+#define TIMER1_TBMR_R           (*((volatile uint32_t *)0x40031008))
+#define TIMER1_CTL_R            (*((volatile uint32_t *)0x4003100C))
+#define TIMER1_SYNC_R           (*((volatile uint32_t *)0x40031010))
+#define TIMER1_IMR_R            (*((volatile uint32_t *)0x40031018))
+#define TIMER1_RIS_R            (*((volatile uint32_t *)0x4003101C))
+#define TIMER1_MIS_R            (*((volatile uint32_t *)0x40031020))
+#define TIMER1_ICR_R            (*((volatile uint32_t *)0x40031024))
+#define TIMER1_TAILR_R          (*((volatile uint32_t *)0x40031028))
+#define TIMER1_TBILR_R          (*((volatile uint32_t *)0x4003102C))
+#define TIMER1_TAMATCHR_R       (*((volatile uint32_t *)0x40031030))
+#define TIMER1_TBMATCHR_R       (*((volatile uint32_t *)0x40031034))
+#define TIMER1_TAPR_R           (*((volatile uint32_t *)0x40031038))
+#define TIMER1_TBPR_R           (*((volatile uint32_t *)0x4003103C))
+#define TIMER1_TAPMR_R          (*((volatile uint32_t *)0x40031040))
+#define TIMER1_TBPMR_R          (*((volatile uint32_t *)0x40031044))
+#define TIMER1_TAR_R            (*((volatile uint32_t *)0x40031048))
+#define TIMER1_TBR_R            (*((volatile uint32_t *)0x4003104C))
+#define TIMER1_TAV_R            (*((volatile uint32_t *)0x40031050))
+#define TIMER1_TBV_R            (*((volatile uint32_t *)0x40031054))
+#define TIMER1_RTCPD_R          (*((volatile uint32_t *)0x40031058))
+#define TIMER1_TAPS_R           (*((volatile uint32_t *)0x4003105C))
+#define TIMER1_TBPS_R           (*((volatile uint32_t *)0x40031060))
+#define TIMER1_TAPV_R           (*((volatile uint32_t *)0x40031064))
+#define TIMER1_TBPV_R           (*((volatile uint32_t *)0x40031068))
+#define TIMER1_PP_R             (*((volatile uint32_t *)0x40031FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER2)
+//
+//*****************************************************************************
+#define TIMER2_CFG_R            (*((volatile uint32_t *)0x40032000))
+#define TIMER2_TAMR_R           (*((volatile uint32_t *)0x40032004))
+#define TIMER2_TBMR_R           (*((volatile uint32_t *)0x40032008))
+#define TIMER2_CTL_R            (*((volatile uint32_t *)0x4003200C))
+#define TIMER2_SYNC_R           (*((volatile uint32_t *)0x40032010))
+#define TIMER2_IMR_R            (*((volatile uint32_t *)0x40032018))
+#define TIMER2_RIS_R            (*((volatile uint32_t *)0x4003201C))
+#define TIMER2_MIS_R            (*((volatile uint32_t *)0x40032020))
+#define TIMER2_ICR_R            (*((volatile uint32_t *)0x40032024))
+#define TIMER2_TAILR_R          (*((volatile uint32_t *)0x40032028))
+#define TIMER2_TBILR_R          (*((volatile uint32_t *)0x4003202C))
+#define TIMER2_TAMATCHR_R       (*((volatile uint32_t *)0x40032030))
+#define TIMER2_TBMATCHR_R       (*((volatile uint32_t *)0x40032034))
+#define TIMER2_TAPR_R           (*((volatile uint32_t *)0x40032038))
+#define TIMER2_TBPR_R           (*((volatile uint32_t *)0x4003203C))
+#define TIMER2_TAPMR_R          (*((volatile uint32_t *)0x40032040))
+#define TIMER2_TBPMR_R          (*((volatile uint32_t *)0x40032044))
+#define TIMER2_TAR_R            (*((volatile uint32_t *)0x40032048))
+#define TIMER2_TBR_R            (*((volatile uint32_t *)0x4003204C))
+#define TIMER2_TAV_R            (*((volatile uint32_t *)0x40032050))
+#define TIMER2_TBV_R            (*((volatile uint32_t *)0x40032054))
+#define TIMER2_RTCPD_R          (*((volatile uint32_t *)0x40032058))
+#define TIMER2_TAPS_R           (*((volatile uint32_t *)0x4003205C))
+#define TIMER2_TBPS_R           (*((volatile uint32_t *)0x40032060))
+#define TIMER2_TAPV_R           (*((volatile uint32_t *)0x40032064))
+#define TIMER2_TBPV_R           (*((volatile uint32_t *)0x40032068))
+#define TIMER2_PP_R             (*((volatile uint32_t *)0x40032FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER3)
+//
+//*****************************************************************************
+#define TIMER3_CFG_R            (*((volatile uint32_t *)0x40033000))
+#define TIMER3_TAMR_R           (*((volatile uint32_t *)0x40033004))
+#define TIMER3_TBMR_R           (*((volatile uint32_t *)0x40033008))
+#define TIMER3_CTL_R            (*((volatile uint32_t *)0x4003300C))
+#define TIMER3_SYNC_R           (*((volatile uint32_t *)0x40033010))
+#define TIMER3_IMR_R            (*((volatile uint32_t *)0x40033018))
+#define TIMER3_RIS_R            (*((volatile uint32_t *)0x4003301C))
+#define TIMER3_MIS_R            (*((volatile uint32_t *)0x40033020))
+#define TIMER3_ICR_R            (*((volatile uint32_t *)0x40033024))
+#define TIMER3_TAILR_R          (*((volatile uint32_t *)0x40033028))
+#define TIMER3_TBILR_R          (*((volatile uint32_t *)0x4003302C))
+#define TIMER3_TAMATCHR_R       (*((volatile uint32_t *)0x40033030))
+#define TIMER3_TBMATCHR_R       (*((volatile uint32_t *)0x40033034))
+#define TIMER3_TAPR_R           (*((volatile uint32_t *)0x40033038))
+#define TIMER3_TBPR_R           (*((volatile uint32_t *)0x4003303C))
+#define TIMER3_TAPMR_R          (*((volatile uint32_t *)0x40033040))
+#define TIMER3_TBPMR_R          (*((volatile uint32_t *)0x40033044))
+#define TIMER3_TAR_R            (*((volatile uint32_t *)0x40033048))
+#define TIMER3_TBR_R            (*((volatile uint32_t *)0x4003304C))
+#define TIMER3_TAV_R            (*((volatile uint32_t *)0x40033050))
+#define TIMER3_TBV_R            (*((volatile uint32_t *)0x40033054))
+#define TIMER3_RTCPD_R          (*((volatile uint32_t *)0x40033058))
+#define TIMER3_TAPS_R           (*((volatile uint32_t *)0x4003305C))
+#define TIMER3_TBPS_R           (*((volatile uint32_t *)0x40033060))
+#define TIMER3_TAPV_R           (*((volatile uint32_t *)0x40033064))
+#define TIMER3_TBPV_R           (*((volatile uint32_t *)0x40033068))
+#define TIMER3_PP_R             (*((volatile uint32_t *)0x40033FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER4)
+//
+//*****************************************************************************
+#define TIMER4_CFG_R            (*((volatile uint32_t *)0x40034000))
+#define TIMER4_TAMR_R           (*((volatile uint32_t *)0x40034004))
+#define TIMER4_TBMR_R           (*((volatile uint32_t *)0x40034008))
+#define TIMER4_CTL_R            (*((volatile uint32_t *)0x4003400C))
+#define TIMER4_SYNC_R           (*((volatile uint32_t *)0x40034010))
+#define TIMER4_IMR_R            (*((volatile uint32_t *)0x40034018))
+#define TIMER4_RIS_R            (*((volatile uint32_t *)0x4003401C))
+#define TIMER4_MIS_R            (*((volatile uint32_t *)0x40034020))
+#define TIMER4_ICR_R            (*((volatile uint32_t *)0x40034024))
+#define TIMER4_TAILR_R          (*((volatile uint32_t *)0x40034028))
+#define TIMER4_TBILR_R          (*((volatile uint32_t *)0x4003402C))
+#define TIMER4_TAMATCHR_R       (*((volatile uint32_t *)0x40034030))
+#define TIMER4_TBMATCHR_R       (*((volatile uint32_t *)0x40034034))
+#define TIMER4_TAPR_R           (*((volatile uint32_t *)0x40034038))
+#define TIMER4_TBPR_R           (*((volatile uint32_t *)0x4003403C))
+#define TIMER4_TAPMR_R          (*((volatile uint32_t *)0x40034040))
+#define TIMER4_TBPMR_R          (*((volatile uint32_t *)0x40034044))
+#define TIMER4_TAR_R            (*((volatile uint32_t *)0x40034048))
+#define TIMER4_TBR_R            (*((volatile uint32_t *)0x4003404C))
+#define TIMER4_TAV_R            (*((volatile uint32_t *)0x40034050))
+#define TIMER4_TBV_R            (*((volatile uint32_t *)0x40034054))
+#define TIMER4_RTCPD_R          (*((volatile uint32_t *)0x40034058))
+#define TIMER4_TAPS_R           (*((volatile uint32_t *)0x4003405C))
+#define TIMER4_TBPS_R           (*((volatile uint32_t *)0x40034060))
+#define TIMER4_TAPV_R           (*((volatile uint32_t *)0x40034064))
+#define TIMER4_TBPV_R           (*((volatile uint32_t *)0x40034068))
+#define TIMER4_PP_R             (*((volatile uint32_t *)0x40034FC0))
+
+//*****************************************************************************
+//
+// Timer registers (TIMER5)
+//
+//*****************************************************************************
+#define TIMER5_CFG_R            (*((volatile uint32_t *)0x40035000))
+#define TIMER5_TAMR_R           (*((volatile uint32_t *)0x40035004))
+#define TIMER5_TBMR_R           (*((volatile uint32_t *)0x40035008))
+#define TIMER5_CTL_R            (*((volatile uint32_t *)0x4003500C))
+#define TIMER5_SYNC_R           (*((volatile uint32_t *)0x40035010))
+#define TIMER5_IMR_R            (*((volatile uint32_t *)0x40035018))
+#define TIMER5_RIS_R            (*((volatile uint32_t *)0x4003501C))
+#define TIMER5_MIS_R            (*((volatile uint32_t *)0x40035020))
+#define TIMER5_ICR_R            (*((volatile uint32_t *)0x40035024))
+#define TIMER5_TAILR_R          (*((volatile uint32_t *)0x40035028))
+#define TIMER5_TBILR_R          (*((volatile uint32_t *)0x4003502C))
+#define TIMER5_TAMATCHR_R       (*((volatile uint32_t *)0x40035030))
+#define TIMER5_TBMATCHR_R       (*((volatile uint32_t *)0x40035034))
+#define TIMER5_TAPR_R           (*((volatile uint32_t *)0x40035038))
+#define TIMER5_TBPR_R           (*((volatile uint32_t *)0x4003503C))
+#define TIMER5_TAPMR_R          (*((volatile uint32_t *)0x40035040))
+#define TIMER5_TBPMR_R          (*((volatile uint32_t *)0x40035044))
+#define TIMER5_TAR_R            (*((volatile uint32_t *)0x40035048))
+#define TIMER5_TBR_R            (*((volatile uint32_t *)0x4003504C))
+#define TIMER5_TAV_R            (*((volatile uint32_t *)0x40035050))
+#define TIMER5_TBV_R            (*((volatile uint32_t *)0x40035054))
+#define TIMER5_RTCPD_R          (*((volatile uint32_t *)0x40035058))
+#define TIMER5_TAPS_R           (*((volatile uint32_t *)0x4003505C))
+#define TIMER5_TBPS_R           (*((volatile uint32_t *)0x40035060))
+#define TIMER5_TAPV_R           (*((volatile uint32_t *)0x40035064))
+#define TIMER5_TBPV_R           (*((volatile uint32_t *)0x40035068))
+#define TIMER5_PP_R             (*((volatile uint32_t *)0x40035FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER0)
+//
+//*****************************************************************************
+#define WTIMER0_CFG_R           (*((volatile uint32_t *)0x40036000))
+#define WTIMER0_TAMR_R          (*((volatile uint32_t *)0x40036004))
+#define WTIMER0_TBMR_R          (*((volatile uint32_t *)0x40036008))
+#define WTIMER0_CTL_R           (*((volatile uint32_t *)0x4003600C))
+#define WTIMER0_SYNC_R          (*((volatile uint32_t *)0x40036010))
+#define WTIMER0_IMR_R           (*((volatile uint32_t *)0x40036018))
+#define WTIMER0_RIS_R           (*((volatile uint32_t *)0x4003601C))
+#define WTIMER0_MIS_R           (*((volatile uint32_t *)0x40036020))
+#define WTIMER0_ICR_R           (*((volatile uint32_t *)0x40036024))
+#define WTIMER0_TAILR_R         (*((volatile uint32_t *)0x40036028))
+#define WTIMER0_TBILR_R         (*((volatile uint32_t *)0x4003602C))
+#define WTIMER0_TAMATCHR_R      (*((volatile uint32_t *)0x40036030))
+#define WTIMER0_TBMATCHR_R      (*((volatile uint32_t *)0x40036034))
+#define WTIMER0_TAPR_R          (*((volatile uint32_t *)0x40036038))
+#define WTIMER0_TBPR_R          (*((volatile uint32_t *)0x4003603C))
+#define WTIMER0_TAPMR_R         (*((volatile uint32_t *)0x40036040))
+#define WTIMER0_TBPMR_R         (*((volatile uint32_t *)0x40036044))
+#define WTIMER0_TAR_R           (*((volatile uint32_t *)0x40036048))
+#define WTIMER0_TBR_R           (*((volatile uint32_t *)0x4003604C))
+#define WTIMER0_TAV_R           (*((volatile uint32_t *)0x40036050))
+#define WTIMER0_TBV_R           (*((volatile uint32_t *)0x40036054))
+#define WTIMER0_RTCPD_R         (*((volatile uint32_t *)0x40036058))
+#define WTIMER0_TAPS_R          (*((volatile uint32_t *)0x4003605C))
+#define WTIMER0_TBPS_R          (*((volatile uint32_t *)0x40036060))
+#define WTIMER0_TAPV_R          (*((volatile uint32_t *)0x40036064))
+#define WTIMER0_TBPV_R          (*((volatile uint32_t *)0x40036068))
+#define WTIMER0_PP_R            (*((volatile uint32_t *)0x40036FC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER1)
+//
+//*****************************************************************************
+#define WTIMER1_CFG_R           (*((volatile uint32_t *)0x40037000))
+#define WTIMER1_TAMR_R          (*((volatile uint32_t *)0x40037004))
+#define WTIMER1_TBMR_R          (*((volatile uint32_t *)0x40037008))
+#define WTIMER1_CTL_R           (*((volatile uint32_t *)0x4003700C))
+#define WTIMER1_SYNC_R          (*((volatile uint32_t *)0x40037010))
+#define WTIMER1_IMR_R           (*((volatile uint32_t *)0x40037018))
+#define WTIMER1_RIS_R           (*((volatile uint32_t *)0x4003701C))
+#define WTIMER1_MIS_R           (*((volatile uint32_t *)0x40037020))
+#define WTIMER1_ICR_R           (*((volatile uint32_t *)0x40037024))
+#define WTIMER1_TAILR_R         (*((volatile uint32_t *)0x40037028))
+#define WTIMER1_TBILR_R         (*((volatile uint32_t *)0x4003702C))
+#define WTIMER1_TAMATCHR_R      (*((volatile uint32_t *)0x40037030))
+#define WTIMER1_TBMATCHR_R      (*((volatile uint32_t *)0x40037034))
+#define WTIMER1_TAPR_R          (*((volatile uint32_t *)0x40037038))
+#define WTIMER1_TBPR_R          (*((volatile uint32_t *)0x4003703C))
+#define WTIMER1_TAPMR_R         (*((volatile uint32_t *)0x40037040))
+#define WTIMER1_TBPMR_R         (*((volatile uint32_t *)0x40037044))
+#define WTIMER1_TAR_R           (*((volatile uint32_t *)0x40037048))
+#define WTIMER1_TBR_R           (*((volatile uint32_t *)0x4003704C))
+#define WTIMER1_TAV_R           (*((volatile uint32_t *)0x40037050))
+#define WTIMER1_TBV_R           (*((volatile uint32_t *)0x40037054))
+#define WTIMER1_RTCPD_R         (*((volatile uint32_t *)0x40037058))
+#define WTIMER1_TAPS_R          (*((volatile uint32_t *)0x4003705C))
+#define WTIMER1_TBPS_R          (*((volatile uint32_t *)0x40037060))
+#define WTIMER1_TAPV_R          (*((volatile uint32_t *)0x40037064))
+#define WTIMER1_TBPV_R          (*((volatile uint32_t *)0x40037068))
+#define WTIMER1_PP_R            (*((volatile uint32_t *)0x40037FC0))
+
+//*****************************************************************************
+//
+// ADC registers (ADC0)
+//
+//*****************************************************************************
+#define ADC0_ACTSS_R            (*((volatile uint32_t *)0x40038000))
+#define ADC0_RIS_R              (*((volatile uint32_t *)0x40038004))
+#define ADC0_IM_R               (*((volatile uint32_t *)0x40038008))
+#define ADC0_ISC_R              (*((volatile uint32_t *)0x4003800C))
+#define ADC0_OSTAT_R            (*((volatile uint32_t *)0x40038010))
+#define ADC0_EMUX_R             (*((volatile uint32_t *)0x40038014))
+#define ADC0_USTAT_R            (*((volatile uint32_t *)0x40038018))
+#define ADC0_TSSEL_R            (*((volatile uint32_t *)0x4003801C))
+#define ADC0_SSPRI_R            (*((volatile uint32_t *)0x40038020))
+#define ADC0_SPC_R              (*((volatile uint32_t *)0x40038024))
+#define ADC0_PSSI_R             (*((volatile uint32_t *)0x40038028))
+#define ADC0_SAC_R              (*((volatile uint32_t *)0x40038030))
+#define ADC0_DCISC_R            (*((volatile uint32_t *)0x40038034))
+#define ADC0_CTL_R              (*((volatile uint32_t *)0x40038038))
+#define ADC0_SSMUX0_R           (*((volatile uint32_t *)0x40038040))
+#define ADC0_SSCTL0_R           (*((volatile uint32_t *)0x40038044))
+#define ADC0_SSFIFO0_R          (*((volatile uint32_t *)0x40038048))
+#define ADC0_SSFSTAT0_R         (*((volatile uint32_t *)0x4003804C))
+#define ADC0_SSOP0_R            (*((volatile uint32_t *)0x40038050))
+#define ADC0_SSDC0_R            (*((volatile uint32_t *)0x40038054))
+#define ADC0_SSMUX1_R           (*((volatile uint32_t *)0x40038060))
+#define ADC0_SSCTL1_R           (*((volatile uint32_t *)0x40038064))
+#define ADC0_SSFIFO1_R          (*((volatile uint32_t *)0x40038068))
+#define ADC0_SSFSTAT1_R         (*((volatile uint32_t *)0x4003806C))
+#define ADC0_SSOP1_R            (*((volatile uint32_t *)0x40038070))
+#define ADC0_SSDC1_R            (*((volatile uint32_t *)0x40038074))
+#define ADC0_SSMUX2_R           (*((volatile uint32_t *)0x40038080))
+#define ADC0_SSCTL2_R           (*((volatile uint32_t *)0x40038084))
+#define ADC0_SSFIFO2_R          (*((volatile uint32_t *)0x40038088))
+#define ADC0_SSFSTAT2_R         (*((volatile uint32_t *)0x4003808C))
+#define ADC0_SSOP2_R            (*((volatile uint32_t *)0x40038090))
+#define ADC0_SSDC2_R            (*((volatile uint32_t *)0x40038094))
+#define ADC0_SSMUX3_R           (*((volatile uint32_t *)0x400380A0))
+#define ADC0_SSCTL3_R           (*((volatile uint32_t *)0x400380A4))
+#define ADC0_SSFIFO3_R          (*((volatile uint32_t *)0x400380A8))
+#define ADC0_SSFSTAT3_R         (*((volatile uint32_t *)0x400380AC))
+#define ADC0_SSOP3_R            (*((volatile uint32_t *)0x400380B0))
+#define ADC0_SSDC3_R            (*((volatile uint32_t *)0x400380B4))
+#define ADC0_DCRIC_R            (*((volatile uint32_t *)0x40038D00))
+#define ADC0_DCCTL0_R           (*((volatile uint32_t *)0x40038E00))
+#define ADC0_DCCTL1_R           (*((volatile uint32_t *)0x40038E04))
+#define ADC0_DCCTL2_R           (*((volatile uint32_t *)0x40038E08))
+#define ADC0_DCCTL3_R           (*((volatile uint32_t *)0x40038E0C))
+#define ADC0_DCCTL4_R           (*((volatile uint32_t *)0x40038E10))
+#define ADC0_DCCTL5_R           (*((volatile uint32_t *)0x40038E14))
+#define ADC0_DCCTL6_R           (*((volatile uint32_t *)0x40038E18))
+#define ADC0_DCCTL7_R           (*((volatile uint32_t *)0x40038E1C))
+#define ADC0_DCCMP0_R           (*((volatile uint32_t *)0x40038E40))
+#define ADC0_DCCMP1_R           (*((volatile uint32_t *)0x40038E44))
+#define ADC0_DCCMP2_R           (*((volatile uint32_t *)0x40038E48))
+#define ADC0_DCCMP3_R           (*((volatile uint32_t *)0x40038E4C))
+#define ADC0_DCCMP4_R           (*((volatile uint32_t *)0x40038E50))
+#define ADC0_DCCMP5_R           (*((volatile uint32_t *)0x40038E54))
+#define ADC0_DCCMP6_R           (*((volatile uint32_t *)0x40038E58))
+#define ADC0_DCCMP7_R           (*((volatile uint32_t *)0x40038E5C))
+#define ADC0_PP_R               (*((volatile uint32_t *)0x40038FC0))
+#define ADC0_PC_R               (*((volatile uint32_t *)0x40038FC4))
+#define ADC0_CC_R               (*((volatile uint32_t *)0x40038FC8))
+
+//*****************************************************************************
+//
+// ADC registers (ADC1)
+//
+//*****************************************************************************
+#define ADC1_ACTSS_R            (*((volatile uint32_t *)0x40039000))
+#define ADC1_RIS_R              (*((volatile uint32_t *)0x40039004))
+#define ADC1_IM_R               (*((volatile uint32_t *)0x40039008))
+#define ADC1_ISC_R              (*((volatile uint32_t *)0x4003900C))
+#define ADC1_OSTAT_R            (*((volatile uint32_t *)0x40039010))
+#define ADC1_EMUX_R             (*((volatile uint32_t *)0x40039014))
+#define ADC1_USTAT_R            (*((volatile uint32_t *)0x40039018))
+#define ADC1_TSSEL_R            (*((volatile uint32_t *)0x4003901C))
+#define ADC1_SSPRI_R            (*((volatile uint32_t *)0x40039020))
+#define ADC1_SPC_R              (*((volatile uint32_t *)0x40039024))
+#define ADC1_PSSI_R             (*((volatile uint32_t *)0x40039028))
+#define ADC1_SAC_R              (*((volatile uint32_t *)0x40039030))
+#define ADC1_DCISC_R            (*((volatile uint32_t *)0x40039034))
+#define ADC1_CTL_R              (*((volatile uint32_t *)0x40039038))
+#define ADC1_SSMUX0_R           (*((volatile uint32_t *)0x40039040))
+#define ADC1_SSCTL0_R           (*((volatile uint32_t *)0x40039044))
+#define ADC1_SSFIFO0_R          (*((volatile uint32_t *)0x40039048))
+#define ADC1_SSFSTAT0_R         (*((volatile uint32_t *)0x4003904C))
+#define ADC1_SSOP0_R            (*((volatile uint32_t *)0x40039050))
+#define ADC1_SSDC0_R            (*((volatile uint32_t *)0x40039054))
+#define ADC1_SSMUX1_R           (*((volatile uint32_t *)0x40039060))
+#define ADC1_SSCTL1_R           (*((volatile uint32_t *)0x40039064))
+#define ADC1_SSFIFO1_R          (*((volatile uint32_t *)0x40039068))
+#define ADC1_SSFSTAT1_R         (*((volatile uint32_t *)0x4003906C))
+#define ADC1_SSOP1_R            (*((volatile uint32_t *)0x40039070))
+#define ADC1_SSDC1_R            (*((volatile uint32_t *)0x40039074))
+#define ADC1_SSMUX2_R           (*((volatile uint32_t *)0x40039080))
+#define ADC1_SSCTL2_R           (*((volatile uint32_t *)0x40039084))
+#define ADC1_SSFIFO2_R          (*((volatile uint32_t *)0x40039088))
+#define ADC1_SSFSTAT2_R         (*((volatile uint32_t *)0x4003908C))
+#define ADC1_SSOP2_R            (*((volatile uint32_t *)0x40039090))
+#define ADC1_SSDC2_R            (*((volatile uint32_t *)0x40039094))
+#define ADC1_SSMUX3_R           (*((volatile uint32_t *)0x400390A0))
+#define ADC1_SSCTL3_R           (*((volatile uint32_t *)0x400390A4))
+#define ADC1_SSFIFO3_R          (*((volatile uint32_t *)0x400390A8))
+#define ADC1_SSFSTAT3_R         (*((volatile uint32_t *)0x400390AC))
+#define ADC1_SSOP3_R            (*((volatile uint32_t *)0x400390B0))
+#define ADC1_SSDC3_R            (*((volatile uint32_t *)0x400390B4))
+#define ADC1_DCRIC_R            (*((volatile uint32_t *)0x40039D00))
+#define ADC1_DCCTL0_R           (*((volatile uint32_t *)0x40039E00))
+#define ADC1_DCCTL1_R           (*((volatile uint32_t *)0x40039E04))
+#define ADC1_DCCTL2_R           (*((volatile uint32_t *)0x40039E08))
+#define ADC1_DCCTL3_R           (*((volatile uint32_t *)0x40039E0C))
+#define ADC1_DCCTL4_R           (*((volatile uint32_t *)0x40039E10))
+#define ADC1_DCCTL5_R           (*((volatile uint32_t *)0x40039E14))
+#define ADC1_DCCTL6_R           (*((volatile uint32_t *)0x40039E18))
+#define ADC1_DCCTL7_R           (*((volatile uint32_t *)0x40039E1C))
+#define ADC1_DCCMP0_R           (*((volatile uint32_t *)0x40039E40))
+#define ADC1_DCCMP1_R           (*((volatile uint32_t *)0x40039E44))
+#define ADC1_DCCMP2_R           (*((volatile uint32_t *)0x40039E48))
+#define ADC1_DCCMP3_R           (*((volatile uint32_t *)0x40039E4C))
+#define ADC1_DCCMP4_R           (*((volatile uint32_t *)0x40039E50))
+#define ADC1_DCCMP5_R           (*((volatile uint32_t *)0x40039E54))
+#define ADC1_DCCMP6_R           (*((volatile uint32_t *)0x40039E58))
+#define ADC1_DCCMP7_R           (*((volatile uint32_t *)0x40039E5C))
+#define ADC1_PP_R               (*((volatile uint32_t *)0x40039FC0))
+#define ADC1_PC_R               (*((volatile uint32_t *)0x40039FC4))
+#define ADC1_CC_R               (*((volatile uint32_t *)0x40039FC8))
+
+//*****************************************************************************
+//
+// Comparator registers (COMP)
+//
+//*****************************************************************************
+#define COMP_ACMIS_R            (*((volatile uint32_t *)0x4003C000))
+#define COMP_ACRIS_R            (*((volatile uint32_t *)0x4003C004))
+#define COMP_ACINTEN_R          (*((volatile uint32_t *)0x4003C008))
+#define COMP_ACREFCTL_R         (*((volatile uint32_t *)0x4003C010))
+#define COMP_ACSTAT0_R          (*((volatile uint32_t *)0x4003C020))
+#define COMP_ACCTL0_R           (*((volatile uint32_t *)0x4003C024))
+#define COMP_ACSTAT1_R          (*((volatile uint32_t *)0x4003C040))
+#define COMP_ACCTL1_R           (*((volatile uint32_t *)0x4003C044))
+#define COMP_PP_R               (*((volatile uint32_t *)0x4003CFC0))
+
+//*****************************************************************************
+//
+// CAN registers (CAN0)
+//
+//*****************************************************************************
+#define CAN0_CTL_R              (*((volatile uint32_t *)0x40040000))
+#define CAN0_STS_R              (*((volatile uint32_t *)0x40040004))
+#define CAN0_ERR_R              (*((volatile uint32_t *)0x40040008))
+#define CAN0_BIT_R              (*((volatile uint32_t *)0x4004000C))
+#define CAN0_INT_R              (*((volatile uint32_t *)0x40040010))
+#define CAN0_TST_R              (*((volatile uint32_t *)0x40040014))
+#define CAN0_BRPE_R             (*((volatile uint32_t *)0x40040018))
+#define CAN0_IF1CRQ_R           (*((volatile uint32_t *)0x40040020))
+#define CAN0_IF1CMSK_R          (*((volatile uint32_t *)0x40040024))
+#define CAN0_IF1MSK1_R          (*((volatile uint32_t *)0x40040028))
+#define CAN0_IF1MSK2_R          (*((volatile uint32_t *)0x4004002C))
+#define CAN0_IF1ARB1_R          (*((volatile uint32_t *)0x40040030))
+#define CAN0_IF1ARB2_R          (*((volatile uint32_t *)0x40040034))
+#define CAN0_IF1MCTL_R          (*((volatile uint32_t *)0x40040038))
+#define CAN0_IF1DA1_R           (*((volatile uint32_t *)0x4004003C))
+#define CAN0_IF1DA2_R           (*((volatile uint32_t *)0x40040040))
+#define CAN0_IF1DB1_R           (*((volatile uint32_t *)0x40040044))
+#define CAN0_IF1DB2_R           (*((volatile uint32_t *)0x40040048))
+#define CAN0_IF2CRQ_R           (*((volatile uint32_t *)0x40040080))
+#define CAN0_IF2CMSK_R          (*((volatile uint32_t *)0x40040084))
+#define CAN0_IF2MSK1_R          (*((volatile uint32_t *)0x40040088))
+#define CAN0_IF2MSK2_R          (*((volatile uint32_t *)0x4004008C))
+#define CAN0_IF2ARB1_R          (*((volatile uint32_t *)0x40040090))
+#define CAN0_IF2ARB2_R          (*((volatile uint32_t *)0x40040094))
+#define CAN0_IF2MCTL_R          (*((volatile uint32_t *)0x40040098))
+#define CAN0_IF2DA1_R           (*((volatile uint32_t *)0x4004009C))
+#define CAN0_IF2DA2_R           (*((volatile uint32_t *)0x400400A0))
+#define CAN0_IF2DB1_R           (*((volatile uint32_t *)0x400400A4))
+#define CAN0_IF2DB2_R           (*((volatile uint32_t *)0x400400A8))
+#define CAN0_TXRQ1_R            (*((volatile uint32_t *)0x40040100))
+#define CAN0_TXRQ2_R            (*((volatile uint32_t *)0x40040104))
+#define CAN0_NWDA1_R            (*((volatile uint32_t *)0x40040120))
+#define CAN0_NWDA2_R            (*((volatile uint32_t *)0x40040124))
+#define CAN0_MSG1INT_R          (*((volatile uint32_t *)0x40040140))
+#define CAN0_MSG2INT_R          (*((volatile uint32_t *)0x40040144))
+#define CAN0_MSG1VAL_R          (*((volatile uint32_t *)0x40040160))
+#define CAN0_MSG2VAL_R          (*((volatile uint32_t *)0x40040164))
+
+//*****************************************************************************
+//
+// CAN registers (CAN1)
+//
+//*****************************************************************************
+#define CAN1_CTL_R              (*((volatile uint32_t *)0x40041000))
+#define CAN1_STS_R              (*((volatile uint32_t *)0x40041004))
+#define CAN1_ERR_R              (*((volatile uint32_t *)0x40041008))
+#define CAN1_BIT_R              (*((volatile uint32_t *)0x4004100C))
+#define CAN1_INT_R              (*((volatile uint32_t *)0x40041010))
+#define CAN1_TST_R              (*((volatile uint32_t *)0x40041014))
+#define CAN1_BRPE_R             (*((volatile uint32_t *)0x40041018))
+#define CAN1_IF1CRQ_R           (*((volatile uint32_t *)0x40041020))
+#define CAN1_IF1CMSK_R          (*((volatile uint32_t *)0x40041024))
+#define CAN1_IF1MSK1_R          (*((volatile uint32_t *)0x40041028))
+#define CAN1_IF1MSK2_R          (*((volatile uint32_t *)0x4004102C))
+#define CAN1_IF1ARB1_R          (*((volatile uint32_t *)0x40041030))
+#define CAN1_IF1ARB2_R          (*((volatile uint32_t *)0x40041034))
+#define CAN1_IF1MCTL_R          (*((volatile uint32_t *)0x40041038))
+#define CAN1_IF1DA1_R           (*((volatile uint32_t *)0x4004103C))
+#define CAN1_IF1DA2_R           (*((volatile uint32_t *)0x40041040))
+#define CAN1_IF1DB1_R           (*((volatile uint32_t *)0x40041044))
+#define CAN1_IF1DB2_R           (*((volatile uint32_t *)0x40041048))
+#define CAN1_IF2CRQ_R           (*((volatile uint32_t *)0x40041080))
+#define CAN1_IF2CMSK_R          (*((volatile uint32_t *)0x40041084))
+#define CAN1_IF2MSK1_R          (*((volatile uint32_t *)0x40041088))
+#define CAN1_IF2MSK2_R          (*((volatile uint32_t *)0x4004108C))
+#define CAN1_IF2ARB1_R          (*((volatile uint32_t *)0x40041090))
+#define CAN1_IF2ARB2_R          (*((volatile uint32_t *)0x40041094))
+#define CAN1_IF2MCTL_R          (*((volatile uint32_t *)0x40041098))
+#define CAN1_IF2DA1_R           (*((volatile uint32_t *)0x4004109C))
+#define CAN1_IF2DA2_R           (*((volatile uint32_t *)0x400410A0))
+#define CAN1_IF2DB1_R           (*((volatile uint32_t *)0x400410A4))
+#define CAN1_IF2DB2_R           (*((volatile uint32_t *)0x400410A8))
+#define CAN1_TXRQ1_R            (*((volatile uint32_t *)0x40041100))
+#define CAN1_TXRQ2_R            (*((volatile uint32_t *)0x40041104))
+#define CAN1_NWDA1_R            (*((volatile uint32_t *)0x40041120))
+#define CAN1_NWDA2_R            (*((volatile uint32_t *)0x40041124))
+#define CAN1_MSG1INT_R          (*((volatile uint32_t *)0x40041140))
+#define CAN1_MSG2INT_R          (*((volatile uint32_t *)0x40041144))
+#define CAN1_MSG1VAL_R          (*((volatile uint32_t *)0x40041160))
+#define CAN1_MSG2VAL_R          (*((volatile uint32_t *)0x40041164))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER2)
+//
+//*****************************************************************************
+#define WTIMER2_CFG_R           (*((volatile uint32_t *)0x4004C000))
+#define WTIMER2_TAMR_R          (*((volatile uint32_t *)0x4004C004))
+#define WTIMER2_TBMR_R          (*((volatile uint32_t *)0x4004C008))
+#define WTIMER2_CTL_R           (*((volatile uint32_t *)0x4004C00C))
+#define WTIMER2_SYNC_R          (*((volatile uint32_t *)0x4004C010))
+#define WTIMER2_IMR_R           (*((volatile uint32_t *)0x4004C018))
+#define WTIMER2_RIS_R           (*((volatile uint32_t *)0x4004C01C))
+#define WTIMER2_MIS_R           (*((volatile uint32_t *)0x4004C020))
+#define WTIMER2_ICR_R           (*((volatile uint32_t *)0x4004C024))
+#define WTIMER2_TAILR_R         (*((volatile uint32_t *)0x4004C028))
+#define WTIMER2_TBILR_R         (*((volatile uint32_t *)0x4004C02C))
+#define WTIMER2_TAMATCHR_R      (*((volatile uint32_t *)0x4004C030))
+#define WTIMER2_TBMATCHR_R      (*((volatile uint32_t *)0x4004C034))
+#define WTIMER2_TAPR_R          (*((volatile uint32_t *)0x4004C038))
+#define WTIMER2_TBPR_R          (*((volatile uint32_t *)0x4004C03C))
+#define WTIMER2_TAPMR_R         (*((volatile uint32_t *)0x4004C040))
+#define WTIMER2_TBPMR_R         (*((volatile uint32_t *)0x4004C044))
+#define WTIMER2_TAR_R           (*((volatile uint32_t *)0x4004C048))
+#define WTIMER2_TBR_R           (*((volatile uint32_t *)0x4004C04C))
+#define WTIMER2_TAV_R           (*((volatile uint32_t *)0x4004C050))
+#define WTIMER2_TBV_R           (*((volatile uint32_t *)0x4004C054))
+#define WTIMER2_RTCPD_R         (*((volatile uint32_t *)0x4004C058))
+#define WTIMER2_TAPS_R          (*((volatile uint32_t *)0x4004C05C))
+#define WTIMER2_TBPS_R          (*((volatile uint32_t *)0x4004C060))
+#define WTIMER2_TAPV_R          (*((volatile uint32_t *)0x4004C064))
+#define WTIMER2_TBPV_R          (*((volatile uint32_t *)0x4004C068))
+#define WTIMER2_PP_R            (*((volatile uint32_t *)0x4004CFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER3)
+//
+//*****************************************************************************
+#define WTIMER3_CFG_R           (*((volatile uint32_t *)0x4004D000))
+#define WTIMER3_TAMR_R          (*((volatile uint32_t *)0x4004D004))
+#define WTIMER3_TBMR_R          (*((volatile uint32_t *)0x4004D008))
+#define WTIMER3_CTL_R           (*((volatile uint32_t *)0x4004D00C))
+#define WTIMER3_SYNC_R          (*((volatile uint32_t *)0x4004D010))
+#define WTIMER3_IMR_R           (*((volatile uint32_t *)0x4004D018))
+#define WTIMER3_RIS_R           (*((volatile uint32_t *)0x4004D01C))
+#define WTIMER3_MIS_R           (*((volatile uint32_t *)0x4004D020))
+#define WTIMER3_ICR_R           (*((volatile uint32_t *)0x4004D024))
+#define WTIMER3_TAILR_R         (*((volatile uint32_t *)0x4004D028))
+#define WTIMER3_TBILR_R         (*((volatile uint32_t *)0x4004D02C))
+#define WTIMER3_TAMATCHR_R      (*((volatile uint32_t *)0x4004D030))
+#define WTIMER3_TBMATCHR_R      (*((volatile uint32_t *)0x4004D034))
+#define WTIMER3_TAPR_R          (*((volatile uint32_t *)0x4004D038))
+#define WTIMER3_TBPR_R          (*((volatile uint32_t *)0x4004D03C))
+#define WTIMER3_TAPMR_R         (*((volatile uint32_t *)0x4004D040))
+#define WTIMER3_TBPMR_R         (*((volatile uint32_t *)0x4004D044))
+#define WTIMER3_TAR_R           (*((volatile uint32_t *)0x4004D048))
+#define WTIMER3_TBR_R           (*((volatile uint32_t *)0x4004D04C))
+#define WTIMER3_TAV_R           (*((volatile uint32_t *)0x4004D050))
+#define WTIMER3_TBV_R           (*((volatile uint32_t *)0x4004D054))
+#define WTIMER3_RTCPD_R         (*((volatile uint32_t *)0x4004D058))
+#define WTIMER3_TAPS_R          (*((volatile uint32_t *)0x4004D05C))
+#define WTIMER3_TBPS_R          (*((volatile uint32_t *)0x4004D060))
+#define WTIMER3_TAPV_R          (*((volatile uint32_t *)0x4004D064))
+#define WTIMER3_TBPV_R          (*((volatile uint32_t *)0x4004D068))
+#define WTIMER3_PP_R            (*((volatile uint32_t *)0x4004DFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER4)
+//
+//*****************************************************************************
+#define WTIMER4_CFG_R           (*((volatile uint32_t *)0x4004E000))
+#define WTIMER4_TAMR_R          (*((volatile uint32_t *)0x4004E004))
+#define WTIMER4_TBMR_R          (*((volatile uint32_t *)0x4004E008))
+#define WTIMER4_CTL_R           (*((volatile uint32_t *)0x4004E00C))
+#define WTIMER4_SYNC_R          (*((volatile uint32_t *)0x4004E010))
+#define WTIMER4_IMR_R           (*((volatile uint32_t *)0x4004E018))
+#define WTIMER4_RIS_R           (*((volatile uint32_t *)0x4004E01C))
+#define WTIMER4_MIS_R           (*((volatile uint32_t *)0x4004E020))
+#define WTIMER4_ICR_R           (*((volatile uint32_t *)0x4004E024))
+#define WTIMER4_TAILR_R         (*((volatile uint32_t *)0x4004E028))
+#define WTIMER4_TBILR_R         (*((volatile uint32_t *)0x4004E02C))
+#define WTIMER4_TAMATCHR_R      (*((volatile uint32_t *)0x4004E030))
+#define WTIMER4_TBMATCHR_R      (*((volatile uint32_t *)0x4004E034))
+#define WTIMER4_TAPR_R          (*((volatile uint32_t *)0x4004E038))
+#define WTIMER4_TBPR_R          (*((volatile uint32_t *)0x4004E03C))
+#define WTIMER4_TAPMR_R         (*((volatile uint32_t *)0x4004E040))
+#define WTIMER4_TBPMR_R         (*((volatile uint32_t *)0x4004E044))
+#define WTIMER4_TAR_R           (*((volatile uint32_t *)0x4004E048))
+#define WTIMER4_TBR_R           (*((volatile uint32_t *)0x4004E04C))
+#define WTIMER4_TAV_R           (*((volatile uint32_t *)0x4004E050))
+#define WTIMER4_TBV_R           (*((volatile uint32_t *)0x4004E054))
+#define WTIMER4_RTCPD_R         (*((volatile uint32_t *)0x4004E058))
+#define WTIMER4_TAPS_R          (*((volatile uint32_t *)0x4004E05C))
+#define WTIMER4_TBPS_R          (*((volatile uint32_t *)0x4004E060))
+#define WTIMER4_TAPV_R          (*((volatile uint32_t *)0x4004E064))
+#define WTIMER4_TBPV_R          (*((volatile uint32_t *)0x4004E068))
+#define WTIMER4_PP_R            (*((volatile uint32_t *)0x4004EFC0))
+
+//*****************************************************************************
+//
+// Timer registers (WTIMER5)
+//
+//*****************************************************************************
+#define WTIMER5_CFG_R           (*((volatile uint32_t *)0x4004F000))
+#define WTIMER5_TAMR_R          (*((volatile uint32_t *)0x4004F004))
+#define WTIMER5_TBMR_R          (*((volatile uint32_t *)0x4004F008))
+#define WTIMER5_CTL_R           (*((volatile uint32_t *)0x4004F00C))
+#define WTIMER5_SYNC_R          (*((volatile uint32_t *)0x4004F010))
+#define WTIMER5_IMR_R           (*((volatile uint32_t *)0x4004F018))
+#define WTIMER5_RIS_R           (*((volatile uint32_t *)0x4004F01C))
+#define WTIMER5_MIS_R           (*((volatile uint32_t *)0x4004F020))
+#define WTIMER5_ICR_R           (*((volatile uint32_t *)0x4004F024))
+#define WTIMER5_TAILR_R         (*((volatile uint32_t *)0x4004F028))
+#define WTIMER5_TBILR_R         (*((volatile uint32_t *)0x4004F02C))
+#define WTIMER5_TAMATCHR_R      (*((volatile uint32_t *)0x4004F030))
+#define WTIMER5_TBMATCHR_R      (*((volatile uint32_t *)0x4004F034))
+#define WTIMER5_TAPR_R          (*((volatile uint32_t *)0x4004F038))
+#define WTIMER5_TBPR_R          (*((volatile uint32_t *)0x4004F03C))
+#define WTIMER5_TAPMR_R         (*((volatile uint32_t *)0x4004F040))
+#define WTIMER5_TBPMR_R         (*((volatile uint32_t *)0x4004F044))
+#define WTIMER5_TAR_R           (*((volatile uint32_t *)0x4004F048))
+#define WTIMER5_TBR_R           (*((volatile uint32_t *)0x4004F04C))
+#define WTIMER5_TAV_R           (*((volatile uint32_t *)0x4004F050))
+#define WTIMER5_TBV_R           (*((volatile uint32_t *)0x4004F054))
+#define WTIMER5_RTCPD_R         (*((volatile uint32_t *)0x4004F058))
+#define WTIMER5_TAPS_R          (*((volatile uint32_t *)0x4004F05C))
+#define WTIMER5_TBPS_R          (*((volatile uint32_t *)0x4004F060))
+#define WTIMER5_TAPV_R          (*((volatile uint32_t *)0x4004F064))
+#define WTIMER5_TBPV_R          (*((volatile uint32_t *)0x4004F068))
+#define WTIMER5_PP_R            (*((volatile uint32_t *)0x4004FFC0))
+
+//*****************************************************************************
+//
+// Univeral Serial Bus registers (USB0)
+//
+//*****************************************************************************
+#define USB0_FADDR_R            (*((volatile uint8_t *)0x40050000))
+#define USB0_POWER_R            (*((volatile uint8_t *)0x40050001))
+#define USB0_TXIS_R             (*((volatile uint16_t *)0x40050002))
+#define USB0_RXIS_R             (*((volatile uint16_t *)0x40050004))
+#define USB0_TXIE_R             (*((volatile uint16_t *)0x40050006))
+#define USB0_RXIE_R             (*((volatile uint16_t *)0x40050008))
+#define USB0_IS_R               (*((volatile uint8_t *)0x4005000A))
+#define USB0_IE_R               (*((volatile uint8_t *)0x4005000B))
+#define USB0_FRAME_R            (*((volatile uint16_t *)0x4005000C))
+#define USB0_EPIDX_R            (*((volatile uint8_t *)0x4005000E))
+#define USB0_TEST_R             (*((volatile uint8_t *)0x4005000F))
+#define USB0_FIFO0_R            (*((volatile uint32_t *)0x40050020))
+#define USB0_FIFO1_R            (*((volatile uint32_t *)0x40050024))
+#define USB0_FIFO2_R            (*((volatile uint32_t *)0x40050028))
+#define USB0_FIFO3_R            (*((volatile uint32_t *)0x4005002C))
+#define USB0_FIFO4_R            (*((volatile uint32_t *)0x40050030))
+#define USB0_FIFO5_R            (*((volatile uint32_t *)0x40050034))
+#define USB0_FIFO6_R            (*((volatile uint32_t *)0x40050038))
+#define USB0_FIFO7_R            (*((volatile uint32_t *)0x4005003C))
+#define USB0_DEVCTL_R           (*((volatile uint8_t *)0x40050060))
+#define USB0_TXFIFOSZ_R         (*((volatile uint8_t *)0x40050062))
+#define USB0_RXFIFOSZ_R         (*((volatile uint8_t *)0x40050063))
+#define USB0_TXFIFOADD_R        (*((volatile uint16_t *)0x40050064))
+#define USB0_RXFIFOADD_R        (*((volatile uint16_t *)0x40050066))
+#define USB0_CONTIM_R           (*((volatile uint8_t *)0x4005007A))
+#define USB0_VPLEN_R            (*((volatile uint8_t *)0x4005007B))
+#define USB0_FSEOF_R            (*((volatile uint8_t *)0x4005007D))
+#define USB0_LSEOF_R            (*((volatile uint8_t *)0x4005007E))
+#define USB0_TXFUNCADDR0_R      (*((volatile uint8_t *)0x40050080))
+#define USB0_TXHUBADDR0_R       (*((volatile uint8_t *)0x40050082))
+#define USB0_TXHUBPORT0_R       (*((volatile uint8_t *)0x40050083))
+#define USB0_TXFUNCADDR1_R      (*((volatile uint8_t *)0x40050088))
+#define USB0_TXHUBADDR1_R       (*((volatile uint8_t *)0x4005008A))
+#define USB0_TXHUBPORT1_R       (*((volatile uint8_t *)0x4005008B))
+#define USB0_RXFUNCADDR1_R      (*((volatile uint8_t *)0x4005008C))
+#define USB0_RXHUBADDR1_R       (*((volatile uint8_t *)0x4005008E))
+#define USB0_RXHUBPORT1_R       (*((volatile uint8_t *)0x4005008F))
+#define USB0_TXFUNCADDR2_R      (*((volatile uint8_t *)0x40050090))
+#define USB0_TXHUBADDR2_R       (*((volatile uint8_t *)0x40050092))
+#define USB0_TXHUBPORT2_R       (*((volatile uint8_t *)0x40050093))
+#define USB0_RXFUNCADDR2_R      (*((volatile uint8_t *)0x40050094))
+#define USB0_RXHUBADDR2_R       (*((volatile uint8_t *)0x40050096))
+#define USB0_RXHUBPORT2_R       (*((volatile uint8_t *)0x40050097))
+#define USB0_TXFUNCADDR3_R      (*((volatile uint8_t *)0x40050098))
+#define USB0_TXHUBADDR3_R       (*((volatile uint8_t *)0x4005009A))
+#define USB0_TXHUBPORT3_R       (*((volatile uint8_t *)0x4005009B))
+#define USB0_RXFUNCADDR3_R      (*((volatile uint8_t *)0x4005009C))
+#define USB0_RXHUBADDR3_R       (*((volatile uint8_t *)0x4005009E))
+#define USB0_RXHUBPORT3_R       (*((volatile uint8_t *)0x4005009F))
+#define USB0_TXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A0))
+#define USB0_TXHUBADDR4_R       (*((volatile uint8_t *)0x400500A2))
+#define USB0_TXHUBPORT4_R       (*((volatile uint8_t *)0x400500A3))
+#define USB0_RXFUNCADDR4_R      (*((volatile uint8_t *)0x400500A4))
+#define USB0_RXHUBADDR4_R       (*((volatile uint8_t *)0x400500A6))
+#define USB0_RXHUBPORT4_R       (*((volatile uint8_t *)0x400500A7))
+#define USB0_TXFUNCADDR5_R      (*((volatile uint8_t *)0x400500A8))
+#define USB0_TXHUBADDR5_R       (*((volatile uint8_t *)0x400500AA))
+#define USB0_TXHUBPORT5_R       (*((volatile uint8_t *)0x400500AB))
+#define USB0_RXFUNCADDR5_R      (*((volatile uint8_t *)0x400500AC))
+#define USB0_RXHUBADDR5_R       (*((volatile uint8_t *)0x400500AE))
+#define USB0_RXHUBPORT5_R       (*((volatile uint8_t *)0x400500AF))
+#define USB0_TXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B0))
+#define USB0_TXHUBADDR6_R       (*((volatile uint8_t *)0x400500B2))
+#define USB0_TXHUBPORT6_R       (*((volatile uint8_t *)0x400500B3))
+#define USB0_RXFUNCADDR6_R      (*((volatile uint8_t *)0x400500B4))
+#define USB0_RXHUBADDR6_R       (*((volatile uint8_t *)0x400500B6))
+#define USB0_RXHUBPORT6_R       (*((volatile uint8_t *)0x400500B7))
+#define USB0_TXFUNCADDR7_R      (*((volatile uint8_t *)0x400500B8))
+#define USB0_TXHUBADDR7_R       (*((volatile uint8_t *)0x400500BA))
+#define USB0_TXHUBPORT7_R       (*((volatile uint8_t *)0x400500BB))
+#define USB0_RXFUNCADDR7_R      (*((volatile uint8_t *)0x400500BC))
+#define USB0_RXHUBADDR7_R       (*((volatile uint8_t *)0x400500BE))
+#define USB0_RXHUBPORT7_R       (*((volatile uint8_t *)0x400500BF))
+#define USB0_CSRL0_R            (*((volatile uint8_t *)0x40050102))
+#define USB0_CSRH0_R            (*((volatile uint8_t *)0x40050103))
+#define USB0_COUNT0_R           (*((volatile uint8_t *)0x40050108))
+#define USB0_TYPE0_R            (*((volatile uint8_t *)0x4005010A))
+#define USB0_NAKLMT_R           (*((volatile uint8_t *)0x4005010B))
+#define USB0_TXMAXP1_R          (*((volatile uint16_t *)0x40050110))
+#define USB0_TXCSRL1_R          (*((volatile uint8_t *)0x40050112))
+#define USB0_TXCSRH1_R          (*((volatile uint8_t *)0x40050113))
+#define USB0_RXMAXP1_R          (*((volatile uint16_t *)0x40050114))
+#define USB0_RXCSRL1_R          (*((volatile uint8_t *)0x40050116))
+#define USB0_RXCSRH1_R          (*((volatile uint8_t *)0x40050117))
+#define USB0_RXCOUNT1_R         (*((volatile uint16_t *)0x40050118))
+#define USB0_TXTYPE1_R          (*((volatile uint8_t *)0x4005011A))
+#define USB0_TXINTERVAL1_R      (*((volatile uint8_t *)0x4005011B))
+#define USB0_RXTYPE1_R          (*((volatile uint8_t *)0x4005011C))
+#define USB0_RXINTERVAL1_R      (*((volatile uint8_t *)0x4005011D))
+#define USB0_TXMAXP2_R          (*((volatile uint16_t *)0x40050120))
+#define USB0_TXCSRL2_R          (*((volatile uint8_t *)0x40050122))
+#define USB0_TXCSRH2_R          (*((volatile uint8_t *)0x40050123))
+#define USB0_RXMAXP2_R          (*((volatile uint16_t *)0x40050124))
+#define USB0_RXCSRL2_R          (*((volatile uint8_t *)0x40050126))
+#define USB0_RXCSRH2_R          (*((volatile uint8_t *)0x40050127))
+#define USB0_RXCOUNT2_R         (*((volatile uint16_t *)0x40050128))
+#define USB0_TXTYPE2_R          (*((volatile uint8_t *)0x4005012A))
+#define USB0_TXINTERVAL2_R      (*((volatile uint8_t *)0x4005012B))
+#define USB0_RXTYPE2_R          (*((volatile uint8_t *)0x4005012C))
+#define USB0_RXINTERVAL2_R      (*((volatile uint8_t *)0x4005012D))
+#define USB0_TXMAXP3_R          (*((volatile uint16_t *)0x40050130))
+#define USB0_TXCSRL3_R          (*((volatile uint8_t *)0x40050132))
+#define USB0_TXCSRH3_R          (*((volatile uint8_t *)0x40050133))
+#define USB0_RXMAXP3_R          (*((volatile uint16_t *)0x40050134))
+#define USB0_RXCSRL3_R          (*((volatile uint8_t *)0x40050136))
+#define USB0_RXCSRH3_R          (*((volatile uint8_t *)0x40050137))
+#define USB0_RXCOUNT3_R         (*((volatile uint16_t *)0x40050138))
+#define USB0_TXTYPE3_R          (*((volatile uint8_t *)0x4005013A))
+#define USB0_TXINTERVAL3_R      (*((volatile uint8_t *)0x4005013B))
+#define USB0_RXTYPE3_R          (*((volatile uint8_t *)0x4005013C))
+#define USB0_RXINTERVAL3_R      (*((volatile uint8_t *)0x4005013D))
+#define USB0_TXMAXP4_R          (*((volatile uint16_t *)0x40050140))
+#define USB0_TXCSRL4_R          (*((volatile uint8_t *)0x40050142))
+#define USB0_TXCSRH4_R          (*((volatile uint8_t *)0x40050143))
+#define USB0_RXMAXP4_R          (*((volatile uint16_t *)0x40050144))
+#define USB0_RXCSRL4_R          (*((volatile uint8_t *)0x40050146))
+#define USB0_RXCSRH4_R          (*((volatile uint8_t *)0x40050147))
+#define USB0_RXCOUNT4_R         (*((volatile uint16_t *)0x40050148))
+#define USB0_TXTYPE4_R          (*((volatile uint8_t *)0x4005014A))
+#define USB0_TXINTERVAL4_R      (*((volatile uint8_t *)0x4005014B))
+#define USB0_RXTYPE4_R          (*((volatile uint8_t *)0x4005014C))
+#define USB0_RXINTERVAL4_R      (*((volatile uint8_t *)0x4005014D))
+#define USB0_TXMAXP5_R          (*((volatile uint16_t *)0x40050150))
+#define USB0_TXCSRL5_R          (*((volatile uint8_t *)0x40050152))
+#define USB0_TXCSRH5_R          (*((volatile uint8_t *)0x40050153))
+#define USB0_RXMAXP5_R          (*((volatile uint16_t *)0x40050154))
+#define USB0_RXCSRL5_R          (*((volatile uint8_t *)0x40050156))
+#define USB0_RXCSRH5_R          (*((volatile uint8_t *)0x40050157))
+#define USB0_RXCOUNT5_R         (*((volatile uint16_t *)0x40050158))
+#define USB0_TXTYPE5_R          (*((volatile uint8_t *)0x4005015A))
+#define USB0_TXINTERVAL5_R      (*((volatile uint8_t *)0x4005015B))
+#define USB0_RXTYPE5_R          (*((volatile uint8_t *)0x4005015C))
+#define USB0_RXINTERVAL5_R      (*((volatile uint8_t *)0x4005015D))
+#define USB0_TXMAXP6_R          (*((volatile uint16_t *)0x40050160))
+#define USB0_TXCSRL6_R          (*((volatile uint8_t *)0x40050162))
+#define USB0_TXCSRH6_R          (*((volatile uint8_t *)0x40050163))
+#define USB0_RXMAXP6_R          (*((volatile uint16_t *)0x40050164))
+#define USB0_RXCSRL6_R          (*((volatile uint8_t *)0x40050166))
+#define USB0_RXCSRH6_R          (*((volatile uint8_t *)0x40050167))
+#define USB0_RXCOUNT6_R         (*((volatile uint16_t *)0x40050168))
+#define USB0_TXTYPE6_R          (*((volatile uint8_t *)0x4005016A))
+#define USB0_TXINTERVAL6_R      (*((volatile uint8_t *)0x4005016B))
+#define USB0_RXTYPE6_R          (*((volatile uint8_t *)0x4005016C))
+#define USB0_RXINTERVAL6_R      (*((volatile uint8_t *)0x4005016D))
+#define USB0_TXMAXP7_R          (*((volatile uint16_t *)0x40050170))
+#define USB0_TXCSRL7_R          (*((volatile uint8_t *)0x40050172))
+#define USB0_TXCSRH7_R          (*((volatile uint8_t *)0x40050173))
+#define USB0_RXMAXP7_R          (*((volatile uint16_t *)0x40050174))
+#define USB0_RXCSRL7_R          (*((volatile uint8_t *)0x40050176))
+#define USB0_RXCSRH7_R          (*((volatile uint8_t *)0x40050177))
+#define USB0_RXCOUNT7_R         (*((volatile uint16_t *)0x40050178))
+#define USB0_TXTYPE7_R          (*((volatile uint8_t *)0x4005017A))
+#define USB0_TXINTERVAL7_R      (*((volatile uint8_t *)0x4005017B))
+#define USB0_RXTYPE7_R          (*((volatile uint8_t *)0x4005017C))
+#define USB0_RXINTERVAL7_R      (*((volatile uint8_t *)0x4005017D))
+#define USB0_RQPKTCOUNT1_R      (*((volatile uint16_t *)0x40050304))
+#define USB0_RQPKTCOUNT2_R      (*((volatile uint16_t *)0x40050308))
+#define USB0_RQPKTCOUNT3_R      (*((volatile uint16_t *)0x4005030C))
+#define USB0_RQPKTCOUNT4_R      (*((volatile uint16_t *)0x40050310))
+#define USB0_RQPKTCOUNT5_R      (*((volatile uint16_t *)0x40050314))
+#define USB0_RQPKTCOUNT6_R      (*((volatile uint16_t *)0x40050318))
+#define USB0_RQPKTCOUNT7_R      (*((volatile uint16_t *)0x4005031C))
+#define USB0_RXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050340))
+#define USB0_TXDPKTBUFDIS_R     (*((volatile uint16_t *)0x40050342))
+#define USB0_EPC_R              (*((volatile uint32_t *)0x40050400))
+#define USB0_EPCRIS_R           (*((volatile uint32_t *)0x40050404))
+#define USB0_EPCIM_R            (*((volatile uint32_t *)0x40050408))
+#define USB0_EPCISC_R           (*((volatile uint32_t *)0x4005040C))
+#define USB0_DRRIS_R            (*((volatile uint32_t *)0x40050410))
+#define USB0_DRIM_R             (*((volatile uint32_t *)0x40050414))
+#define USB0_DRISC_R            (*((volatile uint32_t *)0x40050418))
+#define USB0_GPCS_R             (*((volatile uint32_t *)0x4005041C))
+#define USB0_VDC_R              (*((volatile uint32_t *)0x40050430))
+#define USB0_VDCRIS_R           (*((volatile uint32_t *)0x40050434))
+#define USB0_VDCIM_R            (*((volatile uint32_t *)0x40050438))
+#define USB0_VDCISC_R           (*((volatile uint32_t *)0x4005043C))
+#define USB0_IDVRIS_R           (*((volatile uint32_t *)0x40050444))
+#define USB0_IDVIM_R            (*((volatile uint32_t *)0x40050448))
+#define USB0_IDVISC_R           (*((volatile uint32_t *)0x4005044C))
+#define USB0_DMASEL_R           (*((volatile uint32_t *)0x40050450))
+#define USB0_PP_R               (*((volatile uint32_t *)0x40050FC0))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTA AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTA_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x40058000)
+#define GPIO_PORTA_AHB_DATA_R   (*((volatile uint32_t *)0x400583FC))
+#define GPIO_PORTA_AHB_DIR_R    (*((volatile uint32_t *)0x40058400))
+#define GPIO_PORTA_AHB_IS_R     (*((volatile uint32_t *)0x40058404))
+#define GPIO_PORTA_AHB_IBE_R    (*((volatile uint32_t *)0x40058408))
+#define GPIO_PORTA_AHB_IEV_R    (*((volatile uint32_t *)0x4005840C))
+#define GPIO_PORTA_AHB_IM_R     (*((volatile uint32_t *)0x40058410))
+#define GPIO_PORTA_AHB_RIS_R    (*((volatile uint32_t *)0x40058414))
+#define GPIO_PORTA_AHB_MIS_R    (*((volatile uint32_t *)0x40058418))
+#define GPIO_PORTA_AHB_ICR_R    (*((volatile uint32_t *)0x4005841C))
+#define GPIO_PORTA_AHB_AFSEL_R  (*((volatile uint32_t *)0x40058420))
+#define GPIO_PORTA_AHB_DR2R_R   (*((volatile uint32_t *)0x40058500))
+#define GPIO_PORTA_AHB_DR4R_R   (*((volatile uint32_t *)0x40058504))
+#define GPIO_PORTA_AHB_DR8R_R   (*((volatile uint32_t *)0x40058508))
+#define GPIO_PORTA_AHB_ODR_R    (*((volatile uint32_t *)0x4005850C))
+#define GPIO_PORTA_AHB_PUR_R    (*((volatile uint32_t *)0x40058510))
+#define GPIO_PORTA_AHB_PDR_R    (*((volatile uint32_t *)0x40058514))
+#define GPIO_PORTA_AHB_SLR_R    (*((volatile uint32_t *)0x40058518))
+#define GPIO_PORTA_AHB_DEN_R    (*((volatile uint32_t *)0x4005851C))
+#define GPIO_PORTA_AHB_LOCK_R   (*((volatile uint32_t *)0x40058520))
+#define GPIO_PORTA_AHB_CR_R     (*((volatile uint32_t *)0x40058524))
+#define GPIO_PORTA_AHB_AMSEL_R  (*((volatile uint32_t *)0x40058528))
+#define GPIO_PORTA_AHB_PCTL_R   (*((volatile uint32_t *)0x4005852C))
+#define GPIO_PORTA_AHB_ADCCTL_R (*((volatile uint32_t *)0x40058530))
+#define GPIO_PORTA_AHB_DMACTL_R (*((volatile uint32_t *)0x40058534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTB AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTB_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x40059000)
+#define GPIO_PORTB_AHB_DATA_R   (*((volatile uint32_t *)0x400593FC))
+#define GPIO_PORTB_AHB_DIR_R    (*((volatile uint32_t *)0x40059400))
+#define GPIO_PORTB_AHB_IS_R     (*((volatile uint32_t *)0x40059404))
+#define GPIO_PORTB_AHB_IBE_R    (*((volatile uint32_t *)0x40059408))
+#define GPIO_PORTB_AHB_IEV_R    (*((volatile uint32_t *)0x4005940C))
+#define GPIO_PORTB_AHB_IM_R     (*((volatile uint32_t *)0x40059410))
+#define GPIO_PORTB_AHB_RIS_R    (*((volatile uint32_t *)0x40059414))
+#define GPIO_PORTB_AHB_MIS_R    (*((volatile uint32_t *)0x40059418))
+#define GPIO_PORTB_AHB_ICR_R    (*((volatile uint32_t *)0x4005941C))
+#define GPIO_PORTB_AHB_AFSEL_R  (*((volatile uint32_t *)0x40059420))
+#define GPIO_PORTB_AHB_DR2R_R   (*((volatile uint32_t *)0x40059500))
+#define GPIO_PORTB_AHB_DR4R_R   (*((volatile uint32_t *)0x40059504))
+#define GPIO_PORTB_AHB_DR8R_R   (*((volatile uint32_t *)0x40059508))
+#define GPIO_PORTB_AHB_ODR_R    (*((volatile uint32_t *)0x4005950C))
+#define GPIO_PORTB_AHB_PUR_R    (*((volatile uint32_t *)0x40059510))
+#define GPIO_PORTB_AHB_PDR_R    (*((volatile uint32_t *)0x40059514))
+#define GPIO_PORTB_AHB_SLR_R    (*((volatile uint32_t *)0x40059518))
+#define GPIO_PORTB_AHB_DEN_R    (*((volatile uint32_t *)0x4005951C))
+#define GPIO_PORTB_AHB_LOCK_R   (*((volatile uint32_t *)0x40059520))
+#define GPIO_PORTB_AHB_CR_R     (*((volatile uint32_t *)0x40059524))
+#define GPIO_PORTB_AHB_AMSEL_R  (*((volatile uint32_t *)0x40059528))
+#define GPIO_PORTB_AHB_PCTL_R   (*((volatile uint32_t *)0x4005952C))
+#define GPIO_PORTB_AHB_ADCCTL_R (*((volatile uint32_t *)0x40059530))
+#define GPIO_PORTB_AHB_DMACTL_R (*((volatile uint32_t *)0x40059534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTC AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTC_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005A000)
+#define GPIO_PORTC_AHB_DATA_R   (*((volatile uint32_t *)0x4005A3FC))
+#define GPIO_PORTC_AHB_DIR_R    (*((volatile uint32_t *)0x4005A400))
+#define GPIO_PORTC_AHB_IS_R     (*((volatile uint32_t *)0x4005A404))
+#define GPIO_PORTC_AHB_IBE_R    (*((volatile uint32_t *)0x4005A408))
+#define GPIO_PORTC_AHB_IEV_R    (*((volatile uint32_t *)0x4005A40C))
+#define GPIO_PORTC_AHB_IM_R     (*((volatile uint32_t *)0x4005A410))
+#define GPIO_PORTC_AHB_RIS_R    (*((volatile uint32_t *)0x4005A414))
+#define GPIO_PORTC_AHB_MIS_R    (*((volatile uint32_t *)0x4005A418))
+#define GPIO_PORTC_AHB_ICR_R    (*((volatile uint32_t *)0x4005A41C))
+#define GPIO_PORTC_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005A420))
+#define GPIO_PORTC_AHB_DR2R_R   (*((volatile uint32_t *)0x4005A500))
+#define GPIO_PORTC_AHB_DR4R_R   (*((volatile uint32_t *)0x4005A504))
+#define GPIO_PORTC_AHB_DR8R_R   (*((volatile uint32_t *)0x4005A508))
+#define GPIO_PORTC_AHB_ODR_R    (*((volatile uint32_t *)0x4005A50C))
+#define GPIO_PORTC_AHB_PUR_R    (*((volatile uint32_t *)0x4005A510))
+#define GPIO_PORTC_AHB_PDR_R    (*((volatile uint32_t *)0x4005A514))
+#define GPIO_PORTC_AHB_SLR_R    (*((volatile uint32_t *)0x4005A518))
+#define GPIO_PORTC_AHB_DEN_R    (*((volatile uint32_t *)0x4005A51C))
+#define GPIO_PORTC_AHB_LOCK_R   (*((volatile uint32_t *)0x4005A520))
+#define GPIO_PORTC_AHB_CR_R     (*((volatile uint32_t *)0x4005A524))
+#define GPIO_PORTC_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005A528))
+#define GPIO_PORTC_AHB_PCTL_R   (*((volatile uint32_t *)0x4005A52C))
+#define GPIO_PORTC_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005A530))
+#define GPIO_PORTC_AHB_DMACTL_R (*((volatile uint32_t *)0x4005A534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTD AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTD_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005B000)
+#define GPIO_PORTD_AHB_DATA_R   (*((volatile uint32_t *)0x4005B3FC))
+#define GPIO_PORTD_AHB_DIR_R    (*((volatile uint32_t *)0x4005B400))
+#define GPIO_PORTD_AHB_IS_R     (*((volatile uint32_t *)0x4005B404))
+#define GPIO_PORTD_AHB_IBE_R    (*((volatile uint32_t *)0x4005B408))
+#define GPIO_PORTD_AHB_IEV_R    (*((volatile uint32_t *)0x4005B40C))
+#define GPIO_PORTD_AHB_IM_R     (*((volatile uint32_t *)0x4005B410))
+#define GPIO_PORTD_AHB_RIS_R    (*((volatile uint32_t *)0x4005B414))
+#define GPIO_PORTD_AHB_MIS_R    (*((volatile uint32_t *)0x4005B418))
+#define GPIO_PORTD_AHB_ICR_R    (*((volatile uint32_t *)0x4005B41C))
+#define GPIO_PORTD_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005B420))
+#define GPIO_PORTD_AHB_DR2R_R   (*((volatile uint32_t *)0x4005B500))
+#define GPIO_PORTD_AHB_DR4R_R   (*((volatile uint32_t *)0x4005B504))
+#define GPIO_PORTD_AHB_DR8R_R   (*((volatile uint32_t *)0x4005B508))
+#define GPIO_PORTD_AHB_ODR_R    (*((volatile uint32_t *)0x4005B50C))
+#define GPIO_PORTD_AHB_PUR_R    (*((volatile uint32_t *)0x4005B510))
+#define GPIO_PORTD_AHB_PDR_R    (*((volatile uint32_t *)0x4005B514))
+#define GPIO_PORTD_AHB_SLR_R    (*((volatile uint32_t *)0x4005B518))
+#define GPIO_PORTD_AHB_DEN_R    (*((volatile uint32_t *)0x4005B51C))
+#define GPIO_PORTD_AHB_LOCK_R   (*((volatile uint32_t *)0x4005B520))
+#define GPIO_PORTD_AHB_CR_R     (*((volatile uint32_t *)0x4005B524))
+#define GPIO_PORTD_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005B528))
+#define GPIO_PORTD_AHB_PCTL_R   (*((volatile uint32_t *)0x4005B52C))
+#define GPIO_PORTD_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005B530))
+#define GPIO_PORTD_AHB_DMACTL_R (*((volatile uint32_t *)0x4005B534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTE AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTE_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005C000)
+#define GPIO_PORTE_AHB_DATA_R   (*((volatile uint32_t *)0x4005C3FC))
+#define GPIO_PORTE_AHB_DIR_R    (*((volatile uint32_t *)0x4005C400))
+#define GPIO_PORTE_AHB_IS_R     (*((volatile uint32_t *)0x4005C404))
+#define GPIO_PORTE_AHB_IBE_R    (*((volatile uint32_t *)0x4005C408))
+#define GPIO_PORTE_AHB_IEV_R    (*((volatile uint32_t *)0x4005C40C))
+#define GPIO_PORTE_AHB_IM_R     (*((volatile uint32_t *)0x4005C410))
+#define GPIO_PORTE_AHB_RIS_R    (*((volatile uint32_t *)0x4005C414))
+#define GPIO_PORTE_AHB_MIS_R    (*((volatile uint32_t *)0x4005C418))
+#define GPIO_PORTE_AHB_ICR_R    (*((volatile uint32_t *)0x4005C41C))
+#define GPIO_PORTE_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005C420))
+#define GPIO_PORTE_AHB_DR2R_R   (*((volatile uint32_t *)0x4005C500))
+#define GPIO_PORTE_AHB_DR4R_R   (*((volatile uint32_t *)0x4005C504))
+#define GPIO_PORTE_AHB_DR8R_R   (*((volatile uint32_t *)0x4005C508))
+#define GPIO_PORTE_AHB_ODR_R    (*((volatile uint32_t *)0x4005C50C))
+#define GPIO_PORTE_AHB_PUR_R    (*((volatile uint32_t *)0x4005C510))
+#define GPIO_PORTE_AHB_PDR_R    (*((volatile uint32_t *)0x4005C514))
+#define GPIO_PORTE_AHB_SLR_R    (*((volatile uint32_t *)0x4005C518))
+#define GPIO_PORTE_AHB_DEN_R    (*((volatile uint32_t *)0x4005C51C))
+#define GPIO_PORTE_AHB_LOCK_R   (*((volatile uint32_t *)0x4005C520))
+#define GPIO_PORTE_AHB_CR_R     (*((volatile uint32_t *)0x4005C524))
+#define GPIO_PORTE_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005C528))
+#define GPIO_PORTE_AHB_PCTL_R   (*((volatile uint32_t *)0x4005C52C))
+#define GPIO_PORTE_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005C530))
+#define GPIO_PORTE_AHB_DMACTL_R (*((volatile uint32_t *)0x4005C534))
+
+//*****************************************************************************
+//
+// GPIO registers (PORTF AHB)
+//
+//*****************************************************************************
+#define GPIO_PORTF_AHB_DATA_BITS_R                                            \
+                                ((volatile uint32_t *)0x4005D000)
+#define GPIO_PORTF_AHB_DATA_R   (*((volatile uint32_t *)0x4005D3FC))
+#define GPIO_PORTF_AHB_DIR_R    (*((volatile uint32_t *)0x4005D400))
+#define GPIO_PORTF_AHB_IS_R     (*((volatile uint32_t *)0x4005D404))
+#define GPIO_PORTF_AHB_IBE_R    (*((volatile uint32_t *)0x4005D408))
+#define GPIO_PORTF_AHB_IEV_R    (*((volatile uint32_t *)0x4005D40C))
+#define GPIO_PORTF_AHB_IM_R     (*((volatile uint32_t *)0x4005D410))
+#define GPIO_PORTF_AHB_RIS_R    (*((volatile uint32_t *)0x4005D414))
+#define GPIO_PORTF_AHB_MIS_R    (*((volatile uint32_t *)0x4005D418))
+#define GPIO_PORTF_AHB_ICR_R    (*((volatile uint32_t *)0x4005D41C))
+#define GPIO_PORTF_AHB_AFSEL_R  (*((volatile uint32_t *)0x4005D420))
+#define GPIO_PORTF_AHB_DR2R_R   (*((volatile uint32_t *)0x4005D500))
+#define GPIO_PORTF_AHB_DR4R_R   (*((volatile uint32_t *)0x4005D504))
+#define GPIO_PORTF_AHB_DR8R_R   (*((volatile uint32_t *)0x4005D508))
+#define GPIO_PORTF_AHB_ODR_R    (*((volatile uint32_t *)0x4005D50C))
+#define GPIO_PORTF_AHB_PUR_R    (*((volatile uint32_t *)0x4005D510))
+#define GPIO_PORTF_AHB_PDR_R    (*((volatile uint32_t *)0x4005D514))
+#define GPIO_PORTF_AHB_SLR_R    (*((volatile uint32_t *)0x4005D518))
+#define GPIO_PORTF_AHB_DEN_R    (*((volatile uint32_t *)0x4005D51C))
+#define GPIO_PORTF_AHB_LOCK_R   (*((volatile uint32_t *)0x4005D520))
+#define GPIO_PORTF_AHB_CR_R     (*((volatile uint32_t *)0x4005D524))
+#define GPIO_PORTF_AHB_AMSEL_R  (*((volatile uint32_t *)0x4005D528))
+#define GPIO_PORTF_AHB_PCTL_R   (*((volatile uint32_t *)0x4005D52C))
+#define GPIO_PORTF_AHB_ADCCTL_R (*((volatile uint32_t *)0x4005D530))
+#define GPIO_PORTF_AHB_DMACTL_R (*((volatile uint32_t *)0x4005D534))
+
+//*****************************************************************************
+//
+// EEPROM registers (EEPROM)
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_R         (*((volatile uint32_t *)0x400AF000))
+#define EEPROM_EEBLOCK_R        (*((volatile uint32_t *)0x400AF004))
+#define EEPROM_EEOFFSET_R       (*((volatile uint32_t *)0x400AF008))
+#define EEPROM_EERDWR_R         (*((volatile uint32_t *)0x400AF010))
+#define EEPROM_EERDWRINC_R      (*((volatile uint32_t *)0x400AF014))
+#define EEPROM_EEDONE_R         (*((volatile uint32_t *)0x400AF018))
+#define EEPROM_EESUPP_R         (*((volatile uint32_t *)0x400AF01C))
+#define EEPROM_EEUNLOCK_R       (*((volatile uint32_t *)0x400AF020))
+#define EEPROM_EEPROT_R         (*((volatile uint32_t *)0x400AF030))
+#define EEPROM_EEPASS0_R        (*((volatile uint32_t *)0x400AF034))
+#define EEPROM_EEPASS1_R        (*((volatile uint32_t *)0x400AF038))
+#define EEPROM_EEPASS2_R        (*((volatile uint32_t *)0x400AF03C))
+#define EEPROM_EEINT_R          (*((volatile uint32_t *)0x400AF040))
+#define EEPROM_EEHIDE_R         (*((volatile uint32_t *)0x400AF050))
+#define EEPROM_EEDBGME_R        (*((volatile uint32_t *)0x400AF080))
+#define EEPROM_PP_R             (*((volatile uint32_t *)0x400AFFC0))
+
+//*****************************************************************************
+//
+// System Exception Module registers (SYSEXC)
+//
+//*****************************************************************************
+#define SYSEXC_RIS_R            (*((volatile uint32_t *)0x400F9000))
+#define SYSEXC_IM_R             (*((volatile uint32_t *)0x400F9004))
+#define SYSEXC_MIS_R            (*((volatile uint32_t *)0x400F9008))
+#define SYSEXC_IC_R             (*((volatile uint32_t *)0x400F900C))
+
+//*****************************************************************************
+//
+// Hibernation module registers (HIB)
+//
+//*****************************************************************************
+#define HIB_RTCC_R              (*((volatile uint32_t *)0x400FC000))
+#define HIB_RTCM0_R             (*((volatile uint32_t *)0x400FC004))
+#define HIB_RTCLD_R             (*((volatile uint32_t *)0x400FC00C))
+#define HIB_CTL_R               (*((volatile uint32_t *)0x400FC010))
+#define HIB_IM_R                (*((volatile uint32_t *)0x400FC014))
+#define HIB_RIS_R               (*((volatile uint32_t *)0x400FC018))
+#define HIB_MIS_R               (*((volatile uint32_t *)0x400FC01C))
+#define HIB_IC_R                (*((volatile uint32_t *)0x400FC020))
+#define HIB_RTCT_R              (*((volatile uint32_t *)0x400FC024))
+#define HIB_RTCSS_R             (*((volatile uint32_t *)0x400FC028))
+#define HIB_DATA_R              (*((volatile uint32_t *)0x400FC030))
+
+//*****************************************************************************
+//
+// FLASH registers (FLASH CTRL)
+//
+//*****************************************************************************
+#define FLASH_FMA_R             (*((volatile uint32_t *)0x400FD000))
+#define FLASH_FMD_R             (*((volatile uint32_t *)0x400FD004))
+#define FLASH_FMC_R             (*((volatile uint32_t *)0x400FD008))
+#define FLASH_FCRIS_R           (*((volatile uint32_t *)0x400FD00C))
+#define FLASH_FCIM_R            (*((volatile uint32_t *)0x400FD010))
+#define FLASH_FCMISC_R          (*((volatile uint32_t *)0x400FD014))
+#define FLASH_FMC2_R            (*((volatile uint32_t *)0x400FD020))
+#define FLASH_FWBVAL_R          (*((volatile uint32_t *)0x400FD030))
+#define FLASH_FWBN_R            (*((volatile uint32_t *)0x400FD100))
+#define FLASH_FSIZE_R           (*((volatile uint32_t *)0x400FDFC0))
+#define FLASH_SSIZE_R           (*((volatile uint32_t *)0x400FDFC4))
+#define FLASH_ROMSWMAP_R        (*((volatile uint32_t *)0x400FDFCC))
+#define FLASH_RMCTL_R           (*((volatile uint32_t *)0x400FE0F0))
+#define FLASH_BOOTCFG_R         (*((volatile uint32_t *)0x400FE1D0))
+#define FLASH_USERREG0_R        (*((volatile uint32_t *)0x400FE1E0))
+#define FLASH_USERREG1_R        (*((volatile uint32_t *)0x400FE1E4))
+#define FLASH_USERREG2_R        (*((volatile uint32_t *)0x400FE1E8))
+#define FLASH_USERREG3_R        (*((volatile uint32_t *)0x400FE1EC))
+#define FLASH_FMPRE0_R          (*((volatile uint32_t *)0x400FE200))
+#define FLASH_FMPRE1_R          (*((volatile uint32_t *)0x400FE204))
+#define FLASH_FMPRE2_R          (*((volatile uint32_t *)0x400FE208))
+#define FLASH_FMPRE3_R          (*((volatile uint32_t *)0x400FE20C))
+#define FLASH_FMPPE0_R          (*((volatile uint32_t *)0x400FE400))
+#define FLASH_FMPPE1_R          (*((volatile uint32_t *)0x400FE404))
+#define FLASH_FMPPE2_R          (*((volatile uint32_t *)0x400FE408))
+#define FLASH_FMPPE3_R          (*((volatile uint32_t *)0x400FE40C))
+
+//*****************************************************************************
+//
+// System Control registers (SYSCTL)
+//
+//*****************************************************************************
+#define SYSCTL_DID0_R           (*((volatile uint32_t *)0x400FE000))
+#define SYSCTL_DID1_R           (*((volatile uint32_t *)0x400FE004))
+#define SYSCTL_DC0_R            (*((volatile uint32_t *)0x400FE008))
+#define SYSCTL_DC1_R            (*((volatile uint32_t *)0x400FE010))
+#define SYSCTL_DC2_R            (*((volatile uint32_t *)0x400FE014))
+#define SYSCTL_DC3_R            (*((volatile uint32_t *)0x400FE018))
+#define SYSCTL_DC4_R            (*((volatile uint32_t *)0x400FE01C))
+#define SYSCTL_DC5_R            (*((volatile uint32_t *)0x400FE020))
+#define SYSCTL_DC6_R            (*((volatile uint32_t *)0x400FE024))
+#define SYSCTL_DC7_R            (*((volatile uint32_t *)0x400FE028))
+#define SYSCTL_DC8_R            (*((volatile uint32_t *)0x400FE02C))
+#define SYSCTL_PBORCTL_R        (*((volatile uint32_t *)0x400FE030))
+#define SYSCTL_SRCR0_R          (*((volatile uint32_t *)0x400FE040))
+#define SYSCTL_SRCR1_R          (*((volatile uint32_t *)0x400FE044))
+#define SYSCTL_SRCR2_R          (*((volatile uint32_t *)0x400FE048))
+#define SYSCTL_RIS_R            (*((volatile uint32_t *)0x400FE050))
+#define SYSCTL_IMC_R            (*((volatile uint32_t *)0x400FE054))
+#define SYSCTL_MISC_R           (*((volatile uint32_t *)0x400FE058))
+#define SYSCTL_RESC_R           (*((volatile uint32_t *)0x400FE05C))
+#define SYSCTL_RCC_R            (*((volatile uint32_t *)0x400FE060))
+#define SYSCTL_GPIOHBCTL_R      (*((volatile uint32_t *)0x400FE06C))
+#define SYSCTL_RCC2_R           (*((volatile uint32_t *)0x400FE070))
+#define SYSCTL_MOSCCTL_R        (*((volatile uint32_t *)0x400FE07C))
+#define SYSCTL_RCGC0_R          (*((volatile uint32_t *)0x400FE100))
+#define SYSCTL_RCGC1_R          (*((volatile uint32_t *)0x400FE104))
+#define SYSCTL_RCGC2_R          (*((volatile uint32_t *)0x400FE108))
+#define SYSCTL_SCGC0_R          (*((volatile uint32_t *)0x400FE110))
+#define SYSCTL_SCGC1_R          (*((volatile uint32_t *)0x400FE114))
+#define SYSCTL_SCGC2_R          (*((volatile uint32_t *)0x400FE118))
+#define SYSCTL_DCGC0_R          (*((volatile uint32_t *)0x400FE120))
+#define SYSCTL_DCGC1_R          (*((volatile uint32_t *)0x400FE124))
+#define SYSCTL_DCGC2_R          (*((volatile uint32_t *)0x400FE128))
+#define SYSCTL_DSLPCLKCFG_R     (*((volatile uint32_t *)0x400FE144))
+#define SYSCTL_SYSPROP_R        (*((volatile uint32_t *)0x400FE14C))
+#define SYSCTL_PIOSCCAL_R       (*((volatile uint32_t *)0x400FE150))
+#define SYSCTL_PIOSCSTAT_R      (*((volatile uint32_t *)0x400FE154))
+#define SYSCTL_PLLFREQ0_R       (*((volatile uint32_t *)0x400FE160))
+#define SYSCTL_PLLFREQ1_R       (*((volatile uint32_t *)0x400FE164))
+#define SYSCTL_PLLSTAT_R        (*((volatile uint32_t *)0x400FE168))
+#define SYSCTL_SLPPWRCFG_R      (*((volatile uint32_t *)0x400FE188))
+#define SYSCTL_DSLPPWRCFG_R     (*((volatile uint32_t *)0x400FE18C))
+#define SYSCTL_DC9_R            (*((volatile uint32_t *)0x400FE190))
+#define SYSCTL_NVMSTAT_R        (*((volatile uint32_t *)0x400FE1A0))
+#define SYSCTL_LDOSPCTL_R       (*((volatile uint32_t *)0x400FE1B4))
+#define SYSCTL_LDODPCTL_R       (*((volatile uint32_t *)0x400FE1BC))
+#define SYSCTL_PPWD_R           (*((volatile uint32_t *)0x400FE300))
+#define SYSCTL_PPTIMER_R        (*((volatile uint32_t *)0x400FE304))
+#define SYSCTL_PPGPIO_R         (*((volatile uint32_t *)0x400FE308))
+#define SYSCTL_PPDMA_R          (*((volatile uint32_t *)0x400FE30C))
+#define SYSCTL_PPHIB_R          (*((volatile uint32_t *)0x400FE314))
+#define SYSCTL_PPUART_R         (*((volatile uint32_t *)0x400FE318))
+#define SYSCTL_PPSSI_R          (*((volatile uint32_t *)0x400FE31C))
+#define SYSCTL_PPI2C_R          (*((volatile uint32_t *)0x400FE320))
+#define SYSCTL_PPUSB_R          (*((volatile uint32_t *)0x400FE328))
+#define SYSCTL_PPCAN_R          (*((volatile uint32_t *)0x400FE334))
+#define SYSCTL_PPADC_R          (*((volatile uint32_t *)0x400FE338))
+#define SYSCTL_PPACMP_R         (*((volatile uint32_t *)0x400FE33C))
+#define SYSCTL_PPPWM_R          (*((volatile uint32_t *)0x400FE340))
+#define SYSCTL_PPQEI_R          (*((volatile uint32_t *)0x400FE344))
+#define SYSCTL_PPEEPROM_R       (*((volatile uint32_t *)0x400FE358))
+#define SYSCTL_PPWTIMER_R       (*((volatile uint32_t *)0x400FE35C))
+#define SYSCTL_SRWD_R           (*((volatile uint32_t *)0x400FE500))
+#define SYSCTL_SRTIMER_R        (*((volatile uint32_t *)0x400FE504))
+#define SYSCTL_SRGPIO_R         (*((volatile uint32_t *)0x400FE508))
+#define SYSCTL_SRDMA_R          (*((volatile uint32_t *)0x400FE50C))
+#define SYSCTL_SRHIB_R          (*((volatile uint32_t *)0x400FE514))
+#define SYSCTL_SRUART_R         (*((volatile uint32_t *)0x400FE518))
+#define SYSCTL_SRSSI_R          (*((volatile uint32_t *)0x400FE51C))
+#define SYSCTL_SRI2C_R          (*((volatile uint32_t *)0x400FE520))
+#define SYSCTL_SRUSB_R          (*((volatile uint32_t *)0x400FE528))
+#define SYSCTL_SRCAN_R          (*((volatile uint32_t *)0x400FE534))
+#define SYSCTL_SRADC_R          (*((volatile uint32_t *)0x400FE538))
+#define SYSCTL_SRACMP_R         (*((volatile uint32_t *)0x400FE53C))
+#define SYSCTL_SRPWM_R          (*((volatile uint32_t *)0x400FE540))
+#define SYSCTL_SRQEI_R          (*((volatile uint32_t *)0x400FE544))
+#define SYSCTL_SREEPROM_R       (*((volatile uint32_t *)0x400FE558))
+#define SYSCTL_SRWTIMER_R       (*((volatile uint32_t *)0x400FE55C))
+#define SYSCTL_RCGCWD_R         (*((volatile uint32_t *)0x400FE600))
+#define SYSCTL_RCGCTIMER_R      (*((volatile uint32_t *)0x400FE604))
+#define SYSCTL_RCGCGPIO_R       (*((volatile uint32_t *)0x400FE608))
+#define SYSCTL_RCGCDMA_R        (*((volatile uint32_t *)0x400FE60C))
+#define SYSCTL_RCGCHIB_R        (*((volatile uint32_t *)0x400FE614))
+#define SYSCTL_RCGCUART_R       (*((volatile uint32_t *)0x400FE618))
+#define SYSCTL_RCGCSSI_R        (*((volatile uint32_t *)0x400FE61C))
+#define SYSCTL_RCGCI2C_R        (*((volatile uint32_t *)0x400FE620))
+#define SYSCTL_RCGCUSB_R        (*((volatile uint32_t *)0x400FE628))
+#define SYSCTL_RCGCCAN_R        (*((volatile uint32_t *)0x400FE634))
+#define SYSCTL_RCGCADC_R        (*((volatile uint32_t *)0x400FE638))
+#define SYSCTL_RCGCACMP_R       (*((volatile uint32_t *)0x400FE63C))
+#define SYSCTL_RCGCPWM_R        (*((volatile uint32_t *)0x400FE640))
+#define SYSCTL_RCGCQEI_R        (*((volatile uint32_t *)0x400FE644))
+#define SYSCTL_RCGCEEPROM_R     (*((volatile uint32_t *)0x400FE658))
+#define SYSCTL_RCGCWTIMER_R     (*((volatile uint32_t *)0x400FE65C))
+#define SYSCTL_SCGCWD_R         (*((volatile uint32_t *)0x400FE700))
+#define SYSCTL_SCGCTIMER_R      (*((volatile uint32_t *)0x400FE704))
+#define SYSCTL_SCGCGPIO_R       (*((volatile uint32_t *)0x400FE708))
+#define SYSCTL_SCGCDMA_R        (*((volatile uint32_t *)0x400FE70C))
+#define SYSCTL_SCGCHIB_R        (*((volatile uint32_t *)0x400FE714))
+#define SYSCTL_SCGCUART_R       (*((volatile uint32_t *)0x400FE718))
+#define SYSCTL_SCGCSSI_R        (*((volatile uint32_t *)0x400FE71C))
+#define SYSCTL_SCGCI2C_R        (*((volatile uint32_t *)0x400FE720))
+#define SYSCTL_SCGCUSB_R        (*((volatile uint32_t *)0x400FE728))
+#define SYSCTL_SCGCCAN_R        (*((volatile uint32_t *)0x400FE734))
+#define SYSCTL_SCGCADC_R        (*((volatile uint32_t *)0x400FE738))
+#define SYSCTL_SCGCACMP_R       (*((volatile uint32_t *)0x400FE73C))
+#define SYSCTL_SCGCPWM_R        (*((volatile uint32_t *)0x400FE740))
+#define SYSCTL_SCGCQEI_R        (*((volatile uint32_t *)0x400FE744))
+#define SYSCTL_SCGCEEPROM_R     (*((volatile uint32_t *)0x400FE758))
+#define SYSCTL_SCGCWTIMER_R     (*((volatile uint32_t *)0x400FE75C))
+#define SYSCTL_DCGCWD_R         (*((volatile uint32_t *)0x400FE800))
+#define SYSCTL_DCGCTIMER_R      (*((volatile uint32_t *)0x400FE804))
+#define SYSCTL_DCGCGPIO_R       (*((volatile uint32_t *)0x400FE808))
+#define SYSCTL_DCGCDMA_R        (*((volatile uint32_t *)0x400FE80C))
+#define SYSCTL_DCGCHIB_R        (*((volatile uint32_t *)0x400FE814))
+#define SYSCTL_DCGCUART_R       (*((volatile uint32_t *)0x400FE818))
+#define SYSCTL_DCGCSSI_R        (*((volatile uint32_t *)0x400FE81C))
+#define SYSCTL_DCGCI2C_R        (*((volatile uint32_t *)0x400FE820))
+#define SYSCTL_DCGCUSB_R        (*((volatile uint32_t *)0x400FE828))
+#define SYSCTL_DCGCCAN_R        (*((volatile uint32_t *)0x400FE834))
+#define SYSCTL_DCGCADC_R        (*((volatile uint32_t *)0x400FE838))
+#define SYSCTL_DCGCACMP_R       (*((volatile uint32_t *)0x400FE83C))
+#define SYSCTL_DCGCPWM_R        (*((volatile uint32_t *)0x400FE840))
+#define SYSCTL_DCGCQEI_R        (*((volatile uint32_t *)0x400FE844))
+#define SYSCTL_DCGCEEPROM_R     (*((volatile uint32_t *)0x400FE858))
+#define SYSCTL_DCGCWTIMER_R     (*((volatile uint32_t *)0x400FE85C))
+#define SYSCTL_PRWD_R           (*((volatile uint32_t *)0x400FEA00))
+#define SYSCTL_PRTIMER_R        (*((volatile uint32_t *)0x400FEA04))
+#define SYSCTL_PRGPIO_R         (*((volatile uint32_t *)0x400FEA08))
+#define SYSCTL_PRDMA_R          (*((volatile uint32_t *)0x400FEA0C))
+#define SYSCTL_PRHIB_R          (*((volatile uint32_t *)0x400FEA14))
+#define SYSCTL_PRUART_R         (*((volatile uint32_t *)0x400FEA18))
+#define SYSCTL_PRSSI_R          (*((volatile uint32_t *)0x400FEA1C))
+#define SYSCTL_PRI2C_R          (*((volatile uint32_t *)0x400FEA20))
+#define SYSCTL_PRUSB_R          (*((volatile uint32_t *)0x400FEA28))
+#define SYSCTL_PRCAN_R          (*((volatile uint32_t *)0x400FEA34))
+#define SYSCTL_PRADC_R          (*((volatile uint32_t *)0x400FEA38))
+#define SYSCTL_PRACMP_R         (*((volatile uint32_t *)0x400FEA3C))
+#define SYSCTL_PRPWM_R          (*((volatile uint32_t *)0x400FEA40))
+#define SYSCTL_PRQEI_R          (*((volatile uint32_t *)0x400FEA44))
+#define SYSCTL_PREEPROM_R       (*((volatile uint32_t *)0x400FEA58))
+#define SYSCTL_PRWTIMER_R       (*((volatile uint32_t *)0x400FEA5C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access registers (UDMA)
+//
+//*****************************************************************************
+#define UDMA_STAT_R             (*((volatile uint32_t *)0x400FF000))
+#define UDMA_CFG_R              (*((volatile uint32_t *)0x400FF004))
+#define UDMA_CTLBASE_R          (*((volatile uint32_t *)0x400FF008))
+#define UDMA_ALTBASE_R          (*((volatile uint32_t *)0x400FF00C))
+#define UDMA_WAITSTAT_R         (*((volatile uint32_t *)0x400FF010))
+#define UDMA_SWREQ_R            (*((volatile uint32_t *)0x400FF014))
+#define UDMA_USEBURSTSET_R      (*((volatile uint32_t *)0x400FF018))
+#define UDMA_USEBURSTCLR_R      (*((volatile uint32_t *)0x400FF01C))
+#define UDMA_REQMASKSET_R       (*((volatile uint32_t *)0x400FF020))
+#define UDMA_REQMASKCLR_R       (*((volatile uint32_t *)0x400FF024))
+#define UDMA_ENASET_R           (*((volatile uint32_t *)0x400FF028))
+#define UDMA_ENACLR_R           (*((volatile uint32_t *)0x400FF02C))
+#define UDMA_ALTSET_R           (*((volatile uint32_t *)0x400FF030))
+#define UDMA_ALTCLR_R           (*((volatile uint32_t *)0x400FF034))
+#define UDMA_PRIOSET_R          (*((volatile uint32_t *)0x400FF038))
+#define UDMA_PRIOCLR_R          (*((volatile uint32_t *)0x400FF03C))
+#define UDMA_ERRCLR_R           (*((volatile uint32_t *)0x400FF04C))
+#define UDMA_CHASGN_R           (*((volatile uint32_t *)0x400FF500))
+#define UDMA_CHIS_R             (*((volatile uint32_t *)0x400FF504))
+#define UDMA_CHMAP0_R           (*((volatile uint32_t *)0x400FF510))
+#define UDMA_CHMAP1_R           (*((volatile uint32_t *)0x400FF514))
+#define UDMA_CHMAP2_R           (*((volatile uint32_t *)0x400FF518))
+#define UDMA_CHMAP3_R           (*((volatile uint32_t *)0x400FF51C))
+
+//*****************************************************************************
+//
+// Micro Direct Memory Access (uDMA) offsets (UDMA)
+//
+//*****************************************************************************
+#define UDMA_SRCENDP            0x00000000  // DMA Channel Source Address End
+                                            // Pointer
+#define UDMA_DSTENDP            0x00000004  // DMA Channel Destination Address
+                                            // End Pointer
+#define UDMA_CHCTL              0x00000008  // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// NVIC registers (NVIC)
+//
+//*****************************************************************************
+#define NVIC_ACTLR_R            (*((volatile uint32_t *)0xE000E008))
+#define NVIC_ST_CTRL_R          (*((volatile uint32_t *)0xE000E010))
+#define NVIC_ST_RELOAD_R        (*((volatile uint32_t *)0xE000E014))
+#define NVIC_ST_CURRENT_R       (*((volatile uint32_t *)0xE000E018))
+#define NVIC_EN0_R              (*((volatile uint32_t *)0xE000E100))
+#define NVIC_EN1_R              (*((volatile uint32_t *)0xE000E104))
+#define NVIC_EN2_R              (*((volatile uint32_t *)0xE000E108))
+#define NVIC_EN3_R              (*((volatile uint32_t *)0xE000E10C))
+#define NVIC_EN4_R              (*((volatile uint32_t *)0xE000E110))
+#define NVIC_DIS0_R             (*((volatile uint32_t *)0xE000E180))
+#define NVIC_DIS1_R             (*((volatile uint32_t *)0xE000E184))
+#define NVIC_DIS2_R             (*((volatile uint32_t *)0xE000E188))
+#define NVIC_DIS3_R             (*((volatile uint32_t *)0xE000E18C))
+#define NVIC_DIS4_R             (*((volatile uint32_t *)0xE000E190))
+#define NVIC_PEND0_R            (*((volatile uint32_t *)0xE000E200))
+#define NVIC_PEND1_R            (*((volatile uint32_t *)0xE000E204))
+#define NVIC_PEND2_R            (*((volatile uint32_t *)0xE000E208))
+#define NVIC_PEND3_R            (*((volatile uint32_t *)0xE000E20C))
+#define NVIC_PEND4_R            (*((volatile uint32_t *)0xE000E210))
+#define NVIC_UNPEND0_R          (*((volatile uint32_t *)0xE000E280))
+#define NVIC_UNPEND1_R          (*((volatile uint32_t *)0xE000E284))
+#define NVIC_UNPEND2_R          (*((volatile uint32_t *)0xE000E288))
+#define NVIC_UNPEND3_R          (*((volatile uint32_t *)0xE000E28C))
+#define NVIC_UNPEND4_R          (*((volatile uint32_t *)0xE000E290))
+#define NVIC_ACTIVE0_R          (*((volatile uint32_t *)0xE000E300))
+#define NVIC_ACTIVE1_R          (*((volatile uint32_t *)0xE000E304))
+#define NVIC_ACTIVE2_R          (*((volatile uint32_t *)0xE000E308))
+#define NVIC_ACTIVE3_R          (*((volatile uint32_t *)0xE000E30C))
+#define NVIC_ACTIVE4_R          (*((volatile uint32_t *)0xE000E310))
+#define NVIC_PRI0_R             (*((volatile uint32_t *)0xE000E400))
+#define NVIC_PRI1_R             (*((volatile uint32_t *)0xE000E404))
+#define NVIC_PRI2_R             (*((volatile uint32_t *)0xE000E408))
+#define NVIC_PRI3_R             (*((volatile uint32_t *)0xE000E40C))
+#define NVIC_PRI4_R             (*((volatile uint32_t *)0xE000E410))
+#define NVIC_PRI5_R             (*((volatile uint32_t *)0xE000E414))
+#define NVIC_PRI6_R             (*((volatile uint32_t *)0xE000E418))
+#define NVIC_PRI7_R             (*((volatile uint32_t *)0xE000E41C))
+#define NVIC_PRI8_R             (*((volatile uint32_t *)0xE000E420))
+#define NVIC_PRI9_R             (*((volatile uint32_t *)0xE000E424))
+#define NVIC_PRI10_R            (*((volatile uint32_t *)0xE000E428))
+#define NVIC_PRI11_R            (*((volatile uint32_t *)0xE000E42C))
+#define NVIC_PRI12_R            (*((volatile uint32_t *)0xE000E430))
+#define NVIC_PRI13_R            (*((volatile uint32_t *)0xE000E434))
+#define NVIC_PRI14_R            (*((volatile uint32_t *)0xE000E438))
+#define NVIC_PRI15_R            (*((volatile uint32_t *)0xE000E43C))
+#define NVIC_PRI16_R            (*((volatile uint32_t *)0xE000E440))
+#define NVIC_PRI17_R            (*((volatile uint32_t *)0xE000E444))
+#define NVIC_PRI18_R            (*((volatile uint32_t *)0xE000E448))
+#define NVIC_PRI19_R            (*((volatile uint32_t *)0xE000E44C))
+#define NVIC_PRI20_R            (*((volatile uint32_t *)0xE000E450))
+#define NVIC_PRI21_R            (*((volatile uint32_t *)0xE000E454))
+#define NVIC_PRI22_R            (*((volatile uint32_t *)0xE000E458))
+#define NVIC_PRI23_R            (*((volatile uint32_t *)0xE000E45C))
+#define NVIC_PRI24_R            (*((volatile uint32_t *)0xE000E460))
+#define NVIC_PRI25_R            (*((volatile uint32_t *)0xE000E464))
+#define NVIC_PRI26_R            (*((volatile uint32_t *)0xE000E468))
+#define NVIC_PRI27_R            (*((volatile uint32_t *)0xE000E46C))
+#define NVIC_PRI28_R            (*((volatile uint32_t *)0xE000E470))
+#define NVIC_PRI29_R            (*((volatile uint32_t *)0xE000E474))
+#define NVIC_PRI30_R            (*((volatile uint32_t *)0xE000E478))
+#define NVIC_PRI31_R            (*((volatile uint32_t *)0xE000E47C))
+#define NVIC_PRI32_R            (*((volatile uint32_t *)0xE000E480))
+#define NVIC_PRI33_R            (*((volatile uint32_t *)0xE000E484))
+#define NVIC_PRI34_R            (*((volatile uint32_t *)0xE000E488))
+#define NVIC_CPUID_R            (*((volatile uint32_t *)0xE000ED00))
+#define NVIC_INT_CTRL_R         (*((volatile uint32_t *)0xE000ED04))
+#define NVIC_VTABLE_R           (*((volatile uint32_t *)0xE000ED08))
+#define NVIC_APINT_R            (*((volatile uint32_t *)0xE000ED0C))
+#define NVIC_SYS_CTRL_R         (*((volatile uint32_t *)0xE000ED10))
+#define NVIC_CFG_CTRL_R         (*((volatile uint32_t *)0xE000ED14))
+#define NVIC_SYS_PRI1_R         (*((volatile uint32_t *)0xE000ED18))
+#define NVIC_SYS_PRI2_R         (*((volatile uint32_t *)0xE000ED1C))
+#define NVIC_SYS_PRI3_R         (*((volatile uint32_t *)0xE000ED20))
+#define NVIC_SYS_HND_CTRL_R     (*((volatile uint32_t *)0xE000ED24))
+#define NVIC_FAULT_STAT_R       (*((volatile uint32_t *)0xE000ED28))
+#define NVIC_HFAULT_STAT_R      (*((volatile uint32_t *)0xE000ED2C))
+#define NVIC_DEBUG_STAT_R       (*((volatile uint32_t *)0xE000ED30))
+#define NVIC_MM_ADDR_R          (*((volatile uint32_t *)0xE000ED34))
+#define NVIC_FAULT_ADDR_R       (*((volatile uint32_t *)0xE000ED38))
+#define NVIC_CPAC_R             (*((volatile uint32_t *)0xE000ED88))
+#define NVIC_MPU_TYPE_R         (*((volatile uint32_t *)0xE000ED90))
+#define NVIC_MPU_CTRL_R         (*((volatile uint32_t *)0xE000ED94))
+#define NVIC_MPU_NUMBER_R       (*((volatile uint32_t *)0xE000ED98))
+#define NVIC_MPU_BASE_R         (*((volatile uint32_t *)0xE000ED9C))
+#define NVIC_MPU_ATTR_R         (*((volatile uint32_t *)0xE000EDA0))
+#define NVIC_MPU_BASE1_R        (*((volatile uint32_t *)0xE000EDA4))
+#define NVIC_MPU_ATTR1_R        (*((volatile uint32_t *)0xE000EDA8))
+#define NVIC_MPU_BASE2_R        (*((volatile uint32_t *)0xE000EDAC))
+#define NVIC_MPU_ATTR2_R        (*((volatile uint32_t *)0xE000EDB0))
+#define NVIC_MPU_BASE3_R        (*((volatile uint32_t *)0xE000EDB4))
+#define NVIC_MPU_ATTR3_R        (*((volatile uint32_t *)0xE000EDB8))
+#define NVIC_DBG_CTRL_R         (*((volatile uint32_t *)0xE000EDF0))
+#define NVIC_DBG_XFER_R         (*((volatile uint32_t *)0xE000EDF4))
+#define NVIC_DBG_DATA_R         (*((volatile uint32_t *)0xE000EDF8))
+#define NVIC_DBG_INT_R          (*((volatile uint32_t *)0xE000EDFC))
+#define NVIC_SW_TRIG_R          (*((volatile uint32_t *)0xE000EF00))
+#define NVIC_FPCC_R             (*((volatile uint32_t *)0xE000EF34))
+#define NVIC_FPCA_R             (*((volatile uint32_t *)0xE000EF38))
+#define NVIC_FPDSC_R            (*((volatile uint32_t *)0xE000EF3C))
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M              0xFFFFFFFF  // Watchdog Load Value
+#define WDT_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M             0xFFFFFFFF  // Watchdog Value
+#define WDT_VALUE_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC             0x80000000  // Write Complete
+#define WDT_CTL_INTTYPE         0x00000004  // Watchdog Interrupt Type
+#define WDT_CTL_RESEN           0x00000002  // Watchdog Reset Enable
+#define WDT_CTL_INTEN           0x00000001  // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M               0xFFFFFFFF  // Watchdog Interrupt Clear
+#define WDT_ICR_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS          0x00000001  // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS          0x00000001  // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL          0x00000100  // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M              0xFFFFFFFF  // Watchdog Lock
+#define WDT_LOCK_UNLOCKED       0x00000000  // Unlocked
+#define WDT_LOCK_LOCKED         0x00000001  // Locked
+#define WDT_LOCK_UNLOCK         0x1ACCE551  // Unlocks the watchdog timer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_GPIO_M          0x000000FF  // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_GPIO_M         0x000000FF  // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_GPIO_M         0x000000FF  // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_GPIO_M         0x000000FF  // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M             0xFFFFFFFF  // GPIO Lock
+#define GPIO_LOCK_UNLOCKED      0x00000000  // The GPIOCR register is unlocked
+                                            // and may be modified
+#define GPIO_LOCK_LOCKED        0x00000001  // The GPIOCR register is locked
+                                            // and may not be modified
+#define GPIO_LOCK_KEY           0x4C4F434B  // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port A.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PA7_M         0xF0000000  // PA7 Mask
+#define GPIO_PCTL_PA7_I2C1SDA   0x30000000  // I2C1SDA on PA7
+#define GPIO_PCTL_PA7_M1PWM3    0x50000000  // M1PWM3 on PA7
+#define GPIO_PCTL_PA6_M         0x0F000000  // PA6 Mask
+#define GPIO_PCTL_PA6_I2C1SCL   0x03000000  // I2C1SCL on PA6
+#define GPIO_PCTL_PA6_M1PWM2    0x05000000  // M1PWM2 on PA6
+#define GPIO_PCTL_PA5_M         0x00F00000  // PA5 Mask
+#define GPIO_PCTL_PA5_SSI0TX    0x00200000  // SSI0TX on PA5
+#define GPIO_PCTL_PA4_M         0x000F0000  // PA4 Mask
+#define GPIO_PCTL_PA4_SSI0RX    0x00020000  // SSI0RX on PA4
+#define GPIO_PCTL_PA3_M         0x0000F000  // PA3 Mask
+#define GPIO_PCTL_PA3_SSI0FSS   0x00002000  // SSI0FSS on PA3
+#define GPIO_PCTL_PA2_M         0x00000F00  // PA2 Mask
+#define GPIO_PCTL_PA2_SSI0CLK   0x00000200  // SSI0CLK on PA2
+#define GPIO_PCTL_PA1_M         0x000000F0  // PA1 Mask
+#define GPIO_PCTL_PA1_U0TX      0x00000010  // U0TX on PA1
+#define GPIO_PCTL_PA1_CAN1TX    0x00000080  // CAN1TX on PA1
+#define GPIO_PCTL_PA0_M         0x0000000F  // PA0 Mask
+#define GPIO_PCTL_PA0_U0RX      0x00000001  // U0RX on PA0
+#define GPIO_PCTL_PA0_CAN1RX    0x00000008  // CAN1RX on PA0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port B.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PB7_M         0xF0000000  // PB7 Mask
+#define GPIO_PCTL_PB7_SSI2TX    0x20000000  // SSI2TX on PB7
+#define GPIO_PCTL_PB7_M0PWM1    0x40000000  // M0PWM1 on PB7
+#define GPIO_PCTL_PB7_T0CCP1    0x70000000  // T0CCP1 on PB7
+#define GPIO_PCTL_PB6_M         0x0F000000  // PB6 Mask
+#define GPIO_PCTL_PB6_SSI2RX    0x02000000  // SSI2RX on PB6
+#define GPIO_PCTL_PB6_M0PWM0    0x04000000  // M0PWM0 on PB6
+#define GPIO_PCTL_PB6_T0CCP0    0x07000000  // T0CCP0 on PB6
+#define GPIO_PCTL_PB5_M         0x00F00000  // PB5 Mask
+#define GPIO_PCTL_PB5_SSI2FSS   0x00200000  // SSI2FSS on PB5
+#define GPIO_PCTL_PB5_M0PWM3    0x00400000  // M0PWM3 on PB5
+#define GPIO_PCTL_PB5_T1CCP1    0x00700000  // T1CCP1 on PB5
+#define GPIO_PCTL_PB5_CAN0TX    0x00800000  // CAN0TX on PB5
+#define GPIO_PCTL_PB4_M         0x000F0000  // PB4 Mask
+#define GPIO_PCTL_PB4_SSI2CLK   0x00020000  // SSI2CLK on PB4
+#define GPIO_PCTL_PB4_M0PWM2    0x00040000  // M0PWM2 on PB4
+#define GPIO_PCTL_PB4_T1CCP0    0x00070000  // T1CCP0 on PB4
+#define GPIO_PCTL_PB4_CAN0RX    0x00080000  // CAN0RX on PB4
+#define GPIO_PCTL_PB3_M         0x0000F000  // PB3 Mask
+#define GPIO_PCTL_PB3_I2C0SDA   0x00003000  // I2C0SDA on PB3
+#define GPIO_PCTL_PB3_T3CCP1    0x00007000  // T3CCP1 on PB3
+#define GPIO_PCTL_PB2_M         0x00000F00  // PB2 Mask
+#define GPIO_PCTL_PB2_I2C0SCL   0x00000300  // I2C0SCL on PB2
+#define GPIO_PCTL_PB2_T3CCP0    0x00000700  // T3CCP0 on PB2
+#define GPIO_PCTL_PB1_M         0x000000F0  // PB1 Mask
+#define GPIO_PCTL_PB1_USB0VBUS  0x00000000  // USB0VBUS on PB1
+#define GPIO_PCTL_PB1_U1TX      0x00000010  // U1TX on PB1
+#define GPIO_PCTL_PB1_T2CCP1    0x00000070  // T2CCP1 on PB1
+#define GPIO_PCTL_PB0_M         0x0000000F  // PB0 Mask
+#define GPIO_PCTL_PB0_USB0ID    0x00000000  // USB0ID on PB0
+#define GPIO_PCTL_PB0_U1RX      0x00000001  // U1RX on PB0
+#define GPIO_PCTL_PB0_T2CCP0    0x00000007  // T2CCP0 on PB0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port C.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PC7_M         0xF0000000  // PC7 Mask
+#define GPIO_PCTL_PC7_U3TX      0x10000000  // U3TX on PC7
+#define GPIO_PCTL_PC7_WT1CCP1   0x70000000  // WT1CCP1 on PC7
+#define GPIO_PCTL_PC7_USB0PFLT  0x80000000  // USB0PFLT on PC7
+#define GPIO_PCTL_PC6_M         0x0F000000  // PC6 Mask
+#define GPIO_PCTL_PC6_U3RX      0x01000000  // U3RX on PC6
+#define GPIO_PCTL_PC6_PHB1      0x06000000  // PHB1 on PC6
+#define GPIO_PCTL_PC6_WT1CCP0   0x07000000  // WT1CCP0 on PC6
+#define GPIO_PCTL_PC6_USB0EPEN  0x08000000  // USB0EPEN on PC6
+#define GPIO_PCTL_PC5_M         0x00F00000  // PC5 Mask
+#define GPIO_PCTL_PC5_U4TX      0x00100000  // U4TX on PC5
+#define GPIO_PCTL_PC5_U1TX      0x00200000  // U1TX on PC5
+#define GPIO_PCTL_PC5_M0PWM7    0x00400000  // M0PWM7 on PC5
+#define GPIO_PCTL_PC5_PHA1      0x00600000  // PHA1 on PC5
+#define GPIO_PCTL_PC5_WT0CCP1   0x00700000  // WT0CCP1 on PC5
+#define GPIO_PCTL_PC5_U1CTS     0x00800000  // U1CTS on PC5
+#define GPIO_PCTL_PC4_M         0x000F0000  // PC4 Mask
+#define GPIO_PCTL_PC4_U4RX      0x00010000  // U4RX on PC4
+#define GPIO_PCTL_PC4_U1RX      0x00020000  // U1RX on PC4
+#define GPIO_PCTL_PC4_M0PWM6    0x00040000  // M0PWM6 on PC4
+#define GPIO_PCTL_PC4_IDX1      0x00060000  // IDX1 on PC4
+#define GPIO_PCTL_PC4_WT0CCP0   0x00070000  // WT0CCP0 on PC4
+#define GPIO_PCTL_PC4_U1RTS     0x00080000  // U1RTS on PC4
+#define GPIO_PCTL_PC3_M         0x0000F000  // PC3 Mask
+#define GPIO_PCTL_PC3_TDO       0x00001000  // TDO on PC3
+#define GPIO_PCTL_PC3_T5CCP1    0x00007000  // T5CCP1 on PC3
+#define GPIO_PCTL_PC2_M         0x00000F00  // PC2 Mask
+#define GPIO_PCTL_PC2_TDI       0x00000100  // TDI on PC2
+#define GPIO_PCTL_PC2_T5CCP0    0x00000700  // T5CCP0 on PC2
+#define GPIO_PCTL_PC1_M         0x000000F0  // PC1 Mask
+#define GPIO_PCTL_PC1_TMS       0x00000010  // TMS on PC1
+#define GPIO_PCTL_PC1_T4CCP1    0x00000070  // T4CCP1 on PC1
+#define GPIO_PCTL_PC0_M         0x0000000F  // PC0 Mask
+#define GPIO_PCTL_PC0_TCK       0x00000001  // TCK on PC0
+#define GPIO_PCTL_PC0_T4CCP0    0x00000007  // T4CCP0 on PC0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port D.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PD7_M         0xF0000000  // PD7 Mask
+#define GPIO_PCTL_PD7_U2TX      0x10000000  // U2TX on PD7
+#define GPIO_PCTL_PD7_PHB0      0x60000000  // PHB0 on PD7
+#define GPIO_PCTL_PD7_WT5CCP1   0x70000000  // WT5CCP1 on PD7
+#define GPIO_PCTL_PD7_NMI       0x80000000  // NMI on PD7
+#define GPIO_PCTL_PD6_M         0x0F000000  // PD6 Mask
+#define GPIO_PCTL_PD6_U2RX      0x01000000  // U2RX on PD6
+#define GPIO_PCTL_PD6_M0FAULT0  0x04000000  // M0FAULT0 on PD6
+#define GPIO_PCTL_PD6_PHA0      0x06000000  // PHA0 on PD6
+#define GPIO_PCTL_PD6_WT5CCP0   0x07000000  // WT5CCP0 on PD6
+#define GPIO_PCTL_PD5_M         0x00F00000  // PD5 Mask
+#define GPIO_PCTL_PD5_USB0DP    0x00000000  // USB0DP on PD5
+#define GPIO_PCTL_PD5_U6TX      0x00100000  // U6TX on PD5
+#define GPIO_PCTL_PD5_WT4CCP1   0x00700000  // WT4CCP1 on PD5
+#define GPIO_PCTL_PD4_M         0x000F0000  // PD4 Mask
+#define GPIO_PCTL_PD4_USB0DM    0x00000000  // USB0DM on PD4
+#define GPIO_PCTL_PD4_U6RX      0x00010000  // U6RX on PD4
+#define GPIO_PCTL_PD4_WT4CCP0   0x00070000  // WT4CCP0 on PD4
+#define GPIO_PCTL_PD3_M         0x0000F000  // PD3 Mask
+#define GPIO_PCTL_PD3_AIN4      0x00000000  // AIN4 on PD3
+#define GPIO_PCTL_PD3_SSI3TX    0x00001000  // SSI3TX on PD3
+#define GPIO_PCTL_PD3_SSI1TX    0x00002000  // SSI1TX on PD3
+#define GPIO_PCTL_PD3_IDX0      0x00006000  // IDX0 on PD3
+#define GPIO_PCTL_PD3_WT3CCP1   0x00007000  // WT3CCP1 on PD3
+#define GPIO_PCTL_PD3_USB0PFLT  0x00008000  // USB0PFLT on PD3
+#define GPIO_PCTL_PD2_M         0x00000F00  // PD2 Mask
+#define GPIO_PCTL_PD2_AIN5      0x00000000  // AIN5 on PD2
+#define GPIO_PCTL_PD2_SSI3RX    0x00000100  // SSI3RX on PD2
+#define GPIO_PCTL_PD2_SSI1RX    0x00000200  // SSI1RX on PD2
+#define GPIO_PCTL_PD2_M0FAULT0  0x00000400  // M0FAULT0 on PD2
+#define GPIO_PCTL_PD2_WT3CCP0   0x00000700  // WT3CCP0 on PD2
+#define GPIO_PCTL_PD2_USB0EPEN  0x00000800  // USB0EPEN on PD2
+#define GPIO_PCTL_PD1_M         0x000000F0  // PD1 Mask
+#define GPIO_PCTL_PD1_AIN6      0x00000000  // AIN6 on PD1
+#define GPIO_PCTL_PD1_SSI3FSS   0x00000010  // SSI3FSS on PD1
+#define GPIO_PCTL_PD1_SSI1FSS   0x00000020  // SSI1FSS on PD1
+#define GPIO_PCTL_PD1_I2C3SDA   0x00000030  // I2C3SDA on PD1
+#define GPIO_PCTL_PD1_M0PWM7    0x00000040  // M0PWM7 on PD1
+#define GPIO_PCTL_PD1_M1PWM1    0x00000050  // M1PWM1 on PD1
+#define GPIO_PCTL_PD1_WT2CCP1   0x00000070  // WT2CCP1 on PD1
+#define GPIO_PCTL_PD0_M         0x0000000F  // PD0 Mask
+#define GPIO_PCTL_PD0_AIN7      0x00000000  // AIN7 on PD0
+#define GPIO_PCTL_PD0_SSI3CLK   0x00000001  // SSI3CLK on PD0
+#define GPIO_PCTL_PD0_SSI1CLK   0x00000002  // SSI1CLK on PD0
+#define GPIO_PCTL_PD0_I2C3SCL   0x00000003  // I2C3SCL on PD0
+#define GPIO_PCTL_PD0_M0PWM6    0x00000004  // M0PWM6 on PD0
+#define GPIO_PCTL_PD0_M1PWM0    0x00000005  // M1PWM0 on PD0
+#define GPIO_PCTL_PD0_WT2CCP0   0x00000007  // WT2CCP0 on PD0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port E.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PE5_M         0x00F00000  // PE5 Mask
+#define GPIO_PCTL_PE5_AIN8      0x00000000  // AIN8 on PE5
+#define GPIO_PCTL_PE5_U5TX      0x00100000  // U5TX on PE5
+#define GPIO_PCTL_PE5_I2C2SDA   0x00300000  // I2C2SDA on PE5
+#define GPIO_PCTL_PE5_M0PWM5    0x00400000  // M0PWM5 on PE5
+#define GPIO_PCTL_PE5_M1PWM3    0x00500000  // M1PWM3 on PE5
+#define GPIO_PCTL_PE5_CAN0TX    0x00800000  // CAN0TX on PE5
+#define GPIO_PCTL_PE4_M         0x000F0000  // PE4 Mask
+#define GPIO_PCTL_PE4_AIN9      0x00000000  // AIN9 on PE4
+#define GPIO_PCTL_PE4_U5RX      0x00010000  // U5RX on PE4
+#define GPIO_PCTL_PE4_I2C2SCL   0x00030000  // I2C2SCL on PE4
+#define GPIO_PCTL_PE4_M0PWM4    0x00040000  // M0PWM4 on PE4
+#define GPIO_PCTL_PE4_M1PWM2    0x00050000  // M1PWM2 on PE4
+#define GPIO_PCTL_PE4_CAN0RX    0x00080000  // CAN0RX on PE4
+#define GPIO_PCTL_PE3_M         0x0000F000  // PE3 Mask
+#define GPIO_PCTL_PE3_AIN0      0x00000000  // AIN0 on PE3
+#define GPIO_PCTL_PE2_M         0x00000F00  // PE2 Mask
+#define GPIO_PCTL_PE2_AIN1      0x00000000  // AIN1 on PE2
+#define GPIO_PCTL_PE1_M         0x000000F0  // PE1 Mask
+#define GPIO_PCTL_PE1_AIN2      0x00000000  // AIN2 on PE1
+#define GPIO_PCTL_PE1_U7TX      0x00000010  // U7TX on PE1
+#define GPIO_PCTL_PE0_M         0x0000000F  // PE0 Mask
+#define GPIO_PCTL_PE0_AIN3      0x00000000  // AIN3 on PE0
+#define GPIO_PCTL_PE0_U7RX      0x00000001  // U7RX on PE0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_PCTL register for
+// port F.
+//
+//*****************************************************************************
+#define GPIO_PCTL_PF4_M         0x000F0000  // PF4 Mask
+#define GPIO_PCTL_PF4_M1FAULT0  0x00050000  // M1FAULT0 on PF4
+#define GPIO_PCTL_PF4_IDX0      0x00060000  // IDX0 on PF4
+#define GPIO_PCTL_PF4_T2CCP0    0x00070000  // T2CCP0 on PF4
+#define GPIO_PCTL_PF4_USB0EPEN  0x00080000  // USB0EPEN on PF4
+#define GPIO_PCTL_PF3_M         0x0000F000  // PF3 Mask
+#define GPIO_PCTL_PF3_SSI1FSS   0x00002000  // SSI1FSS on PF3
+#define GPIO_PCTL_PF3_CAN0TX    0x00003000  // CAN0TX on PF3
+#define GPIO_PCTL_PF3_M1PWM7    0x00005000  // M1PWM7 on PF3
+#define GPIO_PCTL_PF3_T1CCP1    0x00007000  // T1CCP1 on PF3
+#define GPIO_PCTL_PF3_TRCLK     0x0000E000  // TRCLK on PF3
+#define GPIO_PCTL_PF2_M         0x00000F00  // PF2 Mask
+#define GPIO_PCTL_PF2_SSI1CLK   0x00000200  // SSI1CLK on PF2
+#define GPIO_PCTL_PF2_M0FAULT0  0x00000400  // M0FAULT0 on PF2
+#define GPIO_PCTL_PF2_M1PWM6    0x00000500  // M1PWM6 on PF2
+#define GPIO_PCTL_PF2_T1CCP0    0x00000700  // T1CCP0 on PF2
+#define GPIO_PCTL_PF2_TRD0      0x00000E00  // TRD0 on PF2
+#define GPIO_PCTL_PF1_M         0x000000F0  // PF1 Mask
+#define GPIO_PCTL_PF1_U1CTS     0x00000010  // U1CTS on PF1
+#define GPIO_PCTL_PF1_SSI1TX    0x00000020  // SSI1TX on PF1
+#define GPIO_PCTL_PF1_M1PWM5    0x00000050  // M1PWM5 on PF1
+#define GPIO_PCTL_PF1_PHB0      0x00000060  // PHB0 on PF1
+#define GPIO_PCTL_PF1_T0CCP1    0x00000070  // T0CCP1 on PF1
+#define GPIO_PCTL_PF1_C1O       0x00000090  // C1O on PF1
+#define GPIO_PCTL_PF1_TRD1      0x000000E0  // TRD1 on PF1
+#define GPIO_PCTL_PF0_M         0x0000000F  // PF0 Mask
+#define GPIO_PCTL_PF0_U1RTS     0x00000001  // U1RTS on PF0
+#define GPIO_PCTL_PF0_SSI1RX    0x00000002  // SSI1RX on PF0
+#define GPIO_PCTL_PF0_CAN0RX    0x00000003  // CAN0RX on PF0
+#define GPIO_PCTL_PF0_M1PWM4    0x00000005  // M1PWM4 on PF0
+#define GPIO_PCTL_PF0_PHA0      0x00000006  // PHA0 on PF0
+#define GPIO_PCTL_PF0_T0CCP0    0x00000007  // T0CCP0 on PF0
+#define GPIO_PCTL_PF0_NMI       0x00000008  // NMI on PF0
+#define GPIO_PCTL_PF0_C0O       0x00000009  // C0O on PF0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M           0x0000FF00  // SSI Serial Clock Rate
+#define SSI_CR0_SPH             0x00000080  // SSI Serial Clock Phase
+#define SSI_CR0_SPO             0x00000040  // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M           0x00000030  // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO        0x00000000  // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI          0x00000010  // Synchronous Serial Frame Format
+#define SSI_CR0_FRF_NMW         0x00000020  // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M           0x0000000F  // SSI Data Size Select
+#define SSI_CR0_DSS_4           0x00000003  // 4-bit data
+#define SSI_CR0_DSS_5           0x00000004  // 5-bit data
+#define SSI_CR0_DSS_6           0x00000005  // 6-bit data
+#define SSI_CR0_DSS_7           0x00000006  // 7-bit data
+#define SSI_CR0_DSS_8           0x00000007  // 8-bit data
+#define SSI_CR0_DSS_9           0x00000008  // 9-bit data
+#define SSI_CR0_DSS_10          0x00000009  // 10-bit data
+#define SSI_CR0_DSS_11          0x0000000A  // 11-bit data
+#define SSI_CR0_DSS_12          0x0000000B  // 12-bit data
+#define SSI_CR0_DSS_13          0x0000000C  // 13-bit data
+#define SSI_CR0_DSS_14          0x0000000D  // 14-bit data
+#define SSI_CR0_DSS_15          0x0000000E  // 15-bit data
+#define SSI_CR0_DSS_16          0x0000000F  // 16-bit data
+#define SSI_CR0_SCR_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOT             0x00000010  // End of Transmission
+#define SSI_CR1_MS              0x00000004  // SSI Master/Slave Select
+#define SSI_CR1_SSE             0x00000002  // SSI Synchronous Serial Port
+                                            // Enable
+#define SSI_CR1_LBM             0x00000001  // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M           0x0000FFFF  // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY              0x00000010  // SSI Busy Bit
+#define SSI_SR_RFF              0x00000008  // SSI Receive FIFO Full
+#define SSI_SR_RNE              0x00000004  // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF              0x00000002  // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE              0x00000001  // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M      0x000000FF  // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_TXIM             0x00000008  // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM             0x00000004  // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM             0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Mask
+#define SSI_IM_RORIM            0x00000001  // SSI Receive Overrun Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_TXRIS           0x00000008  // SSI Transmit FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RXRIS           0x00000004  // SSI Receive FIFO Raw Interrupt
+                                            // Status
+#define SSI_RIS_RTRIS           0x00000002  // SSI Receive Time-Out Raw
+                                            // Interrupt Status
+#define SSI_RIS_RORRIS          0x00000001  // SSI Receive Overrun Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_TXMIS           0x00000008  // SSI Transmit FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RXMIS           0x00000004  // SSI Receive FIFO Masked
+                                            // Interrupt Status
+#define SSI_MIS_RTMIS           0x00000002  // SSI Receive Time-Out Masked
+                                            // Interrupt Status
+#define SSI_MIS_RORMIS          0x00000001  // SSI Receive Overrun Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_RTIC            0x00000002  // SSI Receive Time-Out Interrupt
+                                            // Clear
+#define SSI_ICR_RORIC           0x00000001  // SSI Receive Overrun Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE       0x00000002  // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE       0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M             0x0000000F  // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL        0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define SSI_CC_CS_PIOSC         0x00000005  // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE              0x00000800  // UART Overrun Error
+#define UART_DR_BE              0x00000400  // UART Break Error
+#define UART_DR_PE              0x00000200  // UART Parity Error
+#define UART_DR_FE              0x00000100  // UART Framing Error
+#define UART_DR_DATA_M          0x000000FF  // Data Transmitted or Received
+#define UART_DR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE             0x00000008  // UART Overrun Error
+#define UART_RSR_BE             0x00000004  // UART Break Error
+#define UART_RSR_PE             0x00000002  // UART Parity Error
+#define UART_RSR_FE             0x00000001  // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M         0x000000FF  // Error Clear
+#define UART_ECR_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_TXFE            0x00000080  // UART Transmit FIFO Empty
+#define UART_FR_RXFF            0x00000040  // UART Receive FIFO Full
+#define UART_FR_TXFF            0x00000020  // UART Transmit FIFO Full
+#define UART_FR_RXFE            0x00000010  // UART Receive FIFO Empty
+#define UART_FR_BUSY            0x00000008  // UART Busy
+#define UART_FR_CTS             0x00000001  // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M     0x000000FF  // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M      0x0000FFFF  // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M     0x0000003F  // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS           0x00000080  // UART Stick Parity Select
+#define UART_LCRH_WLEN_M        0x00000060  // UART Word Length
+#define UART_LCRH_WLEN_5        0x00000000  // 5 bits (default)
+#define UART_LCRH_WLEN_6        0x00000020  // 6 bits
+#define UART_LCRH_WLEN_7        0x00000040  // 7 bits
+#define UART_LCRH_WLEN_8        0x00000060  // 8 bits
+#define UART_LCRH_FEN           0x00000010  // UART Enable FIFOs
+#define UART_LCRH_STP2          0x00000008  // UART Two Stop Bits Select
+#define UART_LCRH_EPS           0x00000004  // UART Even Parity Select
+#define UART_LCRH_PEN           0x00000002  // UART Parity Enable
+#define UART_LCRH_BRK           0x00000001  // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN          0x00008000  // Enable Clear To Send
+#define UART_CTL_RTSEN          0x00004000  // Enable Request to Send
+#define UART_CTL_RTS            0x00000800  // Request to Send
+#define UART_CTL_RXE            0x00000200  // UART Receive Enable
+#define UART_CTL_TXE            0x00000100  // UART Transmit Enable
+#define UART_CTL_LBE            0x00000080  // UART Loop Back Enable
+#define UART_CTL_HSE            0x00000020  // High-Speed Enable
+#define UART_CTL_EOT            0x00000010  // End of Transmission
+#define UART_CTL_SMART          0x00000008  // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP          0x00000004  // UART SIR Low-Power Mode
+#define UART_CTL_SIREN          0x00000002  // UART SIR Enable
+#define UART_CTL_UARTEN         0x00000001  // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M          0x00000038  // UART Receive Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_RX1_8         0x00000000  // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8         0x00000008  // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8         0x00000010  // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8         0x00000018  // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8         0x00000020  // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M          0x00000007  // UART Transmit Interrupt FIFO
+                                            // Level Select
+#define UART_IFLS_TX1_8         0x00000000  // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8         0x00000001  // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8         0x00000002  // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8         0x00000003  // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8         0x00000004  // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_9BITIM          0x00001000  // 9-Bit Mode Interrupt Mask
+#define UART_IM_OEIM            0x00000400  // UART Overrun Error Interrupt
+                                            // Mask
+#define UART_IM_BEIM            0x00000200  // UART Break Error Interrupt Mask
+#define UART_IM_PEIM            0x00000100  // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM            0x00000080  // UART Framing Error Interrupt
+                                            // Mask
+#define UART_IM_RTIM            0x00000040  // UART Receive Time-Out Interrupt
+                                            // Mask
+#define UART_IM_TXIM            0x00000020  // UART Transmit Interrupt Mask
+#define UART_IM_RXIM            0x00000010  // UART Receive Interrupt Mask
+#define UART_IM_CTSMIM          0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_9BITRIS        0x00001000  // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_OERIS          0x00000400  // UART Overrun Error Raw Interrupt
+                                            // Status
+#define UART_RIS_BERIS          0x00000200  // UART Break Error Raw Interrupt
+                                            // Status
+#define UART_RIS_PERIS          0x00000100  // UART Parity Error Raw Interrupt
+                                            // Status
+#define UART_RIS_FERIS          0x00000080  // UART Framing Error Raw Interrupt
+                                            // Status
+#define UART_RIS_RTRIS          0x00000040  // UART Receive Time-Out Raw
+                                            // Interrupt Status
+#define UART_RIS_TXRIS          0x00000020  // UART Transmit Raw Interrupt
+                                            // Status
+#define UART_RIS_RXRIS          0x00000010  // UART Receive Raw Interrupt
+                                            // Status
+#define UART_RIS_CTSRIS         0x00000002  // UART Clear to Send Modem Raw
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_9BITMIS        0x00001000  // 9-Bit Mode Masked Interrupt
+                                            // Status
+#define UART_MIS_OEMIS          0x00000400  // UART Overrun Error Masked
+                                            // Interrupt Status
+#define UART_MIS_BEMIS          0x00000200  // UART Break Error Masked
+                                            // Interrupt Status
+#define UART_MIS_PEMIS          0x00000100  // UART Parity Error Masked
+                                            // Interrupt Status
+#define UART_MIS_FEMIS          0x00000080  // UART Framing Error Masked
+                                            // Interrupt Status
+#define UART_MIS_RTMIS          0x00000040  // UART Receive Time-Out Masked
+                                            // Interrupt Status
+#define UART_MIS_TXMIS          0x00000020  // UART Transmit Masked Interrupt
+                                            // Status
+#define UART_MIS_RXMIS          0x00000010  // UART Receive Masked Interrupt
+                                            // Status
+#define UART_MIS_CTSMIS         0x00000002  // UART Clear to Send Modem Masked
+                                            // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_9BITIC         0x00001000  // 9-Bit Mode Interrupt Clear
+#define UART_ICR_OEIC           0x00000400  // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC           0x00000200  // Break Error Interrupt Clear
+#define UART_ICR_PEIC           0x00000100  // Parity Error Interrupt Clear
+#define UART_ICR_FEIC           0x00000080  // Framing Error Interrupt Clear
+#define UART_ICR_RTIC           0x00000040  // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC           0x00000020  // Transmit Interrupt Clear
+#define UART_ICR_RXIC           0x00000010  // Receive Interrupt Clear
+#define UART_ICR_CTSMIC         0x00000002  // UART Clear to Send Modem
+                                            // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR      0x00000004  // DMA on Error
+#define UART_DMACTL_TXDMAE      0x00000002  // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE      0x00000001  // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN    0x00008000  // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M    0x000000FF  // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M   0x000000FF  // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_NB              0x00000002  // 9-Bit Support
+#define UART_PP_SC              0x00000001  // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M            0x0000000F  // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK       0x00000000  // System clock (based on clock
+                                            // source and divisor factor)
+#define UART_CC_CS_PIOSC        0x00000005  // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M            0x000000FE  // I2C Slave Address
+#define I2C_MSA_RS              0x00000001  // Receive not send
+#define I2C_MSA_SA_S            1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_CLKTO           0x00000080  // Clock Timeout Error
+#define I2C_MCS_BUSBSY          0x00000040  // Bus Busy
+#define I2C_MCS_IDLE            0x00000020  // I2C Idle
+#define I2C_MCS_ARBLST          0x00000010  // Arbitration Lost
+#define I2C_MCS_HS              0x00000010  // High-Speed Enable
+#define I2C_MCS_ACK             0x00000008  // Data Acknowledge Enable
+#define I2C_MCS_DATACK          0x00000008  // Acknowledge Data
+#define I2C_MCS_ADRACK          0x00000004  // Acknowledge Address
+#define I2C_MCS_STOP            0x00000004  // Generate STOP
+#define I2C_MCS_ERROR           0x00000002  // Error
+#define I2C_MCS_START           0x00000002  // Generate START
+#define I2C_MCS_RUN             0x00000001  // I2C Master Enable
+#define I2C_MCS_BUSY            0x00000001  // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M          0x000000FF  // This byte contains the data
+                                            // transferred during a transaction
+#define I2C_MDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_HS             0x00000080  // High-Speed Enable
+#define I2C_MTPR_TPR_M          0x0000007F  // Timer Period
+#define I2C_MTPR_TPR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_CLKIM          0x00000002  // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM             0x00000001  // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_CLKRIS         0x00000002  // Clock Timeout Raw Interrupt
+                                            // Status
+#define I2C_MRIS_RIS            0x00000001  // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_CLKMIS         0x00000002  // Clock Timeout Masked Interrupt
+                                            // Status
+#define I2C_MMIS_MIS            0x00000001  // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_CLKIC          0x00000002  // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC             0x00000001  // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE             0x00000040  // I2C Glitch Filter Enable
+#define I2C_MCR_SFE             0x00000020  // I2C Slave Function Enable
+#define I2C_MCR_MFE             0x00000010  // I2C Master Function Enable
+#define I2C_MCR_LPBK            0x00000001  // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M     0x000000FF  // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA           0x00000002  // I2C SDA Status
+#define I2C_MBMON_SCL           0x00000001  // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M         0x00000070  // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS    0x00000000  // Bypass
+#define I2C_MCR2_GFPW_1         0x00000010  // 1 clock
+#define I2C_MCR2_GFPW_2         0x00000020  // 2 clocks
+#define I2C_MCR2_GFPW_3         0x00000030  // 3 clocks
+#define I2C_MCR2_GFPW_4         0x00000040  // 4 clocks
+#define I2C_MCR2_GFPW_8         0x00000050  // 8 clocks
+#define I2C_MCR2_GFPW_16        0x00000060  // 16 clocks
+#define I2C_MCR2_GFPW_31        0x00000070  // 31 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M          0x0000007F  // I2C Slave Own Address
+#define I2C_SOAR_OAR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_OAR2SEL        0x00000008  // OAR2 Address Matched
+#define I2C_SCSR_FBR            0x00000004  // First Byte Received
+#define I2C_SCSR_TREQ           0x00000002  // Transmit Request
+#define I2C_SCSR_DA             0x00000001  // Device Active
+#define I2C_SCSR_RREQ           0x00000001  // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M          0x000000FF  // Data for Transfer
+#define I2C_SDR_DATA_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_STOPIM         0x00000004  // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM        0x00000002  // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM         0x00000001  // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_STOPRIS        0x00000004  // Stop Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_STARTRIS       0x00000002  // Start Condition Raw Interrupt
+                                            // Status
+#define I2C_SRIS_DATARIS        0x00000001  // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_STOPMIS        0x00000004  // Stop Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_STARTMIS       0x00000002  // Start Condition Masked Interrupt
+                                            // Status
+#define I2C_SMIS_DATAMIS        0x00000001  // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_STOPIC         0x00000004  // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC        0x00000002  // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC         0x00000001  // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN        0x00000080  // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M        0x0000007F  // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL     0x00000002  // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN      0x00000001  // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS               0x00000001  // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3     0x00000008  // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2     0x00000004  // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1     0x00000002  // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0     0x00000001  // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3          0x00000008  // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2          0x00000004  // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1          0x00000002  // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0          0x00000001  // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN       0x00000080  // MnPWM7 Output Enable
+#define PWM_ENABLE_PWM6EN       0x00000040  // MnPWM6 Output Enable
+#define PWM_ENABLE_PWM5EN       0x00000020  // MnPWM5 Output Enable
+#define PWM_ENABLE_PWM4EN       0x00000010  // MnPWM4 Output Enable
+#define PWM_ENABLE_PWM3EN       0x00000008  // MnPWM3 Output Enable
+#define PWM_ENABLE_PWM2EN       0x00000004  // MnPWM2 Output Enable
+#define PWM_ENABLE_PWM1EN       0x00000002  // MnPWM1 Output Enable
+#define PWM_ENABLE_PWM0EN       0x00000001  // MnPWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV      0x00000080  // Invert MnPWM7 Signal
+#define PWM_INVERT_PWM6INV      0x00000040  // Invert MnPWM6 Signal
+#define PWM_INVERT_PWM5INV      0x00000020  // Invert MnPWM5 Signal
+#define PWM_INVERT_PWM4INV      0x00000010  // Invert MnPWM4 Signal
+#define PWM_INVERT_PWM3INV      0x00000008  // Invert MnPWM3 Signal
+#define PWM_INVERT_PWM2INV      0x00000004  // Invert MnPWM2 Signal
+#define PWM_INVERT_PWM1INV      0x00000002  // Invert MnPWM1 Signal
+#define PWM_INVERT_PWM0INV      0x00000001  // Invert MnPWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7        0x00000080  // MnPWM7 Fault
+#define PWM_FAULT_FAULT6        0x00000040  // MnPWM6 Fault
+#define PWM_FAULT_FAULT5        0x00000020  // MnPWM5 Fault
+#define PWM_FAULT_FAULT4        0x00000010  // MnPWM4 Fault
+#define PWM_FAULT_FAULT3        0x00000008  // MnPWM3 Fault
+#define PWM_FAULT_FAULT2        0x00000004  // MnPWM2 Fault
+#define PWM_FAULT_FAULT1        0x00000002  // MnPWM1 Fault
+#define PWM_FAULT_FAULT0        0x00000001  // MnPWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT1     0x00020000  // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0     0x00010000  // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3       0x00000008  // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2       0x00000004  // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1       0x00000002  // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0       0x00000001  // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT1       0x00020000  // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0       0x00010000  // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3         0x00000008  // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2         0x00000004  // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1         0x00000002  // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0         0x00000001  // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT1       0x00020000  // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0       0x00010000  // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3         0x00000008  // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2         0x00000004  // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1         0x00000002  // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0         0x00000001  // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT1       0x00000002  // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0       0x00000001  // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7       0x00000080  // MnPWM7 Fault Value
+#define PWM_FAULTVAL_PWM6       0x00000040  // MnPWM6 Fault Value
+#define PWM_FAULTVAL_PWM5       0x00000020  // MnPWM5 Fault Value
+#define PWM_FAULTVAL_PWM4       0x00000010  // MnPWM4 Fault Value
+#define PWM_FAULTVAL_PWM3       0x00000008  // MnPWM3 Fault Value
+#define PWM_FAULTVAL_PWM2       0x00000004  // MnPWM2 Fault Value
+#define PWM_FAULTVAL_PWM1       0x00000002  // MnPWM1 Fault Value
+#define PWM_FAULTVAL_PWM0       0x00000001  // MnPWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M      0x0000C000  // MnPWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC  0x00008000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC  0x0000C000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M      0x00003000  // MnPWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC  0x00002000  // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC  0x00003000  // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M      0x00000C00  // MnPWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC  0x00000800  // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC  0x00000C00  // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M      0x00000300  // MnPWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC  0x00000200  // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC  0x00000300  // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M      0x000000C0  // MnPWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC  0x00000080  // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC  0x000000C0  // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M      0x00000030  // MnPWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC  0x00000020  // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC  0x00000030  // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M      0x0000000C  // MnPWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC  0x00000008  // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC  0x0000000C  // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M      0x00000003  // MnPWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM    0x00000000  // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC  0x00000002  // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC  0x00000003  // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_0_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_0_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_0_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_0_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_0_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_0_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_0_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_0_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_0_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_0_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_0_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_0_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_0_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_0_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M            0x0000FFFF  // Counter Load Value
+#define PWM_0_LOAD_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M           0x0000FFFF  // Counter Value
+#define PWM_0_COUNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M            0x0000FFFF  // Comparator A Value
+#define PWM_0_CMPA_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M            0x0000FFFF  // Comparator B Value
+#define PWM_0_CMPB_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_0_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_0_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_0_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_0_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_0_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_0_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_0_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_0_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_0_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_0_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_0_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_0_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_0_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M    0x00000FFF  // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M    0x00000FFF  // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M       0x0000FFFF  // Minimum Fault Period
+#define PWM_0_MINFLTPER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_1_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_1_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_1_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_1_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_1_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_1_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_1_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_1_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_1_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_1_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_1_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_1_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_1_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_1_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_1_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_1_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_1_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_1_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_1_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_1_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_1_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_1_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_1_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_1_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_1_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_1_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_1_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_1_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_1_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_1_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_1_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_2_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_2_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_2_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_2_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_2_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_2_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_2_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_2_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_2_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_2_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_2_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_2_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_2_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_2_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_2_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_2_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_2_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_2_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_2_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_2_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_2_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_2_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_2_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_2_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_2_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_2_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_2_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_2_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_2_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_2_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_2_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH         0x00040000  // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER     0x00020000  // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC        0x00010000  // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M   0x0000C000  // PWMnDBFALL Update Mode
+#define PWM_3_CTL_DBFALLUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS  0x00008000  // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS  0x0000C000  // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M   0x00003000  // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I   0x00000000  // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS  0x00002000  // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS  0x00003000  // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M    0x00000C00  // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I    0x00000000  // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS   0x00000800  // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS   0x00000C00  // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M     0x00000300  // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENBUPD_LS    0x00000200  // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS    0x00000300  // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M     0x000000C0  // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I     0x00000000  // Immediate
+#define PWM_3_CTL_GENAUPD_LS    0x00000080  // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS    0x000000C0  // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD       0x00000020  // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD       0x00000010  // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD       0x00000008  // Load Register Update Mode
+#define PWM_3_CTL_DEBUG         0x00000004  // Debug Mode
+#define PWM_3_CTL_MODE          0x00000002  // Counter Mode
+#define PWM_3_CTL_ENABLE        0x00000001  // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD     0x00002000  // Trigger for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_TRCMPBU     0x00001000  // Trigger for Counter=PWMnCMPB Up
+#define PWM_3_INTEN_TRCMPAD     0x00000800  // Trigger for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_TRCMPAU     0x00000400  // Trigger for Counter=PWMnCMPA Up
+#define PWM_3_INTEN_TRCNTLOAD   0x00000200  // Trigger for Counter=PWMnLOAD
+#define PWM_3_INTEN_TRCNTZERO   0x00000100  // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD    0x00000020  // Interrupt for Counter=PWMnCMPB
+                                            // Down
+#define PWM_3_INTEN_INTCMPBU    0x00000010  // Interrupt for Counter=PWMnCMPB
+                                            // Up
+#define PWM_3_INTEN_INTCMPAD    0x00000008  // Interrupt for Counter=PWMnCMPA
+                                            // Down
+#define PWM_3_INTEN_INTCMPAU    0x00000004  // Interrupt for Counter=PWMnCMPA
+                                            // Up
+#define PWM_3_INTEN_INTCNTLOAD  0x00000002  // Interrupt for Counter=PWMnLOAD
+#define PWM_3_INTEN_INTCNTZERO  0x00000001  // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPBU      0x00000010  // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+                                            // Status
+#define PWM_3_RIS_INTCMPAU      0x00000004  // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD    0x00000002  // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO    0x00000001  // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD      0x00000020  // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU      0x00000010  // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD      0x00000008  // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU      0x00000004  // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD    0x00000002  // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO    0x00000001  // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M       0x0000FFFF  // Counter Load Value
+#define PWM_3_LOAD_LOAD_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M     0x0000FFFF  // Counter Value
+#define PWM_3_COUNT_COUNT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M      0x0000FFFF  // Comparator A Value
+#define PWM_3_CMPA_COMPA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M      0x0000FFFF  // Comparator B Value
+#define PWM_3_CMPB_COMPB_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100  // Invert pwmA
+#define PWM_3_GENA_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0  // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010  // Invert pwmA
+#define PWM_3_GENA_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030  // Drive pwmA High
+#define PWM_3_GENA_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV  0x00000004  // Invert pwmA
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008  // Drive pwmA Low
+#define PWM_3_GENA_ACTLOAD_ONE  0x0000000C  // Drive pwmA High
+#define PWM_3_GENA_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENA_ACTZERO_INV  0x00000001  // Invert pwmA
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002  // Drive pwmA Low
+#define PWM_3_GENA_ACTZERO_ONE  0x00000003  // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M   0x00000C00  // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBD_ZERO                                              \
+                                0x00000800  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPBU_M   0x00000300  // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100  // Invert pwmB
+#define PWM_3_GENB_ACTCMPBU_ZERO                                              \
+                                0x00000200  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAD_M   0x000000C0  // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAD_ZERO                                              \
+                                0x00000080  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0  // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAU_M   0x00000030  // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE                                              \
+                                0x00000000  // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010  // Invert pwmB
+#define PWM_3_GENB_ACTCMPAU_ZERO                                              \
+                                0x00000020  // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030  // Drive pwmB High
+#define PWM_3_GENB_ACTLOAD_M    0x0000000C  // Action for Counter=LOAD
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV  0x00000004  // Invert pwmB
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008  // Drive pwmB Low
+#define PWM_3_GENB_ACTLOAD_ONE  0x0000000C  // Drive pwmB High
+#define PWM_3_GENB_ACTZERO_M    0x00000003  // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000  // Do nothing
+#define PWM_3_GENB_ACTZERO_INV  0x00000001  // Invert pwmB
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002  // Drive pwmB Low
+#define PWM_3_GENB_ACTZERO_ONE  0x00000003  // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE      0x00000001  // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M                                              \
+                                0x00000FFF  // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT1    0x00000002  // Fault1 Input
+#define PWM_3_FLTSRC0_FAULT0    0x00000001  // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7     0x00000080  // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6     0x00000040  // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5     0x00000020  // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4     0x00000010  // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3     0x00000008  // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2     0x00000004  // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1     0x00000002  // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0     0x00000001  // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M   0x0000FFFF  // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT1     0x00000002  // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0     0x00000001  // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT1   0x00000002  // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0   0x00000001  // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7    0x00000080  // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6    0x00000040  // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5    0x00000020  // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4    0x00000010  // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3    0x00000008  // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2    0x00000004  // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1    0x00000002  // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0    0x00000001  // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_ONE              0x00000400  // One-Shot Mode
+#define PWM_PP_EFAULT           0x00000200  // Extended Fault
+#define PWM_PP_ESYNC            0x00000100  // Extended Synchronization
+#define PWM_PP_FCNT_M           0x000000F0  // Fault Inputs (per PWM unit)
+#define PWM_PP_GCNT_M           0x0000000F  // Generators
+#define PWM_PP_FCNT_S           4
+#define PWM_PP_GCNT_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M       0x000F0000  // Input Filter Prescale Count
+#define QEI_CTL_FILTEN          0x00002000  // Enable Input Filter
+#define QEI_CTL_STALLEN         0x00001000  // Stall QEI
+#define QEI_CTL_INVI            0x00000800  // Invert Index Pulse
+#define QEI_CTL_INVB            0x00000400  // Invert PhB
+#define QEI_CTL_INVA            0x00000200  // Invert PhA
+#define QEI_CTL_VELDIV_M        0x000001C0  // Predivide Velocity
+#define QEI_CTL_VELDIV_1        0x00000000  // QEI clock /1
+#define QEI_CTL_VELDIV_2        0x00000040  // QEI clock /2
+#define QEI_CTL_VELDIV_4        0x00000080  // QEI clock /4
+#define QEI_CTL_VELDIV_8        0x000000C0  // QEI clock /8
+#define QEI_CTL_VELDIV_16       0x00000100  // QEI clock /16
+#define QEI_CTL_VELDIV_32       0x00000140  // QEI clock /32
+#define QEI_CTL_VELDIV_64       0x00000180  // QEI clock /64
+#define QEI_CTL_VELDIV_128      0x000001C0  // QEI clock /128
+#define QEI_CTL_VELEN           0x00000020  // Capture Velocity
+#define QEI_CTL_RESMODE         0x00000010  // Reset Mode
+#define QEI_CTL_CAPMODE         0x00000008  // Capture Mode
+#define QEI_CTL_SIGMODE         0x00000004  // Signal Mode
+#define QEI_CTL_SWAP            0x00000002  // Swap Signals
+#define QEI_CTL_ENABLE          0x00000001  // Enable QEI
+#define QEI_CTL_FILTCNT_S       16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION      0x00000002  // Direction of Rotation
+#define QEI_STAT_ERROR          0x00000001  // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M               0xFFFFFFFF  // Current Position Integrator
+                                            // Value
+#define QEI_POS_S               0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M            0xFFFFFFFF  // Maximum Position Integrator
+                                            // Value
+#define QEI_MAXPOS_S            0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M              0xFFFFFFFF  // Velocity Timer Load Value
+#define QEI_LOAD_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M              0xFFFFFFFF  // Velocity Timer Current Value
+#define QEI_TIME_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M             0xFFFFFFFF  // Velocity Pulse Count
+#define QEI_COUNT_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M             0xFFFFFFFF  // Velocity
+#define QEI_SPEED_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR         0x00000008  // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR           0x00000004  // Direction Change Interrupt
+                                            // Enable
+#define QEI_INTEN_TIMER         0x00000002  // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX         0x00000001  // Index Pulse Detected Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR           0x00000008  // Phase Error Detected
+#define QEI_RIS_DIR             0x00000004  // Direction Change Detected
+#define QEI_RIS_TIMER           0x00000002  // Velocity Timer Expired
+#define QEI_RIS_INDEX           0x00000001  // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR           0x00000008  // Phase Error Interrupt
+#define QEI_ISC_DIR             0x00000004  // Direction Change Interrupt
+#define QEI_ISC_TIMER           0x00000002  // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX           0x00000001  // Index Pulse Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M             0x00000007  // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER  0x00000000  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit timer
+                                            // configuration
+#define TIMER_CFG_32_BIT_RTC    0x00000001  // For a 16/32-bit timer, this
+                                            // value selects the 32-bit
+                                            // real-time clock (RTC) counter
+                                            // configuration
+#define TIMER_CFG_16_BIT        0x00000004  // For a 16/32-bit timer, this
+                                            // value selects the 16-bit timer
+                                            // configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TAPLO        0x00000800  // GPTM Timer A PWM Legacy
+                                            // Operation
+#define TIMER_TAMR_TAMRSU       0x00000400  // GPTM Timer A Match Register
+                                            // Update
+#define TIMER_TAMR_TAPWMIE      0x00000200  // GPTM Timer A PWM Interrupt
+                                            // Enable
+#define TIMER_TAMR_TAILD        0x00000100  // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS      0x00000080  // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT        0x00000040  // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE        0x00000020  // GPTM Timer A Match Interrupt
+                                            // Enable
+#define TIMER_TAMR_TACDIR       0x00000010  // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS        0x00000008  // GPTM Timer A Alternate Mode
+                                            // Select
+#define TIMER_TAMR_TACMR        0x00000004  // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M       0x00000003  // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TBPLO        0x00000800  // GPTM Timer B PWM Legacy
+                                            // Operation
+#define TIMER_TBMR_TBMRSU       0x00000400  // GPTM Timer B Match Register
+                                            // Update
+#define TIMER_TBMR_TBPWMIE      0x00000200  // GPTM Timer B PWM Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBILD        0x00000100  // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS      0x00000080  // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT        0x00000040  // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE        0x00000020  // GPTM Timer B Match Interrupt
+                                            // Enable
+#define TIMER_TBMR_TBCDIR       0x00000010  // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS        0x00000008  // GPTM Timer B Alternate Mode
+                                            // Select
+#define TIMER_TBMR_TBCMR        0x00000004  // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M       0x00000003  // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT  0x00000001  // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD  0x00000002  // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP     0x00000003  // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML        0x00004000  // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE         0x00002000  // GPTM Timer B Output Trigger
+                                            // Enable
+#define TIMER_CTL_TBEVENT_M     0x00000C00  // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TBEVENT_NEG   0x00000400  // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH  0x00000C00  // Both edges
+#define TIMER_CTL_TBSTALL       0x00000200  // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN          0x00000100  // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML        0x00000040  // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE         0x00000020  // GPTM Timer A Output Trigger
+                                            // Enable
+#define TIMER_CTL_RTCEN         0x00000010  // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M     0x0000000C  // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS   0x00000000  // Positive edge
+#define TIMER_CTL_TAEVENT_NEG   0x00000004  // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH  0x0000000C  // Both edges
+#define TIMER_CTL_TASTALL       0x00000002  // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN          0x00000001  // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M    0x00C00000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000  // GPTM 32/64-Bit Timer 5 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT5_TA   0x00400000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TB   0x00800000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M    0x00300000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000  // GPTM 32/64-Bit Timer 4 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT4_TA   0x00100000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TB   0x00200000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M    0x000C0000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000  // GPTM 32/64-Bit Timer 3 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT3_TA   0x00040000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TB   0x00080000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M    0x00030000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000  // GPTM 32/64-Bit Timer 2 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT2_TA   0x00010000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TB   0x00020000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 2 is triggered
+#define TIMER_SYNC_SYNCWT1_M    0x0000C000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000  // GPTM 32/64-Bit Timer 1 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT1_TA   0x00004000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TB   0x00008000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M    0x00003000  // Synchronize GPTM 32/64-Bit Timer
+                                            // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000  // GPTM 32/64-Bit Timer 0 is not
+                                            // affected
+#define TIMER_SYNC_SYNCWT0_TA   0x00001000  // A timeout event for Timer A of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TB   0x00002000  // A timeout event for Timer B of
+                                            // GPTM 32/64-Bit Timer 0 is
+                                            // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000  // A timeout event for both Timer A
+                                            // and Timer B of GPTM 32/64-Bit
+                                            // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT5_M     0x00000C00  // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNCT5_NONE  0x00000000  // GPTM5 is not affected
+#define TIMER_SYNC_SYNCT5_TA    0x00000400  // A timeout event for Timer A of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TB    0x00000800  // A timeout event for Timer B of
+                                            // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TATB  0x00000C00  // A timeout event for both Timer A
+                                            // and Timer B of GPTM5 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT4_M     0x00000300  // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNCT4_NONE  0x00000000  // GPTM4 is not affected
+#define TIMER_SYNC_SYNCT4_TA    0x00000100  // A timeout event for Timer A of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TB    0x00000200  // A timeout event for Timer B of
+                                            // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TATB  0x00000300  // A timeout event for both Timer A
+                                            // and Timer B of GPTM4 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT3_M     0x000000C0  // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNCT3_NONE  0x00000000  // GPTM3 is not affected
+#define TIMER_SYNC_SYNCT3_TA    0x00000040  // A timeout event for Timer A of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TB    0x00000080  // A timeout event for Timer B of
+                                            // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TATB  0x000000C0  // A timeout event for both Timer A
+                                            // and Timer B of GPTM3 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT2_M     0x00000030  // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNCT2_NONE  0x00000000  // GPTM2 is not affected
+#define TIMER_SYNC_SYNCT2_TA    0x00000010  // A timeout event for Timer A of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TB    0x00000020  // A timeout event for Timer B of
+                                            // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TATB  0x00000030  // A timeout event for both Timer A
+                                            // and Timer B of GPTM2 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT1_M     0x0000000C  // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNCT1_NONE  0x00000000  // GPTM1 is not affected
+#define TIMER_SYNC_SYNCT1_TA    0x00000004  // A timeout event for Timer A of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TB    0x00000008  // A timeout event for Timer B of
+                                            // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TATB  0x0000000C  // A timeout event for both Timer A
+                                            // and Timer B of GPTM1 is
+                                            // triggered
+#define TIMER_SYNC_SYNCT0_M     0x00000003  // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNCT0_NONE  0x00000000  // GPTM0 is not affected
+#define TIMER_SYNC_SYNCT0_TA    0x00000001  // A timeout event for Timer A of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TB    0x00000002  // A timeout event for Timer B of
+                                            // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TATB  0x00000003  // A timeout event for both Timer A
+                                            // and Timer B of GPTM0 is
+                                            // triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM         0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Mask
+#define TIMER_IMR_TBMIM         0x00000800  // GPTM Timer B Match Interrupt
+                                            // Mask
+#define TIMER_IMR_CBEIM         0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CBMIM         0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TBTOIM        0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Mask
+#define TIMER_IMR_TAMIM         0x00000010  // GPTM Timer A Match Interrupt
+                                            // Mask
+#define TIMER_IMR_RTCIM         0x00000008  // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM         0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Mask
+#define TIMER_IMR_CAMIM         0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Mask
+#define TIMER_IMR_TATOIM        0x00000001  // GPTM Timer A Time-Out Interrupt
+                                            // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Raw Interrupt Status
+#define TIMER_RIS_TBMRIS        0x00000800  // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CBMRIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TBTORIS       0x00000100  // GPTM Timer B Time-Out Raw
+                                            // Interrupt
+#define TIMER_RIS_TAMRIS        0x00000010  // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS        0x00000008  // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Raw Interrupt
+#define TIMER_RIS_CAMRIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Raw Interrupt
+#define TIMER_RIS_TATORIS       0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS        0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Masked Interrupt Status
+#define TIMER_MIS_TBMMIS        0x00000800  // GPTM Timer B Match Masked
+                                            // Interrupt
+#define TIMER_MIS_CBEMIS        0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CBMMIS        0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TBTOMIS       0x00000100  // GPTM Timer B Time-Out Masked
+                                            // Interrupt
+#define TIMER_MIS_TAMMIS        0x00000010  // GPTM Timer A Match Masked
+                                            // Interrupt
+#define TIMER_MIS_RTCMIS        0x00000008  // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS        0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Masked Interrupt
+#define TIMER_MIS_CAMMIS        0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Masked Interrupt
+#define TIMER_MIS_TATOMIS       0x00000001  // GPTM Timer A Time-Out Masked
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT       0x00010000  // 32/64-Bit Wide GPTM Write Update
+                                            // Error Interrupt Clear
+#define TIMER_ICR_TBMCINT       0x00000800  // GPTM Timer B Match Interrupt
+                                            // Clear
+#define TIMER_ICR_CBECINT       0x00000400  // GPTM Timer B Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CBMCINT       0x00000200  // GPTM Timer B Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TBTOCINT      0x00000100  // GPTM Timer B Time-Out Interrupt
+                                            // Clear
+#define TIMER_ICR_TAMCINT       0x00000010  // GPTM Timer A Match Interrupt
+                                            // Clear
+#define TIMER_ICR_RTCCINT       0x00000008  // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT       0x00000004  // GPTM Timer A Capture Mode Event
+                                            // Interrupt Clear
+#define TIMER_ICR_CAMCINT       0x00000002  // GPTM Timer A Capture Mode Match
+                                            // Interrupt Clear
+#define TIMER_ICR_TATOCINT      0x00000001  // GPTM Timer A Time-Out Raw
+                                            // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M           0xFFFFFFFF  // GPTM Timer A Interval Load
+                                            // Register
+#define TIMER_TAILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M           0xFFFFFFFF  // GPTM Timer B Interval Load
+                                            // Register
+#define TIMER_TBILR_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M   0xFFFFFFFF  // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M   0xFFFFFFFF  // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M     0x0000FF00  // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M      0x000000FF  // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S     8
+#define TIMER_TAPR_TAPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M     0x0000FF00  // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M      0x000000FF  // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S     8
+#define TIMER_TBPR_TBPSR_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M   0x0000FF00  // GPTM Timer A Prescale Match High
+                                            // Byte
+#define TIMER_TAPMR_TAPSMR_M    0x000000FF  // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S   8
+#define TIMER_TAPMR_TAPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M   0x0000FF00  // GPTM Timer B Prescale Match High
+                                            // Byte
+#define TIMER_TBPMR_TBPSMR_M    0x000000FF  // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S   8
+#define TIMER_TBPMR_TBPSMR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M             0xFFFFFFFF  // GPTM Timer A Register
+#define TIMER_TAR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M             0xFFFFFFFF  // GPTM Timer B Register
+#define TIMER_TBR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M             0xFFFFFFFF  // GPTM Timer A Value
+#define TIMER_TAV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M             0xFFFFFFFF  // GPTM Timer B Value
+#define TIMER_TBV_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M     0x0000FFFF  // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M        0x0000FFFF  // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M        0x0000FFFF  // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_SIZE_M         0x0000000F  // Count Size
+#define TIMER_PP_SIZE_16        0x00000000  // Timer A and Timer B counters are
+                                            // 16 bits each with an 8-bit
+                                            // prescale counter
+#define TIMER_PP_SIZE_32        0x00000001  // Timer A and Timer B counters are
+                                            // 32 bits each with a 16-bit
+                                            // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY          0x00010000  // ADC Busy
+#define ADC_ACTSS_ASEN3         0x00000008  // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2         0x00000004  // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1         0x00000002  // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0         0x00000001  // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC           0x00010000  // Digital Comparator Raw Interrupt
+                                            // Status
+#define ADC_RIS_INR3            0x00000008  // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2            0x00000004  // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1            0x00000002  // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0            0x00000001  // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3          0x00080000  // Digital Comparator Interrupt on
+                                            // SS3
+#define ADC_IM_DCONSS2          0x00040000  // Digital Comparator Interrupt on
+                                            // SS2
+#define ADC_IM_DCONSS1          0x00020000  // Digital Comparator Interrupt on
+                                            // SS1
+#define ADC_IM_DCONSS0          0x00010000  // Digital Comparator Interrupt on
+                                            // SS0
+#define ADC_IM_MASK3            0x00000008  // SS3 Interrupt Mask
+#define ADC_IM_MASK2            0x00000004  // SS2 Interrupt Mask
+#define ADC_IM_MASK1            0x00000002  // SS1 Interrupt Mask
+#define ADC_IM_MASK0            0x00000001  // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3         0x00080000  // Digital Comparator Interrupt
+                                            // Status on SS3
+#define ADC_ISC_DCINSS2         0x00040000  // Digital Comparator Interrupt
+                                            // Status on SS2
+#define ADC_ISC_DCINSS1         0x00020000  // Digital Comparator Interrupt
+                                            // Status on SS1
+#define ADC_ISC_DCINSS0         0x00010000  // Digital Comparator Interrupt
+                                            // Status on SS0
+#define ADC_ISC_IN3             0x00000008  // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2             0x00000004  // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1             0x00000002  // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0             0x00000001  // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3           0x00000008  // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2           0x00000004  // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1           0x00000002  // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0           0x00000001  // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M          0x0000F000  // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM3_COMP0      0x00001000  // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1      0x00002000  // Analog Comparator 1
+#define ADC_EMUX_EM3_EXTERNAL   0x00004000  // External (GPIO Pins)
+#define ADC_EMUX_EM3_TIMER      0x00005000  // Timer
+#define ADC_EMUX_EM3_PWM0       0x00006000  // PWM generator 0
+#define ADC_EMUX_EM3_PWM1       0x00007000  // PWM generator 1
+#define ADC_EMUX_EM3_PWM2       0x00008000  // PWM generator 2
+#define ADC_EMUX_EM3_PWM3       0x00009000  // PWM generator 3
+#define ADC_EMUX_EM3_ALWAYS     0x0000F000  // Always (continuously sample)
+#define ADC_EMUX_EM2_M          0x00000F00  // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM2_COMP0      0x00000100  // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1      0x00000200  // Analog Comparator 1
+#define ADC_EMUX_EM2_EXTERNAL   0x00000400  // External (GPIO Pins)
+#define ADC_EMUX_EM2_TIMER      0x00000500  // Timer
+#define ADC_EMUX_EM2_PWM0       0x00000600  // PWM generator 0
+#define ADC_EMUX_EM2_PWM1       0x00000700  // PWM generator 1
+#define ADC_EMUX_EM2_PWM2       0x00000800  // PWM generator 2
+#define ADC_EMUX_EM2_PWM3       0x00000900  // PWM generator 3
+#define ADC_EMUX_EM2_ALWAYS     0x00000F00  // Always (continuously sample)
+#define ADC_EMUX_EM1_M          0x000000F0  // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM1_COMP0      0x00000010  // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1      0x00000020  // Analog Comparator 1
+#define ADC_EMUX_EM1_EXTERNAL   0x00000040  // External (GPIO Pins)
+#define ADC_EMUX_EM1_TIMER      0x00000050  // Timer
+#define ADC_EMUX_EM1_PWM0       0x00000060  // PWM generator 0
+#define ADC_EMUX_EM1_PWM1       0x00000070  // PWM generator 1
+#define ADC_EMUX_EM1_PWM2       0x00000080  // PWM generator 2
+#define ADC_EMUX_EM1_PWM3       0x00000090  // PWM generator 3
+#define ADC_EMUX_EM1_ALWAYS     0x000000F0  // Always (continuously sample)
+#define ADC_EMUX_EM0_M          0x0000000F  // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR  0x00000000  // Processor (default)
+#define ADC_EMUX_EM0_COMP0      0x00000001  // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1      0x00000002  // Analog Comparator 1
+#define ADC_EMUX_EM0_EXTERNAL   0x00000004  // External (GPIO Pins)
+#define ADC_EMUX_EM0_TIMER      0x00000005  // Timer
+#define ADC_EMUX_EM0_PWM0       0x00000006  // PWM generator 0
+#define ADC_EMUX_EM0_PWM1       0x00000007  // PWM generator 1
+#define ADC_EMUX_EM0_PWM2       0x00000008  // PWM generator 2
+#define ADC_EMUX_EM0_PWM3       0x00000009  // PWM generator 3
+#define ADC_EMUX_EM0_ALWAYS     0x0000000F  // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3           0x00000008  // SS3 FIFO Underflow
+#define ADC_USTAT_UV2           0x00000004  // SS2 FIFO Underflow
+#define ADC_USTAT_UV1           0x00000002  // SS1 FIFO Underflow
+#define ADC_USTAT_UV0           0x00000001  // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M         0x30000000  // Generator 3 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS3_0         0x00000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS3_1         0x10000000  // Use Generator 3 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS2_M         0x00300000  // Generator 2 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS2_0         0x00000000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS2_1         0x00100000  // Use Generator 2 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS1_M         0x00003000  // Generator 1 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS1_0         0x00000000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS1_1         0x00001000  // Use Generator 1 (and its
+                                            // trigger) in PWM module 1
+#define ADC_TSSEL_PS0_M         0x00000030  // Generator 0 PWM Module Trigger
+                                            // Select
+#define ADC_TSSEL_PS0_0         0x00000000  // Use Generator 0 (and its
+                                            // trigger) in PWM module 0
+#define ADC_TSSEL_PS0_1         0x00000010  // Use Generator 0 (and its
+                                            // trigger) in PWM module 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M         0x00003000  // SS3 Priority
+#define ADC_SSPRI_SS2_M         0x00000300  // SS2 Priority
+#define ADC_SSPRI_SS1_M         0x00000030  // SS1 Priority
+#define ADC_SSPRI_SS0_M         0x00000003  // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M         0x0000000F  // Phase Difference
+#define ADC_SPC_PHASE_0         0x00000000  // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5      0x00000001  // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45        0x00000002  // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5      0x00000003  // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90        0x00000004  // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5     0x00000005  // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135       0x00000006  // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5     0x00000007  // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180       0x00000008  // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5     0x00000009  // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225       0x0000000A  // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5     0x0000000B  // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270       0x0000000C  // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5     0x0000000D  // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315       0x0000000E  // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5     0x0000000F  // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC          0x80000000  // Global Synchronize
+#define ADC_PSSI_SYNCWAIT       0x08000000  // Synchronize Wait
+#define ADC_PSSI_SS3            0x00000008  // SS3 Initiate
+#define ADC_PSSI_SS2            0x00000004  // SS2 Initiate
+#define ADC_PSSI_SS1            0x00000002  // SS1 Initiate
+#define ADC_PSSI_SS0            0x00000001  // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M           0x00000007  // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF         0x00000000  // No hardware oversampling
+#define ADC_SAC_AVG_2X          0x00000001  // 2x hardware oversampling
+#define ADC_SAC_AVG_4X          0x00000002  // 4x hardware oversampling
+#define ADC_SAC_AVG_8X          0x00000003  // 8x hardware oversampling
+#define ADC_SAC_AVG_16X         0x00000004  // 16x hardware oversampling
+#define ADC_SAC_AVG_32X         0x00000005  // 32x hardware oversampling
+#define ADC_SAC_AVG_64X         0x00000006  // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7        0x00000080  // Digital Comparator 7 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT6        0x00000040  // Digital Comparator 6 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT5        0x00000020  // Digital Comparator 5 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT4        0x00000010  // Digital Comparator 4 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT3        0x00000008  // Digital Comparator 3 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT2        0x00000004  // Digital Comparator 2 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT1        0x00000002  // Digital Comparator 1 Interrupt
+                                            // Status and Clear
+#define ADC_DCISC_DCINT0        0x00000001  // Digital Comparator 0 Interrupt
+                                            // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF_M          0x00000001  // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL   0x00000000  // VDDA and GNDA are the voltage
+                                            // references
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M       0xF0000000  // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M       0x0F000000  // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M       0x00F00000  // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M       0x000F0000  // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S       28
+#define ADC_SSMUX0_MUX6_S       24
+#define ADC_SSMUX0_MUX5_S       20
+#define ADC_SSMUX0_MUX4_S       16
+#define ADC_SSMUX0_MUX3_S       12
+#define ADC_SSMUX0_MUX2_S       8
+#define ADC_SSMUX0_MUX1_S       4
+#define ADC_SSMUX0_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7          0x80000000  // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7          0x40000000  // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7         0x20000000  // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7           0x10000000  // 8th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS6          0x08000000  // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6          0x04000000  // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6         0x02000000  // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6           0x01000000  // 7th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS5          0x00800000  // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5          0x00400000  // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5         0x00200000  // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5           0x00100000  // 6th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS4          0x00080000  // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4          0x00040000  // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4         0x00020000  // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4           0x00010000  // 5th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL0_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT0_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S     4
+#define ADC_SSFSTAT0_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP        0x10000000  // Sample 7 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S6DCOP        0x01000000  // Sample 6 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S5DCOP        0x00100000  // Sample 5 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S4DCOP        0x00010000  // Sample 4 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP0_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M     0xF0000000  // Sample 7 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_M     0x0F000000  // Sample 6 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S5DCSEL_M     0x00F00000  // Sample 5 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S4DCSEL_M     0x000F0000  // Sample 4 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC0_S6DCSEL_S     24
+#define ADC_SSDC0_S5DCSEL_S     20
+#define ADC_SSDC0_S4DCSEL_S     16
+#define ADC_SSDC0_S3DCSEL_S     12
+#define ADC_SSDC0_S2DCSEL_S     8
+#define ADC_SSDC0_S1DCSEL_S     4
+#define ADC_SSDC0_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S       12
+#define ADC_SSMUX1_MUX2_S       8
+#define ADC_SSMUX1_MUX1_S       4
+#define ADC_SSMUX1_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL1_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT1_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S     4
+#define ADC_SSFSTAT1_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP1_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC1_S2DCSEL_S     8
+#define ADC_SSDC1_S1DCSEL_S     4
+#define ADC_SSDC1_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M       0x0000F000  // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M       0x00000F00  // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M       0x000000F0  // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S       12
+#define ADC_SSMUX2_MUX2_S       8
+#define ADC_SSMUX2_MUX1_S       4
+#define ADC_SSMUX2_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3          0x00008000  // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3          0x00004000  // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3         0x00002000  // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3           0x00001000  // 4th Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS2          0x00000800  // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2          0x00000400  // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2         0x00000200  // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2           0x00000100  // 3rd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS1          0x00000080  // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1          0x00000040  // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1         0x00000020  // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1           0x00000010  // 2nd Sample Differential Input
+                                            // Select
+#define ADC_SSCTL2_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0          0x00000004  // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0         0x00000002  // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0           0x00000001  // 1st Sample Differential Input
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT2_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S     4
+#define ADC_SSFSTAT2_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP        0x00001000  // Sample 3 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S2DCOP        0x00000100  // Sample 2 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S1DCOP        0x00000010  // Sample 1 Digital Comparator
+                                            // Operation
+#define ADC_SSOP2_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M     0x0000F000  // Sample 3 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_M     0x00000F00  // Sample 2 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S1DCSEL_M     0x000000F0  // Sample 1 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+#define ADC_SSDC2_S2DCSEL_S     8
+#define ADC_SSDC2_S1DCSEL_S     4
+#define ADC_SSDC2_S0DCSEL_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M       0x0000000F  // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0          0x00000008  // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0          0x00000004  // Sample Interrupt Enable
+#define ADC_SSCTL3_END0         0x00000002  // End of Sequence
+#define ADC_SSCTL3_D0           0x00000001  // Sample Differential Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M      0x00000FFF  // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL       0x00001000  // FIFO Full
+#define ADC_SSFSTAT3_EMPTY      0x00000100  // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M     0x000000F0  // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M     0x0000000F  // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S     4
+#define ADC_SSFSTAT3_TPTR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP        0x00000001  // Sample 0 Digital Comparator
+                                            // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M     0x0000000F  // Sample 0 Digital Comparator
+                                            // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7       0x00800000  // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6       0x00400000  // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5       0x00200000  // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4       0x00100000  // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3       0x00080000  // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2       0x00040000  // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1       0x00020000  // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0       0x00010000  // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7        0x00000080  // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6        0x00000040  // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5        0x00000020  // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4        0x00000010  // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3        0x00000008  // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2        0x00000004  // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1        0x00000002  // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0        0x00000001  // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL0_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL0_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL0_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL0_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL0_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL0_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL0_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL0_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL0_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL1_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL1_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL1_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL1_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL1_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL1_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL1_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL1_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL1_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL2_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL2_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL2_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL2_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL2_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL2_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL2_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL2_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL2_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL3_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL3_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL3_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL3_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL3_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL3_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL3_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL3_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL3_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL4_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL4_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL4_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL4_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL4_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL4_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL4_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL4_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL4_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL5_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL5_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL5_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL5_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL5_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL5_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL5_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL5_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL5_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL6_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL6_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL6_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL6_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL6_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL6_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL6_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL6_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL6_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE          0x00001000  // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M        0x00000C00  // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CTC_MID      0x00000400  // Mid Band
+#define ADC_DCCTL7_CTC_HIGH     0x00000C00  // High Band
+#define ADC_DCCTL7_CTM_M        0x00000300  // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CTM_ONCE     0x00000100  // Once
+#define ADC_DCCTL7_CTM_HALWAYS  0x00000200  // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE    0x00000300  // Hysteresis Once
+#define ADC_DCCTL7_CIE          0x00000010  // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M        0x0000000C  // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW      0x00000000  // Low Band
+#define ADC_DCCTL7_CIC_MID      0x00000004  // Mid Band
+#define ADC_DCCTL7_CIC_HIGH     0x0000000C  // High Band
+#define ADC_DCCTL7_CIM_M        0x00000003  // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS   0x00000000  // Always
+#define ADC_DCCTL7_CIM_ONCE     0x00000001  // Once
+#define ADC_DCCTL7_CIM_HALWAYS  0x00000002  // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE    0x00000003  // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP0_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP0_COMP1_S      16
+#define ADC_DCCMP0_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP1_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP1_COMP1_S      16
+#define ADC_DCCMP1_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP2_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP2_COMP1_S      16
+#define ADC_DCCMP2_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP3_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP3_COMP1_S      16
+#define ADC_DCCMP3_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP4_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP4_COMP1_S      16
+#define ADC_DCCMP4_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP5_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP5_COMP1_S      16
+#define ADC_DCCMP5_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP6_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP6_COMP1_S      16
+#define ADC_DCCMP6_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M      0x0FFF0000  // Compare 1
+#define ADC_DCCMP7_COMP0_M      0x00000FFF  // Compare 0
+#define ADC_DCCMP7_COMP1_S      16
+#define ADC_DCCMP7_COMP0_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_TS               0x00800000  // Temperature Sensor
+#define ADC_PP_RSL_M            0x007C0000  // Resolution
+#define ADC_PP_TYPE_M           0x00030000  // ADC Architecture
+#define ADC_PP_TYPE_SAR         0x00000000  // SAR
+#define ADC_PP_DC_M             0x0000FC00  // Digital Comparator Count
+#define ADC_PP_CH_M             0x000003F0  // ADC Channel Count
+#define ADC_PP_MSR_M            0x0000000F  // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K         0x00000001  // 125 ksps
+#define ADC_PP_MSR_250K         0x00000003  // 250 ksps
+#define ADC_PP_MSR_500K         0x00000005  // 500 ksps
+#define ADC_PP_MSR_1M           0x00000007  // 1 Msps
+#define ADC_PP_RSL_S            18
+#define ADC_PP_DC_S             10
+#define ADC_PP_CH_S             4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M             0x0000000F  // ADC Sample Rate
+#define ADC_PC_SR_125K          0x00000001  // 125 ksps
+#define ADC_PC_SR_250K          0x00000003  // 250 ksps
+#define ADC_PC_SR_500K          0x00000005  // 500 ksps
+#define ADC_PC_SR_1M            0x00000007  // 1 Msps
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CS_M             0x0000000F  // ADC Clock Source
+#define ADC_CC_CS_SYSPLL        0x00000000  // PLL VCO divided by CLKDIV
+#define ADC_CC_CS_PIOSC         0x00000001  // PIOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN1          0x00000002  // Comparator 1 Masked Interrupt
+                                            // Status
+#define COMP_ACMIS_IN0          0x00000001  // Comparator 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN1          0x00000002  // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0          0x00000001  // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN1        0x00000002  // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0        0x00000001  // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN        0x00000200  // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG       0x00000100  // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M    0x0000000F  // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL0_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL0_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL0_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL0_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL       0x00000002  // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN        0x00000800  // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M     0x00000600  // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN   0x00000000  // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0  0x00000200  // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF   0x00000400  // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL      0x00000080  // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M      0x00000060  // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL  0x00000000  // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL   0x00000020  // Falling edge
+#define COMP_ACCTL1_TSEN_RISE   0x00000040  // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH   0x00000060  // Either edge
+#define COMP_ACCTL1_ISLVAL      0x00000010  // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M      0x0000000C  // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL  0x00000000  // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL   0x00000004  // Falling edge
+#define COMP_ACCTL1_ISEN_RISE   0x00000008  // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH   0x0000000C  // Either edge
+#define COMP_ACCTL1_CINV        0x00000002  // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C1O             0x00020000  // Comparator Output 1 Present
+#define COMP_PP_C0O             0x00010000  // Comparator Output 0 Present
+#define COMP_PP_CMP1            0x00000002  // Comparator 1 Present
+#define COMP_PP_CMP0            0x00000001  // Comparator 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST            0x00000080  // Test Mode Enable
+#define CAN_CTL_CCE             0x00000040  // Configuration Change Enable
+#define CAN_CTL_DAR             0x00000020  // Disable Automatic-Retransmission
+#define CAN_CTL_EIE             0x00000008  // Error Interrupt Enable
+#define CAN_CTL_SIE             0x00000004  // Status Interrupt Enable
+#define CAN_CTL_IE              0x00000002  // CAN Interrupt Enable
+#define CAN_CTL_INIT            0x00000001  // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF            0x00000080  // Bus-Off Status
+#define CAN_STS_EWARN           0x00000040  // Warning Status
+#define CAN_STS_EPASS           0x00000020  // Error Passive
+#define CAN_STS_RXOK            0x00000010  // Received a Message Successfully
+#define CAN_STS_TXOK            0x00000008  // Transmitted a Message
+                                            // Successfully
+#define CAN_STS_LEC_M           0x00000007  // Last Error Code
+#define CAN_STS_LEC_NONE        0x00000000  // No Error
+#define CAN_STS_LEC_STUFF       0x00000001  // Stuff Error
+#define CAN_STS_LEC_FORM        0x00000002  // Format Error
+#define CAN_STS_LEC_ACK         0x00000003  // ACK Error
+#define CAN_STS_LEC_BIT1        0x00000004  // Bit 1 Error
+#define CAN_STS_LEC_BIT0        0x00000005  // Bit 0 Error
+#define CAN_STS_LEC_CRC         0x00000006  // CRC Error
+#define CAN_STS_LEC_NOEVENT     0x00000007  // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP              0x00008000  // Received Error Passive
+#define CAN_ERR_REC_M           0x00007F00  // Receive Error Counter
+#define CAN_ERR_TEC_M           0x000000FF  // Transmit Error Counter
+#define CAN_ERR_REC_S           8
+#define CAN_ERR_TEC_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M         0x00007000  // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M         0x00000F00  // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M           0x000000C0  // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M           0x0000003F  // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S         12
+#define CAN_BIT_TSEG1_S         8
+#define CAN_BIT_SJW_S           6
+#define CAN_BIT_BRP_S           0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M         0x0000FFFF  // Interrupt Identifier
+#define CAN_INT_INTID_NONE      0x00000000  // No interrupt pending
+#define CAN_INT_INTID_STATUS    0x00008000  // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX              0x00000080  // Receive Observation
+#define CAN_TST_TX_M            0x00000060  // Transmit Control
+#define CAN_TST_TX_CANCTL       0x00000000  // CAN Module Control
+#define CAN_TST_TX_SAMPLE       0x00000020  // Sample Point
+#define CAN_TST_TX_DOMINANT     0x00000040  // Driven Low
+#define CAN_TST_TX_RECESSIVE    0x00000060  // Driven High
+#define CAN_TST_LBACK           0x00000010  // Loopback Mode
+#define CAN_TST_SILENT          0x00000008  // Silent Mode
+#define CAN_TST_BASIC           0x00000004  // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M         0x0000000F  // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF1CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF1CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF1CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF1CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF1CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF1CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF1ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF1ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF1ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF1ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF1ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF1MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF1MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF1MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF1MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF1MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF1MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF1MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF1DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY         0x00008000  // Busy Flag
+#define CAN_IF2CRQ_MNUM_M       0x0000003F  // Message Number
+#define CAN_IF2CRQ_MNUM_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD       0x00000080  // Write, Not Read
+#define CAN_IF2CMSK_MASK        0x00000040  // Access Mask Bits
+#define CAN_IF2CMSK_ARB         0x00000020  // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL     0x00000010  // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND   0x00000008  // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT      0x00000004  // Access New Data
+#define CAN_IF2CMSK_TXRQST      0x00000004  // Access Transmission Request
+#define CAN_IF2CMSK_DATAA       0x00000002  // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB       0x00000001  // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M     0x0000FFFF  // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD        0x00008000  // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR        0x00004000  // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M     0x00001FFF  // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M        0x0000FFFF  // Message Identifier
+#define CAN_IF2ARB1_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL      0x00008000  // Message Valid
+#define CAN_IF2ARB2_XTD         0x00004000  // Extended Identifier
+#define CAN_IF2ARB2_DIR         0x00002000  // Message Direction
+#define CAN_IF2ARB2_ID_M        0x00001FFF  // Message Identifier
+#define CAN_IF2ARB2_ID_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT      0x00008000  // New Data
+#define CAN_IF2MCTL_MSGLST      0x00004000  // Message Lost
+#define CAN_IF2MCTL_INTPND      0x00002000  // Interrupt Pending
+#define CAN_IF2MCTL_UMASK       0x00001000  // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE        0x00000800  // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE        0x00000400  // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN       0x00000200  // Remote Enable
+#define CAN_IF2MCTL_TXRQST      0x00000100  // Transmit Request
+#define CAN_IF2MCTL_EOB         0x00000080  // End of Buffer
+#define CAN_IF2MCTL_DLC_M       0x0000000F  // Data Length Code
+#define CAN_IF2MCTL_DLC_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DA2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB1_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M       0x0000FFFF  // Data
+#define CAN_IF2DB2_DATA_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M      0x0000FFFF  // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA1_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M      0x0000FFFF  // New Data Bits
+#define CAN_NWDA2_NEWDAT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M    0x0000FFFF  // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M    0x0000FFFF  // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M             0x0000007F  // Function Address
+#define USB_FADDR_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP         0x00000080  // Isochronous Update
+#define USB_POWER_SOFTCONN      0x00000040  // Soft Connect/Disconnect
+#define USB_POWER_RESET         0x00000008  // RESET Signaling
+#define USB_POWER_RESUME        0x00000004  // RESUME Signaling
+#define USB_POWER_SUSPEND       0x00000002  // SUSPEND Mode
+#define USB_POWER_PWRDNPHY      0x00000001  // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7            0x00000080  // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6            0x00000040  // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5            0x00000020  // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4            0x00000010  // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3            0x00000008  // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2            0x00000004  // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1            0x00000002  // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7            0x00000080  // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6            0x00000040  // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5            0x00000020  // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4            0x00000010  // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3            0x00000008  // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2            0x00000004  // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1            0x00000002  // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7            0x00000080  // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6            0x00000040  // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5            0x00000020  // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4            0x00000010  // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3            0x00000008  // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2            0x00000004  // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1            0x00000002  // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0            0x00000001  // TX and RX Endpoint 0 Interrupt
+                                            // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7            0x00000080  // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6            0x00000040  // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5            0x00000020  // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4            0x00000010  // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3            0x00000008  // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2            0x00000004  // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1            0x00000002  // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR          0x00000080  // VBUS Error (OTG only)
+#define USB_IS_SESREQ           0x00000040  // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON           0x00000020  // Session Disconnect (OTG only)
+#define USB_IS_CONN             0x00000010  // Session Connect
+#define USB_IS_SOF              0x00000008  // Start of Frame
+#define USB_IS_BABBLE           0x00000004  // Babble Detected
+#define USB_IS_RESET            0x00000004  // RESET Signaling Detected
+#define USB_IS_RESUME           0x00000002  // RESUME Signaling Detected
+#define USB_IS_SUSPEND          0x00000001  // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR          0x00000080  // Enable VBUS Error Interrupt (OTG
+                                            // only)
+#define USB_IE_SESREQ           0x00000040  // Enable Session Request (OTG
+                                            // only)
+#define USB_IE_DISCON           0x00000020  // Enable Disconnect Interrupt
+#define USB_IE_CONN             0x00000010  // Enable Connect Interrupt
+#define USB_IE_SOF              0x00000008  // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE           0x00000004  // Enable Babble Interrupt
+#define USB_IE_RESET            0x00000004  // Enable RESET Interrupt
+#define USB_IE_RESUME           0x00000002  // Enable RESUME Interrupt
+#define USB_IE_SUSPND           0x00000001  // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M             0x000007FF  // Frame Number
+#define USB_FRAME_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M       0x0000000F  // Endpoint Index
+#define USB_EPIDX_EPIDX_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH         0x00000080  // Force Host Mode
+#define USB_TEST_FIFOACC        0x00000040  // FIFO Access
+#define USB_TEST_FORCEFS        0x00000020  // Force Full-Speed Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO0_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO1_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO2_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO3_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO4_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO5_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO6_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M      0xFFFFFFFF  // Endpoint Data
+#define USB_FIFO7_EPDATA_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV          0x00000080  // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV        0x00000040  // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV        0x00000020  // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M       0x00000018  // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE    0x00000000  // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND    0x00000008  // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID  0x00000010  // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID   0x00000018  // Above VBUSValid
+#define USB_DEVCTL_HOST         0x00000004  // Host Mode
+#define USB_DEVCTL_HOSTREQ      0x00000002  // Host Request (OTG only)
+#define USB_DEVCTL_SESSION      0x00000001  // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_TXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_TXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_TXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_TXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_TXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_TXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_TXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_TXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB        0x00000010  // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M     0x0000000F  // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8     0x00000000  // 8
+#define USB_RXFIFOSZ_SIZE_16    0x00000001  // 16
+#define USB_RXFIFOSZ_SIZE_32    0x00000002  // 32
+#define USB_RXFIFOSZ_SIZE_64    0x00000003  // 64
+#define USB_RXFIFOSZ_SIZE_128   0x00000004  // 128
+#define USB_RXFIFOSZ_SIZE_256   0x00000005  // 256
+#define USB_RXFIFOSZ_SIZE_512   0x00000006  // 512
+#define USB_RXFIFOSZ_SIZE_1024  0x00000007  // 1024
+#define USB_RXFIFOSZ_SIZE_2048  0x00000008  // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M    0x000001FF  // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M      0x000000F0  // Connect Wait
+#define USB_CONTIM_WTID_M       0x0000000F  // Wait ID
+#define USB_CONTIM_WTCON_S      4
+#define USB_CONTIM_WTID_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M       0x000000FF  // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M      0x000000FF  // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M      0x000000FF  // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR0_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR0_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT0_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR1_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR1_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT1_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR2_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR2_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT2_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR3_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR3_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT3_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR4_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR4_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT4_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR5_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR5_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT5_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR6_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR6_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT6_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_TXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_TXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_TXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M  0x0000007F  // Device Address
+#define USB_RXFUNCADDR7_ADDR_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M   0x0000007F  // Hub Address
+#define USB_RXHUBADDR7_ADDR_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M   0x0000007F  // Hub Port
+#define USB_RXHUBPORT7_PORT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO         0x00000080  // NAK Timeout
+#define USB_CSRL0_SETENDC       0x00000080  // Setup End Clear
+#define USB_CSRL0_STATUS        0x00000040  // STATUS Packet
+#define USB_CSRL0_RXRDYC        0x00000040  // RXRDY Clear
+#define USB_CSRL0_REQPKT        0x00000020  // Request Packet
+#define USB_CSRL0_STALL         0x00000020  // Send Stall
+#define USB_CSRL0_SETEND        0x00000010  // Setup End
+#define USB_CSRL0_ERROR         0x00000010  // Error
+#define USB_CSRL0_DATAEND       0x00000008  // Data End
+#define USB_CSRL0_SETUP         0x00000008  // Setup Packet
+#define USB_CSRL0_STALLED       0x00000004  // Endpoint Stalled
+#define USB_CSRL0_TXRDY         0x00000002  // Transmit Packet Ready
+#define USB_CSRL0_RXRDY         0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DTWE          0x00000004  // Data Toggle Write Enable
+#define USB_CSRH0_DT            0x00000002  // Data Toggle
+#define USB_CSRH0_FLUSH         0x00000001  // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M      0x0000007F  // FIFO Count
+#define USB_COUNT0_COUNT_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M       0x000000C0  // Operating Speed
+#define USB_TYPE0_SPEED_FULL    0x00000080  // Full
+#define USB_TYPE0_SPEED_LOW     0x000000C0  // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M     0x0000001F  // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL1_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL1_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL1_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL1_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL1_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL1_ERROR       0x00000004  // Error
+#define USB_TXCSRL1_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL1_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH1_MODE        0x00000020  // Mode
+#define USB_TXCSRH1_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH1_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH1_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH1_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL1_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL1_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL1_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL1_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL1_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL1_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL1_OVER        0x00000004  // Overrun
+#define USB_RXCSRL1_ERROR       0x00000004  // Error
+#define USB_RXCSRL1_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL1_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH1_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH1_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH1_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH1_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH1_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH1_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH1_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE1_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE1_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE1_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE1_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE1_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE1_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE1_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE1_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL1_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL2_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL2_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL2_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL2_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL2_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL2_ERROR       0x00000004  // Error
+#define USB_TXCSRL2_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL2_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH2_MODE        0x00000020  // Mode
+#define USB_TXCSRH2_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH2_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH2_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH2_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL2_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL2_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL2_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL2_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL2_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL2_ERROR       0x00000004  // Error
+#define USB_RXCSRL2_OVER        0x00000004  // Overrun
+#define USB_RXCSRL2_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL2_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH2_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH2_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH2_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH2_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH2_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH2_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH2_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL2_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE2_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE2_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE2_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE2_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE2_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE2_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE2_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE2_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL2_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL3_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL3_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL3_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL3_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL3_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL3_ERROR       0x00000004  // Error
+#define USB_TXCSRL3_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL3_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH3_MODE        0x00000020  // Mode
+#define USB_TXCSRH3_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH3_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH3_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH3_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL3_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL3_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL3_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL3_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL3_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL3_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL3_ERROR       0x00000004  // Error
+#define USB_RXCSRL3_OVER        0x00000004  // Overrun
+#define USB_RXCSRL3_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL3_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH3_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH3_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH3_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH3_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH3_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH3_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH3_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE3_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE3_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE3_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE3_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE3_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE3_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE3_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE3_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL3_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL4_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL4_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL4_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL4_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL4_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL4_ERROR       0x00000004  // Error
+#define USB_TXCSRL4_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL4_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH4_MODE        0x00000020  // Mode
+#define USB_TXCSRH4_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH4_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH4_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH4_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL4_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL4_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL4_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL4_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL4_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL4_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL4_OVER        0x00000004  // Overrun
+#define USB_RXCSRL4_ERROR       0x00000004  // Error
+#define USB_RXCSRL4_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL4_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH4_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH4_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH4_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH4_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH4_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH4_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH4_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE4_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE4_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE4_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE4_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE4_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE4_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE4_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE4_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL4_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL5_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL5_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL5_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL5_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL5_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL5_ERROR       0x00000004  // Error
+#define USB_TXCSRL5_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL5_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH5_MODE        0x00000020  // Mode
+#define USB_TXCSRH5_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH5_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH5_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH5_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL5_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL5_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL5_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL5_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL5_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL5_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL5_ERROR       0x00000004  // Error
+#define USB_RXCSRL5_OVER        0x00000004  // Overrun
+#define USB_RXCSRL5_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL5_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH5_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH5_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH5_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH5_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH5_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH5_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH5_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL5_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE5_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE5_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE5_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE5_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE5_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE5_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE5_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE5_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S                                              \
+                                0
+#define USB_RXINTERVAL5_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL6_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL6_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL6_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL6_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL6_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL6_ERROR       0x00000004  // Error
+#define USB_TXCSRL6_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL6_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH6_MODE        0x00000020  // Mode
+#define USB_TXCSRH6_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH6_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH6_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH6_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL6_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL6_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL6_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL6_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL6_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL6_ERROR       0x00000004  // Error
+#define USB_RXCSRL6_OVER        0x00000004  // Overrun
+#define USB_RXCSRL6_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL6_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH6_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH6_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH6_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH6_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH6_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH6_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH6_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S                                              \
+                                0
+#define USB_TXINTERVAL6_NAKLMT_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE6_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE6_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE6_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE6_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE6_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE6_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE6_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE6_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL6_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO       0x00000080  // NAK Timeout
+#define USB_TXCSRL7_CLRDT       0x00000040  // Clear Data Toggle
+#define USB_TXCSRL7_STALLED     0x00000020  // Endpoint Stalled
+#define USB_TXCSRL7_STALL       0x00000010  // Send STALL
+#define USB_TXCSRL7_SETUP       0x00000010  // Setup Packet
+#define USB_TXCSRL7_FLUSH       0x00000008  // Flush FIFO
+#define USB_TXCSRL7_ERROR       0x00000004  // Error
+#define USB_TXCSRL7_UNDRN       0x00000004  // Underrun
+#define USB_TXCSRL7_FIFONE      0x00000002  // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY       0x00000001  // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET     0x00000080  // Auto Set
+#define USB_TXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_TXCSRH7_MODE        0x00000020  // Mode
+#define USB_TXCSRH7_DMAEN       0x00000010  // DMA Request Enable
+#define USB_TXCSRH7_FDT         0x00000008  // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD      0x00000004  // DMA Request Mode
+#define USB_TXCSRH7_DTWE        0x00000002  // Data Toggle Write Enable
+#define USB_TXCSRH7_DT          0x00000001  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M   0x000007FF  // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT       0x00000080  // Clear Data Toggle
+#define USB_RXCSRL7_STALLED     0x00000040  // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT      0x00000020  // Request Packet
+#define USB_RXCSRL7_STALL       0x00000020  // Send STALL
+#define USB_RXCSRL7_FLUSH       0x00000010  // Flush FIFO
+#define USB_RXCSRL7_DATAERR     0x00000008  // Data Error
+#define USB_RXCSRL7_NAKTO       0x00000008  // NAK Timeout
+#define USB_RXCSRL7_ERROR       0x00000004  // Error
+#define USB_RXCSRL7_OVER        0x00000004  // Overrun
+#define USB_RXCSRL7_FULL        0x00000002  // FIFO Full
+#define USB_RXCSRL7_RXRDY       0x00000001  // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL      0x00000080  // Auto Clear
+#define USB_RXCSRH7_ISO         0x00000040  // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ      0x00000040  // Auto Request
+#define USB_RXCSRH7_DMAEN       0x00000020  // DMA Request Enable
+#define USB_RXCSRH7_PIDERR      0x00000010  // PID Error
+#define USB_RXCSRH7_DISNYET     0x00000010  // Disable NYET
+#define USB_RXCSRH7_DMAMOD      0x00000008  // DMA Request Mode
+#define USB_RXCSRH7_DTWE        0x00000004  // Data Toggle Write Enable
+#define USB_RXCSRH7_DT          0x00000002  // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M    0x00001FFF  // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_TXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_TXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_TXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_TXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_TXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_TXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_TXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_TXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_TXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M     0x000000C0  // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT  0x00000000  // Default
+#define USB_RXTYPE7_SPEED_FULL  0x00000080  // Full
+#define USB_RXTYPE7_SPEED_LOW   0x000000C0  // Low
+#define USB_RXTYPE7_PROTO_M     0x00000030  // Protocol
+#define USB_RXTYPE7_PROTO_CTRL  0x00000000  // Control
+#define USB_RXTYPE7_PROTO_ISOC  0x00000010  // Isochronous
+#define USB_RXTYPE7_PROTO_BULK  0x00000020  // Bulk
+#define USB_RXTYPE7_PROTO_INT   0x00000030  // Interrupt
+#define USB_RXTYPE7_TEP_M       0x0000000F  // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M                                              \
+                                0x000000FF  // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M                                              \
+                                0x000000FF  // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S                                              \
+                                0
+#define USB_RXINTERVAL7_TXPOLL_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M       0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF  // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7    0x00000080  // EP7 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP6    0x00000040  // EP6 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP5    0x00000020  // EP5 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP4    0x00000010  // EP4 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP3    0x00000008  // EP3 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP2    0x00000004  // EP2 RX Double-Packet Buffer
+                                            // Disable
+#define USB_RXDPKTBUFDIS_EP1    0x00000002  // EP1 RX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7    0x00000080  // EP7 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP6    0x00000040  // EP6 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP5    0x00000020  // EP5 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP4    0x00000010  // EP4 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP3    0x00000008  // EP3 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP2    0x00000004  // EP2 TX Double-Packet Buffer
+                                            // Disable
+#define USB_TXDPKTBUFDIS_EP1    0x00000002  // EP1 TX Double-Packet Buffer
+                                            // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M       0x00000300  // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG   0x00000000  // Unchanged
+#define USB_EPC_PFLTACT_TRIS    0x00000100  // Tristate
+#define USB_EPC_PFLTACT_LOW     0x00000200  // Low
+#define USB_EPC_PFLTACT_HIGH    0x00000300  // High
+#define USB_EPC_PFLTAEN         0x00000040  // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH    0x00000020  // Power Fault Sense
+#define USB_EPC_PFLTEN          0x00000010  // Power Fault Input Enable
+#define USB_EPC_EPENDE          0x00000004  // EPEN Drive Enable
+#define USB_EPC_EPEN_M          0x00000003  // External Power Supply Enable
+                                            // Configuration
+#define USB_EPC_EPEN_LOW        0x00000000  // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH       0x00000001  // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW      0x00000002  // Power Enable High if VBUS Low
+                                            // (OTG only)
+#define USB_EPC_EPEN_VBHIGH     0x00000003  // Power Enable High if VBUS High
+                                            // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF           0x00000001  // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF            0x00000001  // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF           0x00000001  // USB Power Fault Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME        0x00000001  // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME         0x00000001  // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME        0x00000001  // RESUME Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMODOTG      0x00000002  // Enable Device Mode
+#define USB_GPCS_DEVMOD         0x00000001  // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN           0x00000001  // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD           0x00000001  // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD            0x00000001  // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD           0x00000001  // VBUS Droop Interrupt Status and
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID           0x00000001  // ID Valid Detect Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID            0x00000001  // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID           0x00000001  // ID Valid Detect Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M     0x00F00000  // DMA C TX Select
+#define USB_DMASEL_DMACRX_M     0x000F0000  // DMA C RX Select
+#define USB_DMASEL_DMABTX_M     0x0000F000  // DMA B TX Select
+#define USB_DMASEL_DMABRX_M     0x00000F00  // DMA B RX Select
+#define USB_DMASEL_DMAATX_M     0x000000F0  // DMA A TX Select
+#define USB_DMASEL_DMAARX_M     0x0000000F  // DMA A RX Select
+#define USB_DMASEL_DMACTX_S     20
+#define USB_DMASEL_DMACRX_S     16
+#define USB_DMASEL_DMABTX_S     12
+#define USB_DMASEL_DMABRX_S     8
+#define USB_DMASEL_DMAATX_S     4
+#define USB_DMASEL_DMAARX_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M           0x0000FF00  // Endpoint Count
+#define USB_PP_USB_M            0x000000C0  // USB Capability
+#define USB_PP_USB_DEVICE       0x00000040  // DEVICE
+#define USB_PP_USB_HOSTDEVICE   0x00000080  // HOST
+#define USB_PP_USB_OTG          0x000000C0  // OTG
+#define USB_PP_PHY              0x00000010  // PHY Present
+#define USB_PP_TYPE_M           0x0000000F  // Controller Type
+#define USB_PP_TYPE_0           0x00000000  // The first-generation USB
+                                            // controller
+#define USB_PP_ECNT_S           8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_BLKCNT_M  0x07FF0000  // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF  // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_S  16
+#define EEPROM_EESIZE_WORDCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M  0x0000FFFF  // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M                                              \
+                                0x0000000F  // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M   0xFFFFFFFF  // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M                                              \
+                                0xFFFFFFFF  // EEPROM Read or Write Data with
+                                            // Increment
+#define EEPROM_EERDWRINC_VALUE_S                                              \
+                                0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WRBUSY    0x00000020  // Write Busy
+#define EEPROM_EEDONE_NOPERM    0x00000010  // Write Without Permission
+#define EEPROM_EEDONE_WKCOPY    0x00000008  // Working on a Copy
+#define EEPROM_EEDONE_WKERASE   0x00000004  // Working on an Erase
+#define EEPROM_EEDONE_WORKING   0x00000001  // EEPROM Working
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_PRETRY    0x00000008  // Programming Must Be Retried
+#define EEPROM_EESUPP_ERETRY    0x00000004  // Erase Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M                                              \
+                                0xFFFFFFFF  // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_ACC       0x00000008  // Access Control
+#define EEPROM_EEPROT_PROT_M    0x00000007  // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW                                              \
+                                0x00000000  // This setting is the default. If
+                                            // there is no password, the block
+                                            // is not protected and is readable
+                                            // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001  // If there is a password, the
+                                            // block is readable or writable
+                                            // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW                                              \
+                                0x00000002  // If there is no password, the
+                                            // block is readable, not writable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS0_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS1_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M   0xFFFFFFFF  // Password
+#define EEPROM_EEPASS2_PASS_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT        0x00000001  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M      0xFFFFFFFE  // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_KEY_M    0xFFFF0000  // Erase Key
+#define EEPROM_EEDBGME_ME       0x00000001  // Mass Erase
+#define EEPROM_EEDBGME_KEY_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M        0x0000001F  // EEPROM Size
+#define EEPROM_PP_SIZE_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS     0x00000020  // Floating-Point Inexact Exception
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS     0x00000010  // Floating-Point Overflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPUFCMIS     0x00000008  // Floating-Point Underflow
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIOCMIS     0x00000004  // Floating-Point Invalid Operation
+                                            // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS     0x00000002  // Floating-Point Divide By 0
+                                            // Exception Masked Interrupt
+                                            // Status
+#define SYSEXC_MIS_FPIDCMIS     0x00000001  // Floating-Point Input Denormal
+                                            // Exception Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC       0x00000020  // Floating-Point Inexact Exception
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC       0x00000010  // Floating-Point Overflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC       0x00000008  // Floating-Point Underflow
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC       0x00000004  // Floating-Point Invalid Operation
+                                            // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC       0x00000002  // Floating-Point Divide By 0
+                                            // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC       0x00000001  // Floating-Point Input Denormal
+                                            // Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M              0xFFFFFFFF  // RTC Counter
+#define HIB_RTCC_S              0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M             0xFFFFFFFF  // RTC Match 0
+#define HIB_RTCM0_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M             0xFFFFFFFF  // RTC Load
+#define HIB_RTCLD_S             0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC             0x80000000  // Write Complete/Capable
+#define HIB_CTL_OSCDRV          0x00020000  // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP          0x00010000  // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M       0x00006000  // Select for Low-Battery
+                                            // Comparator
+#define HIB_CTL_VBATSEL_1_9V    0x00000000  // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V    0x00002000  // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V    0x00004000  // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V    0x00006000  // 2.5 Volts
+#define HIB_CTL_BATCHK          0x00000400  // Check Battery Status
+#define HIB_CTL_BATWKEN         0x00000200  // Wake on Low Battery
+#define HIB_CTL_VDD3ON          0x00000100  // VDD Powered
+#define HIB_CTL_VABORT          0x00000080  // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN         0x00000040  // Clocking Enable
+#define HIB_CTL_PINWEN          0x00000010  // External Wake Pin Enable
+#define HIB_CTL_RTCWEN          0x00000008  // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ          0x00000002  // Hibernation Request
+#define HIB_CTL_RTCEN           0x00000001  // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_WC               0x00000010  // External Write Complete/Capable
+                                            // Interrupt Mask
+#define HIB_IM_EXTW             0x00000008  // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Mask
+#define HIB_IM_RTCALT0          0x00000001  // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_WC              0x00000010  // Write Complete/Capable Raw
+                                            // Interrupt Status
+#define HIB_RIS_EXTW            0x00000008  // External Wake-Up Raw Interrupt
+                                            // Status
+#define HIB_RIS_LOWBAT          0x00000004  // Low Battery Voltage Raw
+                                            // Interrupt Status
+#define HIB_RIS_RTCALT0         0x00000001  // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_WC              0x00000010  // Write Complete/Capable Masked
+                                            // Interrupt Status
+#define HIB_MIS_EXTW            0x00000008  // External Wake-Up Masked
+                                            // Interrupt Status
+#define HIB_MIS_LOWBAT          0x00000004  // Low Battery Voltage Masked
+                                            // Interrupt Status
+#define HIB_MIS_RTCALT0         0x00000001  // RTC Alert 0 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_WC               0x00000010  // Write Complete/Capable Interrupt
+                                            // Clear
+#define HIB_IC_EXTW             0x00000008  // External Wake-Up Interrupt Clear
+#define HIB_IC_LOWBAT           0x00000004  // Low Battery Voltage Interrupt
+                                            // Clear
+#define HIB_IC_RTCALT0          0x00000001  // RTC Alert0 Masked Interrupt
+                                            // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M         0x0000FFFF  // RTC Trim Value
+#define HIB_RTCT_TRIM_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M      0x7FFF0000  // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M      0x00007FFF  // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S      16
+#define HIB_RTCSS_RTCSSC_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M          0xFFFFFFFF  // Hibernation Module NV Data
+#define HIB_DATA_RTD_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M      0x0003FFFF  // Address Offset
+#define FLASH_FMA_OFFSET_S      0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M        0xFFFFFFFF  // Data Value
+#define FLASH_FMD_DATA_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY         0xA4420000  // FLASH write key
+#define FLASH_FMC_COMT          0x00000008  // Commit Register Value
+#define FLASH_FMC_MERASE        0x00000004  // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE         0x00000002  // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE         0x00000001  // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS     0x00002000  // Program Verify Error Raw
+                                            // Interrupt Status
+#define FLASH_FCRIS_ERRIS       0x00000800  // Erase Verify Error Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_INVDRIS     0x00000400  // Invalid Data Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_VOLTRIS     0x00000200  // Pump Voltage Raw Interrupt
+                                            // Status
+#define FLASH_FCRIS_ERIS        0x00000004  // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS        0x00000002  // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS        0x00000001  // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK     0x00002000  // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK       0x00000800  // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK     0x00000400  // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK     0x00000200  // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK        0x00000004  // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK        0x00000002  // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK        0x00000001  // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC   0x00002000  // PROGVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_ERMISC     0x00000800  // ERVER Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_INVDMISC   0x00000400  // Invalid Data Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_VOLTMISC   0x00000200  // VOLT Masked Interrupt Status and
+                                            // Clear
+#define FLASH_FCMISC_EMISC      0x00000004  // EEPROM Masked Interrupt Status
+                                            // and Clear
+#define FLASH_FCMISC_PMISC      0x00000002  // Programming Masked Interrupt
+                                            // Status and Clear
+#define FLASH_FCMISC_AMISC      0x00000001  // Access Masked Interrupt Status
+                                            // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRBUF        0x00000001  // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M      0xFFFFFFFF  // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M       0xFFFFFFFF  // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M      0x0000FFFF  // Flash Size
+#define FLASH_FSIZE_SIZE_256KB  0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M      0x0000FFFF  // SRAM Size
+#define FLASH_SSIZE_SIZE_32KB   0x0000007F  // 32 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001  // SafeRTOS Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA          0x00000001  // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW        0x80000000  // Not Written
+#define FLASH_BOOTCFG_PORT_M    0x0000E000  // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A    0x00000000  // Port A
+#define FLASH_BOOTCFG_PORT_B    0x00002000  // Port B
+#define FLASH_BOOTCFG_PORT_C    0x00004000  // Port C
+#define FLASH_BOOTCFG_PORT_D    0x00006000  // Port D
+#define FLASH_BOOTCFG_PORT_E    0x00008000  // Port E
+#define FLASH_BOOTCFG_PORT_F    0x0000A000  // Port F
+#define FLASH_BOOTCFG_PORT_G    0x0000C000  // Port G
+#define FLASH_BOOTCFG_PORT_H    0x0000E000  // Port H
+#define FLASH_BOOTCFG_PIN_M     0x00001C00  // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0     0x00000000  // Pin 0
+#define FLASH_BOOTCFG_PIN_1     0x00000400  // Pin 1
+#define FLASH_BOOTCFG_PIN_2     0x00000800  // Pin 2
+#define FLASH_BOOTCFG_PIN_3     0x00000C00  // Pin 3
+#define FLASH_BOOTCFG_PIN_4     0x00001000  // Pin 4
+#define FLASH_BOOTCFG_PIN_5     0x00001400  // Pin 5
+#define FLASH_BOOTCFG_PIN_6     0x00001800  // Pin 6
+#define FLASH_BOOTCFG_PIN_7     0x00001C00  // Pin 7
+#define FLASH_BOOTCFG_POL       0x00000200  // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN        0x00000100  // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY       0x00000010  // KEY Select
+#define FLASH_BOOTCFG_DBG1      0x00000002  // Debug Control 1
+#define FLASH_BOOTCFG_DBG0      0x00000001  // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG0_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG1_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG2_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M   0xFFFFFFFF  // User Data
+#define FLASH_USERREG3_DATA_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M       0x70000000  // DID0 Version
+#define SYSCTL_DID0_VER_1       0x10000000  // Second version of the DID0
+                                            // register format.
+#define SYSCTL_DID0_CLASS_M     0x00FF0000  // Device Class
+#define SYSCTL_DID0_CLASS_TM4C123                                             \
+                                0x00050000  // Tiva TM4C123x and TM4E123x
+                                            // microcontrollers
+#define SYSCTL_DID0_MAJ_M       0x0000FF00  // Major Revision
+#define SYSCTL_DID0_MAJ_REVA    0x00000000  // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB    0x00000100  // Revision B (first base layer
+                                            // revision)
+#define SYSCTL_DID0_MAJ_REVC    0x00000200  // Revision C (second base layer
+                                            // revision)
+#define SYSCTL_DID0_MIN_M       0x000000FF  // Minor Revision
+#define SYSCTL_DID0_MIN_0       0x00000000  // Initial device, or a major
+                                            // revision update
+#define SYSCTL_DID0_MIN_1       0x00000001  // First metal layer change
+#define SYSCTL_DID0_MIN_2       0x00000002  // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M       0xF0000000  // DID1 Version
+#define SYSCTL_DID1_VER_1       0x10000000  // fury_ib
+#define SYSCTL_DID1_FAM_M       0x0F000000  // Family
+#define SYSCTL_DID1_FAM_TIVA    0x00000000  // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M     0x00FF0000  // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PM                                        \
+                                0x00A10000  // TM4C123GH6PM
+#define SYSCTL_DID1_PINCNT_M    0x0000E000  // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100  0x00004000  // 100-pin LQFP package
+#define SYSCTL_DID1_PINCNT_64   0x00006000  // 64-pin LQFP package
+#define SYSCTL_DID1_PINCNT_144  0x00008000  // 144-pin LQFP package
+#define SYSCTL_DID1_PINCNT_157  0x0000A000  // 157-pin BGA package
+#define SYSCTL_DID1_PINCNT_128  0x0000C000  // 128-pin TQFP package
+#define SYSCTL_DID1_TEMP_M      0x000000E0  // Temperature Range
+#define SYSCTL_DID1_TEMP_I      0x00000020  // Industrial temperature range
+#define SYSCTL_DID1_TEMP_E      0x00000040  // Extended temperature range
+#define SYSCTL_DID1_TEMP_IE     0x00000060  // Available in both industrial
+                                            // temperature range (-40C to 85C)
+                                            // and extended temperature range
+                                            // (-40C to 105C) devices. See
+#define SYSCTL_DID1_PKG_M       0x00000018  // Package Type
+#define SYSCTL_DID1_PKG_QFP     0x00000008  // QFP package
+#define SYSCTL_DID1_PKG_BGA     0x00000010  // BGA package
+#define SYSCTL_DID1_ROHS        0x00000004  // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M      0x00000003  // Qualification Status
+#define SYSCTL_DID1_QUAL_ES     0x00000000  // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP     0x00000001  // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ     0x00000002  // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M     0xFFFF0000  // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB   0x00070000  // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB   0x000F0000  // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB   0x00170000  // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB   0x001F0000  // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB  0x002F0000  // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB  0x003F0000  // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB  0x004F0000  // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB  0x005F0000  // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB  0x007F0000  // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M    0x0000FFFF  // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB  0x00000003  // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007  // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F  // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F  // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F  // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F  // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F  // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F  // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1         0x10000000  // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1         0x02000000  // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0         0x01000000  // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1         0x00200000  // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0         0x00100000  // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1         0x00020000  // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0         0x00010000  // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M  0x0000F000  // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_80 0x00002000  // Specifies an 80-MHz CPU clock
+                                            // with a PLL divider of 2.5
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000  // Specifies a 50-MHz CPU clock
+                                            // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000  // Specifies a 40-MHz CPU clock
+                                            // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000  // Specifies a 25-MHz clock with a
+                                            // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000  // Specifies a 20-MHz clock with a
+                                            // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M    0x00000C00  // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400  // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800  // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M   0x00000C00  // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M    0x00000300  // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000  // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100  // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200  // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M   0x00000300  // 1M samples/second
+#define SYSCTL_DC1_MPU          0x00000080  // MPU Present
+#define SYSCTL_DC1_HIB          0x00000040  // Hibernation Module Present
+#define SYSCTL_DC1_TEMP         0x00000020  // Temp Sensor Present
+#define SYSCTL_DC1_PLL          0x00000010  // PLL Present
+#define SYSCTL_DC1_WDT0         0x00000008  // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO          0x00000004  // SWO Trace Port Present
+#define SYSCTL_DC1_SWD          0x00000002  // SWD Present
+#define SYSCTL_DC1_JTAG         0x00000001  // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0         0x40000000  // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0         0x10000000  // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2        0x04000000  // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1        0x02000000  // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0        0x01000000  // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3       0x00080000  // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2       0x00040000  // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1       0x00020000  // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0       0x00010000  // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS       0x00008000  // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1         0x00004000  // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS       0x00002000  // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0         0x00001000  // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1         0x00000200  // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0         0x00000100  // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1         0x00000020  // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0         0x00000010  // SSI Module 0 Present
+#define SYSCTL_DC2_UART2        0x00000004  // UART Module 2 Present
+#define SYSCTL_DC2_UART1        0x00000002  // UART Module 1 Present
+#define SYSCTL_DC2_UART0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ        0x80000000  // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5         0x20000000  // T2CCP1 Pin Present
+#define SYSCTL_DC3_CCP4         0x10000000  // T2CCP0 Pin Present
+#define SYSCTL_DC3_CCP3         0x08000000  // T1CCP1 Pin Present
+#define SYSCTL_DC3_CCP2         0x04000000  // T1CCP0 Pin Present
+#define SYSCTL_DC3_CCP1         0x02000000  // T0CCP1 Pin Present
+#define SYSCTL_DC3_CCP0         0x01000000  // T0CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7     0x00800000  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6     0x00400000  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5     0x00200000  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4     0x00100000  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3     0x00080000  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2     0x00040000  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1     0x00020000  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0     0x00010000  // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT     0x00008000  // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O          0x00004000  // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS       0x00002000  // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS      0x00001000  // C2- Pin Present
+#define SYSCTL_DC3_C1O          0x00000800  // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS       0x00000400  // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS      0x00000200  // C1- Pin Present
+#define SYSCTL_DC3_C0O          0x00000100  // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS       0x00000080  // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS      0x00000040  // C0- Pin Present
+#define SYSCTL_DC3_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0        0x40000000  // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0        0x10000000  // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588        0x01000000  // 1588 Capable
+#define SYSCTL_DC4_PICAL        0x00040000  // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7         0x00008000  // T3CCP1 Pin Present
+#define SYSCTL_DC4_CCP6         0x00004000  // T3CCP0 Pin Present
+#define SYSCTL_DC4_UDMA         0x00002000  // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM          0x00001000  // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ        0x00000100  // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH        0x00000080  // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG        0x00000040  // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF        0x00000020  // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE        0x00000010  // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD        0x00000008  // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC        0x00000004  // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB        0x00000002  // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3    0x08000000  // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2    0x04000000  // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1    0x02000000  // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0    0x01000000  // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT      0x00200000  // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC     0x00100000  // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7         0x00000080  // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6         0x00000040  // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5         0x00000020  // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4         0x00000010  // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3         0x00000008  // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2         0x00000004  // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1         0x00000002  // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0         0x00000001  // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY      0x00000010  // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M       0x00000003  // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV     0x00000001  // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002  // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG     0x00000003  // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30      0x40000000  // DMA Channel 30
+#define SYSCTL_DC7_DMACH29      0x20000000  // DMA Channel 29
+#define SYSCTL_DC7_DMACH28      0x10000000  // DMA Channel 28
+#define SYSCTL_DC7_DMACH27      0x08000000  // DMA Channel 27
+#define SYSCTL_DC7_DMACH26      0x04000000  // DMA Channel 26
+#define SYSCTL_DC7_DMACH25      0x02000000  // DMA Channel 25
+#define SYSCTL_DC7_DMACH24      0x01000000  // DMA Channel 24
+#define SYSCTL_DC7_DMACH23      0x00800000  // DMA Channel 23
+#define SYSCTL_DC7_DMACH22      0x00400000  // DMA Channel 22
+#define SYSCTL_DC7_DMACH21      0x00200000  // DMA Channel 21
+#define SYSCTL_DC7_DMACH20      0x00100000  // DMA Channel 20
+#define SYSCTL_DC7_DMACH19      0x00080000  // DMA Channel 19
+#define SYSCTL_DC7_DMACH18      0x00040000  // DMA Channel 18
+#define SYSCTL_DC7_DMACH17      0x00020000  // DMA Channel 17
+#define SYSCTL_DC7_DMACH16      0x00010000  // DMA Channel 16
+#define SYSCTL_DC7_DMACH15      0x00008000  // DMA Channel 15
+#define SYSCTL_DC7_DMACH14      0x00004000  // DMA Channel 14
+#define SYSCTL_DC7_DMACH13      0x00002000  // DMA Channel 13
+#define SYSCTL_DC7_DMACH12      0x00001000  // DMA Channel 12
+#define SYSCTL_DC7_DMACH11      0x00000800  // DMA Channel 11
+#define SYSCTL_DC7_DMACH10      0x00000400  // DMA Channel 10
+#define SYSCTL_DC7_DMACH9       0x00000200  // DMA Channel 9
+#define SYSCTL_DC7_DMACH8       0x00000100  // DMA Channel 8
+#define SYSCTL_DC7_DMACH7       0x00000080  // DMA Channel 7
+#define SYSCTL_DC7_DMACH6       0x00000040  // DMA Channel 6
+#define SYSCTL_DC7_DMACH5       0x00000020  // DMA Channel 5
+#define SYSCTL_DC7_DMACH4       0x00000010  // DMA Channel 4
+#define SYSCTL_DC7_DMACH3       0x00000008  // DMA Channel 3
+#define SYSCTL_DC7_DMACH2       0x00000004  // DMA Channel 2
+#define SYSCTL_DC7_DMACH1       0x00000002  // DMA Channel 1
+#define SYSCTL_DC7_DMACH0       0x00000001  // DMA Channel 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15    0x80000000  // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14    0x40000000  // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13    0x20000000  // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12    0x10000000  // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11    0x08000000  // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10    0x04000000  // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9     0x02000000  // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8     0x01000000  // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7     0x00800000  // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6     0x00400000  // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5     0x00200000  // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4     0x00100000  // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3     0x00080000  // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2     0x00040000  // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1     0x00020000  // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0     0x00010000  // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15    0x00008000  // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14    0x00004000  // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13    0x00002000  // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12    0x00001000  // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11    0x00000800  // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10    0x00000400  // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9     0x00000200  // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8     0x00000100  // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7     0x00000080  // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6     0x00000040  // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5     0x00000020  // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4     0x00000010  // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3     0x00000008  // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2     0x00000004  // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1     0x00000002  // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0     0x00000001  // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0     0x00000004  // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1     0x00000002  // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1       0x10000000  // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1       0x02000000  // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0       0x01000000  // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0       0x00100000  // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1       0x00020000  // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0       0x00010000  // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB        0x00000040  // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0       0x00000008  // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP1      0x02000000  // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0      0x01000000  // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3     0x00080000  // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2     0x00040000  // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1     0x00020000  // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0     0x00010000  // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1       0x00004000  // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0       0x00001000  // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1       0x00000200  // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0       0x00000100  // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1       0x00000020  // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0       0x00000010  // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2      0x00000004  // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1      0x00000002  // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0      0x00000001  // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0       0x00010000  // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA       0x00002000  // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOF      0x00000020  // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE      0x00000010  // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD      0x00000008  // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC      0x00000004  // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB      0x00000002  // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA      0x00000001  // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_BOR0RIS      0x00000800  // VDD under BOR0 Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_VDDARIS      0x00000400  // VDDA Power OK Event Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS   0x00000100  // MOSC Power Up Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_USBPLLLRIS   0x00000080  // USB PLL Lock Raw Interrupt
+                                            // Status
+#define SYSCTL_RIS_PLLLRIS      0x00000040  // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS       0x00000008  // Main Oscillator Failure Raw
+                                            // Interrupt Status
+#define SYSCTL_RIS_BOR1RIS      0x00000002  // VDD under BOR1 Raw Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_BOR0IM       0x00000800  // VDD under BOR0 Interrupt Mask
+#define SYSCTL_IMC_VDDAIM       0x00000400  // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM    0x00000100  // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM    0x00000080  // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM       0x00000040  // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM        0x00000008  // Main Oscillator Failure
+                                            // Interrupt Mask
+#define SYSCTL_IMC_BOR1IM       0x00000002  // VDD under BOR1 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_BOR0MIS     0x00000800  // VDD under BOR0 Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_VDDAMIS     0x00000400  // VDDA Power OK Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_MOSCPUPMIS  0x00000100  // MOSC Power Up Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_USBPLLLMIS  0x00000080  // USB PLL Lock Masked Interrupt
+                                            // Status
+#define SYSCTL_MISC_PLLLMIS     0x00000040  // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS      0x00000008  // Main Oscillator Failure Masked
+                                            // Interrupt Status
+#define SYSCTL_MISC_BOR1MIS     0x00000002  // VDD under BOR1 Masked Interrupt
+                                            // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL    0x00010000  // MOSC Failure Reset
+#define SYSCTL_RESC_WDT1        0x00000020  // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW          0x00000010  // Software Reset
+#define SYSCTL_RESC_WDT0        0x00000008  // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR         0x00000004  // Brown-Out Reset
+#define SYSCTL_RESC_POR         0x00000002  // Power-On Reset
+#define SYSCTL_RESC_EXT         0x00000001  // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG          0x08000000  // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M     0x07800000  // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV    0x00400000  // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV    0x00100000  // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M     0x000E0000  // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2     0x00000000  // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4     0x00020000  // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8     0x00040000  // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16    0x00060000  // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32    0x00080000  // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64    0x000A0000  // PWM clock /64
+#define SYSCTL_RCC_PWRDN        0x00002000  // PLL Power Down
+#define SYSCTL_RCC_BYPASS       0x00000800  // PLL Bypass
+#define SYSCTL_RCC_XTAL_M       0x000007C0  // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ    0x00000180  // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0  // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200  // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ    0x00000240  // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280  // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ    0x000002C0  // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300  // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340  // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ    0x00000380  // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0  // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ   0x00000400  // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ   0x00000440  // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480  // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0  // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500  // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ   0x00000540  // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580  // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ   0x000005C0  // 18.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_20MHZ   0x00000600  // 20.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_24MHZ   0x00000640  // 24.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_25MHZ   0x00000680  // 25.0 MHz (USB)
+#define SYSCTL_RCC_OSCSRC_M     0x00000030  // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN  0x00000000  // MOSC
+#define SYSCTL_RCC_OSCSRC_INT   0x00000010  // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4  0x00000020  // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30    0x00000030  // LFIOSC
+#define SYSCTL_RCC_MOSCDIS      0x00000001  // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S     23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTF  0x00000020  // Port F Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTE  0x00000010  // Port E Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTD  0x00000008  // Port D Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTC  0x00000004  // Port C Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTB  0x00000002  // Port B Advanced High-Performance
+                                            // Bus
+#define SYSCTL_GPIOHBCTL_PORTA  0x00000001  // Port A Advanced High-Performance
+                                            // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2     0x80000000  // Use RCC2
+#define SYSCTL_RCC2_DIV400      0x40000000  // Divide PLL as 400 MHz vs. 200
+                                            // MHz
+#define SYSCTL_RCC2_SYSDIV2_M   0x1F800000  // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB  0x00400000  // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN    0x00004000  // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2      0x00002000  // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2     0x00000800  // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M   0x00000070  // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO  0x00000000  // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO  0x00000010  // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020  // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30  0x00000030  // LFIOSC
+#define SYSCTL_RCC2_OSCSRC2_32  0x00000070  // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_NOXTAL   0x00000004  // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM   0x00000002  // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL     0x00000001  // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M  0x00000C00  // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K                                             \
+                                0x00000400  // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K                                             \
+                                0x00000800  // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00  // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M  0x00000300  // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K                                             \
+                                0x00000000  // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K                                             \
+                                0x00000100  // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K                                             \
+                                0x00000200  // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300  // 1M samples/second
+#define SYSCTL_RCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1       0x10000000  // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1       0x02000000  // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0       0x01000000  // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0       0x00100000  // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1       0x00020000  // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0       0x00010000  // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB        0x00000040  // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0       0x00000008  // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP1      0x02000000  // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0      0x01000000  // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3     0x00080000  // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2     0x00040000  // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1     0x00020000  // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0     0x00010000  // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1       0x00004000  // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0       0x00001000  // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1       0x00000200  // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0       0x00000100  // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1       0x00000020  // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0       0x00000010  // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2      0x00000004  // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1      0x00000002  // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0      0x00000001  // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0       0x00010000  // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA       0x00002000  // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF      0x00000020  // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE      0x00000010  // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD      0x00000008  // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC      0x00000004  // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB      0x00000002  // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA      0x00000001  // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M   0x1F800000  // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M   0x00000070  // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000  // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO  0x00000010  // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30  0x00000030  // LFIOSC
+#define SYSCTL_DSLPCLKCFG_O_32  0x00000070  // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_PIOSCPD                                             \
+                                0x00000002  // PIOSC Power Down Request
+#define SYSCTL_DSLPCLKCFG_D_S   23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU      0x00000001  // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN    0x80000000  // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL     0x00000200  // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE  0x00000100  // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M    0x0000007F  // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M   0x007F0000  // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M   0x00000300  // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000  // Calibration has not been
+                                            // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100  // The last calibration operation
+                                            // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200  // The last calibration operation
+                                            // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M   0x0000007F  // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S   16
+#define SYSCTL_PIOSCSTAT_CT_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00  // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M  0x000003FF  // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M     0x00001F00  // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M     0x0000001F  // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S     8
+#define SYSCTL_PLLFREQ1_N_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK     0x00000001  // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SLPPWRCFG_FLASHPM_M                                            \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_SLPPWRCFG_FLASHPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_FLASHPM_SLP                                          \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_M                                             \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_SLPPWRCFG_SRAMPM_NRM                                           \
+                                0x00000000  // Active Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_SBY                                           \
+                                0x00000001  // Standby Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_LP                                            \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPPWRCFG_FLASHPM_M                                           \
+                                0x00000030  // Flash Power Modes
+#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM                                         \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP                                         \
+                                0x00000020  // Low Power Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_M                                            \
+                                0x00000003  // SRAM Power Modes
+#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM                                          \
+                                0x00000000  // Active Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY                                          \
+                                0x00000001  // Standby Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_LP                                           \
+                                0x00000003  // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7      0x00800000  // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6      0x00400000  // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5      0x00200000  // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4      0x00100000  // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3      0x00080000  // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2      0x00040000  // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1      0x00020000  // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0      0x00010000  // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7      0x00000080  // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6      0x00000040  // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5      0x00000020  // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4      0x00000010  // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3      0x00000008  // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2      0x00000004  // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1      0x00000002  // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0      0x00000001  // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB      0x00000001  // 32 Word Flash Write Buffer
+                                            // Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOSPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDOSPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDOSPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDOSPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDOSPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDOSPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDOSPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDOSPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDOSPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDODPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDODPCTL_VADJEN  0x80000000  // Voltage Adjust Enable
+#define SYSCTL_LDODPCTL_VLDO_M  0x000000FF  // LDO Output Voltage
+#define SYSCTL_LDODPCTL_VLDO_0_90V                                            \
+                                0x00000012  // 0.90 V
+#define SYSCTL_LDODPCTL_VLDO_0_95V                                            \
+                                0x00000013  // 0.95 V
+#define SYSCTL_LDODPCTL_VLDO_1_00V                                            \
+                                0x00000014  // 1.00 V
+#define SYSCTL_LDODPCTL_VLDO_1_05V                                            \
+                                0x00000015  // 1.05 V
+#define SYSCTL_LDODPCTL_VLDO_1_10V                                            \
+                                0x00000016  // 1.10 V
+#define SYSCTL_LDODPCTL_VLDO_1_15V                                            \
+                                0x00000017  // 1.15 V
+#define SYSCTL_LDODPCTL_VLDO_1_20V                                            \
+                                0x00000018  // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1          0x00000002  // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0          0x00000001  // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Present
+#define SYSCTL_PPTIMER_P4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Present
+#define SYSCTL_PPTIMER_P3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Present
+#define SYSCTL_PPTIMER_P2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Present
+#define SYSCTL_PPTIMER_P1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Present
+#define SYSCTL_PPTIMER_P0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P14       0x00004000  // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13       0x00002000  // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12       0x00001000  // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11       0x00000800  // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10       0x00000400  // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9        0x00000200  // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8        0x00000100  // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7        0x00000080  // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6        0x00000040  // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5        0x00000020  // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4        0x00000010  // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3        0x00000008  // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2        0x00000004  // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1        0x00000002  // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0        0x00000001  // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0         0x00000001  // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0         0x00000001  // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7        0x00000080  // UART Module 7 Present
+#define SYSCTL_PPUART_P6        0x00000040  // UART Module 6 Present
+#define SYSCTL_PPUART_P5        0x00000020  // UART Module 5 Present
+#define SYSCTL_PPUART_P4        0x00000010  // UART Module 4 Present
+#define SYSCTL_PPUART_P3        0x00000008  // UART Module 3 Present
+#define SYSCTL_PPUART_P2        0x00000004  // UART Module 2 Present
+#define SYSCTL_PPUART_P1        0x00000002  // UART Module 1 Present
+#define SYSCTL_PPUART_P0        0x00000001  // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3         0x00000008  // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2         0x00000004  // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1         0x00000002  // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0         0x00000001  // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P5         0x00000020  // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4         0x00000010  // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3         0x00000008  // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2         0x00000004  // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1         0x00000002  // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0         0x00000001  // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0         0x00000001  // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1         0x00000002  // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0         0x00000001  // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1         0x00000002  // ADC Module 1 Present
+#define SYSCTL_PPADC_P0         0x00000001  // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0        0x00000001  // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1         0x00000002  // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0         0x00000001  // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1         0x00000002  // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0         0x00000001  // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0      0x00000001  // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Present
+#define SYSCTL_PPWTIMER_P4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Present
+#define SYSCTL_PPWTIMER_P3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Present
+#define SYSCTL_PPWTIMER_P2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Present
+#define SYSCTL_PPWTIMER_P1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Present
+#define SYSCTL_PPWTIMER_P0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1          0x00000002  // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0          0x00000001  // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Software Reset
+#define SYSCTL_SRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Software Reset
+#define SYSCTL_SRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Software Reset
+#define SYSCTL_SRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Software Reset
+#define SYSCTL_SRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Software Reset
+#define SYSCTL_SRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R5        0x00000020  // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4        0x00000010  // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3        0x00000008  // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2        0x00000004  // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1        0x00000002  // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0        0x00000001  // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0         0x00000001  // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0         0x00000001  // Hibernation Module Software
+                                            // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7        0x00000080  // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6        0x00000040  // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5        0x00000020  // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4        0x00000010  // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3        0x00000008  // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2        0x00000004  // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1        0x00000002  // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0        0x00000001  // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3         0x00000008  // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2         0x00000004  // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1         0x00000002  // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0         0x00000001  // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R3         0x00000008  // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2         0x00000004  // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1         0x00000002  // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0         0x00000001  // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0         0x00000001  // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1         0x00000002  // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0         0x00000001  // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1         0x00000002  // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0         0x00000001  // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1         0x00000002  // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0         0x00000001  // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1         0x00000002  // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0         0x00000001  // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0      0x00000001  // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1        0x00000002  // Watchdog Timer 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCWD_R0        0x00000001  // Watchdog Timer 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R5      0x00000020  // GPIO Port F Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R4      0x00000010  // GPIO Port E Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R3      0x00000008  // GPIO Port D Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R2      0x00000004  // GPIO Port C Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R1      0x00000002  // GPIO Port B Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCGPIO_R0      0x00000001  // GPIO Port A Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0       0x00000001  // uDMA Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0       0x00000001  // Hibernation Module Run Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7      0x00000080  // UART Module 7 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R6      0x00000040  // UART Module 6 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R5      0x00000020  // UART Module 5 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R4      0x00000010  // UART Module 4 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R3      0x00000008  // UART Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R2      0x00000004  // UART Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R1      0x00000002  // UART Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCUART_R0      0x00000001  // UART Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3       0x00000008  // SSI Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R2       0x00000004  // SSI Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R1       0x00000002  // SSI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCSSI_R0       0x00000001  // SSI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R3       0x00000008  // I2C Module 3 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R2       0x00000004  // I2C Module 2 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R1       0x00000002  // I2C Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCI2C_R0       0x00000001  // I2C Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0       0x00000001  // USB Module Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1       0x00000002  // CAN Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCCAN_R0       0x00000001  // CAN Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1       0x00000002  // ADC Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCADC_R0       0x00000001  // ADC Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0      0x00000001  // Analog Comparator Module 0 Run
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1       0x00000002  // PWM Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCPWM_R0       0x00000001  // PWM Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1       0x00000002  // QEI Module 1 Run Mode Clock
+                                            // Gating Control
+#define SYSCTL_RCGCQEI_R0       0x00000001  // QEI Module 0 Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0    0x00000001  // EEPROM Module Run Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Run Mode Clock Gating
+                                            // Control
+#define SYSCTL_RCGCWTIMER_R0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Run Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1        0x00000002  // Watchdog Timer 1 Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_SCGCWD_S0        0x00000001  // Watchdog Timer 0 Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCTIMER_S0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S5      0x00000020  // GPIO Port F Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S4      0x00000010  // GPIO Port E Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S3      0x00000008  // GPIO Port D Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S2      0x00000004  // GPIO Port C Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S1      0x00000002  // GPIO Port B Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCGPIO_S0      0x00000001  // GPIO Port A Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0       0x00000001  // uDMA Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0       0x00000001  // Hibernation Module Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7      0x00000080  // UART Module 7 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S6      0x00000040  // UART Module 6 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S5      0x00000020  // UART Module 5 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S4      0x00000010  // UART Module 4 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S3      0x00000008  // UART Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S2      0x00000004  // UART Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S1      0x00000002  // UART Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCUART_S0      0x00000001  // UART Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3       0x00000008  // SSI Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S2       0x00000004  // SSI Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S1       0x00000002  // SSI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCSSI_S0       0x00000001  // SSI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S3       0x00000008  // I2C Module 3 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S2       0x00000004  // I2C Module 2 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S1       0x00000002  // I2C Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCI2C_S0       0x00000001  // I2C Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0       0x00000001  // USB Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1       0x00000002  // CAN Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCCAN_S0       0x00000001  // CAN Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1       0x00000002  // ADC Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCADC_S0       0x00000001  // ADC Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0      0x00000001  // Analog Comparator Module 0 Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1       0x00000002  // PWM Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCPWM_S0       0x00000001  // PWM Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1       0x00000002  // QEI Module 1 Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_SCGCQEI_S0       0x00000001  // QEI Module 0 Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0    0x00000001  // EEPROM Module Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_SCGCWTIMER_S0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1        0x00000002  // Watchdog Timer 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCWD_D0        0x00000001  // Watchdog Timer 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D5     0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D4     0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D3     0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D2     0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D1     0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Deep-Sleep Mode Clock Gating
+                                            // Control
+#define SYSCTL_DCGCTIMER_D0     0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D5      0x00000020  // GPIO Port F Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4      0x00000010  // GPIO Port E Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3      0x00000008  // GPIO Port D Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2      0x00000004  // GPIO Port C Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1      0x00000002  // GPIO Port B Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0      0x00000001  // GPIO Port A Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0       0x00000001  // uDMA Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0       0x00000001  // Hibernation Module Deep-Sleep
+                                            // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7      0x00000080  // UART Module 7 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D6      0x00000040  // UART Module 6 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D5      0x00000020  // UART Module 5 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D4      0x00000010  // UART Module 4 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D3      0x00000008  // UART Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D2      0x00000004  // UART Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D1      0x00000002  // UART Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCUART_D0      0x00000001  // UART Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3       0x00000008  // SSI Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2       0x00000004  // SSI Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1       0x00000002  // SSI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0       0x00000001  // SSI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D3       0x00000008  // I2C Module 3 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2       0x00000004  // I2C Module 2 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1       0x00000002  // I2C Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0       0x00000001  // I2C Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0       0x00000001  // USB Module Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1       0x00000002  // CAN Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0       0x00000001  // CAN Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1       0x00000002  // ADC Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCADC_D0       0x00000001  // ADC Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0      0x00000001  // Analog Comparator Module 0
+                                            // Deep-Sleep Mode Clock Gating
+                                            // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1       0x00000002  // PWM Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0       0x00000001  // PWM Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1       0x00000002  // QEI Module 1 Deep-Sleep Mode
+                                            // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0       0x00000001  // QEI Module 0 Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0    0x00000001  // EEPROM Module Deep-Sleep Mode
+                                            // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5    0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D4    0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D3    0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D2    0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D1    0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Deep-Sleep Mode Clock
+                                            // Gating Control
+#define SYSCTL_DCGCWTIMER_D0    0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Deep-Sleep Mode Clock
+                                            // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1          0x00000002  // Watchdog Timer 1 Peripheral
+                                            // Ready
+#define SYSCTL_PRWD_R0          0x00000001  // Watchdog Timer 0 Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R5       0x00000020  // 16/32-Bit General-Purpose Timer
+                                            // 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4       0x00000010  // 16/32-Bit General-Purpose Timer
+                                            // 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3       0x00000008  // 16/32-Bit General-Purpose Timer
+                                            // 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2       0x00000004  // 16/32-Bit General-Purpose Timer
+                                            // 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1       0x00000002  // 16/32-Bit General-Purpose Timer
+                                            // 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0       0x00000001  // 16/32-Bit General-Purpose Timer
+                                            // 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R5        0x00000020  // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4        0x00000010  // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3        0x00000008  // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2        0x00000004  // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1        0x00000002  // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0        0x00000001  // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0         0x00000001  // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0         0x00000001  // Hibernation Module Peripheral
+                                            // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7        0x00000080  // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6        0x00000040  // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5        0x00000020  // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4        0x00000010  // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3        0x00000008  // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2        0x00000004  // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1        0x00000002  // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0        0x00000001  // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3         0x00000008  // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2         0x00000004  // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1         0x00000002  // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0         0x00000001  // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R3         0x00000008  // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2         0x00000004  // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1         0x00000002  // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0         0x00000001  // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0         0x00000001  // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1         0x00000002  // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0         0x00000001  // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1         0x00000002  // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0         0x00000001  // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0        0x00000001  // Analog Comparator Module 0
+                                            // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1         0x00000002  // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0         0x00000001  // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1         0x00000002  // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0         0x00000001  // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0      0x00000001  // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5      0x00000020  // 32/64-Bit Wide General-Purpose
+                                            // Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4      0x00000010  // 32/64-Bit Wide General-Purpose
+                                            // Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3      0x00000008  // 32/64-Bit Wide General-Purpose
+                                            // Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2      0x00000004  // 32/64-Bit Wide General-Purpose
+                                            // Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1      0x00000002  // 32/64-Bit Wide General-Purpose
+                                            // Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0      0x00000001  // 32/64-Bit Wide General-Purpose
+                                            // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M    0x001F0000  // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M       0x000000F0  // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE    0x00000000  // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010  // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP                                            \
+                                0x00000020  // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP                                            \
+                                0x00000030  // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT                                             \
+                                0x00000040  // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT                                             \
+                                0x00000050  // Writing destination data
+#define UDMA_STAT_STATE_WAIT    0x00000060  // Waiting for uDMA request to
+                                            // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070  // Writing channel controller data
+#define UDMA_STAT_STATE_STALL   0x00000080  // Stalled
+#define UDMA_STAT_STATE_DONE    0x00000090  // Done
+#define UDMA_STAT_STATE_UNDEF   0x000000A0  // Undefined
+#define UDMA_STAT_MASTEN        0x00000001  // Master Enable Status
+#define UDMA_STAT_DMACHANS_S    16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN         0x00000001  // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M     0xFFFFFC00  // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S     10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M     0xFFFFFFFF  // Alternate Channel Address
+                                            // Pointer
+#define UDMA_ALTBASE_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF  // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M            0xFFFFFFFF  // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M  0xFFFFFFFF  // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M  0xFFFFFFFF  // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M   0xFFFFFFFF  // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M   0xFFFFFFFF  // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M       0xFFFFFFFF  // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M       0xFFFFFFFF  // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M       0xFFFFFFFF  // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M       0xFFFFFFFF  // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M      0xFFFFFFFF  // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M      0xFFFFFFFF  // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR      0x00000001  // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M           0xFFFFFFFF  // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY     0x00000000  // Use the primary channel
+                                            // assignment
+#define UDMA_CHASGN_SECONDARY   0x00000001  // Use the secondary channel
+                                            // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M             0xFFFFFFFF  // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M    0xF0000000  // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M    0x0F000000  // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M    0x00F00000  // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M    0x000F0000  // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M    0x0000F000  // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M    0x00000F00  // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M    0x000000F0  // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M    0x0000000F  // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S    28
+#define UDMA_CHMAP0_CH6SEL_S    24
+#define UDMA_CHMAP0_CH5SEL_S    20
+#define UDMA_CHMAP0_CH4SEL_S    16
+#define UDMA_CHMAP0_CH3SEL_S    12
+#define UDMA_CHMAP0_CH2SEL_S    8
+#define UDMA_CHMAP0_CH1SEL_S    4
+#define UDMA_CHMAP0_CH0SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M   0xF0000000  // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M   0x0F000000  // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M   0x00F00000  // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M   0x000F0000  // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M   0x0000F000  // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M   0x00000F00  // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M    0x000000F0  // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M    0x0000000F  // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S   28
+#define UDMA_CHMAP1_CH14SEL_S   24
+#define UDMA_CHMAP1_CH13SEL_S   20
+#define UDMA_CHMAP1_CH12SEL_S   16
+#define UDMA_CHMAP1_CH11SEL_S   12
+#define UDMA_CHMAP1_CH10SEL_S   8
+#define UDMA_CHMAP1_CH9SEL_S    4
+#define UDMA_CHMAP1_CH8SEL_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M   0xF0000000  // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M   0x0F000000  // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M   0x00F00000  // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M   0x000F0000  // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M   0x0000F000  // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M   0x00000F00  // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M   0x000000F0  // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M   0x0000000F  // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S   28
+#define UDMA_CHMAP2_CH22SEL_S   24
+#define UDMA_CHMAP2_CH21SEL_S   20
+#define UDMA_CHMAP2_CH20SEL_S   16
+#define UDMA_CHMAP2_CH19SEL_S   12
+#define UDMA_CHMAP2_CH18SEL_S   8
+#define UDMA_CHMAP2_CH17SEL_S   4
+#define UDMA_CHMAP2_CH16SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M   0xF0000000  // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M   0x0F000000  // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M   0x00F00000  // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M   0x000F0000  // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M   0x0000F000  // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M   0x00000F00  // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M   0x000000F0  // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M   0x0000000F  // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S   28
+#define UDMA_CHMAP3_CH30SEL_S   24
+#define UDMA_CHMAP3_CH29SEL_S   20
+#define UDMA_CHMAP3_CH28SEL_S   16
+#define UDMA_CHMAP3_CH27SEL_S   12
+#define UDMA_CHMAP3_CH26SEL_S   8
+#define UDMA_CHMAP3_CH25SEL_S   4
+#define UDMA_CHMAP3_CH24SEL_S   0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M     0xFFFFFFFF  // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M     0xFFFFFFFF  // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S     0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M     0xC0000000  // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_DSTINC_16    0x40000000  // Half-word
+#define UDMA_CHCTL_DSTINC_32    0x80000000  // Word
+#define UDMA_CHCTL_DSTINC_NONE  0xC0000000  // No increment
+#define UDMA_CHCTL_DSTSIZE_M    0x30000000  // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_DSTSIZE_16   0x10000000  // Half-word
+#define UDMA_CHCTL_DSTSIZE_32   0x20000000  // Word
+#define UDMA_CHCTL_SRCINC_M     0x0C000000  // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8     0x00000000  // Byte
+#define UDMA_CHCTL_SRCINC_16    0x04000000  // Half-word
+#define UDMA_CHCTL_SRCINC_32    0x08000000  // Word
+#define UDMA_CHCTL_SRCINC_NONE  0x0C000000  // No increment
+#define UDMA_CHCTL_SRCSIZE_M    0x03000000  // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8    0x00000000  // Byte
+#define UDMA_CHCTL_SRCSIZE_16   0x01000000  // Half-word
+#define UDMA_CHCTL_SRCSIZE_32   0x02000000  // Word
+#define UDMA_CHCTL_ARBSIZE_M    0x0003C000  // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1    0x00000000  // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2    0x00004000  // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4    0x00008000  // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8    0x0000C000  // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16   0x00010000  // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32   0x00014000  // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64   0x00018000  // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128  0x0001C000  // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256  0x00020000  // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512  0x00024000  // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000  // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M   0x00003FF0  // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST  0x00000008  // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M   0x00000007  // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP                                              \
+                                0x00000000  // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC                                             \
+                                0x00000001  // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO                                              \
+                                0x00000002  // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG                                          \
+                                0x00000003  // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG                                            \
+                                0x00000004  // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA                                           \
+                                0x00000005  // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG                                            \
+                                0x00000006  // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA                                           \
+                                0x00000007  // Alternate Peripheral
+                                            // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S   4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP      0x00000200  // Disable Out-Of-Order Floating
+                                            // Point
+#define NVIC_ACTLR_DISFPCA      0x00000100  // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD      0x00000004  // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF      0x00000002  // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC      0x00000001  // Disable Interrupts of Multiple
+                                            // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT      0x00010000  // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC    0x00000004  // Clock Source
+#define NVIC_ST_CTRL_INTEN      0x00000002  // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE     0x00000001  // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M        0x00FFFFFF  // Reload Value
+#define NVIC_ST_RELOAD_S        0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M       0x00FFFFFF  // Current Value
+#define NVIC_ST_CURRENT_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M          0xFFFFFFFF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M          0x000007FF  // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M         0xFFFFFFFF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M         0x000007FF  // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M        0xFFFFFFFF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M        0x000007FF  // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M      0xFFFFFFFF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M      0x000007FF  // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M      0xFFFFFFFF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M      0x000007FF  // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M        0xE0000000  // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M        0x00E00000  // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M        0x0000E000  // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M        0x000000E0  // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S        29
+#define NVIC_PRI0_INT2_S        21
+#define NVIC_PRI0_INT1_S        13
+#define NVIC_PRI0_INT0_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M        0xE0000000  // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M        0x00E00000  // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M        0x0000E000  // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M        0x000000E0  // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S        29
+#define NVIC_PRI1_INT6_S        21
+#define NVIC_PRI1_INT5_S        13
+#define NVIC_PRI1_INT4_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M       0xE0000000  // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M       0x00E00000  // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M        0x0000E000  // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M        0x000000E0  // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S       29
+#define NVIC_PRI2_INT10_S       21
+#define NVIC_PRI2_INT9_S        13
+#define NVIC_PRI2_INT8_S        5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M       0xE0000000  // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M       0x00E00000  // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M       0x0000E000  // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M       0x000000E0  // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S       29
+#define NVIC_PRI3_INT14_S       21
+#define NVIC_PRI3_INT13_S       13
+#define NVIC_PRI3_INT12_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M       0xE0000000  // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M       0x00E00000  // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M       0x0000E000  // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M       0x000000E0  // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S       29
+#define NVIC_PRI4_INT18_S       21
+#define NVIC_PRI4_INT17_S       13
+#define NVIC_PRI4_INT16_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M       0xE0000000  // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M       0x00E00000  // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M       0x0000E000  // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M       0x000000E0  // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S       29
+#define NVIC_PRI5_INT22_S       21
+#define NVIC_PRI5_INT21_S       13
+#define NVIC_PRI5_INT20_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M       0xE0000000  // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M       0x00E00000  // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M       0x0000E000  // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M       0x000000E0  // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S       29
+#define NVIC_PRI6_INT26_S       21
+#define NVIC_PRI6_INT25_S       13
+#define NVIC_PRI6_INT24_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M       0xE0000000  // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M       0x00E00000  // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M       0x0000E000  // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M       0x000000E0  // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S       29
+#define NVIC_PRI7_INT30_S       21
+#define NVIC_PRI7_INT29_S       13
+#define NVIC_PRI7_INT28_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M       0xE0000000  // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M       0x00E00000  // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M       0x0000E000  // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M       0x000000E0  // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S       29
+#define NVIC_PRI8_INT34_S       21
+#define NVIC_PRI8_INT33_S       13
+#define NVIC_PRI8_INT32_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M       0xE0000000  // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M       0x00E00000  // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M       0x0000E000  // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M       0x000000E0  // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S       29
+#define NVIC_PRI9_INT38_S       21
+#define NVIC_PRI9_INT37_S       13
+#define NVIC_PRI9_INT36_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M      0xE0000000  // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M      0x00E00000  // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M      0x0000E000  // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M      0x000000E0  // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S      29
+#define NVIC_PRI10_INT42_S      21
+#define NVIC_PRI10_INT41_S      13
+#define NVIC_PRI10_INT40_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M      0xE0000000  // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M      0x00E00000  // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M      0x0000E000  // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M      0x000000E0  // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S      29
+#define NVIC_PRI11_INT46_S      21
+#define NVIC_PRI11_INT45_S      13
+#define NVIC_PRI11_INT44_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M      0xE0000000  // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M      0x00E00000  // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M      0x0000E000  // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M      0x000000E0  // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S      29
+#define NVIC_PRI12_INT50_S      21
+#define NVIC_PRI12_INT49_S      13
+#define NVIC_PRI12_INT48_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M      0xE0000000  // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M      0x00E00000  // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M      0x0000E000  // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M      0x000000E0  // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S      29
+#define NVIC_PRI13_INT54_S      21
+#define NVIC_PRI13_INT53_S      13
+#define NVIC_PRI13_INT52_S      5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M       0xE0000000  // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M       0x00E00000  // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M       0x0000E000  // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M       0x000000E0  // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S       29
+#define NVIC_PRI14_INTC_S       21
+#define NVIC_PRI14_INTB_S       13
+#define NVIC_PRI14_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M       0xE0000000  // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M       0x00E00000  // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M       0x0000E000  // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M       0x000000E0  // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S       29
+#define NVIC_PRI15_INTC_S       21
+#define NVIC_PRI15_INTB_S       13
+#define NVIC_PRI15_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M       0xE0000000  // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M       0x00E00000  // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M       0x0000E000  // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M       0x000000E0  // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S       29
+#define NVIC_PRI16_INTC_S       21
+#define NVIC_PRI16_INTB_S       13
+#define NVIC_PRI16_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M       0xE0000000  // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M       0x00E00000  // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M       0x0000E000  // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M       0x000000E0  // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S       29
+#define NVIC_PRI17_INTC_S       21
+#define NVIC_PRI17_INTB_S       13
+#define NVIC_PRI17_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M       0xE0000000  // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M       0x00E00000  // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M       0x0000E000  // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M       0x000000E0  // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S       29
+#define NVIC_PRI18_INTC_S       21
+#define NVIC_PRI18_INTB_S       13
+#define NVIC_PRI18_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M       0xE0000000  // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M       0x00E00000  // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M       0x0000E000  // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M       0x000000E0  // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S       29
+#define NVIC_PRI19_INTC_S       21
+#define NVIC_PRI19_INTB_S       13
+#define NVIC_PRI19_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M       0xE0000000  // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M       0x00E00000  // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M       0x0000E000  // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M       0x000000E0  // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S       29
+#define NVIC_PRI20_INTC_S       21
+#define NVIC_PRI20_INTB_S       13
+#define NVIC_PRI20_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M       0xE0000000  // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M       0x00E00000  // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M       0x0000E000  // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M       0x000000E0  // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S       29
+#define NVIC_PRI21_INTC_S       21
+#define NVIC_PRI21_INTB_S       13
+#define NVIC_PRI21_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M       0xE0000000  // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M       0x00E00000  // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M       0x0000E000  // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M       0x000000E0  // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S       29
+#define NVIC_PRI22_INTC_S       21
+#define NVIC_PRI22_INTB_S       13
+#define NVIC_PRI22_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M       0xE0000000  // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M       0x00E00000  // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M       0x0000E000  // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M       0x000000E0  // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S       29
+#define NVIC_PRI23_INTC_S       21
+#define NVIC_PRI23_INTB_S       13
+#define NVIC_PRI23_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M       0xE0000000  // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M       0x00E00000  // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M       0x0000E000  // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M       0x000000E0  // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S       29
+#define NVIC_PRI24_INTC_S       21
+#define NVIC_PRI24_INTB_S       13
+#define NVIC_PRI24_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M       0xE0000000  // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M       0x00E00000  // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M       0x0000E000  // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M       0x000000E0  // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S       29
+#define NVIC_PRI25_INTC_S       21
+#define NVIC_PRI25_INTB_S       13
+#define NVIC_PRI25_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M       0xE0000000  // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M       0x00E00000  // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M       0x0000E000  // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M       0x000000E0  // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S       29
+#define NVIC_PRI26_INTC_S       21
+#define NVIC_PRI26_INTB_S       13
+#define NVIC_PRI26_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M       0xE0000000  // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M       0x00E00000  // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M       0x0000E000  // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M       0x000000E0  // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S       29
+#define NVIC_PRI27_INTC_S       21
+#define NVIC_PRI27_INTB_S       13
+#define NVIC_PRI27_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M       0xE0000000  // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M       0x00E00000  // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M       0x0000E000  // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M       0x000000E0  // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S       29
+#define NVIC_PRI28_INTC_S       21
+#define NVIC_PRI28_INTB_S       13
+#define NVIC_PRI28_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M       0xE0000000  // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M       0x00E00000  // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M       0x0000E000  // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M       0x000000E0  // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S       29
+#define NVIC_PRI29_INTC_S       21
+#define NVIC_PRI29_INTB_S       13
+#define NVIC_PRI29_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M       0xE0000000  // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M       0x00E00000  // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M       0x0000E000  // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M       0x000000E0  // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S       29
+#define NVIC_PRI30_INTC_S       21
+#define NVIC_PRI30_INTB_S       13
+#define NVIC_PRI30_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M       0xE0000000  // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M       0x00E00000  // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M       0x0000E000  // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M       0x000000E0  // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S       29
+#define NVIC_PRI31_INTC_S       21
+#define NVIC_PRI31_INTB_S       13
+#define NVIC_PRI31_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M       0xE0000000  // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M       0x00E00000  // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M       0x0000E000  // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M       0x000000E0  // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S       29
+#define NVIC_PRI32_INTC_S       21
+#define NVIC_PRI32_INTB_S       13
+#define NVIC_PRI32_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI33_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI33_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI33_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI33_INTD_S       29
+#define NVIC_PRI33_INTC_S       21
+#define NVIC_PRI33_INTB_S       13
+#define NVIC_PRI33_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M       0xE0000000  // Interrupt Priority for Interrupt
+                                            // [4n+3]
+#define NVIC_PRI34_INTC_M       0x00E00000  // Interrupt Priority for Interrupt
+                                            // [4n+2]
+#define NVIC_PRI34_INTB_M       0x0000E000  // Interrupt Priority for Interrupt
+                                            // [4n+1]
+#define NVIC_PRI34_INTA_M       0x000000E0  // Interrupt Priority for Interrupt
+                                            // [4n]
+#define NVIC_PRI34_INTD_S       29
+#define NVIC_PRI34_INTC_S       21
+#define NVIC_PRI34_INTB_S       13
+#define NVIC_PRI34_INTA_S       5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M        0xFF000000  // Implementer Code
+#define NVIC_CPUID_IMP_ARM      0x41000000  // ARM
+#define NVIC_CPUID_VAR_M        0x00F00000  // Variant Number
+#define NVIC_CPUID_CON_M        0x000F0000  // Constant
+#define NVIC_CPUID_PARTNO_M     0x0000FFF0  // Part Number
+#define NVIC_CPUID_PARTNO_CM4   0x0000C240  // Cortex-M4 processor
+#define NVIC_CPUID_REV_M        0x0000000F  // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET   0x80000000  // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV   0x10000000  // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000  // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000  // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000  // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE   0x00800000  // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND  0x00400000  // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI                                             \
+                                0x00002000  // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD                                            \
+                                0x00003000  // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM                                             \
+                                0x00004000  // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS                                             \
+                                0x00005000  // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG                                             \
+                                0x00006000  // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC                                             \
+                                0x0000B000  // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV                                           \
+                                0x0000E000  // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK                                            \
+                                0x0000F000  // SysTick
+#define NVIC_INT_CTRL_RET_BASE  0x00000800  // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF  // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_OFFSET_M    0xFFFFFC00  // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S    10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M    0xFFFF0000  // Register Key
+#define NVIC_APINT_VECTKEY      0x05FA0000  // Vector key
+#define NVIC_APINT_ENDIANESS    0x00008000  // Data Endianess
+#define NVIC_APINT_PRIGROUP_M   0x00000700  // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000  // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100  // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200  // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300  // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400  // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500  // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600  // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700  // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ  0x00000004  // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002  // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET   0x00000001  // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010  // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004  // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002  // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN  0x00000200  // Stack Alignment on Exception
+                                            // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100  // Ignore Bus Fault in NMI and
+                                            // Fault
+#define NVIC_CFG_CTRL_DIV0      0x00000010  // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008  // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002  // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR  0x00000001  // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M   0x00E00000  // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M     0x0000E000  // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M     0x000000E0  // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S   21
+#define NVIC_SYS_PRI1_BUS_S     13
+#define NVIC_SYS_PRI1_MEM_S     5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M     0xE0000000  // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S     29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M    0xE0000000  // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M  0x00E00000  // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M   0x000000E0  // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S    29
+#define NVIC_SYS_PRI3_PENDSV_S  21
+#define NVIC_SYS_PRI3_DEBUG_S   5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000  // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS   0x00020000  // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM   0x00010000  // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC   0x00008000  // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP  0x00004000  // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP  0x00002000  // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP                                              \
+                                0x00001000  // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK  0x00000800  // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400  // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON   0x00000100  // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA  0x00000080  // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA  0x00000008  // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA  0x00000002  // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA  0x00000001  // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0    0x02000000  // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000  // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP    0x00080000  // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC   0x00040000  // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000  // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF   0x00010000  // Undefined Instruction Usage
+                                            // Fault
+#define NVIC_FAULT_STAT_BFARV   0x00008000  // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000  // Bus Fault on Floating-Point Lazy
+                                            // State Preservation
+#define NVIC_FAULT_STAT_BSTKE   0x00001000  // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE  0x00000800  // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE   0x00000400  // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200  // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS    0x00000100  // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV   0x00000080  // Memory Management Fault Address
+                                            // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020  // Memory Management Fault on
+                                            // Floating-Point Lazy State
+                                            // Preservation
+#define NVIC_FAULT_STAT_MSTKE   0x00000010  // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE  0x00000008  // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR    0x00000002  // Data Access Violation
+#define NVIC_FAULT_STAT_IERR    0x00000001  // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG    0x80000000  // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000  // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT   0x00000002  // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL  0x00000010  // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH  0x00000008  // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004  // DWT match
+#define NVIC_DEBUG_STAT_BKPT    0x00000002  // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED  0x00000001  // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M          0xFFFFFFFF  // Fault Address
+#define NVIC_MM_ADDR_S          0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M       0xFFFFFFFF  // Fault Address
+#define NVIC_FAULT_ADDR_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M        0x00C00000  // CP11 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP11_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP11_PRIV     0x00400000  // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL     0x00C00000  // Full Access
+#define NVIC_CPAC_CP10_M        0x00300000  // CP10 Coprocessor Access
+                                            // Privilege
+#define NVIC_CPAC_CP10_DIS      0x00000000  // Access Denied
+#define NVIC_CPAC_CP10_PRIV     0x00100000  // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL     0x00300000  // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000  // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00  // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE  0x00000001  // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004  // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA  0x00000002  // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE    0x00000001  // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M       0x00000007  // MPU Region to Access
+#define NVIC_MPU_NUMBER_S       0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M    0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE_VALID     0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M  0x00000007  // Region Number
+#define NVIC_MPU_BASE_ADDR_S    5
+#define NVIC_MPU_BASE_REGION_S  0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN        0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M      0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR_TEX_M     0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000  // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000  // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000  // Bufferable
+#define NVIC_MPU_ATTR_SRD_M     0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SIZE_M    0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR_ENABLE    0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE1_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE1_ADDR_S   5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE2_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE2_ADDR_S   5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M   0xFFFFFFE0  // Base Address Mask
+#define NVIC_MPU_BASE3_VALID    0x00000010  // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007  // Region Number
+#define NVIC_MPU_BASE3_ADDR_S   5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN       0x10000000  // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M     0x07000000  // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M    0x00380000  // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE                                              \
+                                0x00040000  // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE                                              \
+                                0x00020000  // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE                                              \
+                                0x00010000  // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M    0x0000FF00  // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M   0x0000003E  // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE   0x00000001  // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M  0xFFFF0000  // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY    0xA05F0000  // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST                                              \
+                                0x02000000  // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST                                             \
+                                0x01000000  // Core has executed insruction
+                                            // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP  0x00080000  // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP   0x00040000  // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT    0x00020000  // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY  0x00010000  // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL                                             \
+                                0x00000020  // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008  // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP    0x00000004  // Step the core
+#define NVIC_DBG_CTRL_C_HALT    0x00000002  // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001  // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR   0x00010000  // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F  // Register
+#define NVIC_DBG_XFER_REG_R0    0x00000000  // Register R0
+#define NVIC_DBG_XFER_REG_R1    0x00000001  // Register R1
+#define NVIC_DBG_XFER_REG_R2    0x00000002  // Register R2
+#define NVIC_DBG_XFER_REG_R3    0x00000003  // Register R3
+#define NVIC_DBG_XFER_REG_R4    0x00000004  // Register R4
+#define NVIC_DBG_XFER_REG_R5    0x00000005  // Register R5
+#define NVIC_DBG_XFER_REG_R6    0x00000006  // Register R6
+#define NVIC_DBG_XFER_REG_R7    0x00000007  // Register R7
+#define NVIC_DBG_XFER_REG_R8    0x00000008  // Register R8
+#define NVIC_DBG_XFER_REG_R9    0x00000009  // Register R9
+#define NVIC_DBG_XFER_REG_R10   0x0000000A  // Register R10
+#define NVIC_DBG_XFER_REG_R11   0x0000000B  // Register R11
+#define NVIC_DBG_XFER_REG_R12   0x0000000C  // Register R12
+#define NVIC_DBG_XFER_REG_R13   0x0000000D  // Register R13
+#define NVIC_DBG_XFER_REG_R14   0x0000000E  // Register R14
+#define NVIC_DBG_XFER_REG_R15   0x0000000F  // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010  // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP   0x00000011  // Main SP
+#define NVIC_DBG_XFER_REG_PSP   0x00000012  // Process SP
+#define NVIC_DBG_XFER_REG_DSP   0x00000013  // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP  0x00000014  // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M         0xFFFFFFFF  // Data temporary cache
+#define NVIC_DBG_DATA_S         0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR    0x00000400  // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR     0x00000200  // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR     0x00000100  // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR    0x00000080  // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR     0x00000040  // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR    0x00000020  // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR      0x00000010  // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET      0x00000008  // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004  // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002  // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH  0x00000001  // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M    0x000000FF  // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S    0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN         0x80000000  // Automatic State Preservation
+                                            // Enable
+#define NVIC_FPCC_LSPEN         0x40000000  // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY        0x00000100  // Monitor Ready
+#define NVIC_FPCC_BFRDY         0x00000040  // Bus Fault Ready
+#define NVIC_FPCC_MMRDY         0x00000020  // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY         0x00000010  // Hard Fault Ready
+#define NVIC_FPCC_THREAD        0x00000008  // Thread Mode
+#define NVIC_FPCC_USER          0x00000002  // User Privilege Level
+#define NVIC_FPCC_LSPACT        0x00000001  // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M     0xFFFFFFF8  // Address
+#define NVIC_FPCA_ADDRESS_S     3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP          0x04000000  // AHP Bit Default
+#define NVIC_FPDSC_DN           0x02000000  // DN Bit Default
+#define NVIC_FPDSC_FZ           0x01000000  // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M      0x00C00000  // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN     0x00000000  // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP     0x00400000  // Round towards Plus Infinity (RP)
+                                            // mode
+#define NVIC_FPDSC_RMODE_RM     0x00800000  // Round towards Minus Infinity
+                                            // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ     0x00C00000  // Round towards Zero (RZ) mode
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define SYSCTL_DID0_CLASS_BLIZZARD                                            \
+                                0x00050000  // Tiva(TM) C Series TM4C123-class
+                                            // microcontrollers
+
+#endif
+
+#endif // __TM4C123GH6PM_H__
diff --git a/types.h b/types.h
new file mode 100644
index 0000000..beeafe5
--- /dev/null
+++ b/types.h
@@ -0,0 +1,20 @@
+typedef signed char int_8;
+typedef unsigned char uint_8;
+typedef signed char* int_8_ptr;
+typedef unsigned char* uint_8_ptr;
+typedef signed short int_16;
+typedef unsigned short uint_16;
+typedef signed short* int_16_ptr;
+typedef unsigned short* uint_16_ptr;
+typedef signed int int_32;
+typedef unsigned int uint_32;
+typedef signed int* int_32_ptr;
+typedef unsigned int* uint_32_ptr;
+typedef signed long long int_64;
+typedef unsigned long long uint_64;
+typedef signed long long* int_64_ptr;
+typedef unsigned long long* uint_64_ptr;
+typedef float float_32;
+typedef float* float_32_ptr;
+typedef double float_64;
+typedef double* float_64_ptr;